WO2020047972A1 - 晶圆级封装方法及封装结构 - Google Patents

晶圆级封装方法及封装结构 Download PDF

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Publication number
WO2020047972A1
WO2020047972A1 PCT/CN2018/113101 CN2018113101W WO2020047972A1 WO 2020047972 A1 WO2020047972 A1 WO 2020047972A1 CN 2018113101 W CN2018113101 W CN 2018113101W WO 2020047972 A1 WO2020047972 A1 WO 2020047972A1
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Prior art keywords
oxide layer
chip
wafer
layer
oxide
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PCT/CN2018/113101
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English (en)
French (fr)
Inventor
罗海龙
德劳利·克里夫
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中芯集成电路（宁波）有限公司
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Application filed by 中芯集成电路（宁波）有限公司 filed Critical 中芯集成电路（宁波）有限公司
Priority to JP2021510720A priority Critical patent/JP2021535608A/ja
Priority to KR1020217006433A priority patent/KR20210039440A/ko
Priority to US16/229,850 priority patent/US10784229B2/en
Publication of WO2020047972A1 publication Critical patent/WO2020047972A1/zh

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Definitions

  • Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a wafer-level packaging method and a packaging structure.
  • wafer-level system packaging is a package integration process completed on the wafer, which has the advantages of greatly reducing the area of the packaging structure, reducing manufacturing costs, optimizing electrical performance, and batch manufacturing, which can significantly reduce workload and equipment. Demand.
  • Wafer-level system packaging mainly includes two important processes: physical connection and electrical connection.
  • organic bonding layers such as adhesive films
  • Hole etching processes such as through-silicon via etching processes
  • electroplating techniques achieve electrical connections between semiconductor devices.
  • the problem solved by the embodiments of the present invention is to provide a wafer-level packaging method and a packaging structure to improve packaging yield.
  • an embodiment of the present invention provides a wafer-level packaging method, including: providing a device wafer integrated with a first chip, the device wafer including a first front surface integrated with the first chip, and Forming a first oxide layer on the first front surface; providing a second chip to be integrated, the second chip having a surface to be bonded; on the surface to be bonded Forming a second oxide layer thereon; providing a carrier substrate; temporarily bonding the surface of the second chip facing away from the second oxide layer to the carrier substrate; forming an encapsulation layer on the carrier substrate, the package A layer exposes the top of the second oxide layer; and the bonding of the device wafer and the second chip is achieved by a low temperature fusion bonding process through the first oxide layer and the second oxide layer.
  • an embodiment of the present invention further provides a wafer-level package structure including a device wafer integrated with a first chip, the device wafer including a first front surface integrated with the first chip, and A first front surface opposite to the first front surface, the first front surface having a first oxide layer; a second chip bonded to the device wafer, the second chip having a surface to be bonded, the There is a second oxide layer on the bonding surface, and the second oxide layer and the first oxide layer are connected by a low temperature fusion bonding process; a packaging layer on the first oxide layer, the packaging layer exposing the packaging layer The second chip faces away from the surface of the surface to be bonded.
  • a first oxide layer is formed on a first front surface of a device wafer
  • a second oxide layer is formed on a to-be-bonded surface of a second chip to be integrated
  • the first oxide layer is passed through the first oxide layer.
  • the second oxide layer the low-temperature fusion bonding process is used to realize the bonding between the device wafer and the second chip; on the one hand, the encapsulation layer is used for the low-temperature fusion bonding process in the subsequent
  • the second chip plays an effective supporting role and improves the operability of the low-temperature fusion bonding process.
  • the The surface activity is improved, and the dangling bonds on the surfaces of the first oxide layer and the second oxide layer are increased, so that covalent bonds are formed on the contact surfaces of the first oxide layer and the second oxide layer and bonded with the covalent bonds.
  • the method realizes bonding, and the first oxide layer and the second oxide layer have a high bonding strength, thereby improving the bonding strength of the device wafer and the second chip, and correspondingly improving the package yield. .
  • the method further includes: forming a third oxide layer on the packaging layer, and a top of the third oxide layer and the second oxide layer are formed.
  • the top of the oxide layer is flush; on the one hand, when the surface flatness of the encapsulation layer is poor, a gap is easily formed between the encapsulation layer and the first oxide layer, so the third oxide layer can effectively Reduce the generation of gaps, the third oxide layer and the first oxide layer have a higher degree of adhesion; on the other hand, during the low-temperature fusion bonding process, the first oxide layer can The third oxide layer is bonded in a covalent bond manner. Therefore, the third oxide layer is beneficial to further improve packaging yield.
  • FIGS. 1 to 10 are schematic structural diagrams corresponding to steps in an embodiment of a wafer-level packaging method according to the present invention.
  • the packaging yield of the current wafer-level packaging process is low.
  • the reasons for the lower yield are:
  • Device wafers and chips to be integrated are usually physically connected through an adhesive layer (such as a sticky film or a dry film), but the temperature resistance of the adhesive layer is poor.
  • an adhesive layer such as a sticky film or a dry film
  • the process temperature in the subsequent process is high, the The adhesive layer is prone to failure, thereby reducing the adhesion of the adhesive layer, and even the problem that the device wafer and the chip to be integrated are detached, thereby seriously affecting the package yield of the wafer-level system package.
  • an embodiment of the present invention provides a wafer-level packaging method, including: providing a device wafer integrated with a first chip, the device wafer including a first front surface integrated with the first chip And a first back surface opposite to the first front surface; forming a first oxide layer on the first front surface; providing a second chip to be integrated, the second chip having a surface to be bonded; Forming a second oxide layer on the bonding surface; providing a carrier substrate; temporarily bonding the surface of the second chip facing away from the second oxide layer to the carrier substrate; forming an encapsulation layer on the carrier substrate, so that The packaging layer exposes the top of the second oxide layer; the low-temperature fusion bonding process is used to realize the bonding between the device wafer and the second chip through the first oxide layer and the second oxide layer.
  • the encapsulation layer effectively supports the second chip in the low-temperature fusion bonding process, and improves the operability of the low-temperature fusion bonding process.
  • the contact surface of the first oxide layer and the second oxide layer forms a covalent bond and realizes bonding by means of covalent bond bonding, and the bonding strength is high, thereby significantly improving the bond between the device wafer and the second chip. Combined strength, correspondingly improved packaging yield.
  • FIGS. 1 to 10 are schematic structural diagrams corresponding to steps in an embodiment of a wafer-level packaging method according to the present invention.
  • CMOS Wafer integrated with a first chip 410
  • the device wafer 400 includes a first front surface 401 integrated with the first chip 410 and a phase opposite to the first front surface 401. ⁇ ⁇ ⁇ ⁇ 402.
  • the wafer-level packaging method is used to implement wafer-level system packaging, and the device wafer 400 is used to bond with a chip to be integrated in a subsequent process.
  • the device wafer 400 is a wafer for completing device fabrication.
  • the device wafer 400 may be manufactured using integrated circuit fabrication technology, such as forming NMOS devices and PMOS devices on semiconductor substrates by processes such as deposition and etching.
  • the multiple first chips 410 may be the same type or different types of chips.
  • first chips 410 are integrated in the device wafer 400.
  • the number of the first chips 410 is not limited to three.
  • the semiconductor substrate of the device wafer 400 is a silicon substrate.
  • the material of the semiconductor substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.
  • the semiconductor substrate may also be a silicon substrate on an insulator. Or another type of substrate such as a germanium substrate on an insulator.
  • the material of the semiconductor substrate may be a material suitable for process requirements or easily integrated.
  • the device wafer 400 includes a first front surface 401 integrated with the first chip 410 and a first back surface 402 opposite to the first front surface 401, and the first front surface 401 exposes the First pad 420.
  • the first pad 420 is a bond pad of the device wafer 400, and the first pad 420 is used to achieve electrical connection between the first chip 410 and other circuits.
  • the first back surface 402 refers to a bottom surface of the semiconductor substrate on the device wafer 400 side away from the first pad 420.
  • the thickness of the device wafer 400 is 10 ⁇ m to 100 ⁇ m.
  • a first oxide layer 450 is formed on the first front surface 401.
  • the first oxide layer 450 is used as a bonding layer in a subsequent fusion bonding process, and is used to implement a physical connection between the device wafer 400 and a chip to be integrated. Wherein, after the fusion bonding process, the bonding layer between the device wafer 400 and the chip to be integrated can be bonded in a covalent bond manner, which is beneficial to improving the device wafer 400 and the to-be-integrated chip. The bonding strength of the chip.
  • a material of the first oxide layer 450 is silicon oxide.
  • silicon oxide By selecting a silicon oxide material, during the subsequent fusion bonding process, the device wafer 400 and the chip to be integrated can be bonded by a covalent bond of Si-O-Si. Due to the bonding energy of the silicon-oxygen bond, Larger, which is conducive to further improving the bonding strength of the device wafer 400 and the chip to be integrated; moreover, the silicon oxide material has high process compatibility, and silicon oxide is also a commonly used process and a lower cost material, so By selecting the silicon oxide material, it is helpful to reduce the process difficulty and process cost, and it is also beneficial to reduce the performance impact on the formed packaging structure.
  • the first oxide layer may be hafnium oxide, aluminum oxide, or lanthanum oxide.
  • the first oxide layer 450 is formed by an atomic layer deposition (ALD) process.
  • the atomic layer deposition process refers to a deposition process in which a gas phase precursor pulse is alternately passed into a reaction chamber to chemically adsorb on a substrate to be deposited and a surface reaction occurs.
  • the first oxide layer 450 is formed on the first front surface 401 in the form of an atomic layer, so it is beneficial to improve the uniformity of the deposition rate, the thickness uniformity of the first oxide layer 450, and the The first oxide layer 450 is structurally uniform, and the first oxide layer 450 has good coverage; moreover, the process temperature of the atomic layer deposition process is generally lower, which is also beneficial to reducing the thermal budget. Budget) to reduce the probability of wafer distortion (Wafer Distortion) and device performance deviation.
  • ALD atomic layer deposition
  • the process of forming the first oxide layer may further be a Low Pressure Chemical Vapor Deposition (LPCVD) process, a metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition (MOCVD) process, Physical Vapor Deposition (PVD) process or laser pulse deposition (Pulsed Laser Deposition (PLD) process.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • MOCVD Metal Organic Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • PLD Pulsed Laser Deposition
  • a second chip 200 to be integrated is provided, and the second chip 200 has a surface to be bonded (not labeled).
  • the second chip 200 is used as a chip to be integrated in a wafer-level system package.
  • the number of the second chip 200 is at least one, and the number of the second chip 200 is the same as that of the first chip 410 (see FIG. 1). As shown).
  • the second chip 200 may be one or more of an active element, a passive element, a micro-electro-mechanical system, and an optical element.
  • the second chip 200 may be a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip. In other embodiments, the second chip may also be another functional chip.
  • the wafer-level system package is used to combine multiple second chips 200 with different functions into a package structure. Wafer obtained by dicing. In other embodiments, according to actual process requirements, the function types of the multiple second chips may also be the same.
  • the area of the package structure can be greatly reduced, and The advantages of manufacturing cost, optimized electrical performance, and batch manufacturing can significantly reduce workload and equipment requirements.
  • the wafer-level packaging method of this embodiment is used to implement heterogeneous integration, so the plurality of second chips 200 are chips made of silicon wafers.
  • the second chip may be a chip made of other materials.
  • the number of the second chips 200 is three as an example for description. However, the number of the second chips 200 is not limited to three.
  • the second chip 200 may be manufactured by using integrated circuit manufacturing technology.
  • the second chip 200 also generally includes a device such as an NMOS device or a PMOS device formed on a semiconductor substrate, and further includes a dielectric layer, a metal interconnect structure, and Pads and other structures.
  • the second chip 200 includes a second front surface 201 having a second pad 210 formed thereon, and a second back surface 202 opposite to the second front surface 201, and the second front surface 201 exposes the second Pad 210.
  • the second pad 210 is a lead pad, and the second pad 210 is used to achieve electrical connection between the second chip 200 and other circuits; the second back surface 202 refers to all The bottom surface of the semiconductor substrate on the side of the second chip 200 remote from the second pad 210.
  • the to-be-bonded surface of the second chip 200 is the second front surface 201, that is, the second front surface 201 is subsequently directed toward the device wafer 400, so that the device crystal is formed in the subsequent process.
  • a through-hole structure such as a through-silicon via structure
  • the surface to be bonded may also be the second back surface, that is, the second back surface is subsequently directed toward the device wafer.
  • a second oxide layer 250 is formed on the surface to be bonded (not labeled).
  • the second oxide layer 250 is used as a bonding layer in a subsequent fusion bonding process, and is used to implement a physical connection between the device wafer 400 (as shown in FIG. 1) and the second chip 200 so as to pass a common
  • the valence-to-bond manner significantly increases the bonding strength of the second chip 200 and the device wafer 400.
  • a process of forming the through-hole structure generally includes a through-hole etching process (for example, TSV etching).
  • TSV etching through-hole etching process
  • the through-hole etching process sequentially etches the device wafer 400 and the second oxide layer 250, because the second oxide layer 250 is an inorganic material, and the material of the device wafer 400 is also an inorganic material, Therefore, compared with the solution using an organic adhesive layer (such as a sticky film) as the bonding layer, the solution using the second oxide layer 250 as the bonding layer is also beneficial to reducing the subsequent process of the via hole etching process. It is difficult, and after the through-hole etching process, the problem of too large etched holes in the second oxide layer 250 can be avoided, which is beneficial to improving the electrical connection performance of the through-hole structure.
  • the material of the second oxide layer 250 is the same as the material of the first oxide layer 450, so that covalent bond bonding is better achieved in the subsequent fusion bonding process, which is beneficial to further improve the The bonding strength between the second oxide layer 250 and the first oxide layer 450.
  • the second oxide layer 250 is formed by an atomic layer deposition process, and a material of the second oxide layer 250 is silicon oxide.
  • the second oxide layer may also be hafnium oxide, alumina, or lanthanum oxide, and according to the material of the second oxide layer, the process of forming the second oxide layer may be a low-pressure chemical vapor phase. Deposition process, metal organic chemical vapor deposition process, physical vapor deposition process or laser pulse deposition process.
  • the surface to be bonded of the second chip 200 is the second front surface 201.
  • the second oxide layer 250 is formed on the second front surface 201.
  • the second oxide layer is correspondingly formed on the second back surface.
  • the plurality of second chips 200 are obtained by dicing a wafer. Therefore, in order to improve the formation efficiency and the quality of the second oxide layer 250, the crystals of the second chip 200 are integrated. After the second oxide layer 250 is formed on a circle, the wafer on which the second oxide layer 250 is formed is cut to obtain a second chip 200 on which the second oxide layer 250 is formed.
  • a carrier substrate 100 is provided; a surface of the second chip 200 facing away from the second oxide layer 250 is temporarily bonded to the carrier substrate 100.
  • the carrier substrate 100 is used to support the plurality of second chips 200, thereby facilitating the subsequent processes and improving the operability of the subsequent processes.
  • the carrier substrate 100 can also be used for subsequent injection molding (Molding).
  • the process provides a process platform; and by means of temporary bonding, it is also convenient to subsequently separate the second chip 200 from the carrier substrate 100.
  • the carrier substrate 100 is a carrier wafer.
  • the carrier substrate 100 may be a semiconductor substrate (such as a silicon substrate), an organic glass wafer, an inorganic glass wafer, a resin wafer, a semiconductor material wafer, an oxide crystal wafer, a ceramic wafer, or a metal crystal. Round, organic plastic wafer, inorganic oxide wafer or ceramic material wafer.
  • the second back surface 202 of the second chip 200 is adhered to the carrier substrate 100 through the adhesive layer 150.
  • the adhesive layer 150 is a Die Attach Film (DAF).
  • the adhesive layer may be a dry film, a UV adhesive, or a thermosetting adhesive.
  • the second front surface of the second chip is pasted on the carrier substrate through the adhesive layer.
  • an encapsulation layer 300 is formed on the carrier substrate 100 to cover a sidewall of the second chip 200, and the encapsulation layer 300 exposes the top of the second oxide layer 250.
  • the packaging layer 300 covers the second chip 200. After the subsequent bonding of the second chip 200 and the device wafer 400 (as shown in FIG. 1), the packaging layer 300 can be sealed and moisture-proof. To protect the second chip 200, thereby reducing the probability of the second chip 200 being damaged, contaminated, or oxidized, thereby helping to optimize the performance of the obtained packaging structure; moreover, the packaging layer 300 packs Covering the plurality of second chips 200 can also support the second chip 200, improve the operability of the subsequent fusion bonding process, and help reduce the impact of subsequent processes on the second chip 200. influences.
  • the encapsulation layer 300 exposes the top of the second oxide layer 250, so as to realize the subsequent fusion bonding process of the second oxide layer 250 and the first oxide layer 450 (as shown in FIG. 1).
  • the second oxide layer 250 is formed on a surface to be bonded (not labeled) of the second chip 200, thereby avoiding a process of forming the packaging layer 300.
  • the surface to be bonded has an influence, thereby reducing the effect on the bonding strength between the surface to be bonded and the second oxide layer 250.
  • the material of the packaging layer 300 is epoxy.
  • Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost, so it is widely used as packaging materials for electronic devices and integrated circuits.
  • the material of the encapsulation layer may also be a thermosetting material such as polyimide or silicone.
  • the packaging layer 300 is formed by a liquid molding compound or a solid molding compound through an injection molding process.
  • the shape of the packaging layer 300 is wafer-shaped, and the shape of the wafer-shaped packaging layer 300 is The diameter is the same as the diameter of the device wafer 400.
  • the encapsulation layer may have other suitable shapes.
  • an injection film covering the second chip 200 is formed on the carrier substrate 100; the injection mold is planarized to expose the top of the second oxide layer 250 .
  • the carrier substrate 100 is retained, so that the carrier substrate 100 and the encapsulation layer 300 jointly face each other.
  • the second chip 200 plays a supporting role.
  • a de-bonding process may be performed on the second chip and the carrier substrate to remove the carrier substrate and the adhesive layer.
  • the low-temperature fusion bonding process is used to realize the bonding between the device wafer 400 and the second chip 200.
  • Melt bonding is a process that mainly uses interface chemical forces to complete bonding.
  • a covalent bond is formed on the contact surface of the first oxide layer 450 and the second oxide layer 250 and the Covalent bonding is used to achieve bonding, and the first oxide layer 450 and the second oxide layer 250 have high bonding strength, thereby improving the bond between the device wafer 400 and the second chip 200 Bonding strength, and the subsequent process has a small impact on the bonding strength, correspondingly increasing the package yield of the wafer-level system package.
  • a low-temperature fusion bonding process is adopted to reasonably reduce the process temperature of the annealing treatment in the fusion bonding process, thereby reducing the process temperature.
  • the effect of the fusion bonding process on the packaging layer 300 is also exposed to the process environment of the fusion bonding process.
  • the steps of the fusion bonding process include: forming a surface of the first oxide layer 450 (as shown in FIG. 5) and a second oxide layer 250 (as shown in FIG. 6).
  • the surface is subjected to a plasma activation process 110.
  • pollutants and impurities on the surfaces of the first oxide layer 450 and the second oxide layer 250 are made into a gaseous state and discharged through a vacuum pump of a plasma system, thereby removing pollutants and impurities.
  • Role for example, can better remove metal pollution and organic pollutants.
  • the plasma of the plasma activation process 110 strikes the surface of the first oxide layer 450 and the surface of the second oxide layer 250, and energizes the unstable non-bridged oxygen atoms, so that the oxygen atoms leave The atoms that were originally bonded, the plasma activation treatment 110 will also destroy the hydrocarbons on the surfaces of the first oxide layer 450 and the second oxide layer 250, and increase hydroxyl (OH) in the first oxide layer 450 and the first oxide layer.
  • the formation of the surface of the second oxide layer 250 improves the surface activity of the first oxide layer 450 and the second oxide layer 250, and more dangling bonds are formed on the surfaces of the first oxide layer 450 and the second oxide layer 250.
  • the material of the first oxide layer 450 and the second oxide layer 250 is silicon oxide. Therefore, after the plasma activation process 110, the surfaces of the first oxide layer 450 and the second oxide layer 250 are suspended. There are more Si-OH bonds.
  • the reactive gas used in the plasma activation process 110 may include one or more of Ar, N 2 , O 2 and SF 6 .
  • the reactive gas used in the plasma activation process 110 is O 2 , that is, the plasma activation process 110 is an oxygen plasma activation process.
  • the RF power of the plasma activation process 110 should not be too small or too large.
  • the radio frequency electric field generated by the radio frequency power source is used to accelerate the electrons, and cause each electron to collide with the reactive gas molecules to transfer the moving energy, thereby ionizing each reactive gas molecule to generate a plasma.
  • the reaction gas If the RF power is too small, it is difficult for the reaction gas to be plasmatized, which may cause problems such as insufficient plasma and poor plasma stability, which is not conducive to improving the first oxide layer 450 and the second oxide layer 250.
  • Surface activity resulting in a reduction in the number of dangling bonds on the surfaces of the first oxide layer 450 and the second oxide layer 250, and a corresponding decrease in the number of covalent bonds subsequently formed on the contact surfaces of the first oxide layer 450 and the second oxide layer 250 Further reducing the bonding strength between the first oxide layer 450 and the second oxide layer 250; if the radio frequency power is too large, the kinetic energy obtained after the reactive gas is plasmatized is likely to be too large, The bombardment effect on the first oxide layer 450 and the second oxide layer 250 is correspondingly too strong, so that the surfaces of the first oxide layer 450 and the second oxide layer 250 are easily damaged, so that the first oxide layer 450 is damaged.
  • the RF power of the plasma activation process 110 is 20W to 200W.
  • the process pressure of the plasma activation process 110 should not be too small or too large.
  • the process pressure affects the RF power.
  • the greater the process pressure the shorter the average free path of the plasma and the greater the probability of collisions between the plasmas, resulting in the plasma activation process 110. The effect becomes worse.
  • the required RF power is higher.
  • the process pressure is adjusted within a matching numerical range. Specifically, the process pressure is 0.1 mBar to 10 mBar.
  • the processing time of the plasma activation process 110 should not be too short or too long. If the processing time is too short, the activation effect on the surfaces of the first oxide layer 450 and the second oxide layer 250 is deteriorated correspondingly under the condition that the radio frequency power and the flow rate of the reaction gas are constant.
  • the number of covalent bonds formed on the contact surface between the oxide layer 450 and the second oxide layer 250 is correspondingly reduced, which results in a decrease in the bonding strength between the first oxide layer 450 and the second oxide layer 250; if the processing time passes, If it is long, it is easy to cause damage to the surfaces of the first oxide layer 450 and the second oxide layer 250, so that micro-defects are formed on the surfaces of the first oxide layer 450 and the second oxide layer 250, and if the processing time is too long, Excessive hydroxyl groups are generated.
  • the processing time of the plasma activation process 110 is 0.1 minutes to 10 minutes.
  • the RF power, process pressure, flow rate of reaction gas, and processing time of the plasma activation process 110 are set within a reasonable range and cooperate with each other, thereby improving the processing efficiency and stability and reducing the process. At the same time, the activation effect of the first oxide layer 450 and the second oxide layer 250 is improved.
  • the steps of the fusion bonding process further include: after the plasma activation process 110 (as shown in FIG. 5 and FIG. 6), according to the second chip 200 and the first chip A preset relative positional relationship of a chip 410, the second oxide layer 250 and the first oxide layer 450 are oppositely disposed and bonded, and a bonding pressure is applied to the device wafer 400 and the second chip 200 to perform pre-bonding. ⁇ ⁇ 120 ⁇ Processing 120.
  • the surfaces of the first oxide layer 450 and the second oxide layer 250 have more dangling bonds. Therefore, through the pre-bonding process 120, the first oxide layer 450 and The second oxide layer 250 realizes an interface chemical bond connection.
  • the second chip 200 corresponds to the corresponding one of the first chip 410, and
  • the projections of the second chip 200 and the first chip 410 on the first oxide layer 450 are staggered from each other, and the first back surface 402 of the device wafer 400 and the carrier substrate 100 face away from the second A bonding pressure is applied to the surface of the chip 200 to perform the pre-bonding process 120.
  • the bonding pressure of the pre-bonding process 120 is beneficial to improving the chemical bonding connection effect and strength at the interface between the first oxide layer 450 and the second oxide layer 250.
  • the bonding pressure If it is too large, the device wafer 400, the first oxide layer 450, the second oxide layer 250, and the second chip 200 are likely to cause adverse effects, such as deformation problems. For this reason, in this embodiment, in order to effectively realize the interface chemical bonding between the first oxide layer 450 and the second oxide layer 250 and reduce the process risk, the bonding pressure of the pre-bonding process 120 is 1 Newton to 20 Newton.
  • the processing time of the pre-bonding process 120 should not be too short or too long. Increasing the processing time of the pre-bonding process 120 is also conducive to improving the chemical bonding effect and strength of the contact surface between the first oxide layer 450 and the second oxide layer 250. Therefore, if the bonding pressure is constant, if If the processing time is too short, the problem of poor chemical bond connection at the interface between the first oxide layer 450 and the second oxide layer 250 is easily caused; if the processing time is too much, the process time will be wasted and the efficiency will be reduced. . For this reason, in this embodiment, in order to effectively realize the interface chemical bonding between the first oxide layer 450 and the second oxide layer 250 and improve the process efficiency, the processing time of the pre-bonding process 120 is 10 seconds to 60 seconds. second.
  • the steps of the fusion bonding process further include: after the pre-bonding process 120 (as shown in FIG. 7), the device wafer 400 and the second chip 200 Annealed.
  • a dehydration condensation reaction occurs between the hydroxyl groups on the contact surfaces of the first oxide layer 450 and the second oxide layer 250, so that the first oxide layer 450 and the second oxide layer 250 form Si-O. -Si covalent bond bonding; since the bonding energy of the silicon-oxygen bond is large, the bonding strength of the first oxide layer 450 and the second oxide layer 250 is improved.
  • the process temperature of the annealing treatment should not be too low or too high. If the process temperature is too low, it is easy to reduce the effect of the dehydration condensation reaction, which is not conducive to improving the bonding strength of the first oxide layer 450 and the second oxide layer 250; if the process temperature is too high, it is easy to form
  • the device performance in the device wafer 400 and the second chip 200 has an adverse effect, and the high-temperature resistance of the encapsulation layer 300 is generally poor, so it is easy to cause an adverse effect on the encapsulation layer 300. For this reason, in this embodiment, the process temperature of the annealing treatment is 200 ° C to 500 ° C.
  • the process temperature of the annealing process is relatively low, so it is also beneficial to reduce the influence of the annealing process on the performance of the devices formed in the device wafer 400 and the second chip 200, and the packaging layer 300. .
  • the process time of the annealing treatment should not be too low or too high. If the process time is too short, it is difficult to fully complete the dehydration condensation reaction, which is not conducive to improving the bonding strength of the first oxide layer 450 and the second oxide layer 250; if the process time is too long, it will instead As a result, the process time is wasted and the efficiency is reduced. Moreover, if the device wafer 400 and the second chip 200 are placed in an annealing environment for a long time, the process risk is correspondingly increased. For this reason, in this embodiment, the process time of the annealing treatment is 20 minutes to 200 minutes.
  • the process temperature and process time of the annealing process are set within a reasonable range and cooperate with each other, thereby increasing the bonding strength and reducing the probability of side effects.
  • the temperature resistance of the adhesive layer 150 is relatively low. Poor, at the process temperature of the annealing treatment, it is easy to cause the adhesion of the adhesive layer 150 to decrease, and the possibility of separation between the carrier wafer 100 and the second chip 200 is correspondingly high, and it is easy to The normal progress of the annealing process has an adverse effect.
  • the method further includes: The second chip 200 and the carrier wafer 100 are subjected to a debonding process, thereby removing the carrier wafer 100 and the adhesive layer 150.
  • the process of debonding treatment may be one or more of chemical etching, mechanical peeling, mechanical grinding, thermal baking, ultraviolet light irradiation, laser ablation, chemical mechanical polishing, and wet peeling, and according to the
  • the material of the adhesive layer 150 is selected from a suitable process.
  • the second chip and the carrier substrate may be debonded.
  • the method further includes: performing deionized water cleaning treatment on the surface of the first oxide layer 450 and the surface of the second oxide layer 250; after the pre-cleaning treatment of the deionized water, oxidizing the surface of the first oxide layer 450 and the second oxide The surface of the layer 250 is dried.
  • the surface quality of the first oxide layer 450 and the second oxide layer 250 is improved, so that the bonding between the first oxide layer 450 and the second oxide layer 250 is improved. strength.
  • the surfaces of the first oxide layer 450 and the second oxide layer 250 are rinsed with deionized water to complete the deionized water cleaning treatment; after the deionized water cleaning treatment, the N 2 The first oxide layer 450 and the second oxide layer 250 are described, thereby completing the drying process.
  • the method further includes: forming a third oxide layer on the encapsulation layer 300. 215.
  • the top of the third oxide layer 215 is aligned with the top of the second oxide layer 250, and the material of the third oxide layer 215 is the same as that of the second oxide layer 250.
  • the process of forming the encapsulation layer 300 includes a planarization process. After the planarization process, the encapsulation layer 300 is prone to the problem of poor surface flatness, which easily leads to the encapsulation layer 300 and the first oxidation. A gap is formed between the layers 450 (as shown in FIG. 7). Therefore, the third oxide layer 215 can effectively reduce the generation of gaps. The third oxide layer 215 and the first oxide layer 450 have a relatively small gap. Good fit, which is conducive to improving the performance of the obtained packaging structure.
  • the material of the third oxide layer 215 is the same as the material of the second oxide layer 250 and the first oxide layer 450. While improving process compatibility, during the low-temperature fusion bonding process, the The third oxide layer 215 can also be used as a part of the bonding layer, that is, the first oxide layer 450 can also be bonded with the third oxide layer 215 in a covalent bond manner.
  • the layer 215 is beneficial to further improve the bonding strength of the device wafer 400 and the second chip 200, thereby further improving the package yield of the wafer-level system package.
  • the third oxide layer 215 is formed by an atomic layer deposition process, and a material of the third oxide layer 215 is silicon oxide.
  • the third oxide layer may be hafnium oxide, aluminum oxide, or lanthanum oxide, and the process of forming the third oxide layer may be a low-pressure chemical vapor phase according to the material of the third oxide layer. Deposition process, metal organic chemical vapor deposition process, physical vapor deposition process or laser pulse deposition process.
  • the method further includes: performing a thinning process on the first back surface 402.
  • the first back surface 402 is thinned to reduce the thickness of the device wafer 400, thereby improving the heat dissipation effect of the device wafer 400, and facilitating the subsequent packaging process and reducing the post-packaging process.
  • the overall thickness of the obtained packaging structure thereby improving the performance of the packaging structure.
  • the thinning process may be one or more of a back grinding process, a chemical mechanical polishing (CMP) process, and a wet etching process.
  • CMP chemical mechanical polishing
  • a deep trench isolation for defining the stop position is usually formed in a semiconductor substrate of the device wafer 400 Structure so that the thinning process stops at the bottom of the isolation structure.
  • a neutrally doped ion such as one or two of oxygen ions and nitrogen ions
  • a neutrally doped ion such as one or two of oxygen ions and nitrogen ions
  • a stop region is formed in the substrate, so that the thinning process stops at the bottom of the stop region.
  • the semiconductor substrate of the device wafer is a silicon substrate on an insulator or a germanium substrate on an insulator
  • the bottom substrate layer of the semiconductor substrate may also be thinned, so that It can stop well on the bottom of the said insulator layer.
  • the thickness of the device wafer 400 should not be too small or too large. If the thickness of the device wafer 400 is too small, the mechanical performance of the device wafer 400 is correspondingly poor, and it is easy to adversely affect structures such as devices formed in the device wafer 400; if the device If the thickness of the wafer 400 is too large, it is not beneficial to improve the performance of the formed packaging structure. For this reason, in this embodiment, after the thinning process, the thickness of the device wafer 400 is 5 ⁇ m to 10 ⁇ m.
  • a first via structure 510 electrically connected to the first chip 410 and a second via 200 electrically connected to the second chip 200 are formed in the device wafer 400.
  • the first through-hole structure 510 and the second through-hole structure 520 are used to realize the electrical connection between the first chip 410 and the second chip 200 and other circuits, and the first chip 410 and the second chip 200. Electrical connection between.
  • the first via structure 510 and the second via structure 520 are TSV structures, that is, the first via structure 510 and the second via structure 520 pass through a through-silicon via (Through-Silicon Via, TSV) etch process and electroplating process.
  • TSV through-silicon via
  • the first through-hole structure 510 and the metal interconnection structure in the first chip 410 are electrically connected
  • the second through-hole structure 520 and the second pad 210 in the second chip 200 are electrically connected. Make electrical connections.
  • a material of the first through-hole structure 510 and the second through-hole structure 520 is copper.
  • the materials of the first through-hole structure and the second through-hole structure may also be conductive materials such as aluminum, tungsten, and titanium.
  • the present invention also provides a wafer-level packaging structure.
  • a schematic structural diagram of an embodiment of a wafer-level package structure of the present invention is shown.
  • the wafer-level package structure includes a device wafer 400 integrated with a first chip 410, and the device wafer 400 includes a first front surface 401 integrated with the first chip 410 and a phase opposite to the first front surface 401.
  • the packaging layer 300 exposes a surface of the second chip 210 facing away from the surface to be bonded.
  • the wafer-level package structure is a wafer-level system package structure, which can greatly reduce the advantages of the package structure, reduce manufacturing costs, optimize electrical performance, and batch manufacturing, and can significantly reduce Workload and equipment requirements.
  • the device wafer 400 is a completed wafer.
  • the device wafer 400 may include devices such as NMOS devices and PMOS devices on a semiconductor substrate, and may further include a dielectric layer on the devices, A metal interconnect structure and a structure such as a pad electrically connected to the metal interconnect junction. Therefore, at least one first chip 410 is integrated in the device wafer 400, and a first pad 420 is formed in the first chip 410.
  • the device wafer 400 includes a first front surface 401 integrated with the first chip 410 and a first back surface 402 opposite to the first front surface 401, and the first front surface 401 exposes the First pad 420.
  • the first back surface 402 refers to a bottom surface of the semiconductor substrate on the device wafer 400 side away from the first pad 420.
  • the thickness of the device wafer 400 is 5 ⁇ m to 10 ⁇ m.
  • the thickness of the device wafer 400 is small, so that the heat dissipation effect of the device wafer 400 can be improved, and the packaging process is facilitated, and the overall thickness of the packaging structure is reduced, thereby improving the performance of the packaging structure. .
  • the number of the second chips 200 is at least one, and the number of the second chips 200 is the same as the number of the first chips 410.
  • the second chip 200 may be one or more of an active element, a passive element, a micro-electro-mechanical system, and an optical element.
  • the second chip 200 may be a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip. In other embodiments, the second chip may also be another functional chip.
  • the number of the second chips 200 is multiple, and the multiple second chips 200 are obtained by cutting multiple wafers of different function types.
  • the function types of the multiple second chips may also be the same.
  • the second chip 200 corresponds to the next one on the corresponding first chip 410, and the second chip 200 and the first chip 410 are on the first oxide layer 450
  • the projections of each other are staggered.
  • the second chip 200 may be made by using integrated circuit manufacturing technology.
  • the second chip 200 also generally includes a device such as an NMOS device or a PMOS device formed on a semiconductor substrate, and further includes a dielectric layer on the device. , Metal interconnect structures and pads.
  • the second chip 200 includes a second front surface 201 on which a second pad 210 is formed, and a second back surface 202 opposite to the second front surface 201.
  • the second front surface 201 exposes the second solder. ⁇ 210 ⁇ The plate 210.
  • the second back surface 202 refers to a bottom surface of the semiconductor substrate on the side of the second chip 200 that is far from the second pad 210.
  • the surface to be bonded of the second chip 200 is the second front surface 201, that is, the second front surface 201 faces the device wafer 400; correspondingly, during the manufacturing process of the packaging structure It is beneficial to reduce the process difficulty of forming a via structure (such as a TSV structure), reduce the process cost, and also reduce the thickness of the via structure.
  • the surface to be bonded may also be the second back surface, that is, the second back surface faces the device wafer.
  • the second oxide layer 250 is connected to the first oxide layer 450 through a low-temperature fusion bonding process, and is used to implement a physical connection between the device wafer 400 and the second chip 200.
  • Melt bonding is a process that mainly uses interface chemical forces to complete bonding. Therefore, the first oxide layer 450 and the second oxide layer 250 have higher bonding strength, which is beneficial to improving the yield of the packaging structure.
  • a through-hole etching process is generally included, which etches the device wafer 400 and the second oxide layer 250 in this order.
  • 250 is an inorganic material
  • the material of the device wafer 400 is also an inorganic material. Therefore, compared with a solution using an organic adhesive layer (such as a sticky film) as a bonding layer, the second oxide layer 250 is used as a bond.
  • the combined layer solution is also beneficial to reduce the process difficulty of the through-hole etching process, and after the through-hole etching process, it can avoid the problem that the etching hole diameter in the second oxide layer 250 is too large, thereby It is beneficial to improve the electrical connection performance of the through-hole structure.
  • the steps of the fusion bonding process generally include an annealing process.
  • the second oxide layer 250 and the first oxide layer 450 are connected by a low temperature fusion bonding process, that is, the process temperature of the annealing process is relatively low. It is beneficial to reduce the influence of the annealing process on the performance of the devices formed in the device wafer 400 and the second chip 200.
  • the material of the second oxide layer 250 is the same as that of the first oxide layer 450, so that the covalent bond can be better achieved, which is beneficial to further improve the second oxide layer 250 and The bonding strength of the first oxide layer 450.
  • the material of the first oxide layer 450 is silicon oxide
  • the material of the second oxide layer 250 is silicon oxide.
  • the first oxide layer 450 and the second oxide layer 250 are combined by a covalent bond of Si-O-Si. Since the bond energy of the silicon-oxygen bond is large, the first oxide layer 450 is effectively improved. Bonding strength with the second oxide layer 250;
  • silicon oxide materials have high process compatibility, and silicon oxide is a commonly used process with low cost. Therefore, the selection of silicon oxide materials is beneficial to reduce the process. Difficulty and process cost, and help reduce the performance impact on the formed packaging structure.
  • the first oxide layer may be hafnium oxide, alumina, or lanthanum oxide
  • the second oxide layer may be hafnium oxide, alumina, or lanthanum oxide.
  • the thicknesses of the first oxide layer 450 and the second oxide layer 250 are equal.
  • the thicknesses of the first oxide layer 450 and the second oxide layer 250 should not be too small or too large. If the thickness is too small, it is easy to reduce the thickness uniformity and quality of the first oxide layer 450 and the second oxide layer 250; if the thickness is too large, the overall thickness of the packaging structure is excessively large. It is beneficial to the improvement of process integration, and also increases the difficulty of the via hole etching process and the thickness of the via structure during the manufacturing process of the package structure. For this reason, in this embodiment, the thickness of the first oxide layer 450 is 1000 ⁇ to 30,000 ⁇ , and the thickness of the second oxide layer 250 is 1000 ⁇ to 30,000 ⁇ .
  • the packaging layer 300 can also support the second chip 200 during the low-temperature fusion bonding process, thereby improving the process operability of the low-temperature fusion bonding process.
  • the process temperature of the annealing treatment in the low-temperature fusion bonding process is relatively low. Therefore, the low-temperature fusion bonding process has less influence on the packaging layer 300 and is beneficial to the quality and performance of the packaging layer 300 Guaranteed.
  • the process temperature of the annealing process is 200 ° C. to 500 ° C.
  • the encapsulation layer 300 covers the second chip 200 and can play a role of sealing and preventing moisture to protect the second chip 200, thereby reducing the probability of the second chip 200 being damaged, polluted, or oxidized. It is also beneficial to optimize the performance of the obtained packaging structure.
  • the material of the packaging layer 300 is epoxy resin.
  • Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost, so it is widely used as packaging materials for electronic devices and integrated circuits.
  • the material of the encapsulation layer may also be a thermosetting material such as polyimide or silicone.
  • the shape of the packaging layer 300 is a wafer shape, and the diameter of the wafer-shaped packaging layer 300 is the same as the diameter of the device wafer 400.
  • the encapsulation layer may have other suitable shapes.
  • the second chip 210 is usually pasted on a carrier substrate in a temporary bonding manner, and then the encapsulation layer is formed on the carrier substrate.
  • a process of forming the encapsulation layer 300 in order to achieve bonding between the first oxide layer 450 and the second oxide layer 250, a process of forming the encapsulation layer 300 generally includes a planarization process, so that the encapsulation layer 300 can expose the encapsulation layer 300.
  • the surface to be bonded of the second chip 210 is easy to cause a gap to be formed between the packaging layer 300 and the first oxide layer 450.
  • the packaging structure further includes a third oxide layer 215 located between the packaging layer 300 and the first oxide layer 450, and a material of the third oxide layer 215 and The materials of the second oxide layer 250 are the same.
  • the third oxide layer 215 can effectively reduce the generation of gaps, and the third oxide layer 215 and the first oxide layer 450 have a good degree of adhesion, which is beneficial to improving the obtained packaging structure.
  • the material of the third oxide layer 215 is the same as that of the second oxide layer 250 and the first oxide layer 450. While improving process compatibility, the third oxide layer 215 can also serve as a bond A part of the bonding layer, that is, the first oxide layer 450 can also be bonded with the third oxide layer 215 in a covalent bond manner. Therefore, the third oxide layer 215 is beneficial to further improve the The bonding strength of the device wafer 400 and the second chip 200 further improves the package yield of the wafer-level system package.
  • a material of the third oxide layer 215 is silicon oxide.
  • the third oxide layer may be hafnium oxide, aluminum oxide, or lanthanum oxide.
  • the packaging structure further includes: a first through-hole structure 510 located in the device wafer 400 and electrically connected to the first chip 410; a second through-hole structure 520 located in the The device wafer 400 is electrically connected to the second chip 200.
  • the first through-hole structure 510 and the second through-hole structure 520 are used to realize electrical connection between the first chip 410 and the second chip 200 and other circuits, and between the first chip 410 and the second chip 200. Electrical connection. Specifically, the first through-hole structure 510 and the metal interconnection structure in the first chip 410 are electrically connected, and the second through-hole structure 520 and the second pad 210 in the second chip 200 are electrically connected. Make electrical connections.
  • the first via structure 510 and the second via structure 520 are TSV structures, that is, the first via structure 510 and the second via structure 520 are processed through a TSV etching process and Formed by electroplating process.
  • the material of the first through-hole structure 510 and the second through-hole structure 520 is copper.
  • the materials of the first through-hole structure and the second through-hole structure may also be conductive materials such as aluminum, tungsten, and titanium.
  • the packaging structure described in this embodiment may be formed using the wafer-level packaging method described in the foregoing embodiment, or may be formed using other packaging methods.
  • the wafer-level package structure for a detailed description of the wafer-level package structure, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated in this embodiment.

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Abstract

一种晶圆级封装方法及封装结构，晶圆级封装方法包括：提供集成有第一芯片的器件晶圆，器件晶圆包括集成有第一芯片的第一正面以及与第一正面相背的第一背面；在第一正面形成第一氧化层；提供待集成的第二芯片，第二芯片具有待键合面；在待键合面上形成第二氧化层；将第二芯片背向第二氧化层的表面临时键合于承载基板上；在承载基板上形成露出第二氧化层顶部的封装层；通过第一氧化层和第二氧化层，采用低温熔融键合工艺实现器件晶圆和第二芯片的键合。一方面，封装层对第二芯片起到支撑作用，提高熔融键合工艺的可操作性；另一方面，通过低温熔融键合工艺，第一氧化层和第二氧化层实现键合且键合强度大，从而提高封装成品率。

Description

晶圆级封装方法及封装结构 技术领域
本发明实施例涉及半导体制造领域，尤其涉及一种晶圆级封装方法及封装结构。
 背景技术
随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，人们对集成电路的封装技术的要求相应也不断提高。现有的封装技术包括球栅阵列封装(Ball Grid Array，BGA)、芯片尺寸封装(Chip Scale Package，CSP)、晶圆级封装(Wafer Level Package ，WLP)、三维封装(3D) 和系统封装(System in Package，SiP)等。
目前，为了满足集成电路封装的更低成本、更可靠、更快及更高密度的目标，先进的封装方法主要采用晶圆级系统封装（Wafer Level Package System in Package，WLPSiP），与传统的系统封装相比，晶圆级系统封装是在晶圆上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
晶圆级系统封装主要包括物理连接和电性连接这两个重要工艺，通常采用有机键合层（例如粘片膜）实现所述器件晶圆和待集成芯片之间的物理连接，并通过通孔刻蚀工艺（例如硅通孔刻蚀工艺）和电镀技术实现半导体器件之间的电性连接。
 技术问题
本发明实施例解决的问题是提供一种晶圆级封装方法及封装结构，提高封装成品率。
 技术解决方案
为解决上述问题，本发明实施例提供一种晶圆级封装方法，包括：提供集成有第一芯片的器件晶圆，所述器件晶圆包括集成有所述第一芯片的第一正面以及与所述第一正面相背的第一背面；在所述第一正面形成第一氧化层；提供待集成的第二芯片，所述第二芯片具有待键合面；在所述待键合面上形成第二氧化层；提供承载基板；将所述第二芯片背向所述第二氧化层的表面临时键合于所述承载基板上；在所述承载基板上形成封装层，所述封装层露出所述第二氧化层的顶部；通过所述第一氧化层和所述第二氧化层，采用低温熔融键合工艺实现所述器件晶圆和第二芯片的键合。
相应的，本发明实施例还提供一种晶圆级封装结构，包括：集成有第一芯片的器件晶圆，所述器件晶圆包括集成有所述第一芯片的第一正面以及与所述第一正面相背的第一背面，所述第一正面具有第一氧化层；与所述器件晶圆相键合的第二芯片，所述第二芯片具有待键合面，所述待键合面上具有第二氧化层，且所述第二氧化层与所述第一氧化层通过低温熔融键合工艺连接；位于所述第一氧化层上的封装层，所述封装层露出所述第二芯片背向所述待键合面的表面。
 有益效果
本发明实施例在器件晶圆的第一正面形成第一氧化层、在待集成第二芯片的待键合面上形成第二氧化层，随后在形成封装层后，通过所述第一氧化层和所述第二氧化层，采用低温熔融键合工艺实现所述器件晶圆和第二芯片的键合；一方面，通过所述封装层，在后续所述低温熔融键合工艺中对所述第二芯片起到有效的支撑作用，提高所述低温熔融键合工艺的可操作性；另一方面，在所述低温熔融键合工艺过程中，所述第一氧化层和第二氧化层的表面活性得以提高，增加了所述第一氧化层和第二氧化层表面的悬挂键，从而在所述第一氧化层和第二氧化层的接触面形成共价键并以共价键结合的方式实现键合，且所述第一氧化层和第二氧化层之间具有较高的键合强度，进而提高了所述器件晶圆和第二芯片的键合强度，相应提高了封装成品率。
可选方案中，形成所述封装层后，在所述低温熔融键合工艺之前，还包括：在所述封装层上形成第三氧化层，所述第三氧化层的顶部与所述第二氧化层的顶部齐平；一方面，当所述封装层表面平坦度较差时，所述封装层与所述第一氧化层之间容易形成缝隙，因此通过所述第三氧化层，能有效减少缝隙的产生，所述第三氧化层与所述第一氧化层的贴合度较高；另一方面，在所述低温熔融键合工艺过程中，所述第一氧化层还能与所述第三氧化层以共价键结合的方式实现键合，因此通过所述第三氧化层，有利于进一步提高封装成品率。
 附图说明
图1至图10是本发明晶圆级封装方法一实施例中各步骤对应的结构示意图。
 本发明的实施方式
目前晶圆级封装工艺的封装成品率较低。分析其成品率较低的原因在于：
器件晶圆和待集成芯片通常通过胶粘层（例如粘片膜或干膜）实现物理连接，但胶粘层的耐温性较差，当后续制程工艺中的工艺温度较高时，所述胶粘层容易失效，从而降低所述胶粘层的粘附性，甚至出现所述器件晶圆和待集成芯片发生脱落的问题，从而严重影响晶圆级系统封装的封装成品率。
为了解决所述技术问题，本发明实施例提供一种晶圆级封装方法，包括：提供集成有第一芯片的器件晶圆，所述器件晶圆包括集成有所述第一芯片的第一正面以及与所述第一正面相背的第一背面；在所述第一正面形成第一氧化层；提供待集成的第二芯片，所述第二芯片具有待键合面；在所述待键合面上形成第二氧化层；提供承载基板；将所述第二芯片背向所述第二氧化层的表面临时键合于所述承载基板上；在所述承载基板上形成封装层，所述封装层露出所述第二氧化层的顶部；通过所述第一氧化层和所述第二氧化层，采用低温熔融键合工艺实现所述器件晶圆和第二芯片的键合。
本发明实施例通过封装层，在低温熔融键合工艺中对第二芯片起到有效的支撑作用，提高了低温熔融键合工艺的可操作性；另一方面，通过低温熔融键合工艺，在第一氧化层和第二氧化层的接触面形成共价键并以共价键结合的方式实现键合，且键合强度较高，从而显著提高了所述器件晶圆和第二芯片的键合强度，相应提高了封装成品率。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图10是本发明晶圆级封装方法一实施例中各步骤对应的结构示意图。
参考图1，提供集成有第一芯片410的器件晶圆（CMOS Wafer）400，所述器件晶圆400包括集成有所述第一芯片410的第一正面401以及与所述第一正面401相背的第一背面402。
本实施例中，所述晶圆级封装方法用于实现晶圆级系统封装，所述器件晶圆400用于在后续工艺中与待集成芯片进行键合。
所述器件晶圆400为完成器件制作的晶圆，所述器件晶圆400可以采用集成电路制作技术所制成，例如在半导体衬底上通过沉积、刻蚀等工艺形成NMOS器件和PMOS器件等器件，在所述器件上形成介质层、金属互连结构以及与所述金属互连结电连接的焊盘等结构，从而使所述器件晶圆400中集成有至少一个第一芯片410，且所述第一芯片410中形成有第一焊盘（Pad）420。
需要说明的是，当所述第一芯片410为多个时，所述多个第一芯片410可以为同一类型或不同类型的芯片。
还需要说明的是，为了便于图示，本实施例中，以所述器件晶圆400中集成有三个第一芯片410为例进行说明。但所述第一芯片410的数量不仅限于三个。
本实施例中，所述器件晶圆400的半导体衬底为硅衬底。在其他实施例中，所述半导体衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，所述半导体衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。所述半导体衬底的材料可以是适宜于工艺需要或易于集成的材料。
本实施例中，所述器件晶圆400包括集成有所述第一芯片410的第一正面401以及与所述第一正面401相背的第一背面402，所述第一正面401露出所述第一焊盘420。其中，所述第一焊盘420为所述器件晶圆400的引线焊盘（Bond Pad），所述第一焊盘420用于实现所述第一芯片410与其他电路之间的电性连接；所述第一背面402指的是所述器件晶圆400中远离所述第一焊盘420一侧的半导体衬底的底部表面。
本实施例中，根据实际工艺需求，所述器件晶圆400的厚度为10微米至100微米。
继续参考图1，在所述第一正面401形成第一氧化层450。
所述第一氧化层450作为后续熔融键合（Fusion Bonding）工艺的键合层，用于实现所述器件晶圆400与待集成芯片之间的物理连接。其中，在所述熔融键合工艺后，所述器件晶圆400与待集成芯片之间的键合层能以共价键的方式键合，从而有利于提高所述器件晶圆400与待集成芯片的键合强度。
本实施例中，所述第一氧化层450的材料为氧化硅。通过选取氧化硅材料，在后续熔融键合工艺过程中，能够使所述器件晶圆400与待集成芯片之间以Si-O-Si的共价键进行键合，由于硅氧键的键能较大，进而有利于进一步提高所述器件晶圆400与待集成芯片的键合强度；而且，氧化硅材料具有较高的工艺兼容性，氧化硅还为工艺常用、成本较低的材料，因此通过选取氧化硅材料的方式，有利于降低工艺难度和工艺成本，且有利于降低对所形成封装结构的性能影响。在其他实施例中，所述第一氧化层还可以为氧化铪、氧化铝或氧化镧。
具体地，采用原子层沉积（Atomic Layer Deposition，ALD）工艺形成所述第一氧化层450。原子层沉积工艺是指通过将气相前驱体脉冲交替地通入反应腔室内，在待沉积基体上化学吸附并发生表面反应的沉积工艺。通过原子层沉积工艺，所述第一氧化层450以原子层的形式形成于所述第一正面401，因此有利于提高沉积速率的均匀性、所述第一氧化层450的厚度均一性以及所述第一氧化层450中的结构均一性，且所述第一氧化层450具有良好的覆盖能力；而且，原子层沉积工艺的工艺温度通常较低，因此还有利于减小了热预算 (Thermal Budget)，降低晶圆变形(Wafer Distortion)、器件性能偏移的概率。
在其他实施例中，根据所述第一氧化层的材料，形成所述第一氧化层的工艺还可以为低压化学气相沉积（Low Pressure Chemical Vapor Deposition，LPCVD）工艺、金属有机化学气相沉积（Metal Organic Chemical Vapor Deposition，MOCVD）工艺、物理气相沉积（Physical Vapor Deposition，PVD）工艺或激光脉冲沉积（Pulsed Laser Deposition，PLD）工艺。
参考图2，提供待集成的第二芯片200，所述第二芯片200具有待键合面（未标示）。
所述第二芯片200用于作为晶圆级系统封装中的待集成芯片，所述第二芯片200的数量至少为一个，且所述第二芯片200的数量与第一芯片410（如图1所示）的数量相同。
所述第二芯片200可以为有源元件、无源元件、微机电系统、光学元件等元件中的一种或多种。具体地，所述第二芯片200可以为存储芯片、通讯芯片、处理芯片、闪存芯片或逻辑芯片。在其他实施例中，所述第二芯片还可以是其他功能芯片。
本实施例中，所述晶圆级系统封装用于将多个不同功能的多个第二芯片200组合到一个封装结构中，因此所述多个第二芯片200通过对不同功能类型的多个晶圆进行切割所获得。在其他实施例中，根据实际工艺需求，所述多个第二芯片的功能类型还可以相同。
通过将多个第二芯片200集成于所述器件晶圆400（如图1所示）中，并在所述器件晶圆400上完成封装集成制程，从而能够大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显降低工作量与设备需求。
需要说明的是，本实施例晶圆级封装方法用于实现异质集成，因此所述多个第二芯片200为硅晶圆制成的芯片。在其他实施例中，所述第二芯片也可以是其他材质形成的芯片。
还需要说明的是，为了便于图示，本实施例中，以所述第二芯片200的数量为三个为例进行说明。但所述第二芯片200的数量不仅限于三个。
所述第二芯片200可以采用集成电路制作技术所制成，所述第二芯片200通常也包括形成于半导体衬底上的NMOS器件或PMOS器件等器件，还包括介质层、金属互连结构和焊盘等结构。
本实施中，所述第二芯片200包括形成有第二焊盘210的第二正面201以及与所述第二正面201相背的第二背面202，所述第二正面201露出所述第二焊盘210。其中，所述第二焊盘210为引线焊盘，所述第二焊盘210用于实现所述第二芯片200与其他电路之间的电性连接；所述第二背面202指的是所述第二芯片200中远离所述第二焊盘210一侧的半导体衬底的底部表面。
本实施例中，所述第二芯片200的待键合面为所述第二正面201，即后续将所述第二正面201朝向所述器件晶圆400，从而在后续形成贯穿所述器件晶圆400且与所述第二芯片200电连接的通孔结构（例如硅通孔结构）时，有利于减小所述通孔结构的厚度，且有利于降低形成所述通孔结构的工艺难度，降低工艺成本。在其他实施例中，根据实际工艺需求，所述待键合面还可以为所述第二背面，即后续将所述第二背面朝向所述器件晶圆。
继续参考图2，在所述待键合面（未标示）上形成第二氧化层250。
所述第二氧化层250作为后续熔融键合工艺的键合层，用于实现所述器件晶圆400（如图1所示）和所述第二芯片200之间的物理连接，从而通过共价键结合的方式显著增加所述第二芯片200和所述器件晶圆400的键合强度。
而且，当后续形成贯穿所述器件晶圆400且与所述第二芯片200电连接的通孔结构时，形成所述通孔结构的工艺通常包括通孔刻蚀工艺（例如硅通孔刻蚀工艺），所述通孔刻蚀工艺依次刻蚀所述器件晶圆400和第二氧化层250，由于所述第二氧化层250为无机材料，而器件晶圆400的材料也为无机材料，因此与采用有机胶粘层（例如粘片膜）作为键合层的方案相比，通过采用所述第二氧化层250作为键合层的方案，还有利于降低后续通孔刻蚀工艺的工艺难度，而且在所述通孔刻蚀工艺后，能够避免所述第二氧化层250内刻蚀孔径过大的问题，从而有利于提高所述通孔结构的电连接性能。
本实施例中，所述第二氧化层250的材料与所述第一氧化层450的材料相同，从而在后续熔融键合工艺中较好地实现共价键的结合，有利于进一步提高所述第二氧化层250和第一氧化层450的键合强度。具体地，采用原子层沉积工艺形成所述第二氧化层250，所述第二氧化层250的材料为氧化硅。
在其他实施例中，所述第二氧化层还可以为氧化铪、氧化铝或氧化镧，且根据所述第二氧化层的材料，形成所述第二氧化层的工艺还可以为低压化学气相沉积工艺、金属有机化学气相沉积工艺、物理气相沉积工艺或激光脉冲沉积工艺。
对所述第二氧化层250的具体描述，可参考前述对所述第一氧化层450的相关描述，本实施例在此不再赘述。
本实施例中，所述第二芯片200的待键合面为所述第二正面201，相应的，所述第二氧化层250形成于所述第二正面201上。在其他实施例中，当所述待键合面为第二背面时，所述第二氧化层相应形成于所述第二背面上。
需要说明的是，所述多个第二芯片200通过对晶圆进行切割所获得，因此为了提高所述第二氧化层250的形成效率和形成质量，在集成有所述第二芯片200的晶圆上形成所述第二氧化层250后，对形成有所述第二氧化层250的晶圆进行切割，从而获得形成有所述第二氧化层250的第二芯片200。
继续参考图2，提供承载基板100；将所述第二芯片200背向所述第二氧化层250的表面临时键合于所述承载基板100上。
所述承载基板100用于对所述多个第二芯片200起到支撑作用，从而便于后续工艺的进行，提高后续工艺的可操作性，所述承载基板100还能够为后续的注塑成型（Molding）工艺提供工艺平台；而且通过临时键合（Temporary Bonding）的方式，还便于后续将所述第二芯片200和承载基板100进行分离。
本实施例中，所述承载基板100为载体晶圆（Carrier Wafer）。具体地，所述承载基板100可以半导体衬底（例如硅衬底）、有机玻璃晶圆、无机玻璃晶圆、树脂晶圆、半导体材料晶圆、氧化物晶体晶圆、陶瓷晶圆、金属晶圆、有机塑料晶圆、无机氧化物晶圆或陶瓷材料晶圆。
本实施例中，通过胶粘层150，将所述第二芯片200的第二背面202粘贴于所述承载基板100上。本实施例中，所述胶粘层150为粘片膜（Die Attach Film，DAF）。在其他实施例中，所述胶粘层还可以为干膜（Dry Film）、UV胶或热固胶。
在其他实施例中，当所述第二芯片的待键合面为所述第二背面时，相应通过所述胶粘层将所述第二芯片的第二正面粘贴于所述承载基板上。
参考图3，在所述承载基板100上形成覆盖所述第二芯片200侧壁的封装层300，所述封装层300露出所述第二氧化层250的顶部。
所述封装层300覆盖所述第二芯片200，在后续实现所述第二芯片200和器件晶圆400（如图1所示）的键合后，所述封装层300能够起到密封和防潮的作用，以保护所述第二芯片200，从而降低所述第二芯片200受损、被污染或被氧化的概率，进而有利于优化所获得封装结构的性能；而且，所述封装层300包覆所述多个第二芯片200，还能够对所述第二芯片200起到支撑作用，提高后续熔融键合工艺的可操作性，且有利于减小后续制程对所述第二芯片200的影响。
本实施例中，所述封装层300露出所述第二氧化层250的顶部，从而为后续实现所述第二氧化层250和第一氧化层450（如图1所示）的熔融键合工艺提供工艺基础。而且，在形成所述封装层300的步骤中，所述第二芯片200的待键合面（未标示）上形成有所述第二氧化层250，从而避免形成所述封装层300的工艺对所述待键合面产生影响，进而减小对所述待键合面和第二氧化层250之间结合强度的影响。
本实施例中，所述封装层300的材料为环氧树脂(Epoxy)。环氧树脂具有收缩率低、粘结性好、耐腐蚀性好、电性能优异及成本较低等优点，因此广泛用作电子器件和集成电路的封装材料。在其他实施例中，所述封装层的材料还可以为聚酰亚胺或硅胶等热固性材料。
本实施例中，通过注塑成型工艺，采用液体的塑封料或者固体的塑封料，形成所述封装层300，所述封装层300的形状为晶圆状，且所述晶圆状封装层300的直径与所述器件晶圆400的直径相同。在其他实施例中，所述封装层也可以为其它合适的形状。
具体地，采用热压注塑成型工艺，在所述承载基板100上形成覆盖所述第二芯片200的注塑膜；对所述注塑模进行平坦化处理，以露出所述第二氧化层250的顶部。
本实施例中，为了在后续工艺过程中，增加对所述第二芯片200的支撑作用，形成封装层300后，保留所述承载基板100，使所述承载基板100和封装层300共同对所述第二芯片200起到支撑作用。在其他实施例中，还可以在形成所述封装层后，对所述第二芯片和承载基板进行解键合（De-bonding）处理，以去除所述承载基板和胶粘层。
结合参考图4至图8，通过所述第一氧化层450和所述第二氧化层250，采用低温熔融键合工艺实现所述器件晶圆400和第二芯片200的键合。
熔融键合是一种主要利用界面化学力完成键合的工艺，在所述熔融键合工艺过程中，在所述第一氧化层450和第二氧化层250的接触面形成共价键并以共价键结合的方式实现键合，且所述第一氧化层450和第二氧化层250之间具有较高的键合强度，从而提高了所述器件晶圆400和第二芯片200的键合强度，且后续工艺对所述键合强度的影响较小，相应提高了晶圆级系统封装的封装成品率。而且，由于所述封装层300也暴露在所述熔融键合工艺的工艺环境中，因此通过采用低温熔融键合工艺的方式，合理降低熔融键合工艺中退火处理的工艺温度，从而减小所述熔融键合工艺对所述封装层300的影响。
具体地，结合参考图5和图6，所述熔融键合工艺的步骤包括：对所述第一氧化层450（如图5所示）表面和第二氧化层250（如图6所示）表面进行等离子体活化处理110。
一方面，通过等离子体活化处理110，使所述第一氧化层450和第二氧化层250表面的污染物和杂质等成为气态，并通过等离子系统的真空泵排出，从而起到去除污染物和杂质的作用，例如可以较好地去除金属污染和有机污染物。
另一方面，所述等离子体活化处理110的等离子体对所述第一氧化层450表面和第二氧化层250表面进行撞击，对不稳定的非桥接氧原子赋能，使所述氧原子离开原先成键的原子，所述等离子体活化处理110还会破坏所述第一氧化层450和第二氧化层250表面的碳氢化合物，增加羟基（O-H）在所述第一氧化层450和第二氧化层250表面的形成，从而提高了所述第一氧化层450和第二氧化层250的表面活性，在所述第一氧化层450和第二氧化层250表面形成较多的悬挂键，进而为后续在所述第一氧化层450和第二氧化层250的接触面形成共价键提供良好基础。其中，所述第一氧化层450和第二氧化层250表面的悬挂键越多，表面能越大，后续所形成的共价键数量相应越多，所述接触面以共价键方式键合的效果就越好。
本实施例中，所述第一氧化层450和第二氧化层250的材料为氧化硅，因此在所述等离子体活化处理110后，所述第一氧化层450和第二氧化层250表面悬挂有较多的硅醇（Si-OH）键。
所述等离子体活化处理110所采用的反应气体可以包括Ar、N 2、O 2和SF 6中的一种或多种。本实施例中，所述等离子体活化处理110所采用的反应气体为O 2，即所述等离子体活化处理110为氧等离子体活化处理。
其中，所述等离子体活化处理110的射频功率不宜过小，也不宜过大。在所述等离子体活化处理110的过程中，利用射频功率源产生的射频电场使电子加速，并使各个电子与反应气体分子发生碰撞而转移动能，从而使各个反应气体分子发生电离产生等离子体。
如果射频功率过小，则所述反应气体难以被等离子体化，相应容易引起等离子体不足、等离子体稳定性变差的问题，从而不利于提高所述第一氧化层450和第二氧化层250的表面活性，导致所述第一氧化层450和第二氧化层250表面的悬挂键减少，后续在所述第一氧化层450和第二氧化层250的接触面形成的共价键数量相应减少，进而导致所述第一氧化层450和第二氧化层250之间的键合强度降低；如果所述射频功率过大，则容易导致所述反应气体被等离子体化后获得的动能过大，对所述第一氧化层450和第二氧化层250的轰击作用相应过强，从而容易对所述第一氧化层450和第二氧化层250表面造成损伤，从而在所述第一氧化层450和第二氧化层250表面形成微缺陷（Micro-defect），在后续退火处理后容易产生退火空洞，反而容易降低后续所述第一氧化层450和第二氧化层250之间的键合强度，而且，射频功率过大还会消耗过多能量，从而导致工艺成本的增加。为此，本实施例中，所述等离子体活化处理110的射频功率为20W至200W。
所述等离子体活化处理110的工艺压强不宜过小，也不宜过大。所述工艺压强影响所述射频功率，所述工艺压强越大，则等离子体的平均自由程越短，所述等离子体之间发生碰撞的几率越大，从而导致所述等离子体活化处理110的效果变差，相应的，为了保证所述等离子体活化处理110的效果，所需射频功率则越高；此外，当所述工艺压强过小时，则容易降低所述等离子体的稳定性，相应的，抑制等离子体不稳定所需的射频功率越高。为此，本实施例中，根据所述等离子体活化处理110射频功率，将所述工艺压强调整至相匹配的数值范围内。具体地，所述工艺压强为0.1mBar至10mBar。
所述等离子体活化处理110的处理时间不宜过短，也不宜过长。如果所述处理时间过短，在射频功率和反应气体的流量一定的情况下，则对所述第一氧化层450和第二氧化层250表面的活化效果相应变差，后续在所述第一氧化层450和第二氧化层250的接触面形成的共价键数量相应减少，从而导致所述第一氧化层450和第二氧化层250之间的键合强度降低；如果所述处理时间过长，则容易对所述第一氧化层450和第二氧化层250表面造成损伤，从而在所述第一氧化层450和第二氧化层250表面形成微缺陷，而且，处理时间过长还会产生过量的羟基，在后续退火处理后，容易产生过量副产物（H 2O和H 2等），从而导致退火空洞的产生，反而容易降低后续所述第一氧化层450和第二氧化层250之间的键合强度，此外，工艺时间过大相应还会导致工艺成本的增加。为此，本实施例中，所述等离子体活化处理110的处理时间为0.1分钟至10分钟。
本实施例中，通过将所述等离子体活化处理110的射频功率、工艺压强、反应气体的流量以及处理时间设定在合理范围内，并相互配合，从而在提高处理效率和稳定性、降低工艺成本的同时，提高对所述第一氧化层450和第二氧化层250的活化效果。
结合参考图7，本实施例中，所述熔融键合工艺的步骤还包括：在所述等离子体活化处理110（如图5和图6所示）后，根据所述第二芯片200和第一芯片410的预设相对位置关系，将所述第二氧化层250和第一氧化层450相对设置并贴合，对所述器件晶圆400和第二芯片200施加键合压力，进行预键合处理120。
在所述等离子体活化处理110后，所述第一氧化层450和第二氧化层250表面具有较多的悬挂键，因此通过所述预键合处理120，使所述第一氧化层450和第二氧化层250实现界面化学键连接。
本实施例中，在所述等离子体活化处理110后，所述第一氧化层450和第二氧化层250表面悬挂较多的Si-OH键，因此将所述第二氧化层250和第一氧化层450相对设置并贴合后，所述第一氧化层450和第二氧化层250的接触面在范德华力的作用下桥接在一起。
具体地，根据实际工艺需求，将所述第二氧化层250和第一氧化层450相对设置并贴合后，所述第二芯片200与相对应的第一芯片410上下一一对应，且所述第二芯片200和第一芯片410在所述第一氧化层450上的投影相互错开，并对所述器件晶圆400的第一背面402、以及所述承载基板100背向所述第二芯片200的表面施加键合压力，以进行所述预键合处理120。
其中，通过对所述承载基板100施加键合压力的方式，有利于提高所述多个第二芯片200的受力均匀性，而且，与直接对所述第二芯片200施加键合压力的方案相比，有利于降低所述预键合处理120对所述第二芯片200造成的损伤。
需要说明的是，增加所述预键合处理120的键合压力，有利于提高所述第一氧化层450和第二氧化层250界面的化学键连接效果和强度，但是，如果所述键合压力过大，则反而容易对所述器件晶圆400、第一氧化层450、第二氧化层250和第二芯片200造成不良影响，例如产生变形的问题等。为此，本实施例中，为了使所述第一氧化层450和第二氧化层250有效实现界面化学键连接的同时，降低工艺风险，所述预键合处理120的键合压力为1牛顿至20牛顿。
还需要说明的是，所述预键合处理120的处理时间不宜过短，也不宜过长。增加所述预键合处理120的处理时间，也有利于提高所述第一氧化层450和第二氧化层250接触面的化学键连接效果和强度，因此在键合压力一定的情况下，若所述处理时间过短，则容易导致所述第一氧化层450和第二氧化层250界面的化学键连接效果不佳的问题；所述处理时间过多，反而会造成工艺时间的浪费、效率的下降。为此，本实施例中，为了使所述第一氧化层450和第二氧化层250有效实现界面化学键连接的同时，提高工艺效率，所述预键合处理120的处理时间为10秒至60秒。
结合参考图8，本实施例中，所述熔融键合工艺的步骤还包括：在所述预键合处理120（如图7所示）后，对所述器件晶圆400和第二芯片200进行退火处理。
通过所述退火处理，使所述第一氧化层450和第二氧化层250接触面的羟基之间发生脱水缩合反应，从而使所述第一氧化层450和第二氧化层250形成Si-O-Si的共价键结合；由于硅氧键的键能较大，进而提高了所述第一氧化层450和第二氧化层250的键合强度。
其中，所述退火处理的工艺温度不宜过低，也不宜过高。如果所述工艺温度过低，则容易降低脱水缩合反应的效果，不利于提高所述第一氧化层450和第二氧化层250的键合强度；如果所述工艺温度过高，则容易对形成于所述器件晶圆400和第二芯片200内的器件性能产生不良影响，而且，所述封装层300的耐高温性通常较差，因此还容易对所述封装层300造成不良影响。为此，本实施例中，所述退火处理的工艺温度为200℃至500℃。
本实施例中，所述退火处理的工艺温度较低，因此还有利于减小所述退火处理对形成于器件晶圆400和第二芯片200内的器件性能、以及所述封装层300的影响。
所述退火处理的工艺时间不宜过低，也不宜过高。如果所述工艺时间过短，则难以充分完成所述脱水缩合反应，从而不利于提高所述第一氧化层450和第二氧化层250的键合强度；如果所述工艺时间过长，反而会造成工艺时间浪费、效率降低的问题，而且，将所述器件晶圆400和第二芯片200长期置于退火环境中，工艺风险相应增加。为此，本实施例中，所述退火处理的工艺时间为20分钟至200分钟。
本实施例中，通过将所述退火处理的工艺温度和工艺时间设定在合理范围内，并相互配合，从而在提高键合强度的同时，降低产生副作用的概率。
需要说明的是，由于所述第二芯片200和承载基板上100之间通过所述胶粘层150（如图7所示）实现临时键合，而所述胶粘层150的耐温性较差，在所述退火处理的工艺温度下，容易导致所述胶粘层150的粘附性下降，所述载体晶圆100和第二芯片200之间发生分离的可能性相应较高，容易对所述退火处理的正常进行产生不良影响。
为此，本实施例中，为了保证工艺稳定性和安全性，在所述预键合处理120后，对所述器件晶圆400和第二芯片200进行所述退火处理之前，还包括：对所述第二芯片200和载体晶圆100进行解键合处理，从而去除所述载体晶圆100和胶粘层150。
具体地，所述解键合处理的工艺可以为化学腐蚀、机械剥离、机械研磨、热烘烤、紫外光照射、激光烧蚀、化学机械抛光以及湿法剥离中的一种或多种，并根据所述胶粘层150的材料选取相适宜的工艺。
在其他实施例中，根据实际工艺情况，也可以在完成所述低温熔融键合工艺之后，对所述第二芯片和承载基板进行解键合处理。
还需要说明的是，为了提高所述低温熔融键合工艺的键合强度，在所述等离子体活化处理110（如图5和图6所示）之后，进行所述预键合处理120之前，还包括：对所述第一氧化层450表面和第二氧化层250表面进行去离子水清洗处理；在所述去离子水预清洗处理后，对所述第一氧化层450表面和第二氧化层250表面进行干燥处理。
通过所述去离子水清洗处理和干燥处理，以提高所述第一氧化层450和第二氧化层250的表面质量，从而提高所述第一氧化层450和第二氧化层250的的键合强度。
具体地，采用去离子水冲洗所述第一氧化层450和第二氧化层250的表面，从而完成所述去离子水清洗处理；在所述去离子水清洗处理后，采用N 2吹干所述第一氧化层450和第二氧化层250，从而完成所述干燥处理。
此外，结合参考图4，形成所述封装层300后，在所述等离子体活化处理110（如图5和图6所示）之前，还包括：在所述封装层300上形成第三氧化层215，所述第三氧化层215的顶部与所述第二氧化层250的顶部齐，且所述第三氧化层215的材料与所述第二氧化层250的材料相同。
形成所述封装层300制程包括平坦化处理，在所述平坦化处理后，所述封装层300容易出现表面平坦度较差的问题，从而容易导致在所述封装层300与所述第一氧化层450（如图7所示）之间形成缝隙，因此通过所述第三氧化层215，能有效减少缝隙的产生，所述第三氧化层215与所述第一氧化层450之间具有较好的贴合度，从而有利于提高所获得封装结构的性能。
而且，所述第三氧化层215的材料与所述第二氧化层250、第一氧化层450的材料相同，在提高工艺兼容性的同时，在所述低温熔融键合工艺过程中，所述第三氧化层215也能作为键合层的一部分，即所述第一氧化层450还能与所述第三氧化层215以共价键结合的方式实现键合，因此通过所述第三氧化层215，有利于进一步提高所述器件晶圆400和第二芯片200的键合强度，从而进一步提高晶圆级系统封装的封装成品率。
本实施例中，采用原子层沉积工艺形成所述第三氧化层215，所述第三氧化层215的材料为氧化硅。在其他实施例中，所述第三氧化层还可以为氧化铪、氧化铝或氧化镧，且根据所述第三氧化层的材料，形成所述第三氧化层的工艺还可以为低压化学气相沉积工艺、金属有机化学气相沉积工艺、物理气相沉积工艺或激光脉冲沉积工艺。
对所述第三氧化层215的具体描述，可参考前述对所述第一氧化层450的相关描述，本实施例在此不再赘述。
结合参考图9，需要说明的时候，在所述熔融键合工艺后，还包括：对所述第一背面402进行减薄处理。
通过对所述第一背面402进行减薄处理，以减小所述器件晶圆400的厚度，从而改善所述器件晶圆400的散热效果，且有利于后续封装制程的进行、减小封装后所获得封装结构的整体厚度，从而提高所述封装结构的性能。
本实施例中，所述减薄处理所采用的工艺可以为背部研磨工艺、化学机械抛光(Chemical Mechanical Polishing，CMP)工艺和湿法刻蚀工艺中的一种或多种。
为了有效控制所述减薄处理的停止位置，在所述器件晶圆400的制造工艺中，通常在所述器件晶圆400的半导体衬底内形成用于限定所述停止位置的深沟槽隔离结构，从而使所述减薄处理停止于所述隔离结构的底部。
在另一实施例中，还可以在所述器件晶圆的制造工艺中，采用中性掺杂离子（例如氧离子和氮离子中的一种或两种）在所述器件晶圆400的半导体衬底内形成停止区，从而使所述减薄处理停止于所述停止区的底部。在其他实施例中，当所述器件晶圆的半导体衬底为绝缘体上的硅衬底或者绝缘体上的锗衬底时，还可以对所述半导体衬底的底部衬底层进行减薄处理，从而能够较好地停止于所述绝缘体层的底部。
需要说明的是，在所述减薄处理后，所述器件晶圆400的厚度不宜过小，也不宜过大。如果所述器件晶圆400的厚度过小，则所述器件晶圆400的机械性能相应较差，且容易对形成于所述器件晶圆400内的器件等结构产生不良影响；如果所述器件晶圆400的厚度过大，则不利于提高所形成封装结构的性能。为此，本实施例中，在所述减薄处理后，所述器件晶圆400的厚度为5μm至10μm。
结合参考图10，在所述减薄处理后，在所述器件晶圆400内形成与所述第一芯片410电连接的第一通孔结构510、以及与所述第二芯片200电连接的第二通孔结构520。
通过所述第一通孔结构510和第二通孔结构520，以实现所述第一芯片410和第二芯片200与其他电路的电性连接、以及所述第一芯片410和第二芯片200之间的电性连接。
本实施例中，所述第一通孔结构510和第二通孔结构520为硅通孔结构，即所述第一通孔结构510和第二通孔结构520通过硅通孔（Through-Silicon Via，TSV）刻蚀工艺和电镀工艺所形成。具体地，所述第一通孔结构510与所述第一芯片410内的金属互连结构实现电连接，所述第二通孔结构520与所述第二芯片200内的第二焊盘210实现电连接。
本实施例中，所述第一通孔结构510和第二通孔结构520的材料为铜。在其他实施例中，所述第一通孔结构和第二通孔结构的材料还可以为铝、钨和钛等导电材料。
相应的，本发明还提供一种晶圆级封装结构。继续参考图10，示出了本发明晶圆级封装结构一实施例的结构示意图。
所述晶圆级封装结构包括：集成有第一芯片410的器件晶圆400，所述器件晶圆400包括集成有所述第一芯片410的第一正面401以及与所述第一正面401相背的第一背面402，所述第一正面401具有第一氧化层450；与所述器件晶圆400相键合的第二芯片200，所述第二芯片200具有待键合面（未标示），所述待键合面上具有第二氧化层250，且所述第二氧化层250与所述第一氧化层450通过低温熔融键合工艺连接；位于所述第一氧化层450上的封装层300，所述封装层300露出所述第二芯片210背向所述待键合面的表面。
本实施例中，所述晶圆级封装结构为晶圆级系统封装结构，从而能够大幅减小所述封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
其中，所述器件晶圆400为完成器件制作的晶圆，所述器件晶圆400可以包括位于半导体衬底上的NMOS器件和PMOS器件等器件，还可以包括位于所述器件上的介质层、金属互连结构以及与所述金属互连结电连接的焊盘等结构。因此，所述器件晶圆400中集成有至少一个第一芯片410，且所述第一芯片410中形成有第一焊盘420。
本实施例中，所述器件晶圆400包括集成有所述第一芯片410的第一正面401以及与所述第一正面401相背的第一背面402，所述第一正面401露出所述第一焊盘420。其中，所述第一背面402指的是所述器件晶圆400中远离所述第一焊盘420一侧的半导体衬底的底部表面。
本实施例中，所述器件晶圆400的厚度为5μm至10μm。所述器件晶圆400的厚度较小，从而能够改善所述器件晶圆400的散热效果，且有利于封装制程的进行、减小所述封装结构的整体厚度，从而提高所述封装结构的性能。
对所述器件晶圆400的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
所述第二芯片200的数量至少为一个，且所述第二芯片200的数量与所述第一芯片410的数量相同。其中，所述第二芯片200可以为有源元件、无源元件、微机电系统、光学元件等元件中的一种或多种。具体地，所述第二芯片200可以为存储芯片、通讯芯片、处理芯片、闪存芯片或逻辑芯片。在其他实施例中，所述第二芯片还可以是其他功能芯片。
本实施例中，所述第二芯片200的数量为多个，所述多个第二芯片200通过对不同功能类型的多个晶圆进行切割所获得。在其他实施例中，根据实际工艺需求，所述多个第二芯片的功能类型还可以相同。
本实施例中，根据实际工艺需求，所述第二芯片200与相对应的第一芯片410上下一一对应，且所述第二芯片200和第一芯片410在所述第一氧化层450上的投影相互错开。
所述第二芯片200可以采用集成电路制作技术所制成，所述第二芯片200通常也包括形成于半导体衬底上的NMOS器件或PMOS器件等器件，还包括位于所述器件上的介质层、金属互连结构和焊盘等结构。
具体地，所述第二芯片200包括形成有第二焊盘210的第二正面201以及与所述第二正面201相背的第二背面202，所述第二正面201露出所述第二焊盘210。其中，所述第二背面202指的是所述第二芯片200中远离所述第二焊盘210一侧的半导体衬底的底部表面。
本实施例中，所述第二芯片200的待键合面为所述第二正面201，即所述第二正面201朝向所述器件晶圆400；相应的，在所述封装结构的制造过程中，有利于降低形成通孔结构（例如硅通孔结构）的工艺难度，降低工艺成本，且还有利于减小所述通孔结构的厚度。在其他实施例中，根据实际工艺需求，所述待键合面还可以为所述第二背面，即所述第二背面朝向所述器件晶圆。
对所述第二芯片200的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
所述第二氧化层250与所述第一氧化层450通过低温熔融键合工艺连接，用于实现所述器件晶圆400和所述第二芯片200之间的物理连接。
熔融键合是一种主要利用界面化学力完成键合的工艺，因此所述第一氧化层450和第二氧化层250具有较高的键合强度，有利于提高封装结构的成品率。
而且，在所述封装结构的制造过程中，通常包括通孔刻蚀工艺，所述通孔刻蚀工艺依次刻蚀所述器件晶圆400和第二氧化层250，由于所述第二氧化层250为无机材料，而器件晶圆400的材料也为无机材料，因此与采用有机胶粘层（例如粘片膜）作为键合层的方案相比，通过采用所述第二氧化层250作为键合层的方案，还有利于降低所述通孔刻蚀工艺的工艺难度，且在所述通孔刻蚀工艺后，能够避免所述第二氧化层250内刻蚀孔径过大的问题，从而有利于提高所述通孔结构的电连接性能。
此外，熔融键合工艺的步骤通常包括退火处理，本实施例所述第二氧化层250与所述第一氧化层450通过低温熔融键合工艺连接，即所述退火处理的工艺温度较低，有利于减小所述退火处理对形成于器件晶圆400和第二芯片200内的器件性能的影响。
本实施例中，所述第二氧化层250的材料与所述第一氧化层450的材料相同，从而能较好地实现共价键的结合，有利于进一步提高所述第二氧化层250和第一氧化层450的键合强度。
具体地，所述第一氧化层450的材料为氧化硅，所述第二氧化层250的材料为氧化硅。相应的，所述第一氧化层450和第二氧化层250通过Si-O-Si的共价键实现结合，由于硅氧键的键能较大，因此有效提高了所述第一氧化层450和第二氧化层250的键合强度；而且，氧化硅材料具有较高的工艺兼容性，且氧化硅为工艺常用、成本较低的材料，因此通过选取氧化硅材料的方式，有利于降低工艺难度和工艺成本，且有利于降低对所形成封装结构的性能影响。在其他实施例中，所述第一氧化层还可以为氧化铪、氧化铝或氧化镧，所述第二氧化层还可以为氧化铪、氧化铝或氧化镧。
本实施例中，为了降低工艺难度，所述第一氧化层450和第二氧化层250的厚度相等。但是，所述第一氧化层450和第二氧化层250的厚度不宜过小，也不宜过大。如果所述厚度过小，则容易降低所述第一氧化层450和第二氧化层250的厚度均一性和质量；如果所述厚度过大，相应导致所述封装结构的整体厚度过大，不利于工艺集成度的提高，而且还会在所述封装结构的制造过程中，增加通孔刻蚀工艺的难度以及通孔结构的厚度。为此，本实施例中，所述第一氧化层450的厚度为1000Å至30000Å，所述第二氧化层250的厚度为1000Å至30000Å。
本实施例中，在所述封装结构的形成过程中，在形成覆盖所述第二芯片200的封装层300之后，实现所述第一氧化层450和第二氧化层250的键合。因此所述封装层300还能在所述低温熔融键合工艺过程中对所述第二芯片200起到支撑作用，从而提高所述低温熔融键合工艺的工艺可操作性。
由前述分析可知，低温熔融键合工艺中退火处理的工艺温度较低，因此所述低温熔融键合工艺对所述封装层300的影响较小，有利于使所述封装层300的质量和性能得到保障。具体地，为了保障所述第二氧化层250与所述第一氧化层450的键合效果，且减小副作用的产生，所述退火处理的工艺温度为200℃至500℃。
所述封装层300覆盖所述第二芯片200，能够起到密封和防潮的作用，以保护所述第二芯片200，从而降低所述第二芯片200受损、被污染或被氧化的概率，进而有利于优化所获得封装结构的性能。
本实施例中，所述封装层300的材料为环氧树脂。环氧树脂具有收缩率低、粘结性好、耐腐蚀性好、电性能优异及成本较低等优点，因此广泛用作电子器件和集成电路的封装材料。在其他实施例中，所述封装层的材料还可以为聚酰亚胺或硅胶等热固性材料。
本实施例中，所述封装层300的形状为晶圆状，且所述晶圆状封装层300的直径与所述器件晶圆400的直径相同。在其他实施例中，所述封装层也可以为其它合适的形状。
需要说明的是，在形成所述封装层300的工艺过程中，通常是将所述第二芯片210以临时键合的方式粘贴于承载基板上，再在所述承载基板上形成所述封装层300，其中，为了使所述第一氧化层450和第二氧化层250实现键合，形成所述封装层300的工艺通常包括平坦化处理的制程，从而使所述封装层300能够露出所述第二芯片210的待键合面。但是，在所述平坦化处理后，所述封装层300容易出现表面平坦度较差的问题，从而容易导致在所述封装层300与所述第一氧化层450之间形成缝隙。
为此，本实施例中，所述封装结构还包括：第三氧化层215，位于所述封装层300和所述第一氧化层450之间，且所述第三氧化层215的材料与所述第二氧化层250的材料相同。
通过所述第三氧化层215，能有效减少缝隙的产生，所述第三氧化层215与所述第一氧化层450之间具有较好的贴合度，从而有利于提高所获得封装结构的性能；而且，所述第三氧化层215的材料与所述第二氧化层250、第一氧化层450的材料相同，在提高工艺兼容性的同时，所述第三氧化层215也能作为键合层的一部分，即所述第一氧化层450还能与所述第三氧化层215以共价键结合的方式实现键合，因此通过所述第三氧化层215，有利于进一步提高所述器件晶圆400和第二芯片200的键合强度，从而进一步提高晶圆级系统封装的封装成品率。
本实施例中，所述第三氧化层215的材料为氧化硅。在其他实施例中，所述第三氧化层还可以为氧化铪、氧化铝或氧化镧。
此外，本实施例中，所述封装结构还包括：第一通孔结构510，位于所述器件晶圆400内且与所述第一芯片410电连接；第二通孔结构520，位于所述器件晶圆400内且与所述第二芯片200电连接。
所述第一通孔结构510和第二通孔结构520用于实现所述第一芯片410和第二芯片200与其他电路的电性连接、以及所述第一芯片410和第二芯片200之间的电性连接。具体地，所述第一通孔结构510与所述第一芯片410内的金属互连结构实现电连接，所述第二通孔结构520与所述第二芯片200内的第二焊盘210实现电连接。
本实施例中，所述第一通孔结构510和第二通孔结构520为硅通孔结构，即所述第一通孔结构510和第二通孔结构520通过硅通孔刻蚀工艺和电镀工艺所形成。具体地，所述第一通孔结构510和第二通孔结构520的材料为铜。在其他实施例中，所述第一通孔结构和第二通孔结构的材料还可以为铝、钨和钛等导电材料。
本实施例所述封装结构可以采用前述实施例所述的晶圆级封装方法所形成，也可以采用其他封装方法所形成。本实施例中，对所述晶圆级封装结构的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (19)

  1. 一种晶圆级封装方法，其特征在于，包括：
    提供集成有第一芯片的器件晶圆，所述器件晶圆包括集成有所述第一芯片的第一正面以及与所述第一正面相背的第一背面；
    在所述第一正面形成第一氧化层；
    提供待集成的第二芯片，所述第二芯片具有待键合面；
    在所述待键合面上形成第二氧化层；
    提供承载基板；
    将所述第二芯片背向所述第二氧化层的表面临时键合于所述承载基板上；
    在所述承载基板上形成封装层，所述封装层露出所述第二氧化层的顶部；
    通过所述第一氧化层和所述第二氧化层，采用低温熔融键合工艺实现所述器件晶圆和第二芯片的键合。
  2. 如权利要求1所述的晶圆级封装方法，其特征在于，所述低温熔融键合工艺的步骤包括：对所述第一氧化层表面和第二氧化层表面依次进行等离子体活化处理、去离子水清洗处理和干燥处理；
    在所述干燥处理后，根据所述第二芯片和第一芯片的预设相对位置关系，将所述第二氧化层和第一氧化层相对设置并贴合，对所述器件晶圆和第二芯片施加键合压力，进行预键合处理；
    在所述预键合处理后，对所述器件晶圆和第二芯片进行退火处理。
  3. 如权利要求1所述的晶圆级封装方法，其特征在于，形成所述封装层后，在所述低温熔融键合工艺之前，还包括：在所述封装层上形成第三氧化层，所述第三氧化层的顶部与所述第二氧化层的顶部齐平，且所述第三氧化层和第二氧化层的材料相同。
  4. 如权利要求1或3所述的晶圆级封装方法，其特征在于，形成所述封装层后，在所述低温熔融键合工艺之前，还包括：对所述第二芯片和承载基板进行解键合处理。
  5. 如权利要求2所述的晶圆级封装方法，其特征在于，在所述预键合处理后，在退火处理之前，还包括：对所述第二芯片和承载基板进行解键合处理。
  6. 如权利要求1所述的晶圆级封装方法，其特征在于，在所述低温熔融键合工艺之后，还包括：对所述第二芯片和承载基板进行解键合处理。
  7. 如权利要求1所述的晶圆级封装方法，其特征在于，在所述低温熔融键合工艺后，还包括：对所述第一背面进行减薄处理。
  8. 如权利要求1或2所述的晶圆级封装方法，其特征在于，所述第一氧化层的材料为氧化硅、氧化铪、氧化铝或氧化镧，所述第二氧化层的材料为氧化硅、氧化铪、氧化铝或氧化镧，且所述第一氧化层和第二氧化层的材料相同。
  9. 如权利要求2所述的晶圆级封装方法，其特征在于，所述等离子体活化处理所采用的反应气体包括Ar、N 2、O 2和SF 6中的一种或多种。
  10. 如权利要求2所述的晶圆级封装方法，其特征在于，所述等离子体活化处理的参数包括：射频功率为20W至200W，工艺压强为0.1mBar至10mBar，处理时间为0.1分钟至10分钟。
  11. 如权利要求2所述的晶圆级封装方法，其特征在于，所述预键合处理的键合压力为1牛顿至20牛顿，处理时间为1秒至60秒。
  12. 如权利要求2所述的晶圆级封装方法，其特征在于，所述退火处理的工艺温度为200℃至500℃，工艺时间为20分钟至200分钟。
  13. 如权利要求1所述的晶圆级封装方法，其特征在于，形成所述第一氧化层和第二氧化层中任一个的工艺为原子层沉积工艺、低压化学气相沉积工艺、金属有机化学气相沉积、物理气相沉积工艺或激光脉冲沉积工艺。
  14. 如权利要求1所述的晶圆级封装方法，其特征在于，所述第二芯片包括形成有焊盘的第二正面以及与所述第二正面相背的第二背面；
    所述待键合面为所述第二正面或第二背面。
  15. 一种晶圆级封装结构，其特征在于，包括：
    集成有第一芯片的器件晶圆，所述器件晶圆包括集成有所述第一芯片的第一正面以及与所述第一正面相背的第一背面，所述第一正面具有第一氧化层；
    与所述器件晶圆相键合的第二芯片，所述第二芯片具有待键合面，所述待键合面上具有第二氧化层，且所述第二氧化层与所述第一氧化层通过低温熔融键合工艺连接；
    位于所述第一氧化层上的封装层，所述封装层露出所述第二芯片背向所述待键合面的表面。
  16. 如权利要求15所述的晶圆级封装结构，其特征在于，所述晶圆级封装结构还包括：第三氧化层，位于所述封装层和所述第一氧化层之间，且所述第三氧化层和第一氧化层的材料相同。
  17. 如权利要求15所述的晶圆级封装结构，其特征在于，所述第一氧化层的厚度为1000Å至30000Å，所述第二氧化层的厚度为1000Å至30000Å。
  18. 如权利要求15所述的晶圆级封装结构，其特征在于，所述第一氧化层的材料为氧化硅、氧化铪、氧化铝或氧化镧，所述第二氧化层的材料为氧化硅、氧化铪、氧化铝或氧化镧，且所述第一氧化层和第二氧化层的材料相同。
  19. 如权利要求15所述的晶圆级封装结构，其特征在于，所述第二芯片包括形成有焊盘的第二正面以及与所述第二正面相背的第二背面；
    所述待键合面为所述第二正面或第二背面。
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