WO2020047973A1 - 晶圆级封装方法及封装结构 - Google Patents

晶圆级封装方法及封装结构 Download PDF

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Publication number
WO2020047973A1
WO2020047973A1 PCT/CN2018/113103 CN2018113103W WO2020047973A1 WO 2020047973 A1 WO2020047973 A1 WO 2020047973A1 CN 2018113103 W CN2018113103 W CN 2018113103W WO 2020047973 A1 WO2020047973 A1 WO 2020047973A1
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Prior art keywords
chip
oxide layer
wafer
bonded
oxide
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PCT/CN2018/113103
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English (en)
French (fr)
Inventor
罗海龙
德劳利·克里夫
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中芯集成电路（宁波）有限公司
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Application filed by 中芯集成电路（宁波）有限公司 filed Critical 中芯集成电路（宁波）有限公司
Priority to JP2021511562A priority Critical patent/JP2021535613A/ja
Priority to KR1020217006437A priority patent/KR20210039443A/ko
Priority to US16/231,733 priority patent/US10790211B2/en
Publication of WO2020047973A1 publication Critical patent/WO2020047973A1/zh
Priority to US17/011,493 priority patent/US11450582B2/en

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Definitions

  • Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a wafer-level packaging method and a packaging structure.
  • wafer-level system packaging is a package integration process completed on the wafer, which has the advantages of greatly reducing the area of the packaging structure, reducing manufacturing costs, optimizing electrical performance, and batch manufacturing, which can significantly reduce workload and equipment. Demand.
  • Wafer-level system packaging mainly includes two important processes: physical connection and electrical connection.
  • organic bonding layers such as adhesive films
  • Hole etching processes such as through-silicon via etching processes
  • electroplating techniques achieve electrical connections between semiconductor devices.
  • the problem solved by the embodiments of the present invention is to provide a wafer-level packaging method and a packaging structure to improve packaging yield.
  • an embodiment of the present invention provides a wafer-level packaging method, including: providing a device wafer integrated with a first chip, the device wafer including a first front surface integrated with the first chip, and Forming a first oxide layer on the first front surface; providing a second chip to be integrated, the second chip having a surface to be bonded; on the surface to be bonded Forming a second oxide layer thereon; providing a carrier substrate; temporarily bonding the surface of the second chip facing away from the surface to be bonded to the carrier substrate; backing the second chip toward the to-be-bonded surface After the surface of the surface is temporarily bonded to the carrier substrate, the second oxide layer and the first oxide layer are used to realize the bonding of the second chip and the device wafer by a fusion bonding process; After the second chip and the device wafer are bonded, a debonding process is performed on the second chip and the carrier wafer; after the debonding process, a second layer is formed on the first oxide layer to cover the second chip. Encapsulation layer.
  • the steps of the fusion bonding process include: sequentially performing plasma activation treatment, deionized water cleaning treatment, and drying treatment on the first oxide layer surface and the second oxide layer surface; after the drying treatment, And, according to a preset relative position relationship between the second chip and the first chip, the second oxide layer and the first oxide layer are oppositely disposed and bonded, and a bonding pressure is applied to the device wafer and the second chip.
  • Performing a pre-bonding process after the pre-bonding process, annealing treatment is performed on the device wafer and the second chip.
  • the surface of the second chip facing away from the surface to be bonded is temporarily bonded to the carrier substrate; or After the surface of the second chip facing away from the surface to be bonded is temporarily bonded to the carrier substrate, the second oxide layer is formed on the surface to be bonded.
  • the method further includes: performing a thinning process on the first back surface; and after the thinning process, forming an electrical connection with the first chip in the device wafer.
  • the material of the first oxide layer is silicon oxide, hafnium oxide, aluminum oxide, or lanthanum oxide
  • the material of the second oxide layer is silicon oxide, hafnium oxide, aluminum oxide, or lanthanum oxide
  • the first The material of the first oxide layer and the second oxide layer is the same.
  • the reactive gas used in the plasma activation process includes one or more of Ar, N 2 , O 2 and SF 6 .
  • the parameters of the plasma activation treatment include: RF power is 20W to 200W, process pressure is 0.1mBar to 10mBar, and processing time is 0.1 minute to 10 minutes.
  • the bonding pressure of the pre-bonding process is 1 Newton to 20 Newtons, and the processing time is 1 second to 60 seconds.
  • a process temperature of the annealing process is 200 ° C to 500 ° C, and a process time is 20 minutes to 200 minutes.
  • a process of forming any one of the first oxide layer and the second oxide layer is an atomic layer deposition process, a low-pressure chemical vapor deposition process, a metal organic chemical vapor deposition process, a physical vapor deposition process, or a laser pulse deposition process.
  • the surface of the second chip facing away from the surface to be bonded is temporarily bonded to the carrier substrate through an adhesive layer or electrostatic bonding.
  • the second chip includes a second front surface having a pad formed thereon and a second back surface opposite to the second front surface; and the surface to be bonded is the second front surface or the second back surface.
  • the present invention also provides a wafer-level package structure, including: a device wafer integrated with a first chip, the device wafer including a first front surface integrated with the first chip, and A first back surface opposite to the front side, the first front surface is formed with a first oxide layer; a second chip bonded to the device wafer, the second chip has a surface to be bonded, and the to-be-bonded surface A second oxide layer is formed on the surface, and the second oxide layer and the first oxide layer are connected by a fusion bonding process; a packaging layer is located on the first oxide layer and covers the second chip.
  • the wafer-level packaging structure further includes: a first interconnect structure located in the device wafer and electrically connected to the first chip; a second interconnect structure located in the device wafer And is electrically connected to the second chip.
  • the material of the first oxide layer is silicon oxide, hafnium oxide, aluminum oxide, or lanthanum oxide
  • the material of the second oxide layer is silicon oxide, hafnium oxide, aluminum oxide, or lanthanum oxide
  • the first The material of the first oxide layer and the second oxide layer is the same.
  • the thickness of the first oxide layer is 1000 ⁇ to 30,000 ⁇
  • the thickness of the second oxide layer is 1000 ⁇ to 30,000 ⁇ .
  • the second chip includes a second front surface having a pad formed thereon and a second back surface opposite to the second front surface; and the surface to be bonded is the second front surface or the second back surface.
  • a first oxide layer is formed on a first front surface of a device wafer, a second oxide layer is formed on a bonding surface to be integrated with a second chip, and then the second oxide layer and the first oxide are passed through Layer, using a fusion bonding process to achieve the bonding of the second chip and the device wafer; during the fusion bonding process, the contact surfaces of the first oxide layer and the second oxide layer can be covalently bonded Bonding is achieved in a combined manner, so that the first silicon oxide layer and the second silicon dioxide layer have a higher bonding strength, which improves the reliability of the bonding process, thereby improving the device wafer and the first silicon oxide layer.
  • the bonding strength of the two chips improves the package yield accordingly.
  • the method further includes forming a connection with the first chip in the device wafer.
  • the second oxide layer is an inorganic material and the material of the device wafer is also an inorganic material
  • the solution that the oxide layer is used as the bonding layer is also beneficial to reduce the process difficulty of the subsequent through-hole etching process, thereby improving the electrical connection performance of the second interconnect structure.
  • FIGS. 1 to 9 are schematic structural diagrams corresponding to steps in an embodiment of a wafer-level packaging method according to the present invention.
  • the device wafer and the chip to be integrated are usually physically connected through an adhesive layer (such as an adhesive film or a dry film), but the temperature resistance of the adhesive layer is poor.
  • an adhesive layer such as an adhesive film or a dry film
  • the process temperature in the subsequent process is too high, The adhesive layer is prone to failure, thereby reducing the adhesion of the adhesive layer, and even the problem of the device wafer and the chip to be integrated peeling off, which seriously affects the package yield of the wafer-level system package.
  • an embodiment of the present invention provides a wafer-level packaging method, including: providing a device wafer integrated with a first chip, the device wafer including a first front surface integrated with the first chip And a first back surface opposite to the first front surface; forming a first oxide layer on the first front surface; providing a second chip to be integrated, the second chip having a surface to be bonded; Forming a second oxide layer on the bonding surface; providing a carrier substrate; temporarily bonding the surface of the second chip facing away from the surface to be bonded to the carrier substrate; backing the second chip toward the waiting surface After the surface of the bonding surface is temporarily bonded to the carrier substrate, the second oxide layer and the first oxide layer are used to realize the bonding of the second chip and the device wafer through a fusion bonding process; After the bonding of the second chip and the device wafer is achieved, a debonding process is performed on the second chip and the carrier wafer; after the debonding process, a second covering layer is formed on the first oxide layer
  • a first oxide layer is formed on a first front surface of a device wafer, a second oxide layer is formed on a bonding surface to be integrated with a second chip, and then the second oxide layer and the first oxide are passed through Layer, using a fusion bonding process to achieve the bonding of the second chip and the device wafer; during the fusion bonding process, the contact surfaces of the first oxide layer and the second oxide layer can be covalently bonded Bonding is achieved in a combined manner, so that the first silicon oxide layer and the second silicon dioxide layer have a higher bonding strength, which improves the reliability of the bonding process, thereby improving the device wafer and the first silicon oxide layer.
  • the bonding strength of the two chips improves the package yield accordingly.
  • FIGS. 1 to 9 are schematic structural diagrams corresponding to steps in an embodiment of a wafer-level packaging method according to the present invention.
  • CMOS Wafer 300 integrated with a first chip 310 is provided.
  • the device wafer 300 includes a first front surface 301 integrated with the first chip 310 and a phase opposite to the first front surface 301.
  • the wafer-level packaging method is used to implement wafer-level system packaging, and the device wafer 300 is used to bond with a chip to be integrated in a subsequent process.
  • the device wafer 300 is a wafer for completing device fabrication.
  • the device wafer 300 may be manufactured using integrated circuit fabrication technology, for example, an N-type metal oxide semiconductor is formed on a semiconductor substrate by processes such as deposition and etching. (N-Metal-Oxide-Semiconductor, NMOS) devices and P-type metal oxide semiconductor (P-Metal-Oxide-Semiconductor, PMOS) devices, etc., on which a dielectric layer, a metal interconnect structure, and The structures such as pads electrically connected to the metal interconnection are described, so that at least one first chip 310 is integrated in the device wafer 300, and a first pad 320 is formed in the first chip 310.
  • N-Metal-Oxide-Semiconductor, NMOS N-Metal-Oxide-Semiconductor
  • PMOS P-type metal oxide semiconductor
  • the multiple first chips 310 may be the same type or different types of chips.
  • the semiconductor substrate of the device wafer 300 is a silicon substrate.
  • the material of the semiconductor substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.
  • the semiconductor substrate may also be a silicon substrate on an insulator. Or another type of substrate such as a germanium substrate on an insulator.
  • the material of the semiconductor substrate may be a material suitable for process requirements or easily integrated.
  • the device wafer 300 includes a first front surface 301 integrated with the first chip 310 and a first back surface 302 opposite to the first front surface 301, and the first front surface 301 exposes the first First pad 320.
  • the first pad 320 is a bond pad of the device wafer 300, and the first pad 320 is used to implement electrical connection between the first chip 310 and other circuits.
  • the first back surface 302 refers to a bottom surface of the semiconductor substrate on the device wafer 300 side away from the first pad 320.
  • the thickness T1 of the device wafer 300 is 10 ⁇ m to 100 ⁇ m.
  • a first oxide layer 350 is formed on the first front surface 301.
  • the first oxide layer 350 is used as a bonding layer in a subsequent fusion bonding process, and is used to implement a physical connection between the device wafer 300 and a chip to be bonded. Wherein, after the fusion bonding process, the bonding strength between the device wafer 300 and the chip to be integrated is high.
  • a material of the first oxide layer 350 is silicon oxide.
  • the silicon oxide material By selecting the silicon oxide material, during the subsequent fusion bonding process, the device wafer 300 and the chip to be integrated can be bonded by a covalent bond of Si-O-Si. It can be larger, which is beneficial to further improve the bonding strength between the device wafer 300 and the chip to be integrated; moreover, silicon oxide material has high process compatibility, and silicon oxide is also a commonly used material with low cost. Therefore, by selecting the silicon oxide material, it is beneficial to reduce the difficulty and cost of the process, and to reduce the performance impact on the formed packaging structure.
  • the first oxide layer may be hafnium oxide, aluminum oxide, or lanthanum oxide.
  • the first oxide layer 350 is formed by an atomic layer deposition (ALD) process.
  • the atomic layer deposition process refers to a deposition process in which a gas phase precursor pulse is alternately passed into a reaction chamber to chemically adsorb on a substrate to be deposited and a surface reaction occurs.
  • the first oxide layer 350 is formed on the first front surface 301 in the form of an atomic layer, so it is beneficial to improve the uniformity of the deposition rate, the thickness uniformity of the first oxide layer 350, and the The structure uniformity in the first oxide layer 350 is good, and the first oxide layer 350 has a good covering ability; moreover, the process temperature of the atomic layer deposition process is usually lower, so it is also beneficial to reduce the thermal budget. Budget) to reduce the probability of wafer distortion (Wafer Distortion) and device performance deviation.
  • ALD atomic layer deposition
  • the process of forming the first oxide layer may further be a Low Pressure Chemical Vapor Deposition (LPCVD) process, a metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition (MOCVD) process, Physical Vapor Deposition (PVD) process or laser pulse deposition (Pulsed Laser Deposition (PLD) process.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • MOCVD Metal Organic Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • PLD Pulsed Laser Deposition
  • a second chip 200 to be integrated is provided, and the second chip 200 has a surface to be bonded (not labeled).
  • the second chip 200 is used as a chip to be integrated in a wafer-level system package.
  • the number of the second chip 200 is at least one, and the number of the second chip 200 is the same as that of the first chip 410 (such as (Shown in Figure 1).
  • the second chip 200 may be one or more of an active element, a passive element, a micro-electro-mechanical system, and an optical element.
  • the second chip 200 may be a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip. In other embodiments, the second chip may also be another functional chip.
  • the wafer-level system package is used to combine multiple second chips 200 with different functions into a package structure. Wafer obtained by dicing. In other embodiments, according to actual process requirements, the function types of the multiple second chips may also be the same.
  • the area of the package structure can be greatly reduced, and The advantages of manufacturing cost, optimized electrical performance, and batch manufacturing can significantly reduce workload and equipment requirements.
  • the wafer-level packaging method of this embodiment is used to implement heterogeneous integration, so the plurality of second chips 200 are chips made of silicon wafers.
  • the second chip may be a chip made of other materials.
  • the number of the second chips 200 is three as an example for description. However, the number of the second chips 200 is not limited to three.
  • the second chip 200 may be manufactured by using integrated circuit manufacturing technology.
  • the second chip 200 also generally includes a device such as an NMOS device or a PMOS device formed on a semiconductor substrate, and further includes a dielectric layer, a metal interconnect structure, and Pads and other structures.
  • the second chip 200 includes a second front surface 201 on which a second pad 210 is formed, and a second back surface 202 opposite to the second front surface 201, and the second front surface 201 exposes the first Two pads 210.
  • the second pad 210 is a lead pad, and the second pad 210 is used to achieve electrical connection between the second chip 200 and other circuits; the second back surface 202 refers to all The bottom surface of the semiconductor substrate on the side of the second chip 200 remote from the second pad 210.
  • the surface to be bonded of the second chip 200 is the second front surface 201, that is, the second front surface 201 is subsequently directed toward the device wafer 300, and when the subsequent formation is performed through the device wafer 300 and an interconnect structure (such as a through-silicon via interconnect structure) that is electrically connected to the second chip 200 is beneficial to reducing the thickness of the interconnect structure and reducing the process of forming the interconnect structure Difficulty and reduce process costs.
  • the surface to be bonded may also be the second back surface, that is, the second back surface is subsequently directed toward the device wafer.
  • a second oxide layer 250 is formed on the surface to be bonded (not labeled).
  • the second oxide layer 250 is used as a bonding layer in a subsequent fusion bonding process, and is used to implement a physical connection between the device wafer 300 and the second chip 200, thereby improving the second chip 200 and the second chip 200.
  • the bonding strength of the device wafer 300 is described.
  • the process of forming the interconnect structure generally includes a via-hole etching process, and the via-hole etching
  • the process etches the device wafer 300 and the second oxide layer 250 in sequence. Since the second oxide layer 250 is an inorganic material, and the material of the device wafer 300 is also an inorganic material, the organic adhesive layer is used as a bond. Compared with the solution of the bonding layer, by adopting the solution of the second oxide layer 250 as the bonding layer, it is also beneficial to reduce the technical difficulty of the subsequent through-hole etching process, and can be avoided after the through-hole etching process. The problem that the etched hole diameter in the second oxide layer 250 is too large is beneficial to improving the electrical connection performance of the via structure.
  • the material of the second oxide layer 250 is the same as the material of the first oxide layer 350, which is beneficial to further improve the bonding strength between the second oxide layer 250 and the first oxide layer 350.
  • the second oxide layer 250 is formed by an atomic layer deposition process, and a material of the second oxide layer 250 is silicon oxide.
  • the second oxide layer may also be hafnium oxide, alumina, or lanthanum oxide, and according to the material of the second oxide layer, the process of forming the second oxide layer may be a low-pressure chemical vapor phase. Deposition process, metal organic chemical vapor deposition process, physical vapor deposition process or laser pulse deposition process.
  • the surface to be bonded of the second chip 200 is the second front surface 201.
  • the second oxide layer 250 is formed on the second front surface 201.
  • the second oxide layer is correspondingly formed on the second back surface.
  • the plurality of second chips 200 are obtained by dicing a wafer. Therefore, in order to improve the formation efficiency and the quality of the second oxide layer 250, the crystals of the second chip 200 are integrated. After the second oxide layer 250 is formed on a circle, the wafer on which the second oxide layer 250 is formed is cut to obtain a second chip 200 on which the second oxide layer 250 is formed.
  • a carrier substrate 100 is provided; a surface of the second chip 200 facing away from the surface to be bonded (not labeled) is temporarily bonded to the carrier substrate 100.
  • the carrier substrate 100 is used to support the plurality of second chips 200, thereby facilitating the subsequent processes and improving the operability of the subsequent processes; and by means of temporary bonding, it is also convenient
  • the second chip 200 and the carrier substrate 100 are subsequently separated.
  • the carrier substrate 100 is a carrier wafer.
  • the carrier substrate 100 may be a semiconductor substrate (such as a silicon substrate), an organic glass wafer, an inorganic glass wafer, a resin wafer, a semiconductor material wafer, an oxide crystal wafer, a ceramic wafer, or a metal. Wafer, organic plastic wafer, inorganic oxide wafer or ceramic material wafer.
  • an adhesive layer 150 is formed on the carrier substrate 100, and a surface of the second chip 200 facing away from the surface to be bonded is temporarily bonded to the carrier substrate 100 through the adhesive layer 150. on.
  • the adhesive layer 150 is a sticky film (Die Attach Film (DAF) and Dry Film (Dry Film).
  • DAF Die Attach Film
  • Dry Film Dry Film
  • dry film is a kind of photoresist film with adhesiveness used in semiconductor chip packaging or printed circuit board manufacturing.
  • Dry film photoresist is manufactured by coating solvent-free photoresist on polyester The film base is covered with a polyethylene film; when in use, the polyethylene film is peeled off, the solvent-free photoresist is pressed onto the base plate, and after exposure and development treatment, it can be contained in the dry film photoresist. Form a figure.
  • Adhesive film is an ultra-thin film adhesive used to connect semiconductor chips and package substrates, chips and chips in the semiconductor packaging process. It has high reliability and convenient processability, which is conducive to the lamination of semiconductor packages. And thin. .
  • the surface of the second chip 200 facing away from the surface to be bonded may also be temporarily bonded to the carrier substrate by electrostatic bonding.
  • Electrostatic bonding technology is a method to achieve bonding without any adhesive.
  • the second chip to be bonded and the carrier substrate are respectively connected to different electrodes, and the second chip and the carrier are connected under a voltage.
  • a charge is formed on the surface of the substrate, and the charges on the surface of the second chip and the carrier substrate are electrically different, so that a larger electrostatic attraction force is generated during the bonding process between the second chip and the carrier substrate, and the physical connection between the two is achieved.
  • the surface to be bonded of the second chip 200 is the second front surface 201. Accordingly, the second back surface 202 of the second chip 200 is temporarily bonded to the second chip 200 through the adhesive layer 150. On the carrier substrate 100. In other embodiments, when the surface to be bonded of the second chip is a second back surface, the second front surface of the second chip is temporarily bonded to the carrier substrate through the adhesive layer.
  • the surface of the second chip 200 facing away from the surface to be bonded is temporarily bonded to the surface of the second chip 200.
  • the carrier substrate 100 is described above, which is helpful to simplify the process difficulty of forming the second oxide layer 250.
  • the surface of the second chip facing away from the surface to be bonded may be temporarily bonded to the carrier substrate, and then the second chip is formed on the surface to be bonded. Second oxide layer.
  • a surface of the second chip 200 facing away from the surface to be bonded (not labeled) is temporarily bonded to the carrier substrate 100, and then passes through the second oxide layer 250 and The first oxide layer 350 is bonded to the second chip 200 and the device wafer 300 by a fusion bonding process.
  • Fusion bonding is a process that mainly uses interface chemical forces to complete bonding.
  • the surfaces of the first oxide layer 350 and the second oxide layer 250 will form unsaturated Si atoms to form bonds and can achieve covalent bond bonding.
  • the contact surfaces of the first oxide layer 350 and the second oxide layer 250 are bonded by means of covalent bond bonding, so that the first oxide layer 350 and the second oxide layer 250 have a higher distance. Bonding strength, thereby improving the reliability of the bonding process, thereby increasing the bonding strength of the device wafer 300 and the second chip 200, and the subsequent process has a smaller impact on the bonding strength, correspondingly improved This improves the package yield.
  • the steps of the fusion bonding process include: forming a surface of the first oxide layer 350 (as shown in FIG. 3) and a second oxide layer 250 (as shown in FIG. 4).
  • the surface is subjected to a plasma activation process 110.
  • the pollutants and impurities on the surfaces of the first oxide layer 350 and the second oxide layer 250 are made into a gaseous state and discharged through a vacuum pump of a plasma system, thereby removing pollutants.
  • impurities such as better removal of metal pollution and organic pollutants.
  • the plasma of the plasma activation process 110 impacts the surface of the first oxide layer 350 and the surface of the second oxide layer 250, and energizes the unstable non-bridged oxygen atoms, so that the oxygen atoms leave Atoms that originally formed bonds provide a good basis for subsequent formation of covalent bonds at the contact surfaces of the first oxide layer 350 and the second oxide layer 250.
  • the material of the first oxide layer 350 and the second oxide layer 250 is silicon oxide. Therefore, after the plasma activation process 110, the first oxide layer 350 and the second oxide layer 250 are Unsaturated Si atoms are formed on the surface.
  • the reactive gas used in the plasma activation process 110 may include one or more of Ar, N 2 , O 2 and SF 6 .
  • the reactive gas used in the plasma activation process 110 is O 2 , that is, the plasma activation process 110 is an oxygen plasma activation process.
  • the RF power of the plasma activation process 110 should not be too small or too large.
  • the radio frequency electric field generated by the radio frequency power source is used to accelerate the electrons, and cause each electron to collide with the reactive gas molecules to transfer the moving energy, thereby ionizing each reactive gas molecule to generate a plasma.
  • the RF power is too small, it is difficult for the reaction gas to be plasmatized, which may easily cause problems such as insufficient plasma and poor plasma stability, thereby reducing the effect of the plasma activation treatment 110 and further causing the subsequent
  • the bonding strength between the first oxide layer 350 and the second oxide layer 250 is reduced; if the radio frequency power is too large, the kinetic energy obtained after the reactive gas is plasmaized is likely to be too large.
  • the bombardment effect of the oxide layer 350 and the second oxide layer 250 is correspondingly too strong, so that the surfaces of the first oxide layer 350 and the second oxide layer 250 are easily damaged, so that the first oxide layer 350 and the second oxide layer are damaged.
  • Micro-defects are formed on the surface of 250, and annealing holes are easy to be generated after subsequent annealing, but it is easy to reduce the bonding strength between the first oxide layer 350 and the second oxide layer 250, and the RF power is too high. It also consumes too much energy, which leads to an increase in process costs.
  • the RF power of the plasma activation process 110 is 20W to 200W.
  • the process pressure of the plasma activation process 110 should not be too small or too large.
  • the process pressure affects the RF power.
  • the greater the process pressure the shorter the average free path of the plasma and the greater the probability of collisions between the plasmas, resulting in the plasma activation process 110.
  • the effect becomes worse.
  • the required RF power is higher.
  • the process pressure is too small, it is easy to reduce the stability of the plasma. , The higher the RF power required to suppress plasma instability.
  • the process pressure is adjusted within a matching numerical range.
  • the process pressure is 0.1 mBar to 10 mBar.
  • the processing time of the plasma activation process 110 should not be too short or too long. If the processing time is too short, under the condition that the RF power and the flow rate of the reaction gas are constant, the effect of the plasma activation treatment 110 is correspondingly deteriorated, resulting in the subsequent first oxide layer 350 and the second oxide layer.
  • the bonding strength between 250 is reduced; if the processing time is too long, the surfaces of the first oxide layer 350 and the second oxide layer 250 are likely to be damaged, so that the first oxide layer 350 and the second oxide layer are oxidized. Micro-defects are formed on the surface of the layer 250. In addition, excessive treatment time will also generate excessive hydroxyl groups.
  • the processing time of the plasma activation process 110 is 0.1 minutes to 10 minutes.
  • the RF power, process pressure, flow rate of reaction gas, and processing time of the plasma activation process 110 are set within a reasonable range and cooperate with each other, thereby improving the processing efficiency and stability and reducing the process. At the same time, the activation effect on the first oxide layer 350 and the second oxide layer 250 is improved.
  • the step of the fusion bonding process further includes: after the plasma activation process 110 (as shown in FIG. 3 and FIG. 4), the surface of the first oxide layer 350 and the second oxide layer The surface of 250 is subjected to deionized water cleaning treatment; after the deionized water pre-cleaning treatment, the surface of the first oxide layer 350 and the surface of the second oxide layer 250 are dried.
  • the surface quality of the first oxide layer 350 and the second oxide layer 250 is improved, so that the bonding between the first oxide layer 350 and the second oxide layer 250 is improved. strength.
  • the surfaces of the first oxide layer 350 and the second oxide layer 250 are rinsed with deionized water, thereby completing the deionized water cleaning treatment; after the deionized water cleaning treatment, N 2 is blow-dried.
  • the first oxide layer 350 and the second oxide layer 250 are described, thereby completing the drying process.
  • the steps of the fusion bonding process further include: after the drying process, according to a preset relative position relationship between the second chip 200 and the first chip 310, The second oxide layer 250 and the first oxide layer 350 are oppositely disposed and bonded, and a bonding pressure is applied to the device wafer 300 and the second chip 200 to perform a pre-bonding process 120.
  • the pre-bonding process 120 causes the first The oxide layer 350 and the second oxide layer 250 realize interface chemical bonding.
  • the second chip 200 corresponds to the next one on the corresponding first chip 310, And the projections of the second chip 200 and the first chip 310 on the first oxide layer 350 are staggered from each other, and the first back surface 302 of the device wafer 300 and the carrier substrate 100 face away from the A bonding pressure is applied to a surface of the second chip 200 to perform a pre-bonding process 120.
  • the method of temporarily bonding the second back surface 202 of the second chip 200 to the carrier substrate 100 and then performing the pre-bonding process 120 is beneficial to improving the number of the second chips 200. Uniform force, and compared with the scheme of directly applying bonding pressure to the second chip 200, it is beneficial to reduce the damage caused to the second chip 200 by the pre-bonding process 120.
  • the bonding pressure of the pre-bonding process 120 is beneficial to improving the chemical bonding connection effect and strength at the interface between the first oxide layer 350 and the second oxide layer 250.
  • the bonding pressure If it is too large, the device wafer 300, the first oxide layer 350, the second oxide layer 250, and the second chip 200 are likely to have an adverse effect, such as a problem of deformation.
  • the bonding pressure of the pre-bonding process 120 is 1 Newton to 20 Newton.
  • the processing time of the pre-bonding process 120 is also beneficial to improving the chemical bond connection effect and strength of the contact surface between the first oxide layer 350 and the second oxide layer 250.
  • the processing time of the pre-bonding process 120 is 1 second to 60. second.
  • the steps of the fusion bonding process further include: after the pre-bonding process 120, annealing the device wafer 300 and the second chip 200.
  • the process temperature of the annealing treatment should not be too low or too high. If the process temperature is too low, it is easy to reduce the effect of the dehydration condensation reaction, which is not conducive to improving the bonding strength of the first oxide layer 350 and the second oxide layer 250; The device performance in the device wafer 300 and the second chip 200 has an adverse effect. For this reason, in this embodiment, the process temperature of the annealing treatment is 200 ° C to 500 ° C.
  • the process temperature of the annealing process is relatively low, so it is also beneficial to reduce the influence on the performance of the devices formed in the device wafer 300 and the second chip 200.
  • the process time of the annealing treatment should not be too short or too long. If the process time is too short, it is difficult to fully complete the dehydration condensation reaction, which is not conducive to improving the bonding strength of the first oxide layer 350 and the second oxide layer 250; if the process time is too long, it will instead As a result, the process time is wasted and the efficiency is reduced. Moreover, if the device wafer 300 and the second chip 200 are placed in an annealing environment for a long time, the process risk is correspondingly increased. For this reason, in this embodiment, the process time of the annealing treatment is 20 minutes to 200 minutes.
  • the process temperature and process time of the annealing process are set within a reasonable range and cooperate with each other, thereby increasing the bonding strength and reducing the probability of side effects.
  • the carrier substrate 100 is used to align the plurality of second chips 200. It plays a supporting role, reduces the probability of the second chip 200 falling off, and also facilitates the fusion bonding process.
  • the second chip 200 and the carrier substrate 100 are subjected to de-bonding processing. Therefore, the second chip 200 and the carrier substrate 100 are separated to remove the carrier substrate 100 and the adhesive layer 150 (as shown in FIG. 5).
  • the process of debonding treatment may be one or more of chemical etching, mechanical peeling, mechanical grinding, thermal baking, ultraviolet light irradiation, laser ablation, chemical mechanical polishing, and wet peeling, and according to the
  • the material of the adhesive layer 150 is selected from a suitable process.
  • an encapsulation layer 400 covering the second chip 200 is formed on the first oxide layer 350.
  • the encapsulation layer 400 covers the second chip 200 and the first oxide layer 350, and can play a role of sealing and preventing moisture to protect the first chip 310 and the second chip 200, thereby reducing the first chip 310. And the probability that the second chip 200 is damaged, contaminated, or oxidized, thereby helping to optimize the performance of the obtained packaging structure.
  • the encapsulation layer 400 covering the second chip 200 is formed on the first oxide layer 350, the encapsulation layer 400 is in contact with the first oxide layer 350. Due to the water absorption and chemical properties of the encapsulation layer 400, The stability is good, so it is beneficial to further improve the yield and reliability of the packaging structure.
  • the encapsulation layer 400 is formed after the fusion bonding process, so the process temperature of the annealing treatment in the fusion bonding process can be prevented from adversely affecting the encapsulation layer 400, and the quality of the encapsulation layer 400 And performance is guaranteed.
  • the material of the encapsulation layer 400 is epoxy.
  • Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost, so it is widely used as packaging materials for electronic devices and integrated circuits.
  • the packaging layer 400 is formed by using an injection molding process using a liquid molding compound or a solid molding compound.
  • the injection molding process may be a hot-press injection molding process.
  • the shape of the packaging layer 400 may be a wafer shape, and the diameter of the wafer-shaped packaging layer 400 is the same as the diameter of the device wafer 300.
  • the encapsulation layer may have other suitable shapes.
  • the packaging method further includes: after forming the packaging layer 400, thinning the first back surface 302 of the device wafer 300.
  • the first back surface 302 is thinned to reduce the thickness of the device wafer 300, thereby improving the heat dissipation effect of the device wafer 300, and facilitating the subsequent packaging process and reducing The overall thickness of the obtained packaging structure, thereby improving the performance of the packaging structure.
  • the thinning process may be one or more of a back grinding process, a chemical mechanical polishing (CMP) process, and a wet etching process.
  • CMP chemical mechanical polishing
  • a deep trench isolation for defining the stop position is generally formed in a semiconductor substrate of the device wafer 300 Structure, so that the thinning process stops at the bottom of the deep trench isolation structure.
  • a neutrally doped ion such as one or two of oxygen ions and nitrogen ions
  • a stop region is formed in the substrate, so that the thinning process stops at the bottom of the stop region.
  • the bottom substrate layer of the semiconductor substrate may also be thinned, so that It can stop well on the bottom of the said insulator layer.
  • the thickness of the device wafer 300 should not be too small or too large. If the thickness of the device wafer 300 is too small, the mechanical properties of the device wafer 300 are correspondingly poor, and it is easy to adversely affect structures such as devices formed in the device wafer 300; if the device If the thickness of the wafer 300 is too large, it is not beneficial to improve the performance of the formed packaging structure. For this reason, in this embodiment, after the thinning process, the thickness of the device wafer 300 is 5 ⁇ m to 10 ⁇ m.
  • a first interconnect structure 410 electrically connected to the first chip 310 and a second interconnect 200 electrically connected to the second chip 200 are formed in the device wafer 300.
  • the first interconnection structure 410 and the second interconnection structure 420 are used to achieve electrical connection between the first chip 310 and the second chip 200 and other circuits, and the first chip 310 and the second chip 200. Electrical connection between.
  • the first interconnect structure 410 and the second interconnect structure 420 are TSV interconnect structures, that is, the first interconnect structure 410 and the second interconnect structure 420 pass through a TSV (Through -Silicon Via (TSV) etching process and electroplating process.
  • TSV Thin -Silicon Via
  • the first interconnection structure 410 and the metal interconnection structure in the first chip 310 are electrically connected
  • the second interconnection structure 420 and the second pad 210 in the second chip 200 are electrically connected. Make electrical connections.
  • a material of the first interconnection structure 410 and the second interconnection structure 420 is copper.
  • the materials of the first interconnect structure and the second interconnect structure may also be conductive materials such as aluminum, tungsten, and titanium.
  • the present invention also provides a wafer-level packaging structure.
  • FIG. 9 a schematic structural diagram of an embodiment of a wafer-level package structure of the present invention is shown.
  • the wafer-level package structure includes a device wafer 300 integrated with a first chip 310, and the device wafer 300 includes a first front surface 301 integrated with the first chip 310 and a phase opposite to the first front surface 301.
  • a first back surface 302 on the back, a first oxide layer 350 is formed on the first front surface 301;
  • the second layer 200 is covered on the oxide layer 350.
  • the wafer-level package structure is a wafer-level system package structure, which can greatly reduce the advantages of the package structure, reduce manufacturing costs, optimize electrical performance, and batch manufacturing, and can significantly reduce Workload and equipment requirements.
  • the device wafer 300 is a completed wafer.
  • the device wafer 300 may include devices such as NMOS devices and PMOS devices on a semiconductor substrate, and may further include a dielectric layer, a metal interconnection structure, and A structure such as a pad electrically connected to the metal interconnection junction. Therefore, at least one first chip 310 is integrated in the device wafer 300, and a first pad 320 is formed in the first chip 310.
  • the device wafer 300 includes a first front surface 301 integrated with the first chip 310 and a first back surface 302 opposite to the first front surface 301, and the first front surface 301 exposes the first First pad 320 of the device wafer 300.
  • the first back surface 302 refers to a bottom surface of the semiconductor substrate on the device wafer 300 side away from the first pad 320.
  • the thickness of the device wafer 300 is 5 ⁇ m to 10 ⁇ m.
  • the thickness of the device wafer 400 is small, so that the heat dissipation effect of the device wafer 300 can be improved, and the packaging process is facilitated, and the overall thickness of the packaging structure is reduced, thereby improving the performance of the packaging structure. .
  • the number of the second chips 200 is at least one, and the number of the second chips 200 is the same as the number of the first chips 310.
  • the second chip 200 may be one or more of an active element, a passive element, a micro-electro-mechanical system, and an optical element.
  • the second chip 200 may be a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip. In other embodiments, the second chip may also be another functional chip.
  • the number of the second chips 200 is multiple, and the multiple second chips 200 are obtained by cutting multiple wafers of different function types.
  • the function types of the multiple second chips may also be the same.
  • the second chip 200 corresponds to the next one on the corresponding first chip 310, and the second chip 200 and the first chip 310 are on the first oxide layer 350.
  • the projections of each other are staggered.
  • the second chip 200 may be manufactured by using integrated circuit manufacturing technology.
  • the second chip 200 also generally includes a device such as an NMOS device or a PMOS device formed on a semiconductor substrate, and further includes a dielectric layer, a metal interconnect structure, and Pads and other structures.
  • the second chip 200 includes a second front surface 201 on which a second pad 210 is formed, and a second back surface 202 opposite to the second front surface 201.
  • the second front surface 201 exposes the second solder. ⁇ 210 ⁇ The plate 210.
  • the second back surface 202 refers to a bottom surface of the semiconductor substrate on the side of the second chip 200 that is far from the second pad 210.
  • the surface to be bonded of the second chip 200 is the second front surface 201, that is, the second front surface 201 faces the device wafer 300; correspondingly, the wafer-level packaging structure
  • the surface to be bonded may also be the second back surface.
  • the second oxide layer 250 and the first oxide layer 350 are connected by a fusion bonding process, and are used to implement a physical connection between the device wafer 300 and the second chip 200.
  • Melt bonding is a process that mainly uses interface chemical forces to complete bonding.
  • the contact surfaces of the first oxide layer 350 and the second oxide layer 250 are connected by covalent bonding, so the first oxide layer
  • the high bonding strength between 350 and the second oxide layer 250 is beneficial to improve the yield of the wafer-level packaging structure.
  • a through-hole etching process is generally included, and the through-hole etching process sequentially etches the device wafer 300 and the second oxide layer 250.
  • the second oxide layer 250 is an inorganic material, and the material of the device wafer 300 is also an inorganic material. Therefore, compared with a solution using an organic adhesive layer as the bonding layer, the second oxide layer 250 is used as the bonding layer.
  • the solution is also beneficial to reduce the process difficulty of the through-hole etching process, and after the through-hole etching process, it can avoid the problem that the etching hole diameter in the second oxide layer 250 is too large, which is conducive to improving The electrical connection performance of the through-hole structure.
  • the material of the second oxide layer 250 is the same as that of the first oxide layer 350, so that the covalent bond can be better achieved, which is beneficial to further improve the second oxide layer 250 and The bonding strength of the first oxide layer 350.
  • a material of the first oxide layer 350 is silicon oxide
  • a material of the second oxide layer 250 is silicon oxide.
  • the first oxide layer 350 and the second oxide layer 250 are combined by a covalent bond of Si-O-Si. Since the bond energy of the silicon-oxygen bond is large, the first oxide layer 350 can be effectively improved. Bonding strength with the second oxide layer 250.
  • silicon oxide materials have high process compatibility, and silicon oxide is a commonly used and low-cost material. Therefore, by selecting silicon oxide materials, it is helpful to reduce the difficulty and cost of the process, and to reduce The performance impact of forming a package structure.
  • the first oxide layer may be hafnium oxide, alumina, or lanthanum oxide
  • the second oxide layer may be hafnium oxide, alumina, or lanthanum oxide.
  • the thicknesses of the first oxide layer 350 and the second oxide layer 250 are equal.
  • the thickness of the first oxide layer 350 and the second oxide layer 250 should not be too small or too large. If the thickness is too small, it is easy to reduce the thickness uniformity and quality of the first oxide layer 350 and the second oxide layer 250; if the thickness is too large, the overall thickness of the packaging structure is too large, and It is beneficial to the improvement of process integration, and also increases the difficulty of the via hole etching process and the thickness of the via structure during the manufacturing process of the package structure. For this reason, in this embodiment, the thickness of the first oxide layer 350 is 1000 ⁇ to 30,000 ⁇ , and the thickness of the second oxide layer 250 is 1000 ⁇ to 30,000 ⁇ .
  • the packaging layer 400 covers the front surface 301 of the second chip 200 and the device wafer 300, and can play a role of sealing and preventing moisture to protect the first chip 310 and the second chip 200, thereby reducing the The probability that the first chip 310 and the second chip 200 are damaged, polluted, or oxidized is further beneficial to optimizing the performance of the packaging structure.
  • the encapsulation layer 400 is in contact with the first oxide layer 350. Since the water absorption rate and chemical stability of the encapsulation layer 400 are good, it is beneficial to further improve the yield and reliability of the encapsulation structure.
  • the material of the packaging layer 400 is epoxy resin.
  • Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost, so it is widely used as packaging materials for electronic devices and integrated circuits.
  • the material of the encapsulation layer may also be a thermosetting material such as polyimide or silicone.
  • the shape of the packaging layer 400 is a wafer shape, and the diameter of the wafer-shaped packaging layer 400 is the same as the diameter of the device wafer 400.
  • the encapsulation layer may have other suitable shapes.
  • the wafer-level packaging structure further includes: a first interconnection structure 410 located in the device wafer 300 and electrically connected to the first chip 310; a second interconnection structure 420 located in all The device wafer 300 is electrically connected to the second chip 200.
  • the first interconnection structure 410 and the second interconnection structure 420 are used to achieve electrical connection between the first chip 310 and the second chip 200 and other circuits, and between the first chip 310 and the second chip 200. Electrical connection.
  • first interconnection structure 410 and the metal interconnection structure in the first chip 310 are electrically connected, and the second interconnection structure 420 and the second pad 210 in the second chip 200 are electrically connected. Make electrical connections.
  • the first interconnect structure 510 and the second interconnect structure 520 are TSV interconnect structures, that is, the first interconnect structure 510 and the second interconnect structure 520 are etched through TSVs. Process and electroplating process.
  • a material of the first interconnection structure 410 and the second interconnection structure 420 is copper.
  • the materials of the first interconnect structure and the second interconnect structure may also be conductive materials such as aluminum, tungsten, and titanium.
  • the wafer-level packaging structure described in this embodiment may be formed using the wafer-level packaging method described in the previous embodiment, or may be formed using other packaging methods.
  • the wafer-level package structure for a detailed description of the wafer-level package structure, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated in this embodiment.

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Abstract

一种晶圆级封装方法及封装结构，晶圆级封装方法包括：提供集成有第一芯片的器件晶圆，器件晶圆包括集成有第一芯片的第一正面以及与第一正面相背的第一背面；在第一正面形成第一氧化层；提供待集成的第二芯片，第二芯片具有待键合面；在待键合面上形成第二氧化层；提供承载基板；将第二芯片背向待键合面的表面临时键合于承载基板上；通过第二氧化层和第一氧化层，采用熔融键合工艺实现第二芯片和器件晶圆的键合；实现第二芯片和器件晶圆的键合后，对第二芯片和载体晶圆进行解键合处理；在第一氧化层上形成覆盖第二芯片的封装层。本发明通过熔融键合工艺，提高了第一氧化层和第二氧化层之间的键合强度，从而提高封装成品率。

Description

晶圆级封装方法及封装结构 技术领域
本发明实施例涉及半导体制造领域，尤其涉及一种晶圆级封装方法及封装结构。
 背景技术
随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，人们对集成电路的封装技术的要求相应也不断提高。现有的封装技术包括球栅阵列封装(Ball Grid Array，BGA)、芯片尺寸封装(Chip Scale Package，CSP)、晶圆级封装(Wafer Level Package ，WLP)、三维封装(3D) 和系统封装(System in Package，SiP)等。
目前，为了满足集成电路封装的更低成本、更可靠、更快及更高密度的目标，先进的封装方法主要采用晶圆级系统封装（Wafer Level Package System in Package，WLPSiP），与传统的系统封装相比，晶圆级系统封装是在晶圆上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
晶圆级系统封装主要包括物理连接和电性连接这两个重要工艺，通常采用有机键合层（例如粘片膜）实现所述器件晶圆和待集成芯片之间的物理连接，并通过通孔刻蚀工艺（例如硅通孔刻蚀工艺）和电镀技术实现半导体器件之间的电性连接。
 技术问题
本发明实施例解决的问题是提供一种晶圆级封装方法及封装结构，提高封装成品率。
 技术解决方案
为解决上述问题，本发明实施例提供一种晶圆级封装方法，包括：提供集成有第一芯片的器件晶圆，所述器件晶圆包括集成有所述第一芯片的第一正面以及与所述第一正面相背的第一背面；在所述第一正面形成第一氧化层；提供待集成的第二芯片，所述第二芯片具有待键合面；在所述待键合面上形成第二氧化层；提供承载基板；将所述第二芯片背向所述待键合面的表面临时键合于所述承载基板上；将所述第二芯片背向所述待键合面的表面临时键合于所述承载基板上后，通过所述第二氧化层和所述第一氧化层，采用熔融键合工艺实现所述第二芯片和器件晶圆的键合；实现所述第二芯片和器件晶圆的键合后，对所述第二芯片和载体晶圆进行解键合处理；在所述解键合处理后，在所述第一氧化层上形成覆盖所述第二芯片的封装层。
可选的，所述熔融键合工艺的步骤包括：对所述第一氧化层表面和第二氧化层表面依次进行等离子体活化处理、去离子水清洗处理和干燥处理；在所述干燥处理后，根据所述第二芯片和第一芯片的预设相对位置关系，将所述第二氧化层和第一氧化层相对设置并贴合，对所述器件晶圆和第二芯片施加键合压力，进行预键合处理；在所述预键合处理后，对所述器件晶圆和第二芯片进行退火处理。
可选的，在所述待键合面上形成所述第二氧化层之后，将所述第二芯片背向所述待键合面的表面临时键合于所述承载基板上；或者，将所述第二芯片背向所述待键合面的表面临时键合于所述承载基板之后，在所述待键合面上形成所述第二氧化层。
可选的，形成所述封装层后，还包括：对所述第一背面进行减薄处理；在所述减薄处理后，在所述器件晶圆内形成与所述第一芯片电连接的第一互连结构、以及与所述第二芯片电连接的第二互连结构。
可选的，所述第一氧化层的材料为氧化硅、氧化铪、氧化铝或氧化镧，所述第二氧化层的材料为氧化硅、氧化铪、氧化铝或氧化镧，且所述第一氧化层和第二氧化层的材料相同。
可选的，所述等离子体活化处理所采用的反应气体包括Ar、N 2、O 2和SF 6中的一种或多种。
可选的，所述等离子体活化处理的参数包括：射频功率为20W至200W，工艺压强为0.1mBar至10mBar，处理时间为0.1分钟至10分钟。
可选的，所述预键合处理的键合压力为1牛顿至20牛顿，处理时间为1秒至60秒。
可选的，所述退火处理的工艺温度为200℃至500℃，工艺时间为20分钟至200分钟。
可选的，形成所述第一氧化层和第二氧化层中任一种的工艺为原子层沉积工艺、低压化学气相沉积工艺、金属有机化学气相沉积、物理气相沉积工艺或激光脉冲沉积工艺。
可选的，所述第二芯片背向所述待键合面的表面通过粘合层或静电键合临时键合于所述承载基板上。
可选的，所述第二芯片包括形成有焊盘的第二正面以及与所述第二正面相背的第二背面；所述待键合面为所述第二正面或第二背面。
相应的，本发明还提供一种晶圆级封装结构，包括：集成有第一芯片的器件晶圆，所述器件晶圆包括集成有所述第一芯片的第一正面以及与所述第一正面相背的第一背面，所述第一正面形成有第一氧化层；与所述器件晶圆相键合的第二芯片，所述第二芯片具有待键合面，所述待键合面上形成有第二氧化层，且所述第二氧化层与所述第一氧化层通过熔融键合工艺连接；封装层，位于所述第一氧化层上且覆盖所述第二芯片。
可选的，所述晶圆级封装结构还包括：第一互连结构，位于所述器件晶圆内且与所述第一芯片电连接；第二互连结构，位于所述器件晶圆内且与所述第二芯片电连接。
可选的，所述第一氧化层的材料为氧化硅、氧化铪、氧化铝或氧化镧，所述第二氧化层的材料为氧化硅、氧化铪、氧化铝或氧化镧，且所述第一氧化层和第二氧化层的材料相同。
可选的，所述第一氧化层的厚度为1000Å至30000Å，所述第二氧化层的厚度为1000Å至30000Å。
可选的，所述第二芯片包括形成有焊盘的第二正面以及与所述第二正面相背的第二背面；所述待键合面为所述第二正面或第二背面。
 有益效果
本发明实施例在器件晶圆的第一正面形成第一氧化层、在待集成第二芯片的待键合面上形成第二氧化层后，通过所述第二氧化层和所述第一氧化层，采用熔融键合工艺实现所述第二芯片和器件晶圆的键合；在所述熔融键合工艺过程中，所述第一氧化层和第二氧化层的接触面能够通过共价键结合的方式实现键合，使所述第一氧化硅层和第二氧化硅层之间具有较高的键合强度，提高了键合工艺的可靠性，从而提高了所述器件晶圆和第二芯片的键合强度，相应提高了封装成品率。
可选方案中，为了实现器件晶圆和第二芯片的电性连接，实现所述第二芯片和器件晶圆的键合后，还包括在所述器件晶圆内形成与所述第一芯片电连接的第一互连结构、以及与所述第二芯片电连接的第二互连结构；其中，形成所述第二互连结构的工艺通常包括通孔刻蚀工艺，所述通孔刻蚀工艺依次刻蚀所述器件晶圆和第二氧化层，由于所述第二氧化层为无机材料，而器件晶圆的材料也为无机材料，因此通过采用所述第一氧化层和第二氧化层作为键合层的方案，还有利于降低后续通孔刻蚀工艺的工艺难度，从而有利于提高所述第二互连结构的电连接性能。
 附图说明
图1至图9是本发明晶圆级封装方法一实施例中各步骤对应的结构示意图。
 本发明的实施方式
目前晶圆级系统封装的封装成品率较低。分析其成品率较低的原因在于：
器件晶圆和待集成芯片通常通过胶粘层（例如粘片膜或干膜）实现物理连接，但所述胶粘层的耐温性较差，当后续制程工艺中的工艺温度过高时，所述胶粘层容易失效，从而降低所述胶粘层的粘附性，甚至出现所述器件晶圆和待集成芯片发生脱落的问题，从而严重影响晶圆级系统封装的封装成品率。
为了解决所述技术问题，本发明实施例提供一种晶圆级封装方法，包括：提供集成有第一芯片的器件晶圆，所述器件晶圆包括集成有所述第一芯片的第一正面以及与所述第一正面相背的第一背面；在所述第一正面形成第一氧化层；提供待集成的第二芯片，所述第二芯片具有待键合面；在所述待键合面上形成第二氧化层；提供承载基板；将所述第二芯片背向所述待键合面的表面临时键合于所述承载基板上；将所述第二芯片背向所述待键合面的表面临时键合于所述承载基板上后，通过所述第二氧化层和所述第一氧化层，采用熔融键合工艺实现所述第二芯片和器件晶圆的键合；实现所述第二芯片和器件晶圆的键合后，对所述第二芯片和载体晶圆进行解键合处理；在所述解键合处理后，在所述第一氧化层上形成覆盖所述第二芯片的封装层。
本发明实施例在器件晶圆的第一正面形成第一氧化层、在待集成第二芯片的待键合面上形成第二氧化层后，通过所述第二氧化层和所述第一氧化层，采用熔融键合工艺实现所述第二芯片和器件晶圆的键合；在所述熔融键合工艺过程中，所述第一氧化层和第二氧化层的接触面能够通过共价键结合的方式实现键合，使所述第一氧化硅层和第二氧化硅层之间具有较高的键合强度，提高了键合工艺的可靠性，从而提高了所述器件晶圆和第二芯片的键合强度，相应提高了封装成品率。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图9是本发明晶圆级封装方法一实施例中各步骤对应的结构示意图。
参考图1，提供集成有第一芯片310的器件晶圆（CMOS Wafer）300，所述器件晶圆300包括集成有所述第一芯片310的第一正面301以及与所述第一正面301相背的第一背面302。
本实施例中，所述晶圆级封装方法用于实现晶圆级系统封装，所述器件晶圆300用于在后续工艺中与待集成芯片进行键合。
所述器件晶圆300为完成器件制作的晶圆，所述器件晶圆300可以采用集成电路制作技术所制成，例如在半导体衬底上通过沉积、刻蚀等工艺形成N型金属氧化物半导体（N-Metal-Oxide-Semiconductor，NMOS）器件和P型金属氧化物半导体（P-Metal-Oxide-Semiconductor，PMOS）器件等器件，在所述器件上形成介质层、金属互连结构以及与所述金属互连结电连接的焊盘等结构，从而使所述器件晶圆300中集成至少一个第一芯片310，且所述第一芯片310中形成有第一焊盘（Pad）320。
需要说明的是，当所述第一芯片310为多个时，所述多个第一芯片310可以为同一类型或不同类型的芯片。
还需要说明的是，为了便于图示，本实施例中，以所述器件晶圆300中集成有三个第一芯片310为例进行说明。但所述第一芯片310的数量不仅限于三个。
本实施例中，所述器件晶圆300的半导体衬底为硅衬底。在其他实施例中，所述半导体衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，所述半导体衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。所述半导体衬底的材料可以是适宜于工艺需要或易于集成的材料。
本实施例中，所述器件晶圆300包括集成有所述第一芯片310的第一正面301以及与所述第一正面301相背的第一背面302，所述第一正面301露出所述第一焊盘320。其中，所述第一焊盘320为所述器件晶圆300的引线焊盘（Bond Pad），所述第一焊盘320用于实现所述第一芯片310与其他电路之间的电性连接；所述第一背面302指的是所述器件晶圆300中远离所述第一焊盘320一侧的半导体衬底的底部表面。
本实施例中，根据实际工艺需求，所述器件晶圆300的厚度T1为10微米至100微米。
继续参考图1，在所述第一正面301形成第一氧化层350。
所述第一氧化层350作为后续熔融键合（Fusion Bonding）工艺的键合层，用于实现所述器件晶圆300和待键合芯片之间的物理连接。其中，在所述熔融键合工艺后，所述器件晶圆300与待集成芯片之间的键合强度较高。
本实施例中，所述第一氧化层350的材料为氧化硅。通过选取氧化硅材料，在后续熔融键合工艺的过程中，能够使所述器件晶圆300与待集成芯片之间以Si-O-Si的共价键进行键合，由于硅氧键的键能较大，进而有利于进一步提高所述器件晶圆300与待集成芯片的键合强度；而且，氧化硅材料具有较高的工艺兼容性，氧化硅还为工艺常用、成本较低的材料，因此通过选取氧化硅材料的方式，有利于降低工艺难度和工艺成本，且有利于降低对所形成封装结构的性能影响。在其他实施例中，所述第一氧化层还可以为氧化铪、氧化铝或氧化镧。
具体地，采用原子层沉积（Atomic Layer Deposition，ALD）工艺形成所述第一氧化层350。原子层沉积工艺是指通过将气相前驱体脉冲交替地通入反应腔室内，在待沉积基体上化学吸附并发生表面反应的沉积工艺。通过原子层沉积工艺，所述第一氧化层350以原子层的形式形成于所述第一正面301，因此有利于提高沉积速率的均匀性、所述第一氧化层350的厚度均一性以及所述第一氧化层350中的结构均一性，且所述第一氧化层350具有良好的覆盖能力；而且，原子层沉积工艺的工艺温度通常较低，因此还有利于减小了热预算 (Thermal Budget)，降低晶圆变形(Wafer Distortion)、器件性能偏移的概率。
在其他实施例中，根据所述第一氧化层的材料，形成所述第一氧化层的工艺还可以为低压化学气相沉积（Low Pressure Chemical Vapor Deposition，LPCVD）工艺、金属有机化学气相沉积（Metal Organic Chemical Vapor Deposition，MOCVD）工艺、物理气相沉积（Physical Vapor Deposition，PVD）工艺或激光脉冲沉积（Pulsed Laser Deposition，PLD）工艺。
参考图2，提供待集成的第二芯片200，所述第二芯片200具有待键合面（未标示）。
所述第二芯片200用于作为晶圆级系统封装中的待集成芯片，所述第二芯片200的数量至少为一个，且所述第二芯片200的数量与所述第一芯片410（如图1所示）的数量相同。
所述第二芯片200可以为有源元件、无源元件、微机电系统、光学元件等元件中的一种或多种。具体地，所述第二芯片200可以为存储芯片、通讯芯片、处理芯片、闪存芯片或逻辑芯片。在其他实施例中，所述第二芯片还可以是其他功能芯片。
本实施例中，所述晶圆级系统封装用于将多个不同功能的多个第二芯片200组合到一个封装结构中，因此所述多个第二芯片200通过对不同功能类型的多个晶圆进行切割所获得。在其他实施例中，根据实际工艺需求，所述多个第二芯片的功能类型还可以相同。
通过将多个第二芯片200集成于所述器件晶圆300（如图1所示）中，并在所述器件晶圆300上完成封装集成制程，从而能够大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显降低工作量与设备需求。
需要说明的是，本实施例晶圆级封装方法用于实现异质集成，因此所述多个第二芯片200为硅晶圆制成的芯片。在其他实施例中，所述第二芯片也可以是其他材质形成的芯片。
还需要说明的是，为了便于图示，本实施例中，以所述第二芯片200的数量为三个为例进行说明。但所述第二芯片200的数量不仅限于三个。
所述第二芯片200可以采用集成电路制作技术所制成，所述第二芯片200通常也包括形成于半导体衬底上的NMOS器件或PMOS器件等器件，还包括介质层、金属互连结构和焊盘等结构。
本实施例中，所述第二芯片200包括形成有第二焊盘210的第二正面201以及与所述第二正面201相背的第二背面202，所述第二正面201露出所述第二焊盘210。其中，所述第二焊盘210为引线焊盘，所述第二焊盘210用于实现所述第二芯片200与其他电路之间的电性连接；所述第二背面202指的是所述第二芯片200中远离所述第二焊盘210一侧的半导体衬底的底部表面。
本实施例中，所述第二芯片200的待键合面为所述第二正面201，即后续将所述第二正面201朝向所述器件晶圆300，当后续形成贯穿所述器件晶圆300且与所述第二芯片200电连接的互连结构（例如硅通孔互连结构）时，有利于减小所述互连结构的厚度，且有利于降低形成所述互连结构的工艺难度，降低工艺成本。在其他实施例中，根据实际工艺需求，所述待键合面还可以为所述第二背面，即后续将所述第二背面朝向所述器件晶圆。
继续参考图2，在所述待键合面（未标示）上形成第二氧化层250。
所述第二氧化层250作为后续熔融键合工艺的键合层，用于实现所述器件晶圆300和所述第二芯片200之间的物理连接，从而提高所述第二芯片200和所述器件晶圆300的键合强度。
而且，当后续形成贯穿所述器件晶圆300且与所述第二芯片200电连接的互连结构时，形成所述互连结构的工艺通常包括通孔刻蚀工艺，所述通孔刻蚀工艺依次刻蚀所述器件晶圆300和第二氧化层250，由于所述第二氧化层250为无机材料，而器件晶圆300的材料也为无机材料，因此与采用有机胶粘层作为键合层的方案相比，通过采用所述第二氧化层250作为键合层的方案，还有利于降低后续通孔刻蚀工艺的工艺难度，而且在所述通孔刻蚀工艺后，能够避免所述第二氧化层250内刻蚀孔径过大的问题，从而有利于提高所述通孔结构的电连接性能。
本实施例中，所述第二氧化层250的材料与所述第一氧化层350的材料相同，从而有利于进一步提高所述第二氧化层250和第一氧化层350的键合强度。具体地，采用原子层沉积工艺形成所述第二氧化层250，所述第二氧化层250的材料为氧化硅。
在其他实施例中，所述第二氧化层还可以为氧化铪、氧化铝或氧化镧，且根据所述第二氧化层的材料，形成所述第二氧化层的工艺还可以为低压化学气相沉积工艺、金属有机化学气相沉积工艺、物理气相沉积工艺或激光脉冲沉积工艺。
对所述第二氧化层250的具体描述，可参考前述对所述第一氧化层350的相关描述，本实施例在此不再赘述。
本实施例中，所述第二芯片200的待键合面为所述第二正面201，相应的，所述第二氧化层250形成于所述第二正面201上。在其他实施例中，当所述待键合面为第二背面时，所述第二氧化层相应形成于所述第二背面上。
需要说明的是，所述多个第二芯片200通过对晶圆进行切割所获得，因此为了提高所述第二氧化层250的形成效率和形成质量，在集成有所述第二芯片200的晶圆上形成所述第二氧化层250后，对形成有所述第二氧化层250的晶圆进行切割，从而获得形成有所述第二氧化层250的第二芯片200。
继续参考图2，提供承载基板100；将所述第二芯片200背向所述待键合面（未标示）的表面临时键合于所述承载基板100上。
所述承载基板100用于对所述多个第二芯片200起到支撑作用，从而便于后续工艺的进行，提高后续工艺的可操作性；而且通过临时键合（Temporary Bonding）的方式，还便于后续将所述第二芯片200和承载基板100进行分离。
本实施例中，所述承载基板100为载体晶圆（Carrier Wafer）。具体地，所述承载基板100可以为半导体衬底（例如硅衬底）、有机玻璃晶圆、无机玻璃晶圆、树脂晶圆、半导体材料晶圆、氧化物晶体晶圆、陶瓷晶圆、金属晶圆、有机塑料晶圆、无机氧化物晶圆或陶瓷材料晶圆。
本实施例中，所述承载基板100上形成有粘合层150，所述第二芯片200背向所述待键合面的表面通过所述粘合层150临时键合于所述承载基板100上。
具体地，所述粘合层150为粘片膜（Die Attach Film，DAF）和干膜（Dry Film）中的一种或两种。
其中，干膜是一种用于半导体芯片封装或印刷电路板制造时所采用的具有粘性的光致抗蚀膜，干膜光刻胶的制造是将无溶剂型光致抗蚀剂涂在涤纶片基上，再覆上聚乙烯薄膜；使用时揭去聚乙烯薄膜，把无溶剂型光致抗蚀剂压于基版上，经曝光显影处理，即可在所述干膜光刻胶内形成图形。
粘片膜是在半导体封装工序中用于连接半导体芯片与封装基板、芯片与芯片的超薄型薄膜黏合剂，具有较高的可靠性及方便的工序性，有利于实现半导体封装的积层化和薄型化。。
需要说明的是，在另一些实施例中，所述第二芯片200背向所述待键合面的表面还可以通过静电键合临时键合于所述承载基板上。静电键合技术是不用任何粘结剂实现键合的一种方法，在键合过程中，将要键合的第二芯片和承载基板分别连接不同的电极，在电压作用下使第二芯片和承载基板表面形成电荷，且所述第二芯片与承载基板表面电荷电性不同，从而在第二芯片与承载基板键合过程中产生较大的静电引力，实现两者的物理连接。
本实施例中，所述第二芯片200的待键合面为所述第二正面201，相应的，通过所述粘合层150将所述第二芯片200的第二背面202临时键合于所述承载基板100上。在其他实施例中，当所述第二芯片的待键合面为第二背面时，相应通过所述粘合层将所述第二芯片的第二正面临时键合于所述承载基板上。
本实施例中，在所述第二芯片200的待键合面上形成所述第二氧化层250之后，将所述第二芯片200背向所述待键合面的表面临时键合于所述承载基板100上，从而有利于简化形成所述第二氧化层250的工艺难度。
在其他实施例中，根据实际工艺情况，还可以将所述第二芯片背向所述待键合面的表面临时键合于所述承载基板之后，在所述待键合面上形成所述第二氧化层。
结合参考图3至图4，将所述第二芯片200背向所述待键合面（未标示）的表面临时键合于所述承载基板100上后，通过所述第二氧化层250和所述第一氧化层350，采用熔融键合工艺实现所述第二芯片200和器件晶圆300的键合。
熔融键合是一种主要利用界面化学力完成键合的工艺。在所述熔融键合工艺的过程中，所述第一氧化层350和第二氧化层250的表面会形成未饱和成键的Si原子，并能实现共价键的结合，因此通过所述熔融键合工艺，所述第一氧化层350和第二氧化层250的接触面通过共价键结合的方式实现键合，使所述第一氧化层350和第二氧化层250之间具有较高的键合强度，从而提高了键合工艺的可靠性，进而提高了所述器件晶圆300和第二芯片200的键合强度，且后续工艺对所述键合强度的影响较小，相应提高了封装成品率。
具体地，结合参考图3和图4，所述熔融键合工艺的步骤包括：对所述第一氧化层350表面（如图3所示）和第二氧化层250（如图4所示）表面进行等离子体活化处理110。
一方面，通过所述等离子体活化处理110，使所述第一氧化层350和第二氧化层250表面的污染物和杂质等成为气态，并通过等离子系统的真空泵排出，从而起到去除污染物和杂质的作用，例如可以较好地去除金属污染和有机污染物。
另一方面，所述等离子体活化处理110的等离子体对所述第一氧化层350表面和第二氧化层250表面进行撞击，对不稳定的非桥接氧原子赋能，使所述氧原子离开原先成键的原子，从而为后续在所述第一氧化层350和第二氧化层250的接触面形成共价键提供良好基础。
本实施例中，所述第一氧化层350和第二氧化层250的材料为氧化硅，因此在所述等离子体活化处理110后，在所述第一氧化层350和第二氧化层250的表面形成未饱和成键的Si原子。
所述等离子体活化处理110所采用的反应气体可以包括Ar、N 2、O 2和SF 6中的一种或多种。
本实施例中，所述等离子体活化处理110所采用的反应气体为O 2，即所述等离子体活化处理110为氧等离子体活化处理。
其中，所述等离子体活化处理110的射频功率不宜过小，也不宜过大。在所述等离子体活化处理110的过程中，利用射频功率源产生的射频电场使电子加速，并使各个电子与反应气体分子发生碰撞而转移动能，从而使各个反应气体分子发生电离产生等离子体。
如果射频功率过小，则所述反应气体难以被等离子体化，相应容易引起等离子体不足、等离子体稳定性变差的问题，从而降低所述等离子体活化处理110的效果，进而导致后续所述第一氧化层350和第二氧化层250之间的键合强度降低；如果所述射频功率过大，则容易导致所述反应气体被等离子体化后获得的动能过大，对所述第一氧化层350和第二氧化层250的轰击作用相应过强，从而容易对所述第一氧化层350和第二氧化层250表面造成损伤，从而在所述第一氧化层350和第二氧化层250表面形成微缺陷（Micro-defect），在后续退火处理后容易产生退火空洞，反而容易降低后续所述第一氧化层350和第二氧化层250之间的键合强度，而且，射频功率过大还会消耗过多能量，从而导致工艺成本的增加。
为此，本实施例中，所述等离子体活化处理110的射频功率为20W至200W。
所述等离子体活化处理110的工艺压强不宜过小，也不宜过大。所述工艺压强影响所述射频功率，所述工艺压强越大，则等离子体的平均自由程越短，所述等离子体之间发生碰撞的几率越大，从而导致所述等离子体活化处理110的效果变差，相应的，为了保证所述等离子体活化处理110的效果，所需射频功率则越高；此外，当所述工艺压强过小时，则容易降低所述等离子体的稳定性，相应的，抑制等离子体不稳定所需的射频功率越高。
为此，本实施例中，根据所述等离子体活化处理110射频功率，将所述工艺压强调整至相匹配的数值范围内。具体地，所述工艺压强为0.1mBar至10mBar。
所述等离子体活化处理110的处理时间不宜过短，也不宜过长。如果所述处理时间过短，在射频功率和反应气体的流量一定的情况下，则所述等离子体活化处理110的效果相应变差，从而导致后续所述第一氧化层350和第二氧化层250之间的键合强度降低；如果所述处理时间过长，则容易对所述第一氧化层350和第二氧化层250表面造成损伤，从而在所述第一氧化层350和第二氧化层250表面形成微缺陷，而且，处理时间过长还会产生过量的羟基，在后续退火处理后，容易产生过量副产物（H 2O和H 2等），从而导致退火空洞的产生，反而容易降低后续所述第一氧化层350和第二氧化层250之间的键合强度，此外，工艺时间过长相应还会导致工艺成本的增加。为此，本实施例中，所述等离子体活化处理110的处理时间为0.1分钟至10分钟。
本实施例中，通过将所述等离子体活化处理110的射频功率、工艺压强、反应气体的流量以及处理时间设定在合理范围内，并相互配合，从而在提高处理效率和稳定性、降低工艺成本的同时，提高对所述第一氧化层350和第二氧化层250的活化效果。
本实施例中，所述熔融键合工艺的步骤还包括：在所述等离子体活化处理110（如图3和图4所示）后，对所述第一氧化层350表面和第二氧化层250表面进行去离子水清洗处理；在所述去离子水预清洗处理后，对所第一氧化层350表面和第二氧化层250表面进行干燥处理。
通过所述去离子水清洗处理和干燥处理，以提高所述第一氧化层350和第二氧化层250的表面质量，从而提高所述第一氧化层350和第二氧化层250的的键合强度。
具体地，采用去离子水冲洗所述第一氧化层350和第二氧化层250的表面，从而完成所述去离子水清洗处理；在所述去离子水清洗处理后，采用N 2吹干所述第一氧化层350和第二氧化层250，从而完成所述干燥处理。
参考图5，本实施例中，所述熔融键合工艺的步骤还包括：在所述干燥处理后，根据所述第二芯片200和第一芯片310的预设相对位置关系，将所述第二氧化层250和第一氧化层350相对设置并贴合，对所述器件晶圆300和第二芯片200施加键合压力，进行预键合处理120。
在所述等离子体活化处理110后，在所述第一氧化层350和第二氧化层250的表面形成未饱和成键的Si原子，因此通过所述预键合处理120，使所述第一氧化层350和第二氧化层250实现界面化学键连接。
本实施例中，根据实际工艺需求，将所述第二氧化层250和第一氧化层350相对设置并贴合后，所述第二芯片200与相对应的第一芯片310上下一一对应，且所述第二芯片200和第一芯片310在所述第一氧化层350上的投影相互错开，并对所述器件晶圆300的第一背面302、以及所述承载基板100背向所述第二芯片200的表面施加键合压力，以进行预键合处理120。
其中，通过将所述第二芯片200的第二背面202临时键合于所述承载基板100上后再进行所述预键合处理120的方式，有利于提高所述多个第二芯片200的受力均匀性，而且，与直接对所述第二芯片200施加键合压力的方案相比，有利于降低所述预键合处理120对所述第二芯片200造成的损伤。
需要说明的是，增加所述预键合处理120的键合压力，有利于提高所述第一氧化层350和第二氧化层250界面的化学键连接效果和强度，但是，如果所述键合压力过大，则反而容易对所述器件晶圆300、第一氧化层350、第二氧化层250和第二芯片200造成不良影响，例如产生变形的问题等。为此，本实施例中，为了使所述第一氧化层350和第二氧化层250有效实现界面化学键连接的同时，降低工艺风险，所述预键合处理120的键合压力为1牛顿至20牛顿。
还需要说明的是，增加所述预键合处理120的处理时间，也有利于提高所述第一氧化层350和第二氧化层250接触面的化学键连接效果和强度，但是，如果所述处理时间过多，反而会造成工艺时间的浪费、效率的下降。为此，本实施例中，为了使所述第一氧化层350和第二氧化层250有效实现界面化学键连接的同时，提高工艺效率，所述预键合处理120的处理时间为1秒至60秒。
本实施例中，所述熔融键合工艺的步骤还包括：在所述预键合处理120后，对所述器件晶圆300和第二芯片200进行退火处理。
通过所述退火处理，使所述第一氧化层350和第二氧化层250接触面发生脱水缩合反应，从而使所述第一氧化层350和第二氧化层250形成Si-O-Si的共价键结合；由于硅氧键的键能较大，进而提高了所述第一氧化层350和第二氧化层250的键合强度。
其中，所述退火处理的工艺温度不宜过低，也不宜过高。如果所述工艺温度过低，则容易降低脱水缩合反应的效果，不利于提高所述第一氧化层350和第二氧化层250的键合强度；如果所述工艺温度过高，则容易对形成于所述器件晶圆300和第二芯片200内的器件性能产生不良影响。为此，本实施例中，所述退火处理的工艺温度为200℃至500℃。
本实施例中，所述退火处理的工艺温度较低，因此还有利于减小对形成于器件晶圆300和第二芯片200内的器件性能的影响。
所述退火处理的工艺时间不宜过短，也不宜过长。如果所述工艺时间过短，则难以充分完成所述脱水缩合反应，从而不利于提高所述第一氧化层350和第二氧化层250的键合强度；如果所述工艺时间过长，反而会造成工艺时间浪费、效率降低的问题，而且，将所述器件晶圆300和第二芯片200长期置于退火环境中，工艺风险相应增加。为此，本实施例中，所述退火处理的工艺时间为20分钟至200分钟。
本实施例中，通过将所述退火处理的工艺温度和工艺时间设定在合理范围内，并相互配合，从而在提高键合强度的同时，降低产生副作用的概率。
需要说明的是，由于所述第二芯片200的数量为多个且相互分立，因此，在所述熔融键合工艺的过程中，所述承载基板100用于对所述多个第二芯片200起到支撑作用，降低所述第二芯片200发生脱落的概率，且还便于所述熔融键合工艺的进行。
为此，参考图6，实现所述第二芯片200和器件晶圆300的键合后，对所述第二芯片200和承载基板100（如图5所示）进行解键合（De-bonding）处理，从而对所述第二芯片200和承载基板100进行分离，以去除所述承载基板100和粘合层150（如图5所示）。
具体地，所述解键合处理的工艺可以为化学腐蚀、机械剥离、机械研磨、热烘烤、紫外光照射、激光烧蚀、化学机械抛光以及湿法剥离中的一种或多种，并根据所述粘合层150的材料选取相适宜的工艺。
参考图7，在所述解键合处理，后，在所述第一氧化层350上形成覆盖所述第二芯片200的封装层400。
所述封装层400覆盖所述第二芯片200和第一氧化层350，能够起到密封和防潮的作用，以保护所述第一芯片310和第二芯片200，从而降低所述第一芯片310和第二芯片200受损、被污染或被氧化的概率，进而有利于优化所获得封装结构的性能。
而且，在所述第一氧化层350上形成覆盖所述第二芯片200的封装层400后，所述封装层400与所述第一氧化层350相接触，由于封装层400的吸水率和化学稳定性较好，因此有利于进一步提高封装结构的良率和可靠性。
此外，所述封装层400在所述熔融键合工艺之后形成，因此能够避免所述熔融键合工艺中退火处理的工艺温度对所述封装层400造成不良影响，使得所述封装层400的质量和性能得到保障。
本实施例中，所述封装层400的材料为环氧树脂(Epoxy)。环氧树脂具有收缩率低、粘结性好、耐腐蚀性好、电性能优异及成本较低等优点，因此广泛用作电子器件和集成电路的封装材料。
本实施例中，通过注塑成型工艺，采用液体的塑封料或者固体的塑封料，形成所述封装层400。具体地，所述注塑成型工艺可以为热压注塑成型工艺。
本实施例中，所述封装层400的形状可以为晶圆状，且所述晶圆状封装层400的直径与所述器件晶圆300的直径相同。在其他实施例中，所述封装层也可以为其它合适的形状。
结合参考图8，所述封装方法还包括：形成所述封装层400后，对所述器件晶圆300的第一背面302进行减薄处理。
通过对所述第一背面302进行减薄处理，以减小所述器件晶圆300的厚度，从而改善所述器件晶圆300的散热效果，且有利于后续封装制程的进行、减小封装后所获得封装结构的整体厚度，从而提高所述封装结构的性能。
本实施例中，所述减薄处理所采用的工艺可以为背部研磨工艺、化学机械抛光(Chemical Mechanical Polishing，CMP)工艺和湿法刻蚀工艺中的一种或多种。
为了有效控制所述减薄处理的停止位置，在所述器件晶圆300的制造工艺中，通常在所述器件晶圆300的半导体衬底内形成用于限定所述停止位置的深沟槽隔离结构，从而使所述减薄处理停止于所述深沟槽隔离结构的底部。
在另一实施例中，还可以在所述器件晶圆的制造工艺中，采用中性掺杂离子（例如氧离子和氮离子中的一种或两种）在所述器件晶圆300的半导体衬底内形成停止区，从而使所述减薄处理停止于所述停止区的底部。
在其他实施例中，当所述器件晶圆的半导体衬底为绝缘体上的硅衬底或者绝缘体上的锗衬底时，还可以对所述半导体衬底的底部衬底层进行减薄处理，从而能够较好地停止于所述绝缘体层的底部。
需要说明的是，在所述减薄处理后，所述器件晶圆300的厚度不宜过小，也不宜过大。如果所述器件晶圆300的厚度过小，则所述器件晶圆300的机械性能相应较差，且容易对形成于所述器件晶圆300内的器件等结构产生不良影响；如果所述器件晶圆300的厚度过大，则不利于提高所形成封装结构的性能。为此，本实施例中，在所述减薄处理后，所述器件晶圆300的厚度为5μm至10μm。
结合参考图9，在所述减薄处理后，在所述器件晶圆300内形成与所述第一芯片310电连接的第一互连结构410、以及与所述第二芯片200电连接的第二互连结构420。
通过所述第一互连结构410和第二互连结构420，以实现所述第一芯片310和第二芯片200与其他电路的电性连接、以及所述第一芯片310和第二芯片200之间的电性连接。
本实施例中，所述第一互连结构410和第二互连结构420为硅通孔互连结构，即所述第一互连结构410和第二互连结构420通过硅通孔（Through-Silicon Via，TSV）刻蚀工艺和电镀工艺所形成。具体地，所述第一互连结构410与所述第一芯片310内的金属互连结构实现电连接，所述第二互连结构420与所述第二芯片200内的第二焊盘210实现电连接。
本实施例中，所述第一互连结构410和第二互连结构420的材料为铜。在其他实施例中，所述第一互连结构和第二互连结构的材料还可以为铝、钨和钛等导电材料。
相应的，本发明还提供一种晶圆级封装结构。继续参考图9，示出了本发明晶圆级封装结构一实施例的结构示意图。
所述晶圆级封装结构包括：集成有第一芯片310的器件晶圆300，所述器件晶圆300包括集成有所述第一芯片310的第一正面301以及与所述第一正面301相背的第一背面302，所述第一正面301形成有第一氧化层350；与所述器件晶圆300相键合的第二芯片200，所述第二芯片200具有待键合面（未标示），所述待键合面上形成有第二氧化层250，且所述第二氧化层250与所述第一氧化层350通过熔融键合工艺连接；封装层400，位于所述第一氧化层350上且覆盖所述第二芯片200。
本实施例中，所述晶圆级封装结构为晶圆级系统封装结构，从而能够大幅减小所述封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
其中，所述器件晶圆300为完成器件制作的晶圆，所述器件晶圆300可以包括位于半导体衬底上的NMOS器件和PMOS器件等器件，还可以包括介质层、金属互连结构以及与所述金属互连结电连接的焊盘等结构。因此，所述器件晶圆300中集成至少一个第一芯片310，且所述第一芯片310中形成有第一焊盘320。
本实施例中，所述器件晶圆300包括集成有所述第一芯片310的第一正面301以及与所述第一正面301相背的第一背面302，所述第一正面301露出所述器件晶圆300的第一焊盘320。其中，所述第一背面302指的是所述器件晶圆300中远离所述第一焊盘320一侧的半导体衬底的底部表面。
本实施例中，所述器件晶圆300的厚度为5μm至10μm。所述器件晶圆400的厚度较小，从而能够改善所述器件晶圆300的散热效果，且有利于封装制程的进行、减小所述封装结构的整体厚度，从而提高所述封装结构的性能。
对所述器件晶圆300的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
所述第二芯片200的数量至少为一个，且所述第二芯片200的数量与所述第一芯片310的数量相同。其中，所述第二芯片200可以为有源元件、无源元件、微机电系统、光学元件等元件中的一种或多种。具体地，所述第二芯片200可以为存储芯片、通讯芯片、处理芯片、闪存芯片或逻辑芯片。在其他实施例中，所述第二芯片还可以是其他功能芯片。
本实施例中，所述第二芯片200的数量为多个，所述多个第二芯片200通过对不同功能类型的多个晶圆进行切割所获得。在其他实施例中，根据实际工艺需求，所述多个第二芯片的功能类型还可以相同。
本实施例中，根据实际工艺需求，所述第二芯片200与相对应的第一芯片310上下一一对应，且所述第二芯片200和第一芯片310在所述第一氧化层350上的投影相互错开。
所述第二芯片200可以采用集成电路制作技术所制成，所述第二芯片200通常也包括形成于半导体衬底上的NMOS器件或PMOS器件等器件，还包括介质层、金属互连结构和焊盘等结构。
具体地，所述第二芯片200包括形成有第二焊盘210的第二正面201以及与所述第二正面201相背的第二背面202，所述第二正面201露出所述第二焊盘210。其中，所述第二背面202指的是所述第二芯片200中远离所述第二焊盘210一侧的半导体衬底的底部表面。
本实施例中，所述第二芯片200的待键合面为所述第二正面201，即所述第二正面201朝向所述器件晶圆300；相应的，在所述晶圆级封装结构的制造过程中，有利于降低形成互连结构（例如硅通孔互连结构）的工艺难度，降低工艺成本，且还有利于减小所述互连结构的厚度。在其他实施例中，根据实际工艺需求，所述待键合面还可以为所述第二背面。
对所述第二芯片200的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
所述第二氧化层250与所述第一氧化层350通过熔融键合工艺连接，用于实现所述器件晶圆300和所述第二芯片200之间的物理连接。
熔融键合是一种主要利用界面化学力完成键合的工艺，所述第一氧化层350和第二氧化层250的接触面以共价键结合的方式实现连接，因此所述第一氧化层350和第二氧化层250之间具有较高的键合强度，从而有利于提高所述晶圆级封装结构的成品率。
而且，在所述晶圆级封装结构的制造过程中，通常包括通孔刻蚀工艺，所述通孔刻蚀工艺依次刻蚀所述器件晶圆300和第二氧化层250，由于所述第二氧化层250为无机材料，而器件晶圆300的材料也为无机材料，因此与采用有机胶粘层作为键合层的方案相比，通过采用所述第二氧化层250作为键合层的方案，还有利于降低所述通孔刻蚀工艺的工艺难度，且在所述通孔刻蚀工艺后，能够避免所述第二氧化层250内刻蚀孔径过大的问题，从而有利于提高所述通孔结构的电连接性能。
本实施例中，所述第二氧化层250的材料与所述第一氧化层350的材料相同，从而能较好地实现共价键的结合，有利于进一步提高所述第二氧化层250和第一氧化层350的键合强度。
具体地，所述第一氧化层350的材料为氧化硅，所述第二氧化层250的材料为氧化硅。相应的，所述第一氧化层350和第二氧化层250通过Si-O-Si的共价键实现结合，由于硅氧键的键能较大，因此能有效提高所述第一氧化层350和第二氧化层250的键合强度。
而且，氧化硅材料具有较高的工艺兼容性，且氧化硅为工艺常用、成本较低的材料，因此通过选取氧化硅材料的方式，有利于降低工艺难度和工艺成本，且有利于降低对所形成封装结构的性能影响。
在其他实施例中，所述第一氧化层还可以为氧化铪、氧化铝或氧化镧，所述第二氧化层还可以为氧化铪、氧化铝或氧化镧。
本实施例中，为了降低工艺难度，所述第一氧化层350和第二氧化层250的厚度相等。
但是，所述第一氧化层350和第二氧化层250的厚度不宜过小，也不宜过大。如果所述厚度过小，则容易降低所述第一氧化层350和第二氧化层250的厚度均一性和质量；如果所述厚度过大，相应导致所述封装结构的整体厚度过大，不利于工艺集成度的提高，而且还会在所述封装结构的制造过程中，增加通孔刻蚀工艺的难度以及通孔结构的厚度。为此，本实施例中，所述第一氧化层350的厚度为1000Å至30000Å，所述第二氧化层250的厚度为1000Å至30000Å
所述封装层400覆盖所述第二芯片200和所述器件晶圆300的正面301，能够起到密封和防潮的作用，以保护所述第一芯片310和第二芯片200，从而降低所述第一芯片310和第二芯片200受损、被污染或被氧化的概率，进而有利于优化所述封装结构的性能。
而且，所述封装层400与所述第一氧化层350相接触，由于封装层400的吸水率和化学稳定性较好，因此有利于进一步提高封装结构的良率和可靠性。
本实施例中，所述封装层400的材料为环氧树脂。环氧树脂具有收缩率低、粘结性好、耐腐蚀性好、电性能优异及成本较低等优点，因此广泛用作电子器件和集成电路的封装材料。在其他实施例中，所述封装层的材料还可以为聚酰亚胺或硅胶等热固性材料。
本实施例中，所述封装层400的形状为晶圆状，且所述晶圆状封装层400的直径与所述器件晶圆400的直径相同。在其他实施例中，所述封装层也可以为其它合适的形状。
需要说明的是，所述晶圆级封装结构还包括：第一互连结构410，位于所述器件晶圆300内且与所述第一芯片310电连接；第二互连结构420，位于所述器件晶圆300内且与所述第二芯片200电连接。
所述第一互连结构410和第二互连结构420用于实现所述第一芯片310和第二芯片200与其他电路的电性连接、以及所述第一芯片310和第二芯片200之间的电性连接。
具体地，所述第一互连结构410与所述第一芯片310内的金属互连结构实现电连接，所述第二互连结构420与所述第二芯片200内的第二焊盘210实现电连接。
本实施例中，所述第一互连结构510和第二互连结构520为硅通孔互连结构，即所述第一互连结构510和第二互连结构520通过硅通孔刻蚀工艺和电镀工艺所形成。
本实施例中，所述第一互连结构410和第二互连结构420的材料为铜。在其他实施例中，所述第一互连结构和第二互连结构的材料还可以为铝、钨和钛等导电材料。
本实施例所述晶圆级封装结构可以采用前述实施例所述的晶圆级封装方法所形成，也可以采用其他封装方法所形成。本实施例中，对所述晶圆级封装结构的具体描述，可参考前述实施例中的相应描述，本实施例在此不再赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (17)

  1. 一种晶圆级封装方法，其特征在于，包括：
    提供集成有第一芯片的器件晶圆，所述器件晶圆包括集成有所述第一芯片的第一正面以及与所述第一正面相背的第一背面；
    在所述第一正面形成第一氧化层；
    提供待集成的第二芯片，所述第二芯片具有待键合面；
    在所述待键合面上形成第二氧化层；
    提供承载基板；
    将所述第二芯片背向所述待键合面的表面临时键合于所述承载基板上；
    将所述第二芯片背向所述待键合面的表面临时键合于所述承载基板上后，通过所述第二氧化层和所述第一氧化层，采用熔融键合工艺实现所述第二芯片和器件晶圆的键合；
    实现所述第二芯片和器件晶圆的键合后，对所述第二芯片和载体晶圆进行解键合处理；
    在所述解键合处理后，在所述第一氧化层上形成覆盖所述第二芯片的封装层。
  2. 如权利要求1所述的晶圆级封装方法，其特征在于，所述熔融键合工艺的步骤包括：对所述第一氧化层表面和第二氧化层表面依次进行等离子体活化处理、去离子水清洗处理和干燥处理；
    在所述干燥处理后，根据所述第二芯片和第一芯片的预设相对位置关系，将所述第二氧化层和第一氧化层相对设置并贴合，对所述器件晶圆和第二芯片施加键合压力，进行预键合处理；
    在所述预键合处理后，对所述器件晶圆和第二芯片进行退火处理。
  3. 如权利要求1所述的晶圆级封装方法，其特征在于，在所述待键合面上形成所述第二氧化层之后，将所述第二芯片背向所述待键合面的表面临时键合于所述承载基板上；
    或者，
    将所述第二芯片背向所述待键合面的表面临时键合于所述承载基板之后，在所述待键合面上形成所述第二氧化层。
  4. 如权利要求1所述的晶圆级封装方法，其特征在于，形成所述封装层后，还包括：对所述第一背面进行减薄处理；
    在所述减薄处理后，在所述器件晶圆内形成与所述第一芯片电连接的第一互连结构、以及与所述第二芯片电连接的第二互连结构。
  5. 如权利要求1或2所述的晶圆级封装方法，其特征在于，所述第一氧化层的材料为氧化硅、氧化铪、氧化铝或氧化镧，所述第二氧化层的材料为氧化硅、氧化铪、氧化铝或氧化镧，且所述第一氧化层和第二氧化层的材料相同。
  6. 如权利要求2所述的晶圆级封装方法，其特征在于，所述等离子体活化处理所采用的反应气体包括Ar、N 2、O 2和SF 6中的一种或多种。
  7. 如权利要求2所述的晶圆级封装方法，其特征在于，所述等离子体活化处理的参数包括：射频功率为20W至200W，工艺压强为0.1mBar至10mBar，处理时间为0.1分钟至10分钟。
  8. 如权利要求2所述的晶圆级封装方法，其特征在于，所述预键合处理的键合压力为1牛顿至20牛顿，处理时间为1秒至60秒。
  9. 如权利要求2所述的晶圆级封装方法，其特征在于，所述退火处理的工艺温度为200℃至500℃，工艺时间为20分钟至200分钟。
  10. 如权利要求1所述的晶圆级封装方法，其特征在于，形成所述第一氧化层和第二氧化层中任一个的工艺为原子层沉积工艺、低压化学气相沉积工艺、金属有机化学气相沉积、物理气相沉积工艺或激光脉冲沉积工艺。
  11. 如权利要求1所述的晶圆级封装方法，其特征在于，所述第二芯片背向所述待键合面的表面通过粘合层或静电键合临时键合于所述承载基板上。
  12. 如权利要求1所述的晶圆级封装方法，其特征在于，所述第二芯片包括形成有焊盘的第二正面以及与所述第二正面相背的第二背面；
    所述待键合面为所述第二正面或第二背面。
  13. 一种晶圆级封装结构，其特征在于，包括：
    集成有第一芯片的器件晶圆，所述器件晶圆包括集成有所述第一芯片的第一正面以及与所述第一正面相背的第一背面，所述第一正面形成有第一氧化层；
    与所述器件晶圆相键合的第二芯片，所述第二芯片具有待键合面，所述待键合面上形成有第二氧化层，且所述第二氧化层与所述第一氧化层通过熔融键合工艺连接；
    封装层，位于所述第一氧化层上且覆盖所述第二芯片。
  14. 如权利要求13所述的晶圆级封装结构，其特征在于，所述晶圆级封装结构还包括：第一互连结构，位于所述器件晶圆内且与所述第一芯片电连接；
    第二互连结构，位于所述器件晶圆内且与所述第二芯片电连接。
  15. 如权利要求13所述的晶圆级封装结构，其特征在于，所述第一氧化层的材料为氧化硅、氧化铪、氧化铝或氧化镧，所述第二氧化层的材料为氧化硅、氧化铪、氧化铝或氧化镧，且所述第一氧化层和第二氧化层的材料相同。
  16. 如权利要求13或15所述的晶圆级封装结构，其特征在于，所述第一氧化层的厚度为1000Å至30000Å，所述第二氧化层的厚度为1000Å至30000Å。
  17. 如权利要求13所述的晶圆级封装结构，其特征在于，所述第二芯片包括形成有焊盘的第二正面以及与所述第二正面相背的第二背面；
    所述待键合面为所述第二正面或第二背面。
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