WO2020034994A1 - 倒装发光芯片及其制造方法 - Google Patents

倒装发光芯片及其制造方法 Download PDF

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WO2020034994A1
WO2020034994A1 PCT/CN2019/100574 CN2019100574W WO2020034994A1 WO 2020034994 A1 WO2020034994 A1 WO 2020034994A1 CN 2019100574 W CN2019100574 W CN 2019100574W WO 2020034994 A1 WO2020034994 A1 WO 2020034994A1
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layer
channel
type
electrode
type semiconductor
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PCT/CN2019/100574
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English (en)
French (fr)
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刘英策
刘兆
李俊贤
魏振东
邬新根
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厦门乾照光电股份有限公司
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Priority to US16/625,768 priority Critical patent/US11616171B2/en
Publication of WO2020034994A1 publication Critical patent/WO2020034994A1/zh
Priority to US17/886,444 priority patent/US20220393077A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004—Devices characterised by their operation
    • H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
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    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body

Definitions

  • the invention relates to a semiconductor light emitting diode, and particularly to a flip chip and a manufacturing method thereof.
  • flip-chips and related technologies of light-emitting diodes have developed by leaps and bounds.
  • flip-chips can be divided into flip-chips and metal reflections of ITO + DBR reflective structures according to the reflective materials of the flip-chips.
  • Flip-chips of structures such as Ag / Al, where metal reflective structures (especially Ag metal reflective structures) have higher reflectivity in the visible range, therefore, metal reflective structures are widely used in flip-chips.
  • the flip chip can be divided into a flip chip with a single ISO (Insulation Barrier Layer) structure and a flip chip with a dual ISO structure.
  • ISO Interosulation Barrier Layer
  • the current of the flip chip with dual ISO structure can be expanded more uniformly and the light efficiency is higher, which is widely used in automotive lighting.
  • FIG. 1 is a schematic cross-sectional view of a flip chip with a dual ISO structure in the prior art.
  • the flip chip is manufactured by nine photolithography processes.
  • the flip chip includes a substrate 10P, an epitaxial stack 20P, a reflective layer 30P, a barrier layer 40P, an N ohm contact layer 50P, a first insulating layer 60P, an extended electrode layer 70P, A second insulating layer 80P and an electrode group 90P.
  • the epitaxial stack 20P includes an N-type semiconductor layer 21P, an active region 22P, and a P-type semiconductor layer 23P.
  • the substrate 10P, the N-type semiconductor layer 21P, the active region 22P, and The P-type semiconductor layer 23P is sequentially stacked.
  • the epitaxial stack 20P further includes at least one N-type exposed portion 24P.
  • the N-type exposed portion 24P extends from the P-type semiconductor layer 23P through the active region 22P to the N-type semiconductor layer 21P. A part of the surface of the N-type semiconductor layer 21P is exposed.
  • the reflective layer 30P is stacked on the P-type semiconductor layer 23P, and the barrier layer 40P is stacked on the P-type semiconductor layer 23P so as to cover the reflective layer 30P.
  • the N ohmic contact layer 50P is stacked on the N-type semiconductor layer 21P so as to be held by the N-type exposed portion 24P.
  • the first insulating layer 60P is stacked on the epitaxial stack 20P, the blocking layer 40P, and the N ohmic contact layer 50P, wherein the first insulating layer 60P has at least a first channel 61P and at least a second A channel 62P, wherein the first channel 61P of the first insulating layer 60P extends to the N ohm contact layer 50P, and the second channel 62P of the first insulating layer 60P extends to the blocking layer 40P.
  • the extended electrode layer 70P includes at least one first extended electrode portion 71P and at least one second extended electrode portion 72P, wherein the first extended electrode portion 71P is stacked on the first insulating layer 60P, and the first extended electrode portion 70P
  • the electrode portion 71P extends to and is electrically connected to the N ohm contact layer through the first channel 61P of the first insulating layer 60P, wherein the second extended electrode portion 72P is laminated on the first insulating layer 60P,
  • the second extension electrode portion 72P extends to and is electrically connected to the barrier layer 40P through the second channel 62P of the first insulating layer 60P.
  • the second insulating layer 80P is stacked on the first extension electrode portion 71P and the second extension electrode portion 72P, and the second insulation layer 80P is filled in the first extension electrode portion 71P and the first extension electrode portion 71P. A gap between the second extended electrode portions 72P.
  • the second insulating layer 80P has at least one third channel 81P and at least one fourth channel 82P.
  • the third channel 81P of the second insulating layer 80P extends to the first extended electrode portion 71P.
  • the fourth channel 82P of the second insulating layer 80P extends to the second extended electrode portion 72P.
  • the electrode group 90P includes an N-type electrode 91P and a P-type electrode 92P, wherein the N-type electrode 91P is laminated on the second insulating layer 80P, and the N-type electrode 91P passes through the second insulating layer 80P
  • the third channel 81P extends to and is electrically connected to the first extension electrode portion 71P
  • the P-type electrode 92P extends to and is electrically connected to the first via the fourth channel 82P of the second insulating layer 80P.
  • the second extension electrode portion 72P is described.
  • the manufacturing process of the flip chip shown in FIG. 1 is relatively complicated, which includes the Mesa process, the DE process, the Mirror process, the Barrier process, the N contact electrode process, the first insulating layer process, the extended electrode process, and the second insulating layer process.
  • There are nine photolithography processes in the electrode process which not only leads to the flip chip having higher production cost and lower production efficiency, but also the more the photolithography process in the process of making the flip chip, the easier it is to affect the flip chip. Stability and reliability of flip chip.
  • An object of the present invention is to provide a flip-chip light-emitting chip and a manufacturing method thereof, wherein a process of the flip-chip light-emitting chip can be simplified, so as to improve the production efficiency of the flip-chip light-emitting chip and reduce the flip-chip light emission.
  • the manufacturing cost of the chip is to provide a flip-chip light-emitting chip and a manufacturing method thereof, wherein a process of the flip-chip light-emitting chip can be simplified, so as to improve the production efficiency of the flip-chip light-emitting chip and reduce the flip-chip light emission.
  • An object of the present invention is to provide a flip-chip light-emitting chip and a method for manufacturing the same, wherein the process of the flip-chip light-emitting chip can be simplified to facilitate improving the product yield of the flip-chip light-emitting chip and ensuring the flip-chip. The reliability of the light emitting chip.
  • An object of the present invention is to provide a flip-chip light-emitting chip and a method for manufacturing the same, wherein the flip-chip light-emitting chip provides a barrier layer and a first insulating layer, and a layer between the barrier layer and the first insulating layer is provided.
  • the bonding force can be greatly improved to improve the reliability of the flip chip.
  • An object of the present invention is to provide a flip-chip light-emitting chip and a manufacturing method thereof, wherein the flip-chip light-emitting chip provides an adhesive layer, and the adhesive layer is held between the barrier layer and the first insulating layer. At the same time, the bonding force between the barrier layer and the first insulating layer is improved by the adhesive layer.
  • An object of the present invention is to provide a flip-chip light-emitting chip and a manufacturing method thereof, wherein the flip-chip light-emitting chip provides a cut-off layer, and the cut-off layer is held between the barrier layer and the adhesive layer to Increase the process controllability of the flip chip.
  • An object of the present invention is to provide a flip-chip light emitting chip and a manufacturing method thereof, wherein the cut-off layer has good anti-etching performance, so that the cut-off between the barrier layer and the adhesive layer is maintained.
  • the layer can increase the process controllability of the flip chip.
  • An object of the present invention is to provide a flip-chip light-emitting chip and a manufacturing method thereof, wherein the flip-chip light-emitting chip provides an epitaxial stack and an extension electrode layer, and a first extension electrode portion of the extension electrode layer directly contacts the substrate.
  • the epitaxially stacked N-type semiconductor layer so that the first extension electrode portion can not only function as an extension electrode, but also can function as a contact, which makes the flip-chip light-emitting chip not need to be provided with an N-type ohm. In this way, the contact layer is helpful to simplify the manufacturing process of the flip chip.
  • An object of the present invention is to provide a flip-chip light-emitting chip and a manufacturing method thereof, wherein the flip-chip light-emitting chip provides a first insulating material base layer, wherein the first insulating material base layer is stacked on the epitaxial stack, wherein In the process of manufacturing the flip-chip light emitting chip, a first channel is formed in the first insulating material base layer by etching the first insulating material base layer in sections to make a part of the surface of the N-type semiconductor layer. Being exposed to the first channel, in this way, the reliability of the electrical connection relationship between the first extension electrode portion and the N-type semiconductor layer can be ensured.
  • An object of the present invention is to provide a flip-chip light-emitting chip and a manufacturing method thereof, wherein in the process of manufacturing the flip-chip light-emitting chip, the first insulating material base layer is etched first, and the second etch is performed on the first An interface layer formed on the N-type semiconductor layer during the process of an insulating material base layer. In this way, a part of the surface of the N-type semiconductor layer can be exposed to the first channel, thereby ensuring the first expansion. The reliability of the electrical connection relationship between the electrode portion and the N-type semiconductor layer.
  • An object of the present invention is to provide a flip-chip light-emitting chip and a method for manufacturing the same.
  • a second channel is formed by etching the base layer of the first insulating material in sections.
  • the first insulating material base layer is such that a part of the surface of the barrier layer of the flip chip is exposed to the second channel. In this way, a second extended electrode portion of the extended electrode layer can be ensured. The reliability of the electrical connection relationship of the barrier layer.
  • An object of the present invention is to provide a flip-chip light-emitting chip and a manufacturing method thereof, wherein in the process of manufacturing the flip-chip light-emitting chip, the first insulating material base layer is etched first, and the second etch is performed on the first An interface layer of the barrier layer is formed during the process of an insulating material base layer. In this way, a part of the surface of the barrier layer can be exposed to the second channel, thereby ensuring that the second extended electrode portion is in place. The reliability of the electrical connection relationship of the barrier layer is described.
  • An object of the present invention is to provide a flip-chip light-emitting chip and a manufacturing method thereof, wherein the flip-chip light-emitting chip provides a reflective layer, wherein the reflective layer is stacked on a P-type semiconductor layer of the epitaxial stack, and The reflective layer has a multilayer laminated structure. In this way, the reliability of the flip-chip light emitting chip can be ensured.
  • An object of the present invention is to provide a flip-chip light emitting chip and a manufacturing method thereof, wherein the barrier layer is laminated on the P-type semiconductor layer in a manner of covering the reflection layer, and the barrier layer is a multilayer stack structure In this way, the blocking layer can effectively prevent the diffusion and migration of the reflective layer, thereby ensuring the reliability of the flip chip.
  • the present invention provides a flip chip light emitting chip, which includes:
  • An epitaxial stack including an N-type semiconductor layer, an active region, and a P-type semiconductor layer, wherein the substrate, the N-type semiconductor layer, the active region, and the P-type semiconductor layer are sequentially Cascade
  • a reflective layer wherein the reflective layer is stacked on the P-type semiconductor layer
  • a first insulating layer is laminated on the bonding layer, wherein the first insulating layer has at least a first channel and at least a second channel, and the first channel extends to the N-type semiconductor layer.
  • the second channel extends to the barrier layer;
  • An extended electrode layer including a first extended electrode portion and a second extended electrode portion, wherein the first extended electrode portion has at least one first extended electrode pin, and the first extended electrode portion is laminated on the first extended electrode portion.
  • the first extended electrode pin is formed in the first channel and is electrically connected to the N-type semiconductor layer, wherein the second extended electrode portion has at least one second extended electrode pin.
  • the second extended electrode pin is formed in the second channel and is electrically connected to the barrier layer;
  • An electrode group includes an N-type electrode and a P-type electrode, wherein the N-type electrode is electrically connected to the first extension electrode portion, and the P-type electrode is electrically connected to the second extension electrode portion.
  • the flip chip further includes a cut-off layer, which is stacked on the barrier layer, and the adhesive layer is stacked on the cut-off layer.
  • a material of the bonding layer is titanium (Ti) or cobalt (Cr).
  • a material of the cut-off layer is selected from a material group consisting of nickel (Ni), platinum (Pt), and zirconium (Zr).
  • the epitaxial stack has at least one semiconductor exposed portion extending from the P-type semiconductor layer through the active region to the N-type semiconductor layer, wherein the barrier layer has at least A barrier layer perforation, wherein the exposed semiconductor portion of the epitaxial stack is communicated with the barrier layer perforation of the barrier layer, and the first insulating layer is perforated by the barrier layer and the barrier layer.
  • the exposed semiconductor portion of the epitaxial stack extends to the N-type semiconductor layer.
  • the reflective layer has at least one reflective layer perforation, wherein the exposed semiconductor portion of the epitaxial stack corresponds to the reflective layer perforation of the reflective layer, and the epitaxial stack A size of the exposed semiconductor portion is smaller than a size of the reflective layer perforation, so that a part of the surface of the P-type semiconductor layer is exposed to the reflective layer perforation, thereby allowing the barrier layer to be stacked on the P-type semiconductor The layer is exposed on the perforated surface of the reflective layer.
  • the length and width dimensions of the reflective layer are smaller than the length and width dimensions of the P-type semiconductor layer, so that the peripheral edge of the P-type semiconductor layer is exposed, thereby allowing the barrier layer to be stacked on the substrate.
  • the exposed periphery of the P-type semiconductor layer is described.
  • the epitaxial stack has at least one exposed portion of the substrate, which extends from the P-type semiconductor layer to the substrate through the active region and the N-type semiconductor layer, wherein The first insulating layer is stacked on the substrate so as to be held on the exposed portion of the substrate.
  • the exposed portion of the substrate surrounds the periphery of the epitaxial stack.
  • the reflective layer is a reflective layer of a multilayer laminated structure.
  • the reflective layer includes a first reflective metal material layer and a second reflective metal material layer, the first reflective metal material layer is stacked on the P-type semiconductor layer, and the second A reflective metal material layer is laminated on the first reflective metal material layer, wherein the material of the first reflective metal material layer is selected from the group consisting of aluminum (Al), silver (Ag), platinum (Pt), and gold (Au).
  • the barrier layer is a barrier layer of a multilayer laminated structure.
  • the barrier layer includes a first barrier metal material layer and a second barrier metal material layer, and the first barrier metal material layer is laminated on the reflective layer so as to cover the reflective layer.
  • a P-type semiconductor layer, the second barrier metal material layer is laminated on the first barrier metal material layer, wherein the material of the first barrier metal material layer is selected from the group consisting of nickel (Ni), titanium (Ti), and chromium ( Cr), and the material of the second barrier metal material layer is selected from the group consisting of platinum (Pt), titanium (Ti), tungsten (W), and nickel (Ni).
  • the thickness of the reflective layer ranges from 100 nm to 1000 nm.
  • the minimum thickness dimension of the barrier layer ranges from 0.1 ⁇ m to 3 ⁇ m.
  • the flip-chip light-emitting chip further includes a second insulating layer laminated on the first extended electrode portion, the second extended electrode portion, and the first insulating layer, wherein
  • the second insulating layer has at least a third channel and at least a fourth channel.
  • the third channel extends to the first extended electrode portion
  • the fourth channel extends to the second extended electrode portion.
  • the N-type electrode has at least one N-type electrode connection pin. When the N-type electrode is stacked on the second insulating layer, the N-type electrode connection pin is formed in the third channel and is electrically connected to the first channel.
  • An extended electrode portion wherein the P-type electrode has at least one P-type electrode connection pin, and when the P-type electrode is laminated on the second insulating layer, the P-type electrode connection pin is formed in the fourth channel And is electrically connected to the second extension electrode portion.
  • the present invention further provides a manufacturing method of a flip chip, wherein the manufacturing method includes the following steps:
  • An N-type electrode is electrically connected to the first extension electrode portion and a P-type electrode is electrically connected to the second extension electrode portion, respectively, so as to obtain the flip chip.
  • the manufacturing method before the step (d), further includes a step of laminating a cut-off layer on the barrier layer, so that in the step (d), the bonding is laminated Layer on the cut-off layer.
  • the method further includes the following steps:
  • the first insulating material base layer is etched in sections to form the first channel.
  • the first insulating material base layer is etched in sections to form the second channel.
  • the first insulating material base layer is etched first, and the interface layer formed on the N-type semiconductor layer when the first insulating material base layer is etched is then etched, To form the first channel extending to the N-type semiconductor layer.
  • the first insulating material base layer is first etched, and then the interface layer formed on the barrier layer when the first insulating material base layer is etched is formed to form The second channel extends to the barrier layer.
  • the first insulating material base layer is first etched with a mixed gas of argon (Ar), trifluoromethane (CHF3), and oxygen (O2), and secondly, argon ( Ar), a mixed gas of any two or three of chlorine gas (Cl2) and boron trichloride (BCl3) etches the interface layer.
  • the epitaxial stack in the step (a), is etched to form the P-type semiconductor layer extending from the epitaxial stack to an N-type through an active region. At least one semiconductor exposed portion of the semiconductor layer, and in the step (c), the barrier layer is formed as a barrier layer perforation communicating with the semiconductor exposed portion, so that in the step (e), the first An insulating layer extends to the N-type semiconductor layer through the barrier layer perforation and the semiconductor exposed portion.
  • the epitaxial stack is etched to form the P-type semiconductor layer from the epitaxial stack via the active region and the N-type.
  • the semiconductor layer extends to a substrate exposed portion of the substrate, and in the step (e), the first insulating layer is stacked on the substrate so as to remain on the substrate exposed portion.
  • the epitaxial stack is etched along the periphery of the epitaxial stack, so that in the step (e), the first insulating layer The periphery of the epitaxial stack is covered in a manner of being stacked on the substrate.
  • the blocking layer is laminated on a part of the surface of the P-type semiconductor layer exposed to the reflective layer perforation and the periphery of the P-type semiconductor layer. Covering the reflective layer.
  • the manufacturing method before the step (g), further includes a step of stacking a second insulating layer having at least a third channel and at least a fourth channel on the first extension.
  • an N-type electrode connection pin forming the N-type electrode is connected to the third channel, and the N-type electrode An electrode connection pin is electrically connected to the first extension electrode portion.
  • a P-type electrode connection pin forming the P-type electrode is connected to the first extension electrode portion.
  • Four channels, and the P-type electrode connection pin is electrically connected to the second extension electrode portion.
  • FIG. 1 is a schematic cross-sectional view of a prior art flip chip.
  • FIG. 2 is a schematic cross-sectional view of one of the manufacturing processes of a flip chip according to a preferred embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view of a second manufacturing process of the flip-chip light emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 4A is a schematic cross-sectional view of the third manufacturing process of the flip-chip light emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 4B is a schematic top view of the third manufacturing process of the flip-chip light emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 5A is a schematic cross-sectional view of the fourth manufacturing process of the flip-chip light emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 5B is a schematic top view of the fourth manufacturing process of the flip-chip light emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 6A is a schematic cross-sectional view of the fifth manufacturing process of the flip-chip light emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 6B is a schematic top view of the fifth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • FIG. 7A is a schematic cross-sectional view of the sixth manufacturing process of the flip-chip light emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 7B is a schematic top view of the sixth manufacturing process of the flip-chip light emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 8A is a schematic cross-sectional view of the seventh manufacturing process of the flip-chip light emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 8B is a schematic top view of the seventh manufacturing process of the flip chip according to the preferred embodiment of the present invention.
  • 9A is a schematic cross-sectional view of the eighth manufacturing process of the flip-chip light emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 9B is a schematic top view of the eighth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • FIG. 10A is a schematic cross-sectional view of the ninth embodiment of the manufacturing process of the flip-chip light emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 10B is a schematic top view of the ninth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • FIG. 11A is a schematic cross-sectional view of a manufacturing process of the flip-chip light emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 11B is a schematic top view of the tenth manufacturing process of the flip chip according to the above preferred embodiment of the present invention.
  • FIG. 12A is a schematic cross-sectional view of the eleventh manufacturing process of the flip-chip light-emitting chip according to the above-mentioned preferred embodiment of the present invention, which shows a top-view state of the flip-chip light-emitting chip.
  • FIG. 12B is a schematic top view of the eleventh manufacturing process of the flip-chip light-emitting chip according to the above-mentioned preferred embodiment of the present invention, which illustrates a cross-sectional state of the flip-chip light-emitting chip.
  • FIG. 13 is a schematic cross-sectional view of a modified embodiment of the flip-chip light emitting chip according to the above-mentioned preferred embodiment of the present invention, which illustrates a cross-sectional state of the flip-chip light emitting chip.
  • the flip chip includes A substrate 10, an epitaxial stack 20, a reflective layer 30, a barrier layer 40, a cut-off layer 90, an adhesive layer 100, a first insulating layer 50, an extended electrode layer 60, and a second insulating layer 70 and an electrode group 80.
  • 2 to 12B further illustrate the manufacturing process of the flip-chip light-emitting chip.
  • the manufacturing process of the flip-chip light-emitting chip will be further described and disclosed in conjunction with the manufacturing process of the flip-chip light-emitting chip.
  • the substrate 10 is not limited in the flip chip of the present invention.
  • the substrate 10 may be, but is not limited to, an aluminum oxide (Al2O3) substrate, a silicon carbide (SiC) substrate, and silicon.
  • Al2O3 aluminum oxide
  • SiC silicon carbide
  • Si silicon carbide
  • Si silicon carbide
  • Si silicon carbide
  • Si silicon carbide
  • Si silicon carbide
  • Si silicon carbide
  • Si silicon carbide
  • Si silicon.
  • Si silicon
  • GaN gallium nitride
  • GaAs gallium arsenide
  • GaP gallium phosphide
  • the epitaxial stack 20 further includes an N-type semiconductor layer 21, an active region 22 and a P-type semiconductor layer 23, wherein the N-type semiconductor layer 21 is grown on the substrate 10 to The N-type semiconductor layer 21 is stacked on the substrate 10, and the active region 22 is grown on the N-type semiconductor layer 21 so that the active region 22 is stacked on the N-type semiconductor layer 21.
  • the P-type semiconductor layer 23 is grown on the active region 22, so that the P-type semiconductor layer 23 is stacked on the active region 22.
  • the manner of stacking the epitaxial stack 20 on the substrate 10 is not limited, for example, as shown in FIGS. 12A and 12B.
  • the N-type semiconductor layer 21 can be grown from the substrate 10 by using a metal-organic chemical vapor deposition (MOCVD) equipment, and A type semiconductor layer 21 grows the active region 22, and the P type semiconductor layer 23 grows from the active region 22 to form the epitaxial stack 20 stacked on the substrate 10.
  • MOCVD metal-organic chemical vapor deposition
  • the "lamination" involved in the present invention may be a direct lamination or an indirect lamination.
  • the epitaxial lamination may be directly stacked on the substrate 10, that is, the N-type semiconductor layer 21 of the epitaxial stack 20 is directly grown on the substrate 10.
  • the N-type semiconductor layer 21 of the epitaxial stack 20 may be indirectly stacked on the substrate 10, for example, on the substrate.
  • a buffer layer may be further provided between the bottom 10 and the N-type semiconductor layer 21 of the epitaxial stack 20, that is, the buffer layer is first grown on the substrate 10, and the second layer is grown on the buffer layer.
  • the N-type semiconductor layer 21 is such that the N-type semiconductor layer 21 is indirectly stacked on the substrate 10.
  • the epitaxial stack 20 further has at least one semiconductor exposed portion 24, wherein the semiconductor exposed portion 24 extends from the P-type semiconductor layer 23 through the active region 22 to the N Type semiconductor layer 21 such that a part of the surface of the N-type semiconductor layer 21 is exposed to the semiconductor exposed portion 24.
  • the semiconductor exposed portion 24 may be formed by etching the epitaxial stack 20.
  • an inductively coupled plasma ICP may be used to sequentially dry-etch the P-type semiconductor layer 12 and the active region 13 of the epitaxial stack 20 to form a free-standing layer.
  • the P-type semiconductor layer 23 extends to the semiconductor exposed portion 24 of the N-type semiconductor layer 21 through the active region 22.
  • a part of the N-type semiconductor layer 21 is also etched so that the semiconductor exposed portion 24 is removed from the P-type
  • the semiconductor layer 23 extends to the middle of the N-type semiconductor layer 21 through the active region 22, so that the thickness dimension of the N-type semiconductor layer 21 corresponding to the semiconductor exposed portion 24 is smaller than the N-type semiconductor layer. 21 other thickness dimensions.
  • the epitaxial stack 20 further has a substrate exposed portion 25, wherein the substrate exposed portion 25 extends from the P-type semiconductor layer at an edge of the epitaxial stack 20.
  • 23 extends to the substrate 10 through the active region 22 and the N-type semiconductor layer 21 to expose edges of the substrate 10.
  • the substrate exposed portion 25 surrounds the periphery of the epitaxial stack 20 so that the peripheral edges of the substrate 10 are all exposed to the substrate exposed portion 25.
  • the middle portion of the epitaxial stack 20 may be etched first to form the semiconductor bare portion 24, and the peripheral edge of the epitaxial stack 20 may be etched secondly.
  • the substrate exposed portion 25 is formed.
  • the peripheral edge of the epitaxial stack 20 may be etched first to form the exposed part 25 of the substrate, and the second part of the epitaxial stack 20 may be etched second.
  • the semiconductor exposed portion 24 and the substrate exposed portion 25 of the epitaxial stack 20 may be formed by simultaneously etching the middle and peripheral edges of the epitaxial stack 20.
  • the semiconductor exposed portion 24 of the epitaxial stack 20 is formed on the epitaxial stack. 20, and in other possible examples of the flip-chip light emitting chip of the present invention, the semiconductor exposed portion 24 may also be formed on the edge of the epitaxial stack 20. That is, the specific position of the semiconductor exposed portion 24 is not limited in the flip-chip light emitting chip of the present invention.
  • the reflective layer 30 is grown from the P-type semiconductor layer 23 of the epitaxial stack 20, so that the reflective layer 30 is stacked on the P-type of the epitaxial stack 20.
  • the reflective layer 30 has at least one reflective layer perforation 31, wherein the semiconductor exposed portion 24 of the epitaxial stack 20 corresponds to the reflective layer perforation 31 of the reflective layer 30, so that the epitaxial stack 20
  • the exposed semiconductor portion 24 and the reflective layer perforations 31 of the reflective layer 30 communicate with each other.
  • the shape of the reflection layer perforation 31 of the reflection layer 30 is consistent with the shape of the semiconductor exposed portion 24 of the epitaxial stack 20, and the size of the reflection layer perforation 31 of the reflection layer 30
  • the size of the semiconductor bare portion 24 larger than the epitaxial stack 20 is increased.
  • a part of the surface of the semiconductor layer 23 is exposed in the reflective layer perforations 31 of the reflective layer 30.
  • the shape of the semiconductor exposed portion 24 of the epitaxial stack 20 and the reflective layer The shapes of the reflective layer perforations 31 of 30 are all circular, but it should be understood by those skilled in the art that the shape and shape of the semiconductor exposed portions 24 of the epitaxial stack 20 shown in FIGS. 5A to 6B
  • the shape of the reflective layer perforation 31 of the reflective layer 30 is only an example for exposing and explaining the content and features of the flip chip of the present invention, and it should not be considered as a reflection of the flip chip of the present invention. Limitations on the content and scope of the light-emitting chip.
  • the shape of the semiconductor exposed portion 24 of the epitaxial stack 20 and the reflection layer perforation 31 of the reflection layer 30 may be but Not limited to oval or square.
  • the length and width dimensions of the reflective layer 30 are smaller than the length and width dimensions of the P-type semiconductor layer 23 of the epitaxial stack 20.
  • the reflective layer 30 is laminated on After the P-type semiconductor layer 23 of the epitaxial stack 20, the peripheral edge of the epitaxial stack 20 may not be covered by the reflective layer 30, so as to allow the barrier layer 40 to cover the reflective layer 30 in the future. .
  • the length and width dimensions of the reflective layer 30 and the length and width dimensions of the P-type semiconductor layer 23 of the epitaxial stack 20 are also It can be the same.
  • the blocking layer 40 can cover the reflective layer 30 by growing on the substrate 10.
  • the reflective layer 30 is a multilayer laminated structure, wherein the reflective layer 30 includes a first reflective metal material layer and a second reflective metal material layer, wherein the first reflection of the reflective layer 30 A metal material layer is grown on the P-type semiconductor layer 23 of the epitaxial stack 20, and a material forming the first reflective metal material layer is selected from the group consisting of aluminum (Al), silver (Ag), platinum (Pt), and A material group composed of gold (Au), so that the first reflective metal material layer has good reflection characteristics, wherein the second reflective metal material layer of the reflective layer 30 is grown on the first reflective metal material layer And the material forming the second reflective metal material layer is selected from the group consisting of platinum (Pt), titanium (Ti), tungsten (W), and nickel (Ni), so that the second reflective metal material layer has Good blocking characteristics so that the second reflective metal material layer is laminated on the first reflective metal material layer to prevent the first reflective metal material layer from diffusing and migrating, which is important for ensuring the The stability of the reflective layer 30 is particularly important.
  • the thickness of the reflective layer 30 ranges from 100nm to 1000nm (including 100nm and 1000nm), so as to avoid the reflection performance of the reflective layer 30 being affected by the thickness of the reflective layer 30 being too thin, and avoiding the reflective layer 30 If the thickness is too thick, a large stress is generated which causes the reflection layer 30 to peel off.
  • the thickness of the reflective layer 30 ranges from 100 nm to 200 nm. Specifically, the thickness of the reflective layer 30 is 150 nm.
  • the barrier layer 40 is grown from the P-type semiconductor layer 23 and the reflection layer 30 of the epitaxial stack 20 so that the barrier layer 40 covers the reflection layer.
  • the method 30 is laminated on the P-type semiconductor layer 23 of the epitaxial stack 20.
  • the barrier layer 40 is electrically connected to the P-type semiconductor layer 23 of the epitaxial stack 20.
  • the barrier layer 40 has at least one barrier layer perforation 41, wherein the semiconductor exposed portion 24 of the epitaxial stack 20 corresponds to the barrier layer perforation 41 of the barrier layer 40 so that the epitaxial stack 20
  • the exposed semiconductor portion 24 and the blocking layer perforation 41 of the blocking layer 40 communicate with each other.
  • the shape of the barrier layer perforation 41 of the barrier layer 40 is consistent with the shape of the semiconductor exposed portion 24 of the epitaxial stack 20.
  • the size of the reflective layer perforation 31 of the reflective layer 30 is larger than the size of the semiconductor exposed portion 24 of the epitaxial stack 20, a part of the P-type semiconductor layer 23 of the epitaxial stack 20 is made.
  • the surface is exposed to the reflective layer perforations 31 of the reflective layer 30, and the blocking layer 40 can be laminated on the P-type semiconductor layer 23 of the epitaxial stack 20 to be exposed to the reflective layer 30.
  • the length and width dimensions of the reflective layer 30 are smaller than the length and width dimensions of the P-type semiconductor layer 23 of the epitaxial stack 20, so that the peripheral edge of the P-type semiconductor layer 23 of the epitaxial stack 20
  • the surface is exposed to the outside of the reflective layer 30, and the barrier layer 40 can be laminated on the peripheral surface of the P-type semiconductor layer 23 of the epitaxial stack 20. Therefore, in this preferred example of the flip-chip light emitting chip of the present invention, because the barrier layer 40 can be laminated on the P-type semiconductor layer 23 of the epitaxial stack 20, the reflective layer is exposed.
  • the surface of the reflective layer perforation 31 of 30 and the peripheral surface of the P-type semiconductor layer 23 laminated on the epitaxial stack 20 are exposed outside the reflective layer 30. Therefore, the blocking layer 40 can be The reflective layer 30 is laminated on the P-type semiconductor layer 23 of the epitaxial stack 20.
  • the barrier layer 40 is a multilayer laminated structure, wherein the barrier layer 40 includes a first barrier metal material layer and a second barrier metal material layer, wherein the first barrier of the barrier layer 40 A metal material layer is laminated on the P-type semiconductor layer 23 of the epitaxial stack 20 so as to cover the reflection layer 30, and a material forming the first barrier metal material layer is selected from the group consisting of nickel (Ni), A material group consisting of titanium (Ti) and chromium (Cr), so that the first barrier metal material layer has good adhesion characteristics, wherein the second barrier metal material layer of the barrier layer 40 is grown on the The first barrier metal material layer, and the material forming the second barrier metal material layer is selected from the group consisting of platinum (Pt), titanium (Ti), tungsten (W), and nickel (Ni), so that the The second barrier metal material layer has good barrier characteristics, so as to prevent the reflection layer 30 from causing the undesirable phenomenon of diffusion or migration, which is particularly important for ensuring the stability of the reflection layer 30.
  • the barrier layer 40 completely covers the reflective layer 20, and the minimum thickness dimension of the barrier layer 40 ranges from 0.1 ⁇ m to 3 ⁇ m (including 0.1 ⁇ m and 3 ⁇ m), so as to avoid the blocking layer 40
  • the thickness of the barrier layer 40 is too small to cover sufficiently, and the bad phenomenon of light absorption of the barrier layer 40 caused by the thickness of the barrier layer 40 is too large.
  • a thickness dimension of the barrier layer 40 is 3 ⁇ m to 15 ⁇ m thicker than a thickness dimension of the reflection layer 20.
  • the thickness dimension of the barrier layer 40 is 5 ⁇ m-12 ⁇ m thicker than the thickness dimension of the reflection layer 20.
  • the thickness dimension of the barrier layer 40 is 8 ⁇ m thicker than the thickness dimension of the reflection layer 20.
  • the minimum thickness dimension of the barrier layer 40 is a portion of the barrier layer 40 that covers the sidewall of the reflective layer 30, wherein the sidewall of the reflective layer 30 may be
  • the reflective layer 30 is used to form an inner wall of the reflective layer perforation 31, and may also be an outer peripheral wall of the reflective layer 30.
  • the blocking layer 90 is stacked on the blocking layer 40.
  • the cut-off layer 90 is laminated on the upper surface of the barrier layer 40 to cover the upper surface of the barrier layer 40.
  • the cut-off layer 90 is stacked on the upper surface and the side surface of the barrier layer 40, so that the cut-off layer 90 covers the barrier layer 40.
  • the material forming the cut-off layer 90 is selected from the group consisting of nickel (Ni), platinum (Pt), and zirconium (Zr), so that the cut-off layer 90 has good resistance to etching.
  • the adhesive layer 100 is laminated on the cut-off layer 90 to cover the surface and sides of the cut-off layer 900 with the adhesive layer 100.
  • the material forming the bonding layer 100 is titanium (Ti), cobalt (Cr), or the like.
  • the first insulating layer 50 is laminated on the adhesive layer 100, and the first insulating layer 50 passes through the barrier layer perforation 41 and the epitaxial stack of the barrier layer 40.
  • the semiconductor exposed portion 24 of the layer 20 extends to the N-type semiconductor layer 21 of the epitaxial stack 20.
  • the first insulating layer 50 further extends to the substrate 10 through the substrate exposed portion 25 of the epitaxial stack 20 to cover the epitaxial stack with the first insulating layer 50.
  • Layer 20, the barrier layer 40, and the adhesive layer 100 is held between the barrier layer 40 and the first insulating layer 50. In this manner, the adhesive layer 100 can lift the barrier layer 40 and the first insulating layer 50.
  • the bonding force between the insulating layers 50 is beneficial to ensure the reliability and stability of the flip chip.
  • the first insulating layer 50 has at least a first channel 51 and at least a second channel 52, wherein the first channel 51 and the second channel 52 are formed in a manner in which all of the first insulating layer 50
  • the first channel 51 extends to the N-type semiconductor layer 21 of the epitaxial stack 20, so that a part of the surface of the N-type semiconductor layer 21 is exposed to the first channel 51, wherein the first insulation
  • the second channel 52 of the layer 50 extends to the barrier layer 40 such that a portion of the surface of the barrier layer 40 is exposed to the second channel 52.
  • a first insulating material base layer is grown on the substrate 10, the N-type semiconductor layer 21 and the barrier layer 40 of the epitaxial stack 20.
  • the material forming the first insulating material base layer is selected from the group consisting of silicon dioxide (SiO2), silicon nitride (SiN), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), and magnesium fluoride (MgF). Material group.
  • the first insulating material base layer is etched so that the first insulating material base layer forms the first insulating layer 50, and the first channel 51 and the first channel 51 forming the first insulating layer 50 are formed. Second channel 52.
  • the material forming the first insulating layer 50 is selected from the group consisting of silicon dioxide (SiO2), silicon nitride (SiN), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), and magnesium fluoride (MgF). Composed of material groups.
  • the first insulating material base layer is etched in a segmented etching manner to form the first insulating layer 50.
  • One channel 51 the first insulating material base layer is etched with a mixed gas of argon (Ar), trifluoromethane (CHF3), and oxygen (O2).
  • Ar argon
  • CHF3 trifluoromethane
  • O2 oxygen
  • the interface layer is etched with a mixture of any two or three of argon (Ar), chlorine (Cl2), and boron trichloride (BCl3) to form the first channel 51 and pass through In this manner, a part of the surface of the N-type semiconductor layer 21 of the epitaxial stack 20 can be exposed to the first channel 51.
  • Ar argon
  • Cl2 chlorine
  • BCl3 boron trichloride
  • the first insulating material base layer is etched in a segmented etching manner to form the second channel 52 of the first insulating layer 50.
  • the first insulating material base layer is etched with a mixed gas of argon (Ar), trifluoromethane (CHF3), and oxygen (O2).
  • Ar argon
  • CHF3 trifluoromethane
  • O2 oxygen
  • the interface layer is etched with a mixture of any two or three of argon (Ar), chlorine (Cl2), and boron trichloride (BCl3) to form the second channel 52 and pass through In this way, a part of the surface of the barrier layer 40 can be exposed to the second channel 52.
  • Ar argon
  • Cl2 chlorine
  • BCl3 boron trichloride
  • the extended electrode layer 60 includes a first extended electrode portion 61 and a second extended electrode portion 62, wherein the first extended electrode portion 61 and the second extended electrode portion 62 are They are laminated on the first insulating layer 50 in a spaced-apart manner, and the first extension electrode portion 61 extends to and is electrically connected to the epitaxial stack via the first channel 51 of the first insulating layer 50.
  • the second extension electrode portion 62 extends to and is electrically connected to the barrier layer 40 through the second channel 52 of the first insulating layer 50.
  • the first extended electrode portion 61 has at least one first extended electrode pin 611, and when the first extended electrode portion 61 is laminated on the first insulating layer 50, the first extended electrode pin 61 611 is formed on and held in the first channel 51 of the first insulating layer 50. At this time, the first extension electrode pin 611 is directly in contact with the N-type semiconductor layer 21 of the epitaxial stack 20. So that the first extension electrode portion 61 extends to the N-type semiconductor layer 21 electrically connected to the epitaxial stack 20 through the first channel 51 of the first insulating layer 50.
  • the second extended electrode portion 62 has at least one second extended electrode pin 621, and when the second extended electrode portion 62 is stacked on the first insulating layer 50, the second extended electrode pin 621 The second channel 52 formed in and held by the first insulating layer 50. At this time, the second extension electrode pin 621 is directly in contact with the barrier layer 40 so that the second extension electrode portion 62 extends to and is electrically connected to the barrier layer 40 through the second channel 52 of the first insulating layer 50.
  • the material of the first extended electrode portion 61 and the second extended electrode portion 62 of the extended electrode layer 60 is a metal material, so that the first extended electrode portion 61 and the first The two extended electrode portions 62 have good electrical conduction characteristics.
  • the material forming the first extended electrode portion 61 and the second extended electrode portion 62 may be selected from the group consisting of gold (Au), aluminum (Al), cobalt (Cu), platinum (Pt), and titanium (Ti). And chromium (Cr).
  • the second insulating layer 70 is laminated on the first and second extended electrode portions 61 and 62 and the first insulating layer 50 of the extended electrode layer 60. To isolate the first extended electrode portion 61 and the second extended electrode portion 62 by the second insulating layer 70.
  • the second insulating layer 70 has at least one third channel 71 and at least one fourth channel 72, wherein the third channel 71 of the second insulating layer 70 extends to the first of the extended electrode layer 60.
  • the material forming the second insulating layer 70 is the same as the material forming the first insulating layer 50, that is, the material forming the second insulating layer 70 is selected from: silicon dioxide (SiO2), nitride Material group consisting of silicon (SiN), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), and magnesium fluoride (MgF).
  • SiO2 silicon dioxide
  • TiN nitride Material group consisting of silicon
  • TiO2 titanium dioxide
  • Ta2O5 tantalum pentoxide
  • MgF magnesium fluoride
  • the electrode group 80 includes an N-type electrode 81 and a P-type electrode 82, wherein the N-type electrode 81 and the P-type electrode 82 are stacked on the second insulating layer 70, respectively.
  • the N-type electrode 81 extends through the third channel 71 of the second insulation layer 70 to the first extension electrode portion 61 electrically connected to the extension electrode layer 60
  • the P-type The electrode 82 extends through the fourth channel 72 of the second insulating layer 70 to the second extended electrode portion 62 which is electrically connected to the extended electrode layer 60.
  • the N-type electrode 81 has at least one N-type electrode connection pin 811, and when the N-type electrode 81 is stacked on the second insulating layer 70, the N-type electrode connection pin 811 is formed on and The third channel 71 is held in the second insulating layer 70. At this time, the N-type electrode connection pin 811 directly contacts the first extension electrode portion 61, so that the N-type electrode 81 passes through The third channel 71 of the second insulating layer 70 extends to and is electrically connected to the first extension electrode portion 61.
  • the P-type electrode 82 has at least one P-type electrode connection pin 821, and when the P-type electrode 82 is stacked on the second insulating layer 70, the P-type electrode connection pin 821 is formed on and by It is held in the fourth channel 72 of the second insulating layer 70. At this time, the P-type electrode connection pin 821 is directly in contact with the second extension electrode portion 62, so that the P-type electrode 82 passes through The fourth channel 72 of the second insulating layer 70 extends to and is electrically connected to the second extension electrode portion 62.
  • the materials forming the N-type electrode 81 and the P-type electrode 82 are metal materials, so that the N-type electrode 81 and the P-type electrode 82 have good electrical conductivity characteristics.
  • the materials forming the N-type electrode 81 and the P-type electrode 82 may be selected from the group consisting of gold (Au), aluminum (Al), cobalt (Cu), platinum (Pt), titanium (Ti), and chromium (Cr ) Group of materials.
  • FIG. 13 illustrates a cross-sectional state of a modified embodiment of the flip-chip light-emitting chip, which is different from the flip-chip light-emitting chip shown in FIGS. 12A and 12B in that the flip-chip light-emitting chip shown in FIG.
  • the flip-chip light-emitting chip shown in FIG. After the barrier layer 40 is stacked on the reflective layer 30 and the P-type semiconductor layer 23 of the epitaxial stack 20 to cover the reflective layer 30, The adhesive layer 100 is on the barrier layer 40, so that the adhesive layer 100 covers the barrier layer 40. Consistent with the flip-chip light-emitting chip shown in FIGS. 12A and 12B, in this preferred example of the flip-chip light-emitting chip shown in FIG.
  • the material forming the adhesive layer 100 is Titanium (Ti) or cobalt (Cr).
  • the first insulating layer 50 is laminated on the adhesive layer 100 so that the adhesive layer 100 is held between the barrier layer 40 and the first insulating layer 50. In this way, The bonding layer 100 can improve the bonding force between the barrier layer 40 and the first insulating layer 50 to help ensure the reliability and stability of the flip chip.
  • the present invention further provides a method for manufacturing the flip chip, wherein the method includes the following steps:
  • the N-type electrode 81 is electrically connected to the first extension electrode portion 61 and the P-type electrode 82 is electrically connected to the second extension electrode portion 62, respectively, to obtain the flip-chip light emitting chip.
  • the manufacturing method includes a step of laminating the cut-off layer 90 on the barrier layer 40, so that in the step (d), the adhesive layer 100 is laminated on The cut-off layer 90.
  • step (e) further comprising the steps:
  • the first insulating material base layer is etched in sections to form the first channel 51.
  • the first insulating material base layer is etched in sections to form the second channel 52.
  • the first insulating material base layer is first etched, and then the interface layer formed on the N-type semiconductor layer 21 when the first insulating material base layer is etched is formed to form an extension to the N Type semiconductor layer 21 of said first channel 51.
  • the first insulating material base layer is first etched, and then the interface layer formed on the barrier layer 40 when the first insulating material base layer is etched is formed to form the barrier layer 40 extending to the barrier layer 40.
  • the second channel 52 is first etched, and then the interface layer formed on the barrier layer 40 when the first insulating material base layer is etched is formed to form the barrier layer 40 extending to the barrier layer 40.
  • the first insulating material base layer is etched first with a mixed gas of argon (Ar), trifluoromethane (CHF3) and oxygen (O2), and secondly argon (Ar), chlorine ( Cl2) and a mixed gas of any two or three of boron trichloride (BCl3) etches the interface layer.
  • argon Ar
  • CHF3 trifluoromethane
  • O2 oxygen
  • Cl2 chlorine
  • BCl3 boron trichloride
  • the epitaxial stack 20 is etched to form the P-type semiconductor layer 23 extending from the epitaxial stack 20 through the active region 22 to the N-type.
  • the blocking layer 40 is formed with the blocking layer perforations 41 communicating with the semiconductor exposed portions 24, so that in the step In (e), the first insulating layer 50 extends to the N-type semiconductor layer 21 through the barrier layer through-hole 41 and the semiconductor exposed portion 24.
  • the epitaxial stack 20 is etched to form the P-type semiconductor layer 23 from the epitaxial stack 20 via the active region 22 and the N-type semiconductor.
  • the layer 21 extends to the substrate exposed portion 25 of the substrate 10, and in the step (e), the first insulating layer 50 is stacked on the substrate exposed portion 25 so as to remain on the substrate exposed portion 25. Describing the substrate 10.
  • the epitaxial stack 20 is etched along the periphery of the epitaxial stack 20, so that in the step (d), the first insulating layer 50 is stacked The periphery of the epitaxial stack 20 is covered in the manner of the substrate 10.
  • the blocking layer 40 is laminated on a part of the surface of the P-type semiconductor layer 23 exposed to the reflective layer perforation 31 and the P-type semiconductor layer.
  • the peripheral layer 23 covers the reflective layer 30.
  • the manufacturing method further includes a step of laminating the second insulating layer 70 having at least one of the third channel 71 and at least one of the fourth channel 72 on the The first extended electrode portion 61, the second extended electrode portion 62, and the first insulating layer 50, wherein the third channel 71 extends to the first extended electrode portion 61, and the fourth channel 72 extends to The second extension electrode portion 62 is configured to form the N-type electrode of the N-type electrode 81 when the N-type electrode 81 is stacked on the second insulating layer 70 in the step (g).
  • a connection pin 811 is connected to the third channel 71, and the N-type electrode connection pin 811 is electrically connected to the first extension electrode portion 61.
  • the P-type electrode 82 is stacked on the second insulating layer.
  • the P-type electrode connection pin 821 forming the P-type electrode 82 is connected to the fourth channel 72, and the P-type electrode connection pin 821 is electrically connected to the second extension electrode portion 62.
  • the substrate 10, the N-type semiconductor layer 21, the active region 22, and the P-type semiconductor layer 23 of the flip-chip light emitting chip shown in the drawings of the present invention The reflective layer 30, the barrier layer 40, the cut-off layer 90, the adhesive layer 100, the first insulating layer 50, the first extended electrode portion 61, and the second extended electrode portion 62.
  • the thickness of the second insulating layer 70, the N-type electrode 81, and the P-type electrode 82 are merely examples, and do not represent the substrate 10, the N-type semiconductor layer 21, the Source region 22, the P-type semiconductor layer 23, the reflective layer 30, the barrier layer 40, the cut-off layer 90, the adhesive layer 100, the first insulating layer 50, and the first extension
  • the true thicknesses of the electrode portion 61, the second extended electrode portion 62, the second insulating layer 70, the N-type electrode 81, and the P-type electrode 82 are merely examples, and do not represent the substrate 10, the N-type semiconductor layer 21, the Source region 22, the P-type semiconductor layer 23, the reflective layer 30, the barrier layer 40, the cut-off layer 90, the adhesive layer 100, the first insulating layer 50, and the first extension.
  • the substrate 10 the N-type semiconductor layer 21, the active region 22, the P-type semiconductor layer 23, the reflection layer 30, the barrier layer 40, the cut-off layer 90,
  • the bonding layer 100 the first insulating layer 50, the first extended electrode portion 61, the second extended electrode portion 62, the second insulating layer 70, the N-type electrode 81, and the P
  • the true ratio between the type electrodes 82 is also not as shown in the drawings.
  • the ratio of the sizes of the N-type electrode 81 and the P-type electrode 82 to the sizes of other layers of the flip-chip light-emitting chip is not limited to those shown in the drawings.

Abstract

一倒装发光芯片及其制造方法，其中所述倒装发光芯片包括一衬底(10)和自所述衬底依次生长的一N型半导体层(21)、一有源区(22)、一P型半导体层(23)、一反射层(30)、一阻挡层(40)、一粘结层(100)、一第一绝缘层(50)、一扩展电极层(60)、一第二绝缘层(70)、一N型电极(81)和一P型电极(82)，所述第一绝缘层(50)具有至少一第一通道(51)和至少一第二通道(52)，所述扩展电极层(60)的一第一扩展电极部(61)和一第二扩展电极部(62)分别层叠于所述第一绝缘层(50)，并经所述第一通道(51)延伸至所述N型半导体层(21)和经所述第二通道(52)延伸至所述阻挡层(40)，其中所述第二绝缘层(70)具有至少一第三通道(71)和至少一第四通道(72)，其中所述N型电极(81)经所述第三通道(71)延伸至所述第一扩展电极部(61)，所述P型电极(82)经所述第四通道(72)延伸至所述第二扩展电极部(62)。

Description

倒装发光芯片及其制造方法 技术领域
本发明涉及半导体发光二极管，特别涉及一倒装发光芯片及其制造方法。
背景技术
近年来，发光二极管的倒装芯片及其相关技术得到了突飞猛进式的发展，其中根据倒装芯片的反射材料的不同，可以将倒装芯片区分为ITO+DBR反射结构的倒装芯片和金属反射结构(例如Ag/Al)的倒装芯片，其中因为金属反射结构(特别是Ag金属反射结构)在可见光范围具有更高的反射率，因此，金属反射结构被广泛地应用于倒装芯片中。并且，根据倒装芯片的绝缘层的对数的不同，倒装芯片可以被区分为单ISO(绝缘阻挡层)结构的倒装芯片和双ISO结构的倒装芯片，相对于单ISO结构的倒装芯片来说，双ISO结构的倒装芯片的电流能够被扩展的更均匀，光效更高，其被广泛地应用于汽车照明中。
图1示出了现有技术的双ISO结构的倒装芯片的剖视示意图，其中该倒装芯片藉由九道光刻制程制作。具体地说，该倒装芯片包括一衬底10P、一外延叠层20P、一反射层30P、一阻挡层40P、一N欧姆接触层50P、一第一绝缘层60P、一扩展电极层70P、一第二绝缘层80P以及一电极组90P。所述外延叠层20P包括一N型半导体层21P、一有源区22P以及一P型半导体层23P，其中所述衬底10P、所述N型半导体层21P、所述有源区22P以及所述P型半导体层23P依次层叠。所述外延叠层20P进一步包括至少一N型裸露部24P，其中所述N型裸露部24P自所述P型半导体层23P经所述有源区22P延伸至所述N型半导体层21P，以暴露所述N型半导体层21P的一部分表面。所述反射层30P层叠于所述P型半导体层23P，所述阻挡层40P以包覆所述反射层30P的方式层叠于所述P型半导体层23P。所述N欧姆接触层50P以被保持在所述N型裸露部24P的方式层叠于所述N型半导体层21P。所述第一绝缘层60P层叠于所述外延叠层20P、所述阻挡层40P和所述N欧姆接触层50P，其中所述第一绝缘层60P具有至少一第一通道61P和至少一第二通道62P，其中所述第一绝缘层60P的所述第一通道61P延伸至所述N欧姆接触层50P，所述第一绝缘层60P的所述第二通道62P延伸至所述阻挡层40P。所述扩展电极层70P包括至少一第一扩展电极部71P和至少一第二扩展电极部72P，其中所述第一扩展电极部71P层叠于所述第一绝缘层60P，并且所述第一扩展电极部71P经所述第一绝缘层60P的所述第一通道61P延伸至和电连接于所述N欧姆接触层，其中所述第二扩展电极部72P层叠于所述第一绝缘层60P，并且所述第二扩展电极部72P经所述第一绝缘层60P的所述第二通道62P延伸至和电连接于所述阻挡层40P。所述第二绝缘层80P层叠于所述第一扩展电极部71P和所述第二扩展电极部72P，并且所述第二绝缘层80P填充在形成于所述第一扩展电极部71P和所述第二扩展电极部72P之间的缝隙。所述第二绝缘层80P具有至少一第三通道81P和至少一第四通道82P，其中所述第二绝缘层80P的所述第三通道81P延伸至所述第一扩展电极部71P，所述第二绝缘层80P的所述第四通道82P延伸至所述第二扩展电极部72P。所述电极组90P包括一N 型电极91P和一P型电极92P，其中所述N型电极91P层叠于所述第二绝缘层80P，并且所述N型电极91P经所述第二绝缘层80P的所述第三通道81P延伸至和电连接于所述第一扩展电极部71P，所述P型电极92P经所述第二绝缘层80P的所述第四通道82P延伸至和电连接于所述第二扩展电极部72P。
制作附图1示出的该倒装芯片的制程较为复杂，其包括Mesa制程、DE制程、Mirror制程、Barrier制程、N接触电极制程、第一绝缘层制程、扩展电极制程、第二绝缘层制程、电极制程共九道光刻制程，这不仅导致该倒装芯片具有较高的生产成本和较低的生产效率，而且在制作该倒装芯片的过程中，光刻制程越多越容易影响该倒装芯片的稳定性和可靠性。
发明内容
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中所述倒装发光芯片的制程能够被简化，以有利于提高所述倒装发光芯片的生产效率和降低所述倒装发光芯片的制造成本。
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中所述倒装发光芯片的制程能够被简化，以有利于提高所述倒装发光芯片的产品良率和保证所述倒装发光芯片的可靠性。
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中所述倒装发光芯片提供一阻挡层和一第一绝缘层，其中所述阻挡层和所述第一绝缘层之间的结合力能够被大幅度地提升，以改善所述倒装发光芯片的可靠性。
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中所述倒装发光芯片提供一粘结层，所述粘结层被保持在所述阻挡层和所述第一绝缘层之间，以藉由所述粘结层提升所述阻挡层和所述第一绝缘层之间的结合力。
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中所述倒装发光芯片提供一截止层，所述截止层被保持在所述阻挡层和所述粘结层之间，以增加所述倒装发光芯片的制程可控性。
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中所述截止层具有良好的抗刻蚀性能，从而被保持在所述阻挡层和所述粘结层之间的所述截止层能够增加所述倒装发光芯片的制程可控性。
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中所述倒装发光芯片提供一外延叠层和一扩展电极层，所述扩展电极层的一第一扩展电极部直接接触所述外延叠层的一N型半导体层，从而所述第一扩展电极部不仅能够起到扩展电极的作用，而且还能够起到接触作用，这使得所述倒装发光芯片不需要设置N型欧姆接触层，通过这样的方式，有利于简化所述倒装发光芯片的制程。
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中所述倒装发光芯片提供一第一绝缘材料基层，其中所述第一绝缘材料基层层叠于所述外延叠层，其中在制作所述倒装发光芯片的过程中，采用分段刻蚀所述第一绝缘材料基层的方式形成一第一通道于所述第一绝缘材料基层，以使所述N型半导体层的一部分表面被暴露在所述第一通道，通过这样的方式，能够保证所述第一扩展电极部与所述N型半导体层的电气连接关系的可靠性。
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中在制造所述倒装发光芯片的过程中，首先刻蚀所述第一绝缘材料基层，其次刻蚀在刻蚀所述第一绝缘材料基层的过程中形成于所述N型半导体层的界面层，通过这样的方式，所述N型半导体层的一部分表面能够被暴露在所述第一通道，从而保证所述第一扩展电极部与所述N型半导体层的电气连接关系的可靠性。
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中在制造所述倒装发光芯片的过程中，采用分段刻蚀所述第一绝缘材料基层的方式形成一第二通道于所述第一绝缘材料基层，以使所述倒装发光芯片的阻挡层的一部分表面暴露在所述第二通道，通过这样的方式，能够保证所述扩展电极层的一第二扩展电极部于所述阻挡层的电气连接关系的可靠性。
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中在制造所述倒装发光芯片的过程中，首先刻蚀所述第一绝缘材料基层，其次刻蚀在刻蚀所述第一绝缘材料基层的过程中形成于所述阻挡层的界面层，通过这样的方式，所述阻挡层的一部分表面能够被暴露在所述第二通道，从而保证所述第二扩展电极部于所述阻挡层的电气连接关系的可靠性。
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中所述倒装发光芯片提供一反射层，其中所述反射层层叠于所述外延叠层的一P型半导体层，并且所述反射层为多层层叠结构，通过这样的方式，能够保证所述倒装发光芯片的可靠性。
本发明的一个目的在于提供一倒装发光芯片及其制造方法，其中所述阻挡层以包覆所述反射层的方式层叠于所述P型半导体层，并且所述阻挡层为多层层叠结构，通过这样的方式，所述阻挡层能够有效地防止所述反射层的扩散和迁移，从而保证所述倒装发光芯片的可靠性。
依本发明的一个方面，本发明提供一倒装发光芯片，其包括：
一衬底；
一外延叠层，其包括一N型半导体层、一有源区以及一P型半导体层，其中所述衬底、所述N型半导体层、所述有源区和所述P型半导体层依次层叠；
一反射层，其中所述反射层层叠于所述P型半导体层；
一阻挡层，其以包覆所述反射层的方式层叠于所述P型半导体层；
一粘结层，其层叠于所述阻挡层；
一第一绝缘层，其层叠于所述粘结层，其中所述第一绝缘层具有至少一第一通道和至少一第二通道，所述第一通道延伸至所述N型半导体层，所述第二通道延伸至所述阻挡层；
一扩展电极层，其包括一第一扩展电极部和一第二扩展电极部，其中所述第一扩展电极部具有至少一第一扩展电极针，在所述第一扩展电极部层叠于所述第一绝缘层时，所述第一扩展电极针形成于所述第一通道和电连接于所述N型半导体层，其中所述第二扩展电极部具有至少一第二扩展电极针，在所述第二扩展电极部层叠于所述第一绝缘层时，所述第二扩展电极针形成于所述第二通道和电连接于所述阻挡层；以及
一电极组，其包括一N型电极和一P型电极，其中所述N型电极电连接于所述第一扩展电极部，所述P型电极电连接于所述第二扩展电极部。
根据本发明的一个实施例，所述倒装发光芯片进一步包括一截止层，其层叠于所述阻挡层，所述粘结层层叠于所述截止层。
根据本发明的一个实施例，所述粘结层的材料为钛(Ti)或钴(Cr)。
根据本发明的一个实施例，所述截止层的材料选自：镍(Ni)、铂(Pt)和锆(Zr)组成的材料组。
根据本发明的一个实施例，所述外延叠层具有至少一半导体裸露部，其自所述P型半导体层经所述有源区延伸至所述N型半导体层，其中所述阻挡层具有至少一阻挡层穿孔，其中所述外延叠层的所述半导体裸露部和所述阻挡层的所述阻挡层穿孔相连通，所述第一绝缘层经所述阻挡层的所述阻挡层穿孔和所述外延叠层的所述半导体裸露部延伸至所述N型半导体层。
根据本发明的一个实施例，所述反射层具有至少一反射层穿孔，其中所述外延叠层的所述半导体裸露部对应于所述反射层的所述反射层穿孔，并且所述外延叠层的所述半导体裸露部的尺寸小于所述反射层穿孔的尺寸，以使所述P型半导体层的一部分表面被暴露在所述反射层穿孔，从而允许所述阻挡层层叠于所述P型半导体层的被暴露在所述反射层穿孔的表面。
根据本发明的一个实施例，所述反射层的长宽尺寸小于所述P型半导体层的长宽尺寸，以使所述P型半导体层的周缘被暴露，从而允许所述阻挡层层叠于所述P型半导体层的被暴露的周缘。
根据本发明的一个实施例，所述外延叠层具有至少一衬底裸露部，其自所述P型半导体层经所述有源区和所述N型半导体层延伸至所述衬底，其中所述第一绝缘层以被保持在所述衬底裸露部的方式层叠于所述衬底。
根据本发明的一个实施例，所述衬底裸露部环绕所述外延叠层的四周。
根据本发明的一个实施例，所述反射层是一个多层层叠结构的反射层。
根据本发明的一个实施例，所述反射层包括一第一反射金属材料层和一第二反射金属材料层，所述第一反射金属材料层层叠于所述P型半导体层，所述第二反射金属材料层层叠于所述第一反射金属材料层，其中所述第一反射金属材料层的材料选自：铝(Al)、银(Ag)、铂(Pt)和金(Au)组成的材料组，其中所述第二反射金属材料层的材料选自：铂(Pt)、钛(Ti)、钨(W)、镍(Ni)组成的材料组。
根据本发明的一个实施例，所述阻挡层是一个多层层叠结构的阻挡层。
根据本发明的一个实施例，所述阻挡层包括一第一阻挡金属材料层和一第二阻挡金属材料层，所述第一阻挡金属材料层以包覆所述反射层的方式层叠于所述P型半导体层，所述第二阻挡金属材料层层叠于所述第一阻挡金属材料层，其中所述第一阻挡金属材料层的材料选自：镍(Ni)、钛(Ti)和铬(Cr)组成的材料组，所述第二阻挡金属材料层的材料选自：铂(Pt)、钛(Ti)、钨(W)、镍(Ni)组成的材料组。
根据本发明的一个实施例，所述反射层的厚度尺寸范围为100nm-1000nm。
根据本发明的一个实施例，所述阻挡层的最小厚度尺寸范围为0.1μm-3μm。
根据本发明的一个实施例，所述倒装发光芯片进一步包括一第二绝缘层，其层叠于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第二绝缘层具有至少一第三通道和至少一第四通道，所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸至所述第二扩展电极部，其中所述N型电极具有至少一N型电极连接针，在所述N型电极 层叠于所述第二绝缘层时，所述N型电极连接针形成于所述第三通道和电连接于所述第一扩展电极部，其中所述P型电极具有至少一P型电极连接针，在所述P型电极层叠于所述第二绝缘层时，所述P型电极连接针形成于所述第四通道和电连接于所述第二扩展电极部。
依本发明的另一个方面，本发明进一步提供一倒装发光芯片的制造方法，其中所述制造方法包括如下步骤：
(a)层叠一外延叠层于所述衬底；
(b)层叠一反射层于所述外延叠层的一P型半导体层；
(c)以包覆所述反射层的方式层叠一阻挡层于所述P型半导体层；
(d)层叠一粘结层于所述阻挡层；
(e)层叠具有至少一第一通道和至少一第二通道的一第一绝缘层于所述粘结层，其中所述第一通道延伸至所述外延叠层的一N型半导体层，所述第二通道延伸至所述阻挡层；
(f)在层叠一第一扩展电极部于所述第一绝缘层时，形成所述第一扩展电极部的一第一扩展电极针于所述第一绝缘层的所述第一通道，并且所述第一扩展电极针电连接于所述N型半导体层，相应地，在层叠一第二扩展电极部于所述第一绝缘层时，形成所述第二扩展电极部的一第二扩展电极针于所述第一绝缘层的所述第二通道，并且所述第二扩展电极针连接于所述阻挡层；以及
(g)分别电连接一N型电极于所述第一扩展电极部和电连接一P型电极于所述第二扩展电极部，以制得所述倒装发光芯片。
根据本发明的一个实施例，在所述步骤(d)之前，所述制造方法进一步包括步骤：层叠一截止层于所述阻挡层，从而在所述步骤(d)中，层叠所述粘结层于所述截止层。
根据本发明的一个实施例，在所述步骤(e)中，进一步包括步骤：
(e.1)层叠一第一绝缘材料基层于所述粘结层；和
(e.2)刻蚀所述第一绝缘材料基层，以形成具有所述第一通道和所述第二通道的所述第一绝缘层。
根据本发明的一个实施例，在所述步骤(e.2)中，分段刻蚀所述第一绝缘材料基层，以形成所述第一通道。
根据本发明的一个实施例，在所述步骤(e.2)中，分段刻蚀所述第一绝缘材料基层，以形成所述第二通道。
根据本发明的一个实施例，在上述方法中，首先刻蚀所述第一绝缘材料基层，其次刻蚀在刻蚀所述第一绝缘材料基层时形成于所述N型半导体层的界面层，以形成延伸至所述N型半导体层的所述第一通道。
根据本发明的一个实施例，在上述方法中，首先刻蚀所述第一绝缘材料基层，其次刻蚀在刻蚀所述第一绝缘材料基层时形成于所述阻挡层的界面层，以形成延伸至所述阻挡层的所述第二通道。
根据本发明的一个实施例，在上述方法中，首先使用氩气(Ar)、三氟甲烷(CHF3)和氧气(O2)的混合气体刻蚀所述第一绝缘材料基层，其次使用氩气(Ar)、氯气(Cl2)和三氯化硼(BCl3)中的任意两者或三者的混合气体刻蚀所述界面层。
根据本发明的一个实施例，在所述步骤(a)中，刻蚀所述外延叠层以形成自所述外延 叠层的所述P型半导体层经一有源区延伸至所述N型半导体层的至少一半导体裸露部，和在所述步骤(c)中，使所述阻挡层形成连通所述半导体裸露部的一阻挡层穿孔，以在所述步骤(e)中，所述第一绝缘层经所述阻挡层穿孔和所述半导体裸露部延伸至所述N型半导体层。
根据本发明的一个实施例，在所述步骤(a)中，刻蚀所述外延叠层以形成自所述外延叠层的所述P型半导体层经所述有源区和所述N型半导体层延伸至所述衬底的一衬底裸露部，以在所述步骤(e)中，所述第一绝缘层以保持在所述衬底裸露部的方式层叠于所述衬底。
根据本发明的一个实施例，在所述步骤(a)中，沿着所述外延叠层的四周刻蚀所述外延叠层，从而在所述步骤(e)中，所述第一绝缘层以层叠于所述衬底的方式包覆所述外延叠层的四周。
根据本发明的一个实施例，在所述步骤(b)中，暴露所述P型半导体层的一部分表面于所述反射层的一反射层穿孔和暴露所述P型半导体层的周缘于所述反射层的四周，以在所述步骤(c)中，所述阻挡层以层叠于所述P型半导体层的暴露于所述反射层穿孔的一部分表面和所述P型半导体层的周缘的方式包覆所述反射层。
根据本发明的一个实施例，在所述步骤(g)之前，所述制造方法进一步包括步骤：层叠具有至少一第三通道和至少一第四通道的一第二绝缘层于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸至所述第二扩展电极部，以在所述步骤(g)中，在层叠所述N型电极于所述第二绝缘层时，形成所述N型电极的一N型电极连接针于所述第三通道，并且所述N型电极连接针电连接于所述第一扩展电极部，相应地，在层叠所述P型电极于所述第二绝缘层时，形成所述P型电极的一P型电极连接针于所述第四通道，并且所述P型电极连接针电连接于所述第二扩展电极部。
附图说明
图1是现有技术的一倒装芯片的剖视示意图。
图2是依本发明的一较佳实施例的一倒装发光芯片的制作过程之一的剖视示意图。
图3是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之二的剖视示意图。
图4A是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之三的剖视示意图。
图4B是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之三的俯视示意图。
图5A是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之四的剖视示意图。
图5B是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之四的俯视示意图。
图6A是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之五的剖视示意图。
图6B是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之五的俯视示意图。
图7A是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之六的剖视示意图。
图7B是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之六的俯视示意图。
图8A是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之七的剖视示意图。
图8B是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之七的俯视示意图。
图9A是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之八的剖视示意图。
图9B是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之八的俯视示意图。
图10A是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之九的剖视示意图。
图10B是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之九的俯视示意图。
图11A是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之使的剖视示意图。
图11B是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之十的俯视示意图。
图12A是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之十一的剖视示意图，其示出了所述倒装发光芯片的俯视状态。
图12B是依本发明的上述较佳实施例的所述倒装发光芯片的制作过程之十一的俯视示意图，其示出了所述倒装发光芯片的剖视状态。
图13是依本发明的上述较佳实施例的所述倒装发光芯片的一个变形实施方式的剖视示意图，其示意了所述倒装发光芯片的剖视状态。
具体实施方式
以下描述用于揭露本发明以使本领域技术人员能够实现本发明。以下描述中的优选实施例只作为举例，本领域技术人员可以想到其他显而易见的变型。在以下描述中界定的本发明的基本原理可以应用于其他实施方案、变形方案、改进方案、等同方案以及没有背离本发明的精神和范围的其他技术方案。
本领域技术人员应理解的是，在本发明的揭露中，术语“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系是基于附图所示的方位或位置关系，其仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位 构造和操作，因此上述术语不能理解为对本发明的限制。
可以理解的是，术语“一”应理解为“至少一”或“一个或多个”，即在一个实施例中，一个元件的数量可以为一个，而在另外的实施例中，该元件的数量可以为多个，术语“一”不能理解为对数量的限制。
参考本发明的说明书附图之附图12A和图12B，依本发明的一较佳实施例的一倒装发光芯片在接下来的描述中被揭露和被阐述，其中所述倒装发光芯片包括一衬底10、一外延叠层20、一反射层30、一阻挡层40、一截止层90、一粘结层100、一第一绝缘层50、一扩展电极层60、一第二绝缘层70以及一电极组80。
附图2至图12B进一步示出了所述倒装发光芯片的制造过程，在接下来的描述中，将结合所述倒装发光芯片的制造过程进一步描述和揭露所述倒装发光芯片的所述衬底10、所述外延叠层20、所述反射层30、所述阻挡层40、所述截止层90、所述粘结层100、所述第一绝缘层50、所述扩展电极层60、所述第二绝缘层70以及所述电极组80之间的关系。
参考附图2示出了所述衬底10的剖视状态。所述衬底10的类型在本发明的所述倒装发光芯片中不受限制，例如所述衬底10可以是但不限于氧化铝(Al2O3)衬底、碳化硅(SiC)衬底、硅(Si)衬底、氮化镓(GaN)衬底、砷化镓(GaAs)衬底和磷化镓(GaP)衬底。
参考附图3，所述外延叠层20进一步包括一N型半导体层21、一有源区22以及一P型半导体层23，其中所述N型半导体层21生长于所述衬底10，以使所述N型半导体层21层叠于所述衬底10，其中所述有源区22生长于所述N型半导体层21，以使所述有源区22层叠于所述N型半导体层21，其中所述P型半导体层23生长于所述有源区22，以使所述P型半导体层23层叠于所述有源区22。
值得一提的是，在本发明的所述倒装发光芯片中，在所述衬底10上层叠所述外延叠层20的方式不受限制，例如在附图12A和图12B示出的所述倒装发光芯片的这个较佳示例中，可以利用金属有机化合物化学气相沉淀设备(Metal-organic Chemical Vapor Deposition，MOCVD)自所述衬底10生长所述N型半导体层21、自所述N型半导体层21生长所述有源区22、自所述有源区22生长所述P型半导体层23，以形成层叠于所述衬底10的所述外延叠层20。
值得一提的是，本发明中所涉及的“层叠”可以是直接层叠，也可以是间接层叠，例如，在本发明的所述倒装发光芯片的一个较佳示例中，所述外延叠层20的所述N型半导体层21可以直接地层叠于所述衬底10，即，在所述衬底10上直接生长所述外延叠层20的所述N型半导体层21。而在本发明的所述倒装发光芯片的另一个较佳示例中，所述外延叠层20的所述N型半导体层21可以间接地层叠于所述衬底10，例如，在所述衬底10和所述外延叠层20的所述N型半导体层21之间还可以设置有缓冲层，即，首先在所述衬底10上生长所述缓冲层，其次在所述缓冲层上生长所述N型半导体层21，从而使得所述N型半导体层21间接地层叠于所述衬底10。
参考附图4A和图4B，所述外延叠层20进一步具有至少一半导体裸露部24，其中所述半导体裸露部24自所述P型半导体层23经所述有源区22延伸至所述N型半导体层21，以使所述N型半导体层21的一部分表面被暴露在所述半导体裸露部24。
优选地，在所述外延叠层20层叠于所述衬底10之后，可以通过刻蚀所述外延叠层20 的方式形成所述半导体裸露部24。具体地说，可以使用感应耦合等离子体(Inductively Coupled Plasma，ICP)依次对所述外延叠层20的所述P型半导体层12和所述有源区13进行干法刻蚀，以形成自所述P型半导体层23经所述有源区22延伸至所述N型半导体层21的所述半导体裸露部24。
在附图12A和图12B示出的所述倒装发光芯片的这个较佳示例中，所述N型半导体层21的一部分也被刻蚀，以使所述半导体裸露部24自所述P型半导体层23经所述有源区22延伸至所述N型半导体层21的中部，从而使得所述N型半导体层21的对应于所述半导体裸露部24的厚度尺寸小于所述N型半导体层21的其他部分的厚度尺寸。
优选地，参考附图5A和图5B，所述外延叠层20进一步具有一衬底裸露部25，其中所述衬底裸露部25在所述外延叠层20的边缘自所述P型半导体层23经所述有源区22和所述N型半导体层21延伸至所述衬底10，以暴露所述衬底10的边缘。优选地，所述衬底裸露部25环绕在所述外延叠层20的一周，从而使得所述衬底10的周缘均被暴露在所述衬底裸露部25。
在本发明的所述倒装发光芯片的一个较佳示例中，可以首先刻蚀所述外延叠层20的中部以形成所述半导体裸露部24，其次刻蚀所述外延叠层20的周缘以形成所述衬底裸露部25。在本发明的所述倒装发光芯片的另一个较佳示例中，可以首先刻蚀所述外延叠层20的周缘以形成所述衬底裸露部25，其次刻蚀所述外延叠层20的中部以形成所述半导体裸露部24。优选地，所述外延叠层20的所述半导体裸露部24和所述衬底裸露部25可以通过同时刻蚀所述外延叠层20的中部和周缘的方式形成。
值得一提的是，尽管在附图2至图12B示出的所述倒装发光芯片的这个较佳示例中，所述外延叠层20的所述半导体裸露部24形成于所述外延叠层20的中部，而在本发明的所述倒装发光芯片的其他可能示例中，所述半导体裸露部24也可以形成于所述外延叠层20的边缘。也就是说，所述半导体裸露部24的具体位置在本发明的所述倒装发光芯片中不受限制。
参考附图6A和图6B，自所述外延叠层20的所述P型半导体层23生长所述反射层30，以使所述反射层30层叠于所述外延叠层20的所述P型半导体层23。所述反射层30具有至少一反射层穿孔31，其中所述外延叠层20的所述半导体裸露部24对应于所述反射层30的所述反射层穿孔31，以使所述外延叠层20的所述半导体裸露部24和所述反射层30的所述反射层穿孔31相互连通。优选地，所述反射层30的所述反射层穿孔31的形状与所述外延叠层20的所述半导体裸露部24的形状一致，并且所述反射层30的所述反射层穿孔31的尺寸大于所述外延叠层20的所述半导体裸露部24的尺寸，通过这样的方式，在所述反射层30层叠于所述外延叠层20的所述P型半导体层23之后，所述P型半导体层23的一部分表面被暴露在所述反射层30的所述反射层穿孔31。
值得一提的是，尽管在附图5A至图6B示出的所述倒装发光芯片的这个较佳的示例中所述外延叠层20的所述半导体裸露部24的形状和所述反射层30的所述反射层穿孔31的形状均为圆形，但是本领域技术应当理解的是，附图5A至图6B示出的所述外延叠层20的所述半导体裸露部24的形状和所述反射层30的所述反射层穿孔31的形状仅是举例，以用于揭露和阐述本发明的所述倒装发光芯片的内容和特征，其并不应被视为对本发明的所述倒装 发光芯片的内容和范围的限制。例如，在本发明的所述倒装发光芯片的其他可能的示例中，所述外延叠层20的所述半导体裸露部24的形状和所述反射层30的所述反射层穿孔31可以是但不限于椭圆形或者方形。
优选地，参考附图6A和图6B，所述反射层30的长宽尺寸小于所述外延叠层20的所述P型半导体层23的长宽尺寸，这样，在所述反射层30层叠于所述外延叠层20的所述P型半导体层23之后，所述外延叠层20的周缘可以没有被所述反射层30覆盖，以在后续允许所述阻挡层40包覆所述反射层30。
值得一提的是，在本发明的所述倒装发光芯片的其他示例中，所述反射层30的长宽尺寸与所述外延叠层20的所述P型半导体层23的长宽尺寸也可以相同，在后续，所述阻挡层40可以通过生长于所述衬底10的方式包覆所述反射层30。
进一步地，所述反射层30是一个多层层叠结构，其中所述反射层30包括一第一反射金属材料层和一第二反射金属材料层，其中所述反射层30的所述第一反射金属材料层生长于所述外延叠层20的所述P型半导体层23，并且形成所述第一反射金属材料层的材料选自：铝(Al)、银(Ag)、铂(Pt)和金(Au)组成的材料组，从而使得所述第一反射金属材料层具有良好的反射特性，其中所述反射层30的所述第二反射金属材料层生长于所述第一反射金属材料层，并且形成所述第二反射金属材料层的材料选自：铂(Pt)、钛(Ti)、钨(W)、镍(Ni)组成的材料组，从而所述第二反射金属材料层具有良好的阻挡特征，以使得所述第二反射金属材料层以层叠于所述第一反射金属材料层的方式防止所述第一反射金属材料层出现扩散和迁移的不良现象，这对于保证所述反射层30的稳定性来说是特别重要的。
所述反射层30的厚度范围为100nm-1000nm(包括100nm和1000nm)，以避免因所述反射层30的厚度过薄而影响所述反射层30的反射性能，和避免因所述反射层30的厚度过厚而产生导致所述反射层30剥落的较大应力。优选地，所述反射层30的厚度范围为100nm-200nm。具体地说，所述反射层30的厚度尺寸为150nm。
参考附图7A和图7B，自所述外延叠层20的所述P型半导体层23和所述反射层30生长所述阻挡层40，以使所述阻挡层40以包覆所述反射层30的方式层叠于所述外延叠层20的所述P型半导体层23。所述阻挡层40电连接于所述外延叠层20的所述P型半导体层23。所述阻挡层40具有至少一阻挡层穿孔41，其中所述外延叠层20的所述半导体裸露部24对应于所述阻挡层40的所述阻挡层穿孔41，以使所述外延叠层20的所述半导体裸露部24和所述阻挡层40的所述阻挡层穿孔41相互连通。优选地，所述阻挡层40的所述阻挡层穿孔41的形状与所述外延叠层20的所述半导体裸露部24的形状一致。
因为所述反射层30的所述反射层穿孔31的尺寸大于所述外延叠层20的所述半导体裸露部24的尺寸，从而使得所述外延叠层20的所述P型半导体层23的一部分表面被暴露在所述反射层30的所述反射层穿孔31，进而所述阻挡层40能够层叠于所述外延叠层20的所述P型半导体层23的被暴露在所述反射层30的所述反射层穿孔31的表面。另外，因为所述反射层30的长宽尺寸小于所述外延叠层20的所述P型半导体层23的长宽尺寸，从而使得所述外延叠层20的所述P型半导体层23的周缘表面被暴露在所述反射层30的外部，进而所述阻挡层40能够层叠于所述外延叠层20的所述P型半导体层23的周缘表面。因此， 在本发明的所述倒装发光芯片的这个较佳示例中，因为所述阻挡层40能够层叠于所述外延叠层20的所述P型半导体层23的被暴露在所述反射层30的所述反射层穿孔31的表面和层叠于所述外延叠层20的所述P型半导体层23的被暴露在所述反射层30外部的周缘表面，因此，所述阻挡层40能够以包覆所述反射层30的方式层叠于所述外延叠层20的所述P型半导体层23。
进一步地，所述阻挡层40是一个多层层叠结构，其中所述阻挡层40包括一第一阻挡金属材料层和一第二阻挡金属材料层，其中所述阻挡层40的所述第一阻挡金属材料层以包覆所述反射层30的方式层叠于所述外延叠层20的所述P型半导体层23，并且形成所述第一阻挡金属材料层的材料选自：镍(Ni)、钛(Ti)和铬(Cr)组成的材料组，从而使得所述第一阻挡金属材料层具有良好的粘附特性，其中所述阻挡层40的所述第二阻挡金属材料层生长于所述第一阻挡金属材料层，并且形成所述第二阻挡金属材料层的材料选自：铂(Pt)、钛(Ti)、钨(W)、镍(Ni)组成的材料组，以使得所述第二阻挡金属材料层具有良好的阻挡特性，从而防止所述反射层30出现扩散或迁移的不良现象，这对于保证所述反射层30的稳定性来说是特别重要的。
也就是说，所述阻挡层40完全包覆所述反射层20，其中所述阻挡层40的最小厚度尺寸范围为0.1μm-3μm(包括0.1μm和3μm)，以避免因所述阻挡层40的厚度过小而无法充分包覆，和避免因所述阻挡层40的厚度过大而导致所述阻挡层40出现吸光的不良现象。另外，所述阻挡层40的厚度尺寸比所述反射层20的厚度尺寸厚3μm-15μm。优选地，所述阻挡层40的厚度尺寸比所述反射层20的厚度尺寸厚5μm-12μm。具体地说，所述阻挡层40的厚度尺寸比所述反射层20的厚度尺寸厚8μm。
值得一提的是，通常情况下，所述阻挡层40的最小厚度尺寸为所述阻挡层40包覆所述反射层30的侧壁的部分，其中所述反射层30的侧壁可以是所述反射层30用于形成所述反射层穿孔31的内壁，也可以是所述反射层30的外周壁。
参考附图8A和图8B，层叠所述截止层90于所述阻挡层40。在本发明的所述倒装发光芯片的一个较佳示例中，所述截止层90层叠于所述阻挡层40的上表面以包覆所述阻挡层40的上表面。在本发明的所述倒装发光芯片的另一个较佳示例中，所述截止层90层叠于所述阻挡层40的上表面和侧表面，从而所述截止层90包覆所述阻挡层40。优选地，形成所述截止层90的材料选自：镍(Ni)、铂(Pt)和锆(Zr)组成的材料组，从而使得所述截止层90具有良好的抗蚀刻性能。
继续参考附图8A和图8B，层叠所述粘结层100于所述截止层90，以藉由所述粘结层100包覆所述截止层900的表面和侧面。优选地，形成所述粘结层100的材料为钛(Ti)或钴(Cr)等。
参考附图9A和图9B，层叠所述第一绝缘层50于所述粘结层100，并且所述第一绝缘层50经所述阻挡层40的所述阻挡层穿孔41和所述外延叠层20的所述半导体裸露部24延伸至所述外延叠层20的所述N型半导体层21。优选地，所述第一绝缘层50进一步经所述外延叠层20的所述衬底裸露部25延伸至所述衬底10，以藉由所述第一绝缘层50包覆所述外延叠层20、所述阻挡层40和所述粘结层100。并且，所述粘结层100被保持在所述阻挡层40和所述第一绝缘层50之间，通过这样的方式，所述粘结层100能够提升所述阻挡层 40和所述第一绝缘层50之间的结合力，以有利于保证所述倒装发光芯片的可靠性和稳定性。
所述第一绝缘层50具有至少一第一通道51和至少一第二通道52，其中所述第一通道51和所述第二通道52的方式形成，其中所述第一绝缘层50的所述第一通道51延伸至所述外延叠层20的所述N型半导体层21，以使所述N型半导体层21的一部分表面被暴露在所述第一通道51，其中所述第一绝缘层50的所述第二通道52延伸至所述阻挡层40，以使所述阻挡层40的一部分表面被暴露在所述第二通道52。
具体地说，首先，在所述衬底10、所述外延叠层20的所述N型半导体层21和所述阻挡层40生长一第一绝缘材料基层。优选地，形成所述第一绝缘材料基层的材料选自：二氧化硅(SiO2)、氮化硅(SiN)、二氧化钛(TiO2)、五氧化二钽(Ta2O5)和氟化镁(MgF)组成的材料组。其次，刻蚀所述第一绝缘材料基层，以使所述第一绝缘材料基层形成所述第一绝缘层50，和形成所述第一绝缘层50的所述第一通道51和所述第二通道52。也就是说，形成所述第一绝缘层50的材料选自：二氧化硅(SiO2)、氮化硅(SiN)、二氧化钛(TiO2)、五氧化二钽(Ta2O5)和氟化镁(MgF)组成的材料组。
优选地，在本发明的所述倒装发光芯片的一个较佳示例中，以分段刻蚀的方式刻蚀所述第一绝缘材料基层，以形成所述第一绝缘层50的所述第一通道51。具体地说，首先，采用氩气(Ar)、三氟甲烷(CHF3)和氧气(O2)的混合气体刻蚀所述第一绝缘材料基层。可以理解的是，在利用氩气、三氟甲烷和氧气的混合气体刻蚀所述第一绝缘材料基层的过程中与所述外延叠层20的所述N型半导体层21接触时，会在所述N型半导体层21的表面形成界面层。其次，采用氩气(Ar)、氯气(Cl2)和三氯化硼(BCl3)中的任意两者或三者的混合气体刻蚀所述界面层，以形成所述第一通道51，并且通过这样的方式，所述外延叠层20的所述N型半导体层21的一部分表面能够被暴露在所述第一通道51。
相应地，以分段刻蚀的方式刻蚀所述第一绝缘材料基层，以形成所述第一绝缘层50的所述第二通道52。具体地说，首先，采用氩气(Ar)、三氟甲烷(CHF3)和氧气(O2)的混合气体刻蚀所述第一绝缘材料基层。可以理解的是，在利用氩气、三氟甲烷和氧气的混合气体刻蚀所述第一绝缘材料基层的过程中与所述阻挡层40接触时，会在所述阻挡层40的表面形成界面层。其次，采用氩气(Ar)、氯气(Cl2)和三氯化硼(BCl3)中的任意两者或三者的混合气体刻蚀所述界面层，以形成所述第二通道52，并且通过这样的方式，所述阻挡层40的一部分表面能够被暴露在所述第二通道52。
参考附图10A和图10B，所述扩展电极层60包括一第一扩展电极部61和一第二扩展电极部62，其中所述第一扩展电极部61和所述第二扩展电极部62以相互间隔的方式分别层叠于所述第一绝缘层50，并且所述第一扩展电极部61经所述第一绝缘层50的所述第一通道51延伸至和被电连接于所述外延叠层20的所述N型半导体层21，所述第二扩展电极部62经所述第一绝缘层50的所述第二通道52延伸至和被电连接于所述阻挡层40。
具体地说，所述第一扩展电极部61具有至少一第一扩展电极针611，其中在所述第一扩展电极部61层叠于所述第一绝缘层50时，所述第一扩展电极针611形成于和被保持在所述第一绝缘层50的所述第一通道51，此时，所述第一扩展电极针611直接与所述外延叠层20的所述N型半导体层21接触，以使所述第一扩展电极部61经所述第一绝缘层50的所述第一通道51延伸至和被电连接于所述外延叠层20的所述N型半导体层21。相应地，所述 第二扩展电极部62具有至少一第二扩展电极针621，其中在所述第二扩展电极部62层叠于所述第一绝缘层50时，所述第二扩展电极针621形成于和被保持在所述第一绝缘层50的所述第二通道52，此时，所述第二扩展电极针621直接与所述阻挡层40接触，以使所述第二扩展电极部62经所述第一绝缘层50的所述第二通道52延伸至和被电连接于所述阻挡层40。
值得一提的是，所述扩展电极层60的所述第一扩展电极部61和所述第二扩展电极部62的材料为金属材料，以使得所述第一扩展电极部61和所述第二扩展电极部62具有良好的电传导特性。例如，形成所述第一扩展电极部61和所述第二扩展电极部62的材料可以选自：金(Au)、铝(Al)、钴(Cu)、铂(Pt)、钛(Ti)和铬(Cr)组成的材料组。
参考附图11A和图11B，叠层所述第二绝缘层70于所述扩展电极层60的所述第一扩展电极部61和所述第二扩展电极部62以及所述第一绝缘层50，以藉由所述第二绝缘层70隔离所述第一扩展电极部61和所述第二扩展电极部62。所述第二绝缘层70具有至少一第三通道71和至少一第四通道72，其中所述第二绝缘层70的所述第三通道71延伸至所述扩展电极层60的所述第一扩展电极部61，以使所述第一扩展电极部61的一部分表面被暴露在所述第二绝缘层70的所述第三通道71，其中所述第二绝缘层72的所述第四通道72延伸至所述扩展电极层60的所述第二扩展电极部62，以使所述第二扩展电极部62的一部分表面被暴露在所述第二绝缘层70的所述第四通道72。
优选地，形成所述第二绝缘层70的材料与形成所述第一绝缘层50的材料一致，即，形成所述第二绝缘层70的材料选自：二氧化硅(SiO2)、氮化硅(SiN)、二氧化钛(TiO2)、五氧化二钽(Ta2O5)和氟化镁(MgF)组成的材料组。
参考附图12A和图12B，所述电极组80包括一N型电极81和一P型电极82，其中所述N型电极81和所述P型电极82分别层叠于所述第二绝缘层70，并且所述N型电极81经所述第二绝缘层70的所述第三通道71延伸至和被电连接于所述扩展电极层60的所述第一扩展电极部61，所述P型电极82经所述第二绝缘层70的所述第四通道72延伸至和被电连接于所述扩展电极层60的所述第二扩展电极部62。
具体地说，所述N型电极81具有至少一N型电极连接针811，其中在所述N型电极81层叠于所述第二绝缘层70时，所述N型电极连接针811形成于和被保持在所述第二绝缘层70的所述第三通道71，此时，所述N型电极连接针811直接与所述第一扩展电极部61接触，以使所述N型电极81经所述第二绝缘层70的所述第三通道71延伸至和被电连接于所述第一扩展电极部61。相应地，所述P型电极82具有至少一P型电极连接针821，其中在所述P型电极82层叠于所述第二绝缘层70时，所述P型电极连接针821形成于和被保持在所述第二绝缘层70的所述第四通道72，此时，所述P型电极连接针821直接与所述第二扩展电极部62接触，以使所述P型电极82经所述第二绝缘层70的所述第四通道72延伸至和被电连接于所述第二扩展电极部62。
值得一提的是，形成所述N型电极81和所述P型电极82的材料为金属材料，以使所述N型电极81和所述P型电极82具有良好的电传导特性。例如，形成所述N型电极81和所述P型电极82的材料可以选自：金(Au)、铝(Al)、钴(Cu)、铂(Pt)、钛(Ti)和铬(Cr)组成的材料组。
附图13示出了所述倒装发光芯片的一个变形实施方式的剖视状态，与附图12A和图12B 示出的所述倒装发光芯片不同的是，在附图13示出的所述倒装芯片的这个较佳示例中，在所述阻挡层40层叠于所述反射层30和所述外延叠层20的所述P型半导体层23以包覆所述反射层30之后，层叠所述粘结层100于所述阻挡层40，以使所述粘结层100包覆所述阻挡层40。与附图12A和图12B示出的所述倒装发光芯片一致的是，在附图13示出的所述倒装发光芯片的这个较佳示例中，形成所述粘结层100的材料为钛(Ti)或钴(Cr)等。然后，层叠所述第一绝缘层50于所述粘结层100，以使所述粘接层100被保持在所述阻挡层40和所述第一绝缘层50之间，通过这样的方式，所述粘结层100能够提升所述阻挡层40和所述第一绝缘层50之间的结合力，以有利于保证所述倒装发光芯片的可靠性和稳定性。
依本发明的另一个方面，本发明进一步提供所述倒装发光芯片的制造方法，其中所述制造方法包括如下步骤：
(a)层叠所述外延叠层20于所述衬底10；
(b)层叠所述反射层30于所述外延叠层20的所述P型半导体层23；
(c)以包覆所述反射层30的方式层叠所述阻挡层40于所述P型半导体层23；
(d)层叠所述粘结层100于所述阻挡层40；
(e)层叠具有至少一个所述第一通道51和至少一个所述第二通道52的所述第一绝缘层50于所述粘结层100，其中所述第一通道51延伸至所述外延叠层20的所述N型半导体层21，所述第二通道52延伸至所述阻挡层40；
(f)在层叠所述第一扩展电极部61于所述第一绝缘层50时，形成所述第一扩展电极部61的所述第一扩展电极针611于所述第一绝缘层50的所述第一通道51，并且所述第一扩展电极针611电连接于所述N型半导体层21，相应地，在层叠所述第二扩展电极部62于所述第一绝缘层50时，形成所述第二扩展电极部62的所述第二扩展电极针621于所述第一绝缘层50的所述第二通道52，并且所述第二扩展电极针621连接于所述阻挡层50；以及
(g)分别电连接所述N型电极81于所述第一扩展电极部61和电连接所述P型电极82于所述第二扩展电极部62，以制得所述倒装发光芯片。
进一步地，在所述步骤(d)之前，所述制造方法包括步骤：层叠所述截止层90于所述阻挡层40，从而在所述步骤(d)中，层叠所述粘结层100于所述截止层90。
进一步地，在所述步骤(e)中，进一步包括步骤：
(e.1)层叠所述第一绝缘材料基层于所述粘结层100；和
(e.2)刻蚀所述第一绝缘材料基层，以形成具有所述第一通道51和所述第二通道52的所述第一绝缘层50。
更进一步地，在所述步骤(e.2)中，分段刻蚀所述第一绝缘材料基层，以形成所述第一通道51。在所述步骤(e.2)中，分段刻蚀所述第一绝缘材料基层，以形成所述第二通道52。
在上述方法中，首先刻蚀所述第一绝缘材料基层，其次刻蚀在刻蚀所述第一绝缘材料基层时形成于所述N型半导体层21的界面层，以形成延伸至所述N型半导体层21的所述第一通道51。在上述方法中，首先刻蚀所述第一绝缘材料基层，其次刻蚀在刻蚀所述第一绝缘材料基层时形成于所述阻挡层40的界面层，以形成延伸至所述阻挡层40的所述第二通道52。优选地，在上述方法中，首先使用氩气(Ar)、三氟甲烷(CHF3)和氧气(O2)的混 合气体刻蚀所述第一绝缘材料基层，其次使用氩气(Ar)、氯气(Cl2)和三氯化硼(BCl3)中的任意两者或三者的混合气体刻蚀所述界面层。
进一步地，在所述步骤(a)中，刻蚀所述外延叠层20以形成自所述外延叠层20的所述P型半导体层23经所述有源区22延伸至所述N型半导体层21的至少一个所述半导体裸露部24，和在所述步骤(c)中，使所述阻挡层40形成连通所述半导体裸露部24的所述阻挡层穿孔41，以在所述步骤(e)中，所述第一绝缘层50经所述阻挡层穿孔41和所述半导体裸露部24延伸至所述N型半导体层21。
进一步地，在所述步骤(a)中，刻蚀所述外延叠层20以形成自所述外延叠层20的所述P型半导体层23经所述有源区22和所述N型半导体层21延伸至所述衬底10的所述衬底裸露部25，以在所述步骤(e)中，所述第一绝缘层50以保持在所述衬底裸露部25的方式层叠于所述衬底10。优选地，在所述步骤(a)中，沿着所述外延叠层20的四周刻蚀所述外延叠层20，从而在所述步骤(d)中，所述第一绝缘层50以层叠于所述衬底10的方式包覆所述外延叠层20的四周。
进一步地，在所述步骤(b)中，暴露所述P型半导体层23的一部分表面于所述反射层30的所述反射层穿孔31和暴露所述P型半导体层23的周缘于所述反射层30的四周，以在所述步骤(c)中，所述阻挡层40以层叠于所述P型半导体层23的暴露于所述反射层穿孔31的一部分表面和所述P型半导体层23的周缘的方式包覆所述反射层30。
进一步地，在所述步骤(g)之前，所述制造方法进一步包括步骤：层叠具有至少一个所述第三通道71和至少一个所述第四通道72的所述第二绝缘层70于所述第一扩展电极部61、所述第二扩展电极部62和所述第一绝缘层50，其中所述第三通道71延伸至所述第一扩展电极部61，所述第四通道72延伸至所述第二扩展电极部62，以在所述步骤(g)中，在层叠所述N型电极81于所述第二绝缘层70时，形成所述N型电极81的所述N型电极连接针811于所述第三通道71，并且所述N型电极连接针811电连接于所述第一扩展电极部61，相应地，在层叠所述P型电极82于所述第二绝缘层70时，形成所述P型电极82的所述P型电极连接针821于所述第四通道72，并且所述P型电极连接针821电连接于所述第二扩展电极部62。
值得注意的是，在本发明的附图中示出的所述倒装发光芯片的所述衬底10、所述N型半导体层21、所述有源区22、所述P型半导体层23、所述反射层30、所述阻挡层40、所述截止层90、所述粘结层100、所述第一绝缘层50、所述第一扩展电极部61、所述第二扩展电极部62、所述第二绝缘层70、所述N型电极81和所述P型电极82的厚度仅为示例，其并不表示所述衬底10、所述N型半导体层21、所述有源区22、所述P型半导体层23、所述反射层30、所述阻挡层40、所述截止层90、所述粘结层100、所述第一绝缘层50、所述第一扩展电极部61、所述第二扩展电极部62、所述第二绝缘层70、所述N型电极81和所述P型电极82的真实厚度。并且，所述衬底10、所述N型半导体层21、所述有源区22、所述P型半导体层23、所述反射层30、所述阻挡层40、所述截止层90、所述粘结层100、所述第一绝缘层50、所述第一扩展电极部61、所述第二扩展电极部62、所述第二绝缘层70、所述N型电极81和所述P型电极82之间的真实比例也并不像附图中示出的那样。另外，所述N型电极81和所述P型电极82的尺寸与所述倒装发光芯片的其他层的尺寸比例也并 不受限于附图中示出的那样。
本领域的技术人员可以理解的是，以上实施例仅为举例，其中不同实施例的特征可以相互组合，以得到根据本发明揭露的内容很容易想到但是在附图中没有明确指出的实施方式。
本领域的技术人员应理解，上述描述及附图中所示的本发明的实施例只作为举例而并不限制本发明。本发明的目的已经完整并有效地实现。本发明的功能及结构原理已在实施例中展示和说明，在没有背离所述原理下，本发明的实施方式可以有任何变形或修改。

Claims (55)

  1. 一倒装发光芯片，其特征在于，包括：
    一衬底；
    一外延叠层，其包括一N型半导体层、一有源区以及一P型半导体层，其中所述衬底、所述N型半导体层、所述有源区和所述P型半导体层依次层叠；
    一反射层，其中所述反射层层叠于所述P型半导体层；
    一阻挡层，其以包覆所述反射层的方式层叠于所述P型半导体层；
    一粘结层，其层叠于所述阻挡层；
    一第一绝缘层，其层叠于所述粘结层，其中所述第一绝缘层具有至少一第一通道和至少一第二通道，所述第一通道延伸至所述N型半导体层，所述第二通道延伸至所述阻挡层；
    一扩展电极层，其包括一第一扩展电极部和一第二扩展电极部，其中所述第一扩展电极部具有至少一第一扩展电极针，在所述第一扩展电极部层叠于所述第一绝缘层时，所述第一扩展电极针形成于所述第一通道和电连接于所述N型半导体层，其中所述第二扩展电极部具有至少一第二扩展电极针，在所述第二扩展电极部层叠于所述第一绝缘层时，所述第二扩展电极针形成于所述第二通道和电连接于所述阻挡层；以及
    一电极组，其包括一N型电极和一P型电极，其中所述N型电极电连接于所述第一扩展电极部，所述P型电极电连接于所述第二扩展电极部。
  2. 根据权利要求1所述的倒装发光芯片，进一步包括一截止层，其层叠于所述阻挡层，所述粘结层层叠于所述截止层。
  3. 根据权利要求1所述的倒装发光芯片，其中所述粘结层的材料为钛(Ti)或钴(Cr)。
  4. 根据权利要求2所述的倒装发光芯片，其中所述截止层的材料选自：镍(Ni)、铂(Pt)和锆(Zr)组成的材料组。
  5. 根据权利要求1所述的倒装发光芯片，其中所述外延叠层具有至少一半导体裸露部，其自所述P型半导体层经所述有源区延伸至所述N型半导体层，其中所述阻挡层具有至少一阻挡层穿孔，其中所述外延叠层的所述半导体裸露部和所述阻挡层的所述阻挡层穿孔相连通，所述第一绝缘层经所述阻挡层的所述阻挡层穿孔和所述外延叠层的所述半导体裸露部延伸至所述N型半导体层。
  6. 根据权利要求2所述的倒装发光芯片，其中所述外延叠层具有至少一半导体裸露部，其自所述P型半导体层经所述有源区延伸至所述N型半导体层，其中所述阻挡层具有至少一阻挡层穿孔，其中所述外延叠层的所述半导体裸露部和所述阻挡层的所述阻挡层穿孔相连通，所述第一绝缘层经所述阻挡层的所述阻挡层穿孔和所述外延叠层的所述半导体裸露部延伸至所述N型半导体层。
  7. 根据权利要求3所述的倒装发光芯片，其中所述外延叠层具有至少一半导体裸露部，其自所述P型半导体层经所述有源区延伸至所述N型半导体层，其中所述阻挡层具有至少一阻挡层穿孔，其中所述外延叠层的所述半导体裸露部和所述阻挡层的所述阻挡层穿孔相连通，所述第一绝缘层经所述阻挡层的所述阻挡层穿孔和所述外延叠层的所述半导体裸露部延 伸至所述N型半导体层。
  8. 根据权利要求4所述的倒装发光芯片，其中所述外延叠层具有至少一半导体裸露部，其自所述P型半导体层经所述有源区延伸至所述N型半导体层，其中所述阻挡层具有至少一阻挡层穿孔，其中所述外延叠层的所述半导体裸露部和所述阻挡层的所述阻挡层穿孔相连通，所述第一绝缘层经所述阻挡层的所述阻挡层穿孔和所述外延叠层的所述半导体裸露部延伸至所述N型半导体层。
  9. 根据权利要求5所述的倒装发光芯片，其中所述反射层具有至少一反射层穿孔，其中所述外延叠层的所述半导体裸露部对应于所述反射层的所述反射层穿孔，并且所述外延叠层的所述半导体裸露部的尺寸小于所述反射层穿孔的尺寸，以使所述P型半导体层的一部分表面被暴露在所述反射层穿孔，从而允许所述阻挡层层叠于所述P型半导体层的被暴露在所述反射层穿孔的表面。
  10. 根据权利要求6所述的倒装发光芯片，其中所述反射层具有至少一反射层穿孔，其中所述外延叠层的所述半导体裸露部对应于所述反射层的所述反射层穿孔，并且所述外延叠层的所述半导体裸露部的尺寸小于所述反射层穿孔的尺寸，以使所述P型半导体层的一部分表面被暴露在所述反射层穿孔，从而允许所述阻挡层层叠于所述P型半导体层的被暴露在所述反射层穿孔的表面。
  11. 根据权利要求7所述的倒装发光芯片，其中所述反射层具有至少一反射层穿孔，其中所述外延叠层的所述半导体裸露部对应于所述反射层的所述反射层穿孔，并且所述外延叠层的所述半导体裸露部的尺寸小于所述反射层穿孔的尺寸，以使所述P型半导体层的一部分表面被暴露在所述反射层穿孔，从而允许所述阻挡层层叠于所述P型半导体层的被暴露在所述反射层穿孔的表面。
  12. 根据权利要求8所述的倒装发光芯片，其中所述反射层具有至少一反射层穿孔，其中所述外延叠层的所述半导体裸露部对应于所述反射层的所述反射层穿孔，并且所述外延叠层的所述半导体裸露部的尺寸小于所述反射层穿孔的尺寸，以使所述P型半导体层的一部分表面被暴露在所述反射层穿孔，从而允许所述阻挡层层叠于所述P型半导体层的被暴露在所述反射层穿孔的表面。
  13. 根据权利要求9所述的倒装发光芯片，其中所述反射层的长宽尺寸小于所述P型半导体层的长宽尺寸，以使所述P型半导体层的周缘被暴露，从而允许所述阻挡层层叠于所述P型半导体层的被暴露的周缘。
  14. 根据权利要求10所述的倒装发光芯片，其中所述反射层的长宽尺寸小于所述P型半导体层的长宽尺寸，以使所述P型半导体层的周缘被暴露，从而允许所述阻挡层层叠于所述P型半导体层的被暴露的周缘。
  15. 根据权利要求11所述的倒装发光芯片，其中所述反射层的长宽尺寸小于所述P型半导体层的长宽尺寸，以使所述P型半导体层的周缘被暴露，从而允许所述阻挡层层叠于所述P型半导体层的被暴露的周缘。
  16. 根据权利要求12所述的倒装发光芯片，其中所述反射层的长宽尺寸小于所述P型半导体层的长宽尺寸，以使所述P型半导体层的周缘被暴露，从而允许所述阻挡层层叠于所述P型半导体层的被暴露的周缘。
  17. 根据权利要求1至16中任一所述的倒装发光芯片，其中所述外延叠层具有至少一衬底裸露部，其自所述P型半导体层经所述有源区和所述N型半导体层延伸至所述衬底，其中所述第一绝缘层以被保持在所述衬底裸露部的方式层叠于所述衬底。
  18. 根据权利要求17所述的倒装发光芯片，其中所述衬底裸露部环绕所述外延叠层的四周。
  19. 根据权利要求1至16中任一所述的倒装发光芯片，其中所述反射层是一个多层层叠结构的反射层。
  20. 根据权利要求18所述的倒装发光芯片，其中所述反射层是一个多层层叠结构的反射层。
  21. 根据权利要求20所述的倒装发光芯片，其中所述反射层包括一第一反射金属材料层和一第二反射金属材料层，所述第一反射金属材料层层叠于所述P型半导体层，所述第二反射金属材料层层叠于所述第一反射金属材料层，其中所述第一反射金属材料层的材料选自：铝(Al)、银(Ag)、铂(Pt)和金(Au)组成的材料组，其中所述第二反射金属材料层的材料选自：铂(Pt)、钛(Ti)、钨(W)、镍(Ni)组成的材料组。
  22. 根据权利要求1至16中任一所述的倒装发光芯片，其中所述阻挡层是一个多层层叠结构的阻挡层。
  23. 根据权利要求21所述的倒装发光芯片，其中所述阻挡层是一个多层层叠结构的阻挡层。
  24. 根据权利要求23所述的倒装发光芯片，其中所述阻挡层包括一第一阻挡金属材料层和一第二阻挡金属材料层，所述第一阻挡金属材料层以包覆所述反射层的方式层叠于所述P型半导体层，所述第二阻挡金属材料层层叠于所述第一阻挡金属材料层，其中所述第一阻挡金属材料层的材料选自：镍(Ni)、钛(Ti)和铬(Cr)组成的材料组，所述第二阻挡金属材料层的材料选自：铂(Pt)、钛(Ti)、钨(W)、镍(Ni)组成的材料组。
  25. 根据权利要求1至16中任一所述的倒装发光芯片，其中所述反射层的厚度尺寸范围为100nm-1000nm。
  26. 根据权利要求1至16中任一所述的倒装发光芯片，其中所述阻挡层的最小厚度尺寸范围为0.1μm-3μm。
  27. 根据权利要求1至16中任一所述的倒装发光芯片，进一步包括一第二绝缘层，其层叠于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第二绝缘层具有至少一第三通道和至少一第四通道，所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸至所述第二扩展电极部，其中所述N型电极具有至少一N型电极连接针，在所述N型电极层叠于所述第二绝缘层时，所述N型电极连接针形成于所述第三通道和电连接于所述第一扩展电极部，其中所述P型电极具有至少一P型电极连接针，在所述P型电极层叠于所述第二绝缘层时，所述P型电极连接针形成于所述第四通道和电连接于所述第二扩展电极部。
  28. 根据权利要求17所述的倒装发光芯片，进一步包括一第二绝缘层，其层叠于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第二绝缘层具有至少一第三通道和至少一第四通道，所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸 至所述第二扩展电极部，其中所述N型电极具有至少一N型电极连接针，在所述N型电极层叠于所述第二绝缘层时，所述N型电极连接针形成于所述第三通道和电连接于所述第一扩展电极部，其中所述P型电极具有至少一P型电极连接针，在所述P型电极层叠于所述第二绝缘层时，所述P型电极连接针形成于所述第四通道和电连接于所述第二扩展电极部。
  29. 根据权利要求19所述的倒装发光芯片，进一步包括一第二绝缘层，其层叠于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第二绝缘层具有至少一第三通道和至少一第四通道，所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸至所述第二扩展电极部，其中所述N型电极具有至少一N型电极连接针，在所述N型电极层叠于所述第二绝缘层时，所述N型电极连接针形成于所述第三通道和电连接于所述第一扩展电极部，其中所述P型电极具有至少一P型电极连接针，在所述P型电极层叠于所述第二绝缘层时，所述P型电极连接针形成于所述第四通道和电连接于所述第二扩展电极部。
  30. 根据权利要求22所述的倒装发光芯片，进一步包括一第二绝缘层，其层叠于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第二绝缘层具有至少一第三通道和至少一第四通道，所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸至所述第二扩展电极部，其中所述N型电极具有至少一N型电极连接针，在所述N型电极层叠于所述第二绝缘层时，所述N型电极连接针形成于所述第三通道和电连接于所述第一扩展电极部，其中所述P型电极具有至少一P型电极连接针，在所述P型电极层叠于所述第二绝缘层时，所述P型电极连接针形成于所述第四通道和电连接于所述第二扩展电极部。
  31. 根据权利要求25所述的倒装发光芯片，进一步包括一第二绝缘层，其层叠于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第二绝缘层具有至少一第三通道和至少一第四通道，所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸至所述第二扩展电极部，其中所述N型电极具有至少一N型电极连接针，在所述N型电极层叠于所述第二绝缘层时，所述N型电极连接针形成于所述第三通道和电连接于所述第一扩展电极部，其中所述P型电极具有至少一P型电极连接针，在所述P型电极层叠于所述第二绝缘层时，所述P型电极连接针形成于所述第四通道和电连接于所述第二扩展电极部。
  32. 根据权利要求26所述的倒装发光芯片，进一步包括一第二绝缘层，其层叠于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第二绝缘层具有至少一第三通道和至少一第四通道，所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸至所述第二扩展电极部，其中所述N型电极具有至少一N型电极连接针，在所述N型电极层叠于所述第二绝缘层时，所述N型电极连接针形成于所述第三通道和电连接于所述第一扩展电极部，其中所述P型电极具有至少一P型电极连接针，在所述P型电极层叠于所述第二绝缘层时，所述P型电极连接针形成于所述第四通道和电连接于所述第二扩展电极部。
  33. 一倒装发光芯片的制造方法，其特征在于，所述制造方法包括如下步骤：
    (a)层叠一外延叠层于所述衬底；
    (b)层叠一反射层于所述外延叠层的一P型半导体层；
    (c)以包覆所述反射层的方式层叠一阻挡层于所述P型半导体层；
    (d)层叠一粘结层于所述阻挡层；
    (e)层叠具有至少一第一通道和至少一第二通道的一第一绝缘层于所述粘结层，其中 所述第一通道延伸至所述外延叠层的一N型半导体层，所述第二通道延伸至所述阻挡层；
    (f)在层叠一第一扩展电极部于所述第一绝缘层时，形成所述第一扩展电极部的一第一扩展电极针于所述第一绝缘层的所述第一通道，并且所述第一扩展电极针电连接于所述N型半导体层，相应地，在层叠一第二扩展电极部于所述第一绝缘层时，形成所述第二扩展电极部的一第二扩展电极针于所述第一绝缘层的所述第二通道，并且所述第二扩展电极针连接于所述阻挡层；以及
    (g)分别电连接一N型电极于所述第一扩展电极部和电连接一P型电极于所述第二扩展电极部，以制得所述倒装发光芯片。
  34. 根据权利要求33所述的制造方法，其中在所述步骤(d)之前，所述制造方法进一步包括步骤：层叠一截止层于所述阻挡层，从而在所述步骤(d)中，层叠所述粘结层于所述截止层。
  35. 根据权利要求33所述的制造方法，其中在所述步骤(e)中，进一步包括步骤：
    (e.1)层叠一第一绝缘材料基层于所述粘结层；和
    (e.2)刻蚀所述第一绝缘材料基层，以形成具有所述第一通道和所述第二通道的所述第一绝缘层。
  36. 根据权利要求34所述的制造方法，其中在所述步骤(e)中，进一步包括步骤：
    (e.1)层叠一第一绝缘材料基层于所述粘结层；和
    (e.2)刻蚀所述第一绝缘材料基层，以形成具有所述第一通道和所述第二通道的所述第一绝缘层。
  37. 根据权利要求35所述的制造方法，其中在所述步骤(e.2)中，分段刻蚀所述第一绝缘材料基层，以形成所述第一通道。
  38. 根据权利要求36所述的制造方法，其中在所述步骤(e.2)中，分段刻蚀所述第一绝缘材料基层，以形成所述第一通道。
  39. 根据权利要求37所述的制造方法，其中在所述步骤(e.2)中，分段刻蚀所述第一绝缘材料基层，以形成所述第二通道。
  40. 根据权利要求38所述的制造方法，其中在所述步骤(e.2)中，分段刻蚀所述第一绝缘材料基层，以形成所述第二通道。
  41. 根据权利要求37所述的制造方法，其中在上述方法中，首先刻蚀所述第一绝缘材料基层，其次刻蚀在刻蚀所述第一绝缘材料基层时形成于所述N型半导体层的界面层，以形成延伸至所述N型半导体层的所述第一通道。
  42. 根据权利要求38所述的制造方法，其中在上述方法中，首先刻蚀所述第一绝缘材料基层，其次刻蚀在刻蚀所述第一绝缘材料基层时形成于所述N型半导体层的界面层，以形成延伸至所述N型半导体层的所述第一通道。
  43. 根据权利要求39所述的制造方法，其中在上述方法中，首先刻蚀所述第一绝缘材料基层，其次刻蚀在刻蚀所述第一绝缘材料基层时形成于所述阻挡层的界面层，以形成延伸至所述阻挡层的所述第二通道。
  44. 根据权利要求40所述的制造方法，其中在上述方法中，首先刻蚀所述第一绝缘材料基层，其次刻蚀在刻蚀所述第一绝缘材料基层时形成于所述阻挡层的界面层，以形成延伸 至所述阻挡层的所述第二通道。
  45. 根据权利要求41所述的制造方法，其中在上述方法中，首先使用氩气(Ar)、三氟甲烷(CHF3)和氧气(O2)的混合气体刻蚀所述第一绝缘材料基层，其次使用氩气(Ar)、氯气(Cl2)和三氯化硼(BCl3)中的任意两者或三者的混合气体刻蚀所述界面层。
  46. 根据权利要求42所述的制造方法，其中在上述方法中，首先使用氩气(Ar)、三氟甲烷(CHF3)和氧气(O2)的混合气体刻蚀所述第一绝缘材料基层，其次使用氩气(Ar)、氯气(Cl2)和三氯化硼(BCl3)中的任意两者或三者的混合气体刻蚀所述界面层。
  47. 根据权利要求33至46中任一所述的制造方法，其中在所述步骤(a)中，刻蚀所述外延叠层以形成自所述外延叠层的所述P型半导体层经一有源区延伸至所述N型半导体层的至少一半导体裸露部，和在所述步骤(c)中，使所述阻挡层形成连通所述半导体裸露部的一阻挡层穿孔，以在所述步骤(e)中，所述第一绝缘层经所述阻挡层穿孔和所述半导体裸露部延伸至所述N型半导体层。
  48. 根据权利要求47所述的制造方法，其中在所述步骤(a)中，刻蚀所述外延叠层以形成自所述外延叠层的所述P型半导体层经所述有源区和所述N型半导体层延伸至所述衬底的一衬底裸露部，以在所述步骤(e)中，所述第一绝缘层以保持在所述衬底裸露部的方式层叠于所述衬底。
  49. 根据权利要求48所述的制造方法，其中在所述步骤(a)中，沿着所述外延叠层的四周刻蚀所述外延叠层，从而在所述步骤(e)中，所述第一绝缘层以层叠于所述衬底的方式包覆所述外延叠层的四周。
  50. 根据权利要求47所述的制造方法，其中在所述步骤(b)中，暴露所述P型半导体层的一部分表面于所述反射层的一反射层穿孔和暴露所述P型半导体层的周缘于所述反射层的四周，以在所述步骤(c)中，所述阻挡层以层叠于所述P型半导体层的暴露于所述反射层穿孔的一部分表面和所述P型半导体层的周缘的方式包覆所述反射层。
  51. 根据权利要求34至46中任一所述的制造方法，其中在所述步骤(g)之前，所述制造方法进一步包括步骤：层叠具有至少一第三通道和至少一第四通道的一第二绝缘层于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸至所述第二扩展电极部，以在所述步骤(g)中，在层叠所述N型电极于所述第二绝缘层时，形成所述N型电极的一N型电极连接针于所述第三通道，并且所述N型电极连接针电连接于所述第一扩展电极部，相应地，在层叠所述P型电极于所述第二绝缘层时，形成所述P型电极的一P型电极连接针于所述第四通道，并且所述P型电极连接针电连接于所述第二扩展电极部。
  52. 根据权利要求47所述的制造方法，其中在所述步骤(g)之前，所述制造方法进一步包括步骤：层叠具有至少一第三通道和至少一第四通道的一第二绝缘层于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸至所述第二扩展电极部，以在所述步骤(g)中，在层叠所述N型电极于所述第二绝缘层时，形成所述N型电极的一N型电极连接针于所述第三通道，并且所述N型电极连接针电连接于所述第一扩展电极部，相应地，在层叠所述P型电极于所述第二绝缘层时，形成所述P型电极的一P型电极连接针于所述第四通道，并且所述P型电极 连接针电连接于所述第二扩展电极部。
  53. 根据权利要求48所述的制造方法，其中在所述步骤(g)之前，所述制造方法进一步包括步骤：层叠具有至少一第三通道和至少一第四通道的一第二绝缘层于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸至所述第二扩展电极部，以在所述步骤(g)中，在层叠所述N型电极于所述第二绝缘层时，形成所述N型电极的一N型电极连接针于所述第三通道，并且所述N型电极连接针电连接于所述第一扩展电极部，相应地，在层叠所述P型电极于所述第二绝缘层时，形成所述P型电极的一P型电极连接针于所述第四通道，并且所述P型电极连接针电连接于所述第二扩展电极部。
  54. 根据权利要求49所述的制造方法，其中在所述步骤(g)之前，所述制造方法进一步包括步骤：层叠具有至少一第三通道和至少一第四通道的一第二绝缘层于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸至所述第二扩展电极部，以在所述步骤(g)中，在层叠所述N型电极于所述第二绝缘层时，形成所述N型电极的一N型电极连接针于所述第三通道，并且所述N型电极连接针电连接于所述第一扩展电极部，相应地，在层叠所述P型电极于所述第二绝缘层时，形成所述P型电极的一P型电极连接针于所述第四通道，并且所述P型电极连接针电连接于所述第二扩展电极部。
  55. 根据权利要求50所述的制造方法，其中在所述步骤(g)之前，所述制造方法进一步包括步骤：层叠具有至少一第三通道和至少一第四通道的一第二绝缘层于所述第一扩展电极部、所述第二扩展电极部和所述第一绝缘层，其中所述第三通道延伸至所述第一扩展电极部，所述第四通道延伸至所述第二扩展电极部，以在所述步骤(g)中，在层叠所述N型电极于所述第二绝缘层时，形成所述N型电极的一N型电极连接针于所述第三通道，并且所述N型电极连接针电连接于所述第一扩展电极部，相应地，在层叠所述P型电极于所述第二绝缘层时，形成所述P型电极的一P型电极连接针于所述第四通道，并且所述P型电极连接针电连接于所述第二扩展电极部。
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