WO2020024935A1 - 半导体发光芯片及其制造方法 - Google Patents

半导体发光芯片及其制造方法 Download PDF

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WO2020024935A1
WO2020024935A1 PCT/CN2019/098369 CN2019098369W WO2020024935A1 WO 2020024935 A1 WO2020024935 A1 WO 2020024935A1 CN 2019098369 W CN2019098369 W CN 2019098369W WO 2020024935 A1 WO2020024935 A1 WO 2020024935A1
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type
layer
electrode
channel
isolation
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PCT/CN2019/098369
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English (en)
French (fr)
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邬新根
刘英策
李俊贤
魏振东
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厦门乾照光电股份有限公司
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Priority to US16/626,516 priority Critical patent/US11527679B2/en
Publication of WO2020024935A1 publication Critical patent/WO2020024935A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials

Definitions

  • the present invention relates to a semiconductor light emitting diode, and in particular, to a semiconductor light emitting chip and a manufacturing method thereof.
  • high-brightness flip-chips generally use metallic silver as the material of the mirror to form a silver mirror laminated on a P-type GaN layer.
  • the work function of the silver mirror is 4.26eV, and theoretically only when the work function of the silver mirror is greater than the work function of the P-type gallium nitride layer can the silver mirror form a low level with the p-type gallium nitride layer. Resistive ohmic contact, but in fact, because the work function of the silver mirror is smaller than the work function of the P-type GaN layer, the silver mirror cannot form a low-resistance ohmic contact with the P-type GaN layer.
  • the silver metal forming the silver mirror is an active metal, the silver mirror is prone to the phenomenon of metal migration under the conditions of potential difference, high humidity and high temperature, and once the silver mirror has the phenomenon of metal migration, it is easy to As a result, abnormal conditions such as leakage and device failure occur. Therefore, the high-brightness flip chip using the silver mirror also needs to provide a diffusion prevention layer covering the silver mirror, that is, the diffusion prevention layer needs to be connected with the P-type gallium nitride. Only when the layers are in direct contact (the anti-diffusion layer is stacked on the P-type GaN layer) can the silver mirror be completely covered.
  • the length and width dimensions of the anti-diffusion layer need to be larger than the length and width dimensions of the silver mirror, which results in that the anti-diffusion layer is directly stacked on the P-type gallium nitride in a manner that contacts the P-type gallium nitride layer Floor.
  • the material forming the anti-diffusion layer is usually a metal material such as titanium (Ti), titanium tungsten (TiW), nickel (Ni), etc.
  • the contact resistance between the anti-diffusion layer and the P-type gallium nitride layer Lower than the contact resistance of the silver mirror and the P-type GaN layer, which easily causes current injected from the P-type electrode to be concentrated in the region (the region where the anti-diffusion layer is in contact with the P-type GaN layer) , which causes the current density in this area to be too high, which in turn causes abnormal electrostatic breakdown.
  • An object of the present invention is to provide a semiconductor light emitting chip and a method for manufacturing the same, wherein the semiconductor light emitting chip can avoid the phenomenon of electrostatic breakdown to ensure the reliability of the semiconductor chip when it is used.
  • An object of the present invention is to provide a semiconductor light emitting chip and a manufacturing method thereof, wherein the semiconductor light emitting chip prevents abnormal breakdown of static electricity caused by current accumulation by preventing a diffusion preventing layer from directly contacting a P-type semiconductor layer, thereby ensuring that The reliability of the semiconductor light emitting chip when it is used.
  • An object of the present invention is to provide a semiconductor light emitting chip and a manufacturing method thereof, wherein the semiconductor light emitting chip provides an insulating layer to isolate the diffusion preventing layer and the P-type semiconductor layer by the insulating layer. Preventing the diffusion preventing layer from directly contacting the P-type semiconductor layer.
  • An object of the present invention is to provide a semiconductor light emitting chip and a method for manufacturing the same, wherein the insulating layer surrounds a reflection layer, and the anti-diffusion layer is stacked on the reflection layer and the insulation layer to avoid interference.
  • the reflective layer has a poor metal migration phenomenon, thereby ensuring the stability of the semiconductor light emitting chip.
  • An object of the present invention is to provide a semiconductor light emitting chip and a manufacturing method thereof, wherein after the insulating layer is laminated on the P-type semiconductor layer, the diffusion prevention layer is laminated on the insulating layer and the reflective layer, and In this way, not only can the insulating layer prevent the diffusion preventing layer from contacting the P-type semiconductor layer, but the insulating layer and the diffusion preventing layer can cooperate with each other to cover the reflective layer, thereby avoiding the The reflective layer has a poor metal migration phenomenon.
  • the present invention provides a semiconductor light emitting chip, including:
  • the epitaxial stack includes an N-type GaN layer, an active region, and a P-type GaN layer, wherein the substrate, the N-type GaN layer, the An active region and the P-type GaN layer are sequentially stacked;
  • At least one reflective layer wherein the reflective layer is laminated on a part of the surface of the P-type gallium nitride layer;
  • At least two insulating layers one of the insulating layers surrounds the inside of the reflective layer so as to be laminated on a part of the surface of the P-type gallium nitride layer, and the other of the insulating layers is laminated on the P-type nitrogen The way of a part of the surface of the gallium layer surrounds the outside of the reflective layer;
  • At least one diffusion prevention layer wherein the diffusion prevention layer is laminated on the reflection layer and the insulation layer;
  • An electrode group wherein the electrode group includes an N-type electrode and a P-type electrode, wherein the N-type electrode is electrically connected to the N-type gallium nitride layer of the epitaxial stack, and the P-type electrode Is electrically connected to the diffusion preventing layer.
  • the present invention further provides a method for manufacturing a semiconductor light emitting chip, wherein the manufacturing method includes the following steps:
  • An N-type electrode is electrically connected to the N-type gallium nitride layer and a P-type electrode is electrically connected to the anti-diffusion layer to obtain the semiconductor light emitting chip.
  • FIG. 1A and FIG. 1B are a schematic cross-sectional view and a schematic plan view, respectively, of one of the manufacturing steps of a semiconductor light-emitting chip according to a preferred embodiment of the present invention.
  • 2A and 2B are a schematic cross-sectional view and a schematic plan view of the second manufacturing step of the semiconductor light-emitting chip according to the foregoing preferred embodiment of the present invention.
  • 3A and 3B are a schematic cross-sectional view and a schematic plan view, respectively, of a third step of manufacturing the semiconductor light-emitting chip according to the foregoing preferred embodiment of the present invention.
  • 4A and 4B are a schematic cross-sectional view and a schematic plan view, respectively, of a manufacturing step 4 of the semiconductor light-emitting chip according to the foregoing preferred embodiment of the present invention.
  • 5A and 5B are a schematic cross-sectional view and a schematic plan view, respectively, of a fifth step of manufacturing the semiconductor light-emitting chip according to the foregoing preferred embodiment of the present invention.
  • FIGS. 6A and 6B are a schematic cross-sectional view and a schematic plan view, respectively, of a sixth manufacturing step of the semiconductor light-emitting chip according to the above preferred embodiment of the present invention.
  • FIG. 7A and FIG. 7B are a schematic cross-sectional view and a schematic plan view, respectively, of a manufacturing step 7 of the semiconductor light-emitting chip according to the above-mentioned preferred embodiment of the present invention, and FIG. 7A shows a cross-sectional state of the semiconductor light-emitting chip FIG. 7B shows a plan view of the semiconductor light emitting chip.
  • 8A and 8B are respectively a schematic cross-sectional view and a schematic plan view of one of the manufacturing steps of a semiconductor light-emitting chip according to a preferred embodiment of the present invention.
  • 9A and 9B are a schematic cross-sectional view and a schematic plan view, respectively, of a manufacturing process step 2 of the semiconductor light-emitting chip according to the foregoing preferred embodiment of the present invention.
  • FIGS. 10A and 10B are a schematic cross-sectional view and a schematic plan view, respectively, of the third manufacturing step of the semiconductor light-emitting chip according to the foregoing preferred embodiment of the present invention.
  • FIG. 11A and FIG. 11B are a schematic cross-sectional view and a schematic plan view, respectively, of a manufacturing step 4 of the semiconductor light-emitting chip according to the foregoing preferred embodiment of the present invention.
  • 12A and 12B are a schematic cross-sectional view and a schematic plan view, respectively, of a fifth step of manufacturing the semiconductor light-emitting chip according to the foregoing preferred embodiment of the present invention.
  • FIG. 13A and FIG. 14B are a schematic cross-sectional view and a schematic plan view, respectively, of a sixth manufacturing step of the semiconductor light-emitting chip according to the foregoing preferred embodiment of the present invention.
  • 14A and 14B are a schematic cross-sectional view and a schematic plan view, respectively, of the seventh manufacturing step of the semiconductor light-emitting chip according to the preferred embodiment of the present invention.
  • FIG. 15A and 15B are respectively a schematic cross-sectional view and a schematic plan view of the eighth step of manufacturing the semiconductor light-emitting chip according to the above-mentioned preferred embodiment of the present invention, and FIG. 15A illustrates a cross-sectional state of the semiconductor light-emitting chip FIG. 15B shows a plan view of the semiconductor chip.
  • the semiconductor light emitting chip includes a The substrate 10, an epitaxial stack 20, a reflective layer 30, at least one insulating layer 40, a diffusion prevention layer 50, an extended electrode layer 60, a current isolation layer 70, and an electrode group 80.
  • 1A to 7B further illustrate a manufacturing process of the semiconductor light emitting chip.
  • the substrate of the semiconductor light emitting chip will be further disclosed and explained in conjunction with the manufacturing process of the semiconductor light emitting chip. 10.
  • the epitaxial stack 20 the reflective layer 30, the insulating layer 40, the anti-diffusion layer 50, the extended electrode layer 60, the current isolation layer 70, and the electrode group 80 relationship.
  • the epitaxial stack 20 includes an N-type semiconductor layer 21, an active region 22, and a P-type semiconductor layer 23, wherein the N-type semiconductor layer 21 is grown on the substrate 10. So that the N-type semiconductor layer 21 is stacked on the substrate 10, wherein the active region 22 is grown on the N-type semiconductor layer 21, so that the active region 22 is stacked on the N-type semiconductor Layer 21, wherein the P-type semiconductor layer 23 is grown on the active region 22, so that the P-type semiconductor layer 23 is stacked on the active region 22.
  • both the N-type semiconductor layer 21 and the P-type semiconductor layer 23 may be implemented as a gallium nitride layer, that is, the epitaxial stack
  • the layer 20 includes an N-type GaN layer stacked on the substrate 10, the active region 22 stacked on the N-type GaN layer, and a P-type nitrogen stacked on the active region 22.
  • Gallium layer is an N-type GaN layer stacked on the substrate 10, the active region 22 stacked on the N-type GaN layer, and a P-type nitrogen stacked on the active region 22.
  • the manner in which the epitaxial stack 20 is laminated on the substrate 10 is not limited, for example, as shown in FIG. 1A to FIG. 7B
  • a metal-organic chemical vapor deposition device MOCVD
  • MOCVD metal-organic chemical vapor deposition device
  • the type of the substrate 10 is not limited in the semiconductor light emitting chip of the present invention.
  • the substrate 10 may be, but is not limited to, an aluminum oxide (Al2O3) substrate, silicon carbide (SiC ) Substrate, silicon (Si) substrate, gallium nitride (GaN) substrate, gallium arsenide (GaAs) substrate, and gallium phosphide (GaP) substrate.
  • Al2O3 aluminum oxide
  • SiC silicon carbide
  • Si silicon
  • GaN gallium nitride
  • GaAs gallium arsenide
  • GaP gallium phosphide
  • the epitaxial stack 20 further has at least one semiconductor exposed portion 24, wherein the semiconductor exposed portion 24 extends from the P-type semiconductor layer 23 through the active region 22 to the
  • the N-type semiconductor layer 21 is such that a part of the surface of the N-type semiconductor layer 21 is exposed to the semiconductor exposed portion 24.
  • the semiconductor exposed portion 24 may be formed by etching the epitaxial stack 20.
  • the epitaxial stack 20 laminated on the substrate 10 is subjected to photolithography using a positive photoresist, so as to expose a region to be etched of the epitaxial stack 20, and set
  • the thickness of the photoresist is 3 ⁇ m to 5 ⁇ m (including 3 ⁇ m and 5 ⁇ m).
  • the epitaxial stack 20 is dry-etched using an inductively coupled plasma machine (ICP), so that the epitaxial stack 20 is formed from the P
  • the semiconductor layer 23 extends to the semiconductor exposed portion 24 of the N-type semiconductor layer 21 through the active region 22.
  • the photoresist on the surface of the P-type semiconductor layer 23 is removed.
  • Gases used in dry-etching the epitaxial stack 20 using an inductively coupled plasma machine are chlorine (Cl2), boron trichloride (BCl3), and argon (Ar).
  • the epitaxial stack 20 is etched to a depth ranging from 0.9 ⁇ m to 2 ⁇ m (including 0.9 ⁇ m and 2 ⁇ m) using an inductively coupled plasma machine. That is, the depth of the semiconductor exposed portion 24 of the epitaxial stack 20 is 0.9 ⁇ m to 2 ⁇ m (including 0.9 ⁇ m and 2 ⁇ m).
  • a part of the thickness of the N-type semiconductor layer 21 is also etched so that the semiconductor exposed portion 24 is removed from the P-type
  • the semiconductor layer 23 extends to the middle of the N-type semiconductor layer 21 through the active region 22, so that the thickness dimension of the N-type semiconductor layer 21 corresponding to the semiconductor exposed portion 24 is smaller than the N-type semiconductor layer. 21 other thickness dimensions.
  • the number and type of the semiconductor exposed portions 24 of the epitaxial stack 20 are not limited in the semiconductor light emitting chip of the present invention.
  • the number of the semiconductor exposed portions 24 may be four, of which two of the semiconductor exposed portions 24 are circular and are located at one end of the semiconductor light emitting chip, and the other two of the semiconductor exposed portions 24 each have one located at The pad exposed portion in the middle of the semiconductor exposed portion chip and an extension bar exposed portion extending from the pad exposed portion to the other end portion of the semiconductor light emitting chip.
  • the type of the semiconductor exposed portion 24 shown in FIG. 1B is only an example, and it should not be considered as a limitation on the content and scope of the semiconductor light emitting chip of the present invention.
  • the reflective layer 30 is grown from the P-type semiconductor layer 23 of the epitaxial stack 20 so that the reflective layer 30 is stacked on the P-type of the epitaxial stack 20. A part of the surface of the semiconductor layer 23.
  • a pattern of the reflective layer 30 to be deposited is photoetched on the surface of the P-type semiconductor layer 23 of the epitaxial stack 20 with a negative photoresist, and secondly, evaporation or sputtering is used.
  • the reflective layer 30 is deposited on the pattern by a spray coating method.
  • the negative photoresist is removed.
  • the reflective layer 30 has a laminated structure.
  • the reflective layer 30 may be a laminated structure of silver (Ag) and titanium tungsten (TiW), wherein the thickness of the silver layer ranges from 1000 angstroms to 3000 angstroms (including 1000 angstroms and 3,000 angstroms), and the thickness of the titanium tungsten layer ranges from 200 angstroms to 2000 angstroms (including 200 angstroms and 2000 angstroms).
  • the reflective layer 30 is deposited on a part of the surface of the P-type semiconductor layer 23 by evaporation or sputtering, a blue film needs to be peeled off before the negative photoresist is removed. Excess metal layer.
  • the reflective layer 30 has at least one reflective layer perforation 31, wherein the semiconductor exposed portion 24 of the epitaxial stack 20 corresponds to the reflective layer perforation 31 of the reflective layer 30, so that the epitaxial stack 20
  • the exposed semiconductor portion 24 is connected to the reflective layer perforation 31 of the reflective layer 30.
  • the shape of the reflection layer perforation 31 of the reflection layer 30 is consistent with the shape of the semiconductor exposed portion 24 of the epitaxial stack 20, and the size of the reflection layer perforation 31 of the reflection layer 30 After the reflective layer 30 is laminated on the P-type semiconductor layer 23 of the epitaxial stack 20, the size of the semiconductor bare portion 24 larger than the epitaxial stack 20 is increased.
  • the length and width dimensions of the reflective layer 30 are smaller than the length and width dimensions of the P-type semiconductor layer 23 of the epitaxial stack 20, so that the reflective layer 30 is laminated on the epitaxial stack 20 After the P-type semiconductor layer 23, the peripheral surface of the epitaxial stack 20 is exposed because it is not covered by the reflective layer 30.
  • the surface of the P-type semiconductor layer 23 of the epitaxial stack 20 has at least one first region 231 and at least two second regions 232, and the outer and inner sides of any one of the first regions 231 are respectively provided There is one said second area 232.
  • the surface of the P-type semiconductor layer 23 of the epitaxial stack 20 has one of the first region 231 and two of the second region 232, one of which The second region 232 is formed in a middle portion of the P-type semiconductor layer 23 so as to surround the semiconductor exposed portion 24, and another second region 232 is formed on a peripheral surface of the P-type semiconductor layer 23.
  • the first region 231 is formed before the two second regions 232, wherein the reflective layer 30 is stacked on the P-type semiconductor layer in a manner that grows from the first region 231 of the P-type semiconductor layer 23 twenty three. That is, one of the second regions 232 of the P-type semiconductor layer 23 is a region of the P-type semiconductor layer 23 that is exposed to the reflective layer perforations 31 of the reflective layer 30. The other second region 232 of the semiconductor layer 23 is a peripheral surface of the P-type semiconductor layer 23 that is not covered by the reflective layer 30.
  • the insulating layer 40 is grown from at least a part of the surface of the second region 232 of the P-type semiconductor layer 23 of the epitaxial stack 20, so that the insulating layer 40 surrounds The outer side and the inner side of the reflective layer 30, wherein the insulating layer 40 can prevent the reflective layer 30 from moving to the outer side and the inner side in a manner that surrounds the outer side and the inner side of the reflective layer 30, thereby ensuring that The stability of the reflective layer 30 further ensures the stability of the semiconductor light emitting chip.
  • a vapor deposition method using vapor deposition, sputtering, or plasma enhanced chemistry is used to grow the insulating layer 40 from at least a part of the surface of the second region 232 of the P-type semiconductor layer 23, so that the insulating layer 40 surrounds the reflective layer 30. Outside and inside.
  • the insulating layer 40 is stacked on the entire region of the second region 232 of the P-type semiconductor layer 23. It is worth mentioning that the insulating layer 40 can further cover at least a part of the surface of the reflective layer 30.
  • the insulating layer 40 can be manufactured by using, but not limited to, negative adhesive peeling or positive adhesive etching.
  • the material for forming the insulating layer 40 is silicon dioxide (SiO2), so that the insulating layer 40 is dioxide that is laminated on the P-type semiconductor layer 23 and surrounds the inside and outside of the reflective layer 30. Silicon layer.
  • the thickness of the insulating layer 40 ranges from 100 angstroms to 5000 angstroms (including 100 angstroms and 5000 angstroms).
  • a thickness dimension of the insulating layer 40 is consistent with the thickness dimension of the reflective layer 30 in the specific example shown in FIGS. 3A and 3B, those skilled in the art should understand that In other possible examples of the semiconductor light emitting chip of the present invention, a thickness dimension of the insulating layer 40 may be larger than a thickness dimension of the reflective layer 30, so that the insulating layer 40 is higher than the reflective layer 30, Or the thickness dimension of the insulating layer 40 may be smaller than the thickness dimension of the reflective layer 30, so that the insulating layer 40 is lower than the reflective layer 30.
  • the diffusion prevention layer 50 is grown from the reflection layer 30 and the insulation layer 40, so that the diffusion prevention layer 50 is laminated on the reflection layer 30 and laminated on the insulation layer. 40, wherein the anti-diffusion layer 50 is capable of preventing a metal migration from occurring on the surface of the reflective layer 30 in a manner of being laminated on the surface of the reflective layer 30.
  • the insulating layer 40 surrounds the inside and the outside of the reflective layer 30 to prevent the reflective layer 30 from moving to the inside and the outside by the insulating layer 40, and the undesirable phenomenon of metal migration occurs, it is laminated with the anti-diffusion layer 50 On the surface of the reflection layer 30 to prevent the metal migration from occurring on the surface of the reflection layer 30 by the diffusion prevention layer 50, the reflection layer 30 is protected by the insulation layer 40 and the diffusion prevention The layers 50 are collectively covered to avoid the undesirable phenomenon of metal migration. In this way, the stability of the reflective layer 30 can be ensured, and the stability of the semiconductor light emitting chip can be further ensured.
  • the insulating layer 40 can isolate the anti-diffusion layer 50 and the P-type semiconductor layer 23 to pass through the insulation.
  • the layer 40 prevents the anti-diffusion layer 50 from directly contacting the P-type semiconductor layer 23. In this way, the semiconductor light-emitting chip can avoid abnormal breakdown of static electricity caused by current accumulation after being energized, thereby ensuring the semiconductor The reliability of the light-emitting chip when it is used.
  • the anti-diffusion layer 50 has at least one anti-diffusion layer perforation 51, wherein the semiconductor exposed portion 24 of the epitaxial stack 20 corresponds to the anti-diffusion layer perforation 51 of the anti-diffusion layer 50, so that the The exposed semiconductor portion 24 of the epitaxial stack 20 is in communication with the diffusion prevention layer through-hole 51 of the diffusion prevention layer 50.
  • the shape of the diffusion preventing layer perforation 51 of the diffusion preventing layer 50 is consistent with the shape of the semiconductor exposed portion 24 of the epitaxial stack 20.
  • the diffusion preventing layer perforation 51 of the diffusion preventing layer 50 is formed while the diffusion preventing layer 50 grows from the reflective layer 30 and the insulating layer 40.
  • a pattern of the anti-diffusion layer 50 to be deposited is produced on the outer surface of the insulating layer 40 by using negative photoresist photolithography, and secondly, it is deposited by evaporation or sputtering.
  • the anti-diffusion layer 50 is formed on the pattern so that the anti-diffusion layer 50 is laminated on the inner surfaces of the reflective layer 30 and the insulating layer 40.
  • the excess metal layer is peeled off using a blue film, and finally, it is removed.
  • a photoresist layer on the surface of the insulating layer 40 is used to form the diffusion preventing layer perforation 51 of the diffusion preventing layer 50.
  • the diffusion prevention layer 50 has a laminated structure.
  • the diffusion prevention layer 50 is a laminated structure of titanium tungsten (TiW) and platinum (Pt).
  • the extension electrode layer 60 includes at least one N-type extension electrode portion 61, wherein the N-type extension electrode portion 61 is held by the semiconductor bare portion 24 of the epitaxial stack 20. In this manner, the N-type semiconductor layer 21 is stacked.
  • the size and shape of the N-type extension electrode portion 61 are consistent with the size and shape of the semiconductor bare portion 24 of the epitaxial stack 20. Specifically, when the shape of the semiconductor exposed portion 24 of the epitaxial stack 20 is circular, the shape of the N-type extension electrode portion 61 is correspondingly circular. When the semiconductor exposed portion 24 is formed of the pad exposed portion and the extension bar exposed portion, the N-type extension electrode portion 61 includes a pad and an extension bar extending from the pad, respectively.
  • the size of the N-type extension electrode portion 61 is consistent with the size of the semiconductor bare portion 24 of the epitaxial stack 20 means that the size of the N-type extension electrode portion 61 is slightly smaller than that of the epitaxial stack 20
  • the size of the exposed semiconductor portion 24 is such that the N-type extension electrode portion 61 does not contact the active region 22 and the P-type semiconductor layer 23 used to form the exposed semiconductor portion 24.
  • the N-type extension electrode portion 61 is laminated on the N-type semiconductor layer 21 by using a negative adhesive peeling method. Specifically, first, a pattern of the N-type extended electrode portion 61 to be deposited is formed on the semiconductor bare portion 24 of the epitaxial stack 20 by using a negative photoresist photolithography method, and secondly, evaporation or The N-type extension electrode portion 61 is deposited on the pattern by sputtering, so that the N-type extension electrode portion 61 is stacked on the N-type semiconductor layer 21 so as to be held by the semiconductor bare portion 24, and then The blue metal film is used to peel off the excess metal layer. Finally, the photoresist layer is removed to form the N-type extended electrode portion 61.
  • the N-type extended electrode portion 61 is a reflective extended electrode portion capable of reflecting light generated by the active region 22.
  • the material forming the N-type extended electrode portion 61 is selected from the group consisting of chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), and gold (Au), so that the The N-type extended electrode portion 61 has a function of reflecting light generated by the active region 22.
  • the current isolation layer 70 includes a first isolation portion 71, wherein the first isolation portion 71 is grown from the insulating layer 40, the anti-diffusion layer 50, and the epitaxial stack. 20 and the N-type extension electrode portion 61, that is, the first isolation portion 71 is sequentially penetrated through the diffusion prevention layer 51 of the diffusion prevention layer 50 and the semiconductor bare portion 24 of the epitaxial stack 20 Extending to the N-type semiconductor layer 21 so that the first isolation portion 71 isolates the N-type extension electrode portion 61 from the active region 22 and isolates the N-type extension electrode portion 61 from the P-type Semiconductor layer 23.
  • the first isolation portion 71 has at least one first channel 711 and at least one second channel 712, wherein the first channel 711 extends to the N-type extension electrode portion 61 to expose the N-type extension electrode portion 61.
  • the second channel 712 extends to the diffusion prevention layer 50 to expose the diffusion prevention layer 50 in the second channel 712.
  • a first isolation base layer is grown from the insulating layer 40, the diffusion prevention layer 50, the epitaxial stack 20, and the N-type extension electrode portion 61, wherein the first isolation portion
  • the base layer extends to the N-type semiconductor layer 21 through the diffusion preventing layer perforation 51 of the diffusion preventing layer 50 and the semiconductor exposed portion 24 of the epitaxial stack 20 in order, so that the first isolation portion base layer Isolating the N-type extended electrode portion 61 from the active region 22 and isolating the N-type extended electrode portion 61 from the P-type semiconductor layer 23.
  • a photoresist photolithography method is used to determine the etched position of the first isolation base layer, and then an inductively coupled plasma machine (ICP) is used to etch the first isolation base layer to The first channel 711 extending to the N-type extension electrode portion 61 and the second channel 712 extending to the diffusion prevention layer 50 are formed, and the first isolation portion base layer forms the first isolation portion 71.
  • ICP inductively coupled plasma machine
  • the first isolation portion 71 is a distributed Bragg reflector (DBR) structure, wherein the first isolation portion 71 uses an overlap structure of silicon oxide and titanium oxide, and the first isolation portion 71.
  • DBR distributed Bragg reflector
  • the number of pairs of reflective layer pairs of the first isolation portion 71 ranges from 20 to -50. Pairs (including 20 pairs and 50 pairs).
  • the electrode group 80 includes an N-type electrode 81 and a P-type electrode 82, wherein the N-type electrode 81 and the P-type electrode 82 are stacked on the first electrode in a spaced manner.
  • An isolation portion 71, and the N-type electrode 81 extends to the N-type extension electrode portion 61 via the first channel 711 of the first isolation portion 71, and the P-type electrode 82 passes through the first isolation
  • the second channel 712 of the portion 71 extends to the diffusion prevention layer 50.
  • the N-type electrode 81 further has at least one N-type electrode connection pin 811, wherein when the N-type electrode 81 is stacked on the first isolation portion 71, the N-type electrode connection pin 811 is formed on And the first channel 711 held in the first isolation portion 71, so that the N-type electrode connection pin 811 of the N-type electrode 81 passes through the first channel of the first isolation portion 71 711 extends to the N-type extension electrode portion 61.
  • the P-type electrode 82 further has at least one P-type electrode connection pin 821, and when the P-type electrode 82 is stacked on the first isolation portion 71, the P-type electrode connection pin 821 is formed on and Is held in the second channel 712 of the first isolation portion 71 such that the P-type electrode connection pin 821 of the P-type electrode 82 passes through the second channel 712 of the first isolation portion 71 Extending to the diffusion prevention layer 50.
  • the thickness dimension range of the N-type electrode 81 and the P-type electrode 82 is 1 ⁇ m to 5 ⁇ m (including 1 ⁇ m and 5 ⁇ m), wherein the thickness dimension of the N-type electrode 81 refers to the thickness of the N-type electrode 81.
  • the thickness dimension of the main body that is, the thickness dimension of the N-type electrode 81 does not include the extension length of the N-type electrode connection pin 811.
  • the thickness dimension range of the P-type electrode 82 refers to the P-type The thickness dimension of the body portion of the electrode 82, that is, the thickness dimension of the P-type electrode 82 does not include the extension length of the P-type electrode connection pin 821.
  • the N-type electrode 81 and the P-type electrode 82 are laminated on the first isolation portion 71 by using a negative adhesive peeling method. Specifically, first, a pattern of the N-type electrode 81 and the P-type electrode 82 to be deposited is prepared by using a negative photoresist photolithography method in the first isolation portion 71, and secondly, evaporation or The N-type electrode 81 and the P-type electrode 82 are deposited on the pattern by sputtering, so that the N-type electrode connection pin 811 of the N-type electrode 81 is held on the first isolation portion 71.
  • the first channel 711 and the N-type extension electrode portion 61 extending through the first channel 711 and the P-type electrode connection pin 821 of the P-type electrode 82 are maintained at the first isolation.
  • the second channel 712 of the portion 71 and the diffusion prevention layer 50 are extended through the second channel 712. Then, a blue film is used to strip off excess metal, and finally, the photoresist layer is removed to form the N And a P-type electrode 81.
  • the N-type electrode 81 and the P-type electrode 82 are reflective electrodes capable of reflecting light generated by the active region 22.
  • a material forming the N-type electrode 81 and the P-type electrode 82 is selected from the group consisting of chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), and gold (Au). Material group, so that the N-type electrode 81 and the P-type electrode 82 have the function of reflecting light generated by the active region 22.
  • the present invention further provides a method for manufacturing a semiconductor light emitting chip, wherein the manufacturing method includes the following steps:
  • the N-type electrode 81 is electrically connected to the N-type semiconductor layer 21 and the P-type electrode 82 is electrically connected to the diffusion prevention layer 50 to obtain the semiconductor light emitting chip.
  • the substrate 10, the N-type semiconductor layer 21, the active region 22, the P-type semiconductor layer 23, The reflection layer 30, the insulation layer 40, the diffusion prevention layer 50, the N-type extension electrode portion 61, the first isolation portion 71, the N-type electrode 81, and the P-type electrode 82 The thickness is only an example, and it does not mean that the substrate 10, the N-type semiconductor layer 21, the active region 22, the P-type semiconductor layer 23, the reflective layer 30, the insulating layer 40, The true thicknesses of the diffusion preventing layer 50, the N-type extension electrode portion 61, the first isolation portion 71, the N-type electrode 81, and the P-type electrode 82.
  • the true ratio between the N-type extension electrode portion 61, the first isolation portion 71, the N-type electrode 81, and the P-type electrode 82 is not as shown in the drawings.
  • the ratios of the sizes of the N-type electrode 81 and the P-type electrode 82 to the sizes of other layers of the semiconductor light emitting chip are not limited to those shown in the drawings.
  • the semiconductor light emitting chip includes A substrate 10A, an epitaxial stack 20A, a reflective layer 30A, at least one insulating layer 40A, a diffusion prevention layer 50A, an extended electrode layer 60A, a current isolation layer 70A, and an electrode group 80A.
  • 8A to 15B further illustrate a manufacturing process of the semiconductor light emitting chip.
  • the substrate of the semiconductor light emitting chip will be further disclosed and explained in conjunction with the manufacturing process of the semiconductor light emitting chip.
  • 10A between the epitaxial stack 20A, the reflective layer 30A, the insulating layer 40A, the diffusion preventing layer 50A, the extension electrode layer 60A, the current isolation layer 70A, and the electrode group 80A relationship.
  • the epitaxial stack 20A includes an N-type semiconductor layer 21A, an active region 22A, and a P-type semiconductor layer 23A.
  • the N-type semiconductor layer 21A is grown on the substrate 10A. So that the N-type semiconductor layer 21A is stacked on the substrate 10A, wherein the active region 22A is grown on the N-type semiconductor layer 21A, so that the active region 22A is stacked on the N-type semiconductor Layer 21A, wherein the P-type semiconductor layer 23A is grown on the active region 22A, so that the P-type semiconductor layer 23A is stacked on the active region 22A.
  • both the N-type semiconductor layer 21A and the P-type semiconductor layer 23A may be implemented as a gallium nitride layer, that is, the epitaxial stack
  • the layer 20A includes an N-type gallium nitride layer stacked on the substrate 10A, the active region 22A stacked on the N-type gallium nitride layer, and a P-type nitrogen stacked on the active region 22A.
  • Gallium layer is an N-type gallium nitride layer stacked on the substrate 10A, the active region 22A stacked on the N-type gallium nitride layer, and a P-type nitrogen stacked on the active region 22A.
  • the manner in which the epitaxial stack 20A is stacked on the substrate 10A is not limited, for example, as shown in FIGS. 8A to 8B
  • the metal-organic compound chemical vapor deposition equipment MOCVD
  • MOCVD metal-organic compound chemical vapor deposition equipment
  • the type of the substrate 10A is not limited in the semiconductor light emitting chip of the present invention.
  • the substrate 10A may be, but is not limited to, an aluminum oxide (Al2O3) substrate, silicon carbide (SiC ) Substrate, silicon (Si) substrate, gallium nitride (GaN) substrate, gallium arsenide (GaAs) substrate, and gallium phosphide (GaP) substrate.
  • Al2O3 aluminum oxide
  • SiC silicon carbide
  • SiC silicon carbide
  • Si silicon
  • GaN gallium nitride
  • GaAs gallium arsenide
  • GaP gallium phosphide
  • the epitaxial stack 20A further has at least one semiconductor exposed portion 24A, wherein the semiconductor exposed portion 24A extends from the P-type semiconductor layer 23A through the active region 22A to the
  • the N-type semiconductor layer 21A is such that a part of the surface of the N-type semiconductor layer 21A is exposed to the semiconductor exposed portion 24A.
  • the semiconductor exposed portion 24A may be formed by etching the epitaxial stack 20A.
  • a photoresist is used to photoetch the epitaxial stack 20A laminated on the substrate 10A to expose the area of the epitaxial stack 20A that needs to be etched.
  • the thickness of the photoresist is 3 ⁇ m to 5 ⁇ m (including 3 ⁇ m and 5 ⁇ m).
  • the epitaxial stack 20A is dry-etched using an inductively coupled plasma machine (ICP), so that the epitaxial stack 20A is formed from the P A type semiconductor layer 23A extends to the semiconductor exposed portion 24A of the N type semiconductor layer 21A through the active region 22A. Finally, the photoresist on the surface of the P-type semiconductor layer 23A is removed.
  • the gases used when dry etching the epitaxial stack 20A using an inductively coupled plasma machine are chlorine (Cl2), boron trichloride (BCl3), and argon (Ar).
  • the epitaxial stack 20A is etched to a depth ranging from 0.9 ⁇ m to 2 ⁇ m (including 0.9 ⁇ m and 2 ⁇ m) using an inductively coupled plasma machine. That is, the depth of the semiconductor exposed portion 24A of the epitaxial stack 20A is in a range of 0.9 ⁇ m to 2 ⁇ m (including 0.9 ⁇ m and 2 ⁇ m).
  • a part of the thickness of the N-type semiconductor layer 21A is also etched so that the semiconductor exposed portion 24A is changed from the P-type
  • the semiconductor layer 23A extends to the middle of the N-type semiconductor layer 21A through the active region 22A, so that the thickness dimension of the N-type semiconductor layer 21A corresponding to the semiconductor exposed portion 24A is smaller than the N-type semiconductor layer 21A thickness of other parts.
  • the number and type of the semiconductor exposed portions 24A of the epitaxial stack 20A are not limited in the semiconductor light emitting chip of the present invention.
  • the epitaxial stack 20A shown in FIG. 8B Specific examples are merely examples, and they do not constitute a limitation on the content and scope of the semiconductor light emitting chip of the present invention.
  • the reflective layer 30A is grown from the P-type semiconductor layer 23A of the epitaxial stack 20A, so that the reflective layer 30A is stacked on the P-type of the epitaxial stack 20A. A part of the surface of the semiconductor layer 23A.
  • a pattern of the reflective layer 30A to be deposited is photoetched on the surface of the P-type semiconductor layer 23A of the epitaxial stack 20A with a negative photoresist, and secondly, evaporation or sputtering is used.
  • the reflective layer 30A is deposited on the pattern by a spray coating method. Finally, the negative photoresist is removed.
  • the reflective layer 30A adopts a laminated structure.
  • the reflective layer 30A may be a laminated structure of silver (Ag) and titanium tungsten (TiW), wherein the thickness of the silver layer ranges from 1000 angstroms to 3000 angstroms (including 1000 angstroms and 3000 angstroms), and the thickness of the titanium tungsten layer ranges from 200 angstroms to 2000 angstroms (including 200 angstroms and 2000 angstroms).
  • the reflective layer 30A is deposited on a part of the surface of the P-type semiconductor layer 23A by evaporation or sputtering, a blue film needs to be peeled off before the negative photoresist is removed. Excess metal layer.
  • the reflective layer 30A has at least one reflective layer perforation 31A, wherein the semiconductor exposed portion 24A of the epitaxial stack 20A corresponds to the reflective layer perforation 31A of the reflective layer 30A, so that the epitaxial stack 20A The exposed semiconductor portion 24A and the reflective layer perforation 31A of the reflective layer 30A are in communication with each other.
  • the shape of the reflection layer perforation 31A of the reflection layer 30A is consistent with the shape of the semiconductor exposed portion 24A of the epitaxial stack 20A, and the size of the reflection layer perforation 31A of the reflection layer 30A
  • the size of the exposed semiconductor portion 24A that is larger than the epitaxial stack 20A is such that after the reflective layer 30A is stacked on the P-type semiconductor layer 23A of the epitaxial stack 20A, the P-type A part of the surface of the semiconductor layer 23A is exposed in the reflective layer perforation 31A of the reflective layer 30A.
  • the length and width dimensions of the reflective layer 30A are smaller than the length and width dimensions of the P-type semiconductor layer 23A of the epitaxial stack 20A, so that the reflective layer 30A is stacked on the epitaxial stack 20A. After the P-type semiconductor layer 23A, the peripheral surface of the epitaxial stack 20A is exposed because it is not covered by the reflective layer 30A.
  • the surface of the P-type semiconductor layer 23A of the epitaxial stack 20A has at least one first region 231A and at least two second regions 232A, and the outside and the inside of any one of the first regions 231A are respectively provided There is one said second area 232A.
  • the surface of the P-type semiconductor layer 23A of the epitaxial stack 20A has one of the first region 231A and two of the second region 232A, one of which The second region 232A is formed in a middle portion of the P-type semiconductor layer 23A so as to surround the semiconductor exposed portion 24A, and another second region 232A is formed on a peripheral surface of the P-type semiconductor layer 23A.
  • the first region 231A is formed before the two second regions 232A, wherein the reflective layer 30A is stacked on the P-type semiconductor layer in a manner of growing from the first region 231A of the P-type semiconductor layer 23A.
  • 23A one of the second regions 232A of the P-type semiconductor layer 23A is an area of the P-type semiconductor layer 23A that is exposed to the reflective layer perforation 31A of the reflective layer 30A, and the P-type
  • the other second region 232A of the semiconductor layer 23A is a peripheral surface of the P-type semiconductor layer 23A that is not covered by the reflective layer 30A.
  • the insulating layer 40A is grown from at least a part of the surface of the second region 232A of the P-type semiconductor layer 23A of the epitaxial stack 20A, so that the insulating layer 40A surrounds The outside and inside of the reflective layer 30A, wherein the insulating layer 40A can prevent the reflection of the reflective layer 30A from appearing to the outside and inside in a manner that surrounds the outside and inside of the reflection layer 30A, thereby ensuring that The stability of the reflective layer 30A further ensures the stability of the semiconductor light emitting chip.
  • a vapor deposition method using vapor deposition, sputtering, or plasma enhanced chemistry is used to grow the insulating layer 40A from at least a part of the surface of the second region 232A of the P-type semiconductor layer 23A, so that the insulating layer 40A surrounds the reflective layer 30A. Outside and inside.
  • the insulating layer 40A is stacked on the entire region of the second region 232A of the P-type semiconductor layer 23A.
  • the insulating layer 40A can further cover at least a part of the surface of the reflective layer 30A.
  • the insulating layer 40A can be manufactured by using, but not limited to, a negative adhesive peeling or a positive adhesive etching.
  • the material for forming the insulating layer 40A is silicon dioxide (SiO2), so that the insulating layer 40A is dioxide that is laminated on the P-type semiconductor layer 23A and surrounds the inside and outside of the reflective layer 30A. Silicon layer.
  • the thickness of the insulating layer 40A ranges from 100 angstroms to 5000 angstroms (including 100 angstroms and 5000 angstroms).
  • a thickness dimension of the insulating layer 40A may be larger than a thickness dimension of the reflective layer 30A, so that the insulating layer 40A is higher than the reflective layer 30A, Alternatively, the thickness of the insulating layer 40A may be smaller than the thickness of the reflective layer 30A, so that the insulating layer 40A is lower than the reflective layer 30A.
  • the diffusion preventing layer 50A is grown from the reflective layer 30A and the insulating layer 40A, so that the diffusion preventing layer 50A is stacked on the reflective layer 30A and stacked on the insulating layer.
  • 40A wherein the anti-diffusion layer 50A is capable of preventing the metal migration from occurring on the surface of the reflective layer 30A in a manner of being laminated on the surface of the reflective layer 30A. Because the insulation layer 40A surrounds the inside and outside of the reflection layer 30A to prevent the reflection of the reflection layer 30A from appearing to the inside and the outside by the insulation layer 40A, a metal migration defect occurs, and the diffusion prevention layer 50A is laminated.
  • the reflective layer 30A On the surface of the reflective layer 30A to prevent the metal migration from occurring on the surface of the reflective layer 30A by the anti-diffusion layer 50A, the reflective layer 30A is protected by the insulating layer 40A and the anti-diffusion.
  • the layers 50A are collectively covered to avoid the undesirable phenomenon of metal migration. In this way, the stability of the reflective layer 30A can be ensured, and the stability of the semiconductor light-emitting chip is further ensured.
  • the insulating layer 40A can isolate the anti-diffusion layer 50A and the P-type semiconductor layer 23A so as to pass through the insulation.
  • the layer 40A prevents the anti-diffusion layer 50A from directly contacting the P-type semiconductor layer 23A. In this way, the semiconductor light-emitting chip can avoid abnormal breakdown of static electricity caused by current accumulation after being energized, thereby ensuring the semiconductor The reliability of the light-emitting chip when it is used.
  • the diffusion prevention layer 50A has at least one diffusion prevention layer perforation 51A, wherein the semiconductor exposed portion 24A of the epitaxial stack 20A corresponds to the diffusion prevention layer perforation 51A of the diffusion prevention layer 50A, so that the diffusion prevention layer 50A
  • the semiconductor bare portion 24A of the epitaxial stack 20A is in communication with the diffusion preventing layer perforation 51A of the diffusion preventing layer 50A.
  • the shape of the diffusion prevention layer perforation 51A of the diffusion prevention layer 50A is consistent with the shape of the semiconductor bare portion 24A of the epitaxial stack 20A.
  • the diffusion preventing layer 50A of the diffusion preventing layer 50A is formed while the diffusion preventing layer 50A grows from the reflective layer 30A and the insulating layer 40A.
  • a pattern of the anti-diffusion layer 50A needs to be deposited on the outer surface of the insulating layer 40A by using negative photoresist photolithography, and secondly, it is deposited by evaporation or sputtering.
  • the anti-diffusion layer 50A is formed on the pattern so that the anti-diffusion layer 50A is laminated on the inner surfaces of the reflective layer 30A and the insulating layer 40A.
  • the excess metal layer is peeled off using a blue film, and finally, A photoresist layer on the surface of the insulating layer 40A to form the diffusion preventing layer 51A of the diffusion preventing layer 50A.
  • the anti-diffusion layer 50A has a laminated structure.
  • the anti-diffusion layer 50A is a laminated structure of titanium tungsten (TiW) and platinum (Pt).
  • the current isolation layer 70A includes a first isolation portion 71A, wherein the first isolation portion 71A is grown from the insulating layer 40A, the anti-diffusion layer 50A, and the epitaxial stack. 20A, that is, the first isolation portion 71A extends to the N-type semiconductor layer 21A through the diffusion prevention layer perforation 51A of the diffusion prevention layer 50A and the semiconductor bare portion 24A of the epitaxial stack 20A in this order. .
  • the first isolation portion 71A has at least one first channel 711A and at least one second channel 712A, wherein the first channel 711A extends to the N-type semiconductor layer 21A of the epitaxial stack 20A to expose the A portion of the surface of the N-type semiconductor layer 21A is on the first channel 711A, and the second channel 712A extends to the diffusion prevention layer 50A to expose a portion of the surface of the diffusion prevention layer 50A on the second channel 712A.
  • a first isolation base layer is grown from the insulating layer 40A, the diffusion prevention layer 50A, and the epitaxial stack 20A, wherein the first isolation base layer passes through the diffusion prevention layer 50A in order.
  • the anti-diffusion layer perforation 51A and the semiconductor bare portion 24A of the epitaxial stack 20A extend to the N-type semiconductor layer 21A.
  • a photoresist photolithography method is used to determine the etched position of the first isolation base layer, and then an inductively coupled plasma machine (ICP) is used to etch the first isolation base layer to The first channel 711A extending to the N-type semiconductor layer 21A of the epitaxial stack 20A and the second channel 712A extending to the diffusion prevention layer 50A are formed, and the first spacer base layer is formed The first isolation portion 71A.
  • ICP inductively coupled plasma machine
  • the first isolation portion 71A is a distributed Bragg reflector structure (Distributed Bragg reflection, DBR), wherein the first isolation portion 71A uses an overlapping structure of silicon oxide and titanium oxide, and the first isolation portion 71A designs different reflection layer pairs for different wavelengths.
  • DBR distributed Bragg reflection
  • the number of pairs of the reflection layer pairs of the first isolation portion 71A ranges from 20 to -50. Pairs (including 20 pairs and 50 pairs).
  • the extended electrode layer 60A includes at least one N-type extended electrode portion 61A and at least one P-type extended electrode portion 62A, wherein the N-type extended electrode portion 61A and the P-type extended electrode portion 62A are stacked on the first isolation portion 71A at intervals, and the N-type extension electrode portion 61A extends to the epitaxial stack 20A through the first channel 711A of the first isolation portion 71A.
  • the N-type semiconductor layer 21A and the P-type extension electrode portion 62A extend to the anti-diffusion layer 50A through the second channel 712A of the first isolation portion 71A.
  • the N-type extension electrode portion 61A has at least one N-type extension electrode pin 611A, and when the N-type extension electrode portion 61A is stacked on the first isolation portion 71A, the N-type extension electrode pin 611A is formed in and held by the first channel 711A of the first isolation portion 71A, so that the N-type extension electrode portion 61A extends through the first channel 711A of the first isolation portion 71A to The N-type semiconductor layer 21A of the epitaxial stack 20A.
  • the P-type extension electrode portion 62A has at least one P-type extension electrode pin 621A, and when the P-type extension electrode portion 62A is stacked on the first isolation portion 71A, the P-type extension electrode pin 621A The second channel 712A formed and held in the first isolation portion 71A, so that the P-type extension electrode portion 62A extends to the second channel 712A through the first isolation portion 71A Anti-diffusion layer 50A.
  • the N-type extension electrode portion 61A and the P-type extension electrode portion 62A are laminated on the first separation portion 71A by using a negative adhesive peeling method. Specifically, first, a pattern for depositing the N-type extension electrode portion 61A and the P-type extension electrode portion 62A is produced by using a negative photoresist photolithography method on the first isolation portion 71A, and secondly, using The N-type extension electrode portion 61A and the P-type extension electrode portion 62A are deposited on the pattern by vapor deposition or sputtering so that the N-type extension electrode pin 611A of the N-type extension electrode portion 61A is held.
  • the P-type extended electrode needle 621A is held in the second channel 712A of the first isolation portion 71A and extends to the diffusion prevention layer 50A through the second channel 712A.
  • the N-type extension electrode portion 61A and the P-type extension electrode portion 62A are reflective extension electrode portions capable of reflecting light generated in the active region 22A.
  • a material forming the N-type extension electrode portion 61A and the P-type extension electrode portion 62A is selected from the group consisting of chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), and gold (Au). The material group is formed so that the N-type extension electrode portion 61A and the P-type extension electrode portion 62A have a function of reflecting light generated by the active region 22A.
  • the current isolation layer 70A includes a second isolation portion 72A, wherein the second isolation portion 72A is grown from the N-type extension electrode portion 61A, the P-type extension electrode portion 62A, and The first isolation portion 71A, that is, the second isolation portion 72A fills a gap formed between the N-type extension electrode portion 61A and the P-type extension electrode portion 62A.
  • the second isolation portion 72A has at least a third channel 721A and at least a fourth channel 722A, wherein the third channel 721A extends to the N-type extension electrode portion 61A, so that the N-type extension electrode portion 61A A portion of the surface of the P-type extended electrode portion 62A is exposed to the third channel 721A, and the fourth channel 722A extends to the P-type extended electrode portion 62A.
  • Four channels 722A extends to the P-type extended electrode portion 62A.
  • a second isolation base layer is grown from the N-type extension electrode portion 61A, the P-type extension electrode portion 62A, and the first isolation portion 71A, wherein the second isolation portion base layer is filled in A gap formed between the N-type extension electrode portion 61A and the P-type extension electrode portion 62A.
  • a positive photoresist is used to determine the etched position of the second isolation base layer, and then a dry etching is used to etch the etched position of the second isolation base layer to form an extension to the N
  • the third channel 721A of the type extension electrode portion 61A and the fourth channel 722A extending to the P-type extension electrode portion 62A are formed.
  • the base layer of the second isolation portion is grown on the N-type extension electrode portion 61A and the P-type extension electrode portion 62A by a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Deposition, PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the first isolation portion 71A wherein the gas used when depositing the base layer of the second isolation portion using a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Deposition, PECVD) is silane (SiH4), a Nitrogen oxide (N2O) and nitrogen (N2).
  • the thickness of the base layer of the second isolation portion ranges from 5000 angstroms to 20,000 angstroms (including 5000 angstroms and 20,000 angstroms).
  • the electrode group 80A includes an N-type electrode 81A and a P-type electrode 82A, wherein the N-type electrode 81A and the P-type electrode 82A are stacked on the first electrode at a distance from each other.
  • Two isolation portions 72A, and the N-type electrode 81A extends through the third channel 721A of the second isolation portion 72A to the N-type extension electrode portion 61A, and the P-type electrode 82A is separated by the second isolation
  • the fourth channel 722A of the portion 72A extends to the P-type extension electrode portion 62A.
  • the N-type electrode 81A further has at least one N-type electrode connection pin 811A, wherein when the N-type electrode 81A is stacked on the first isolation portion 71A, the N-type electrode connection pin 811A is formed on And the third channel 721A held in the second isolation portion 72A, so that the N-type electrode connection pin 811A of the N-type electrode 81A passes through the third channel of the second isolation portion 72A 721A extends to the N-type extension electrode portion 61A.
  • the P-type electrode 82A further has at least one P-type electrode connection pin 821A, wherein when the P-type electrode 82A is stacked on the first isolation portion 71A, the P-type electrode connection pin 821A is formed on and The fourth channel 722A is held in the second isolation portion 72A, so that the P-type electrode connection pin 821A of the P-type electrode 82A passes through the fourth channel 722A of the second isolation portion 72A. Extending to the P-type extension electrode portion 62A.
  • the thickness dimension range of the N-type electrode 81A and the P-type electrode 82A is 1 ⁇ m to 5 ⁇ m (including 1 ⁇ m and 5 ⁇ m), where the thickness dimension of the N-type electrode 81A refers to The thickness dimension of the main body, that is, the thickness dimension of the N-type electrode 81A does not include the extension length of the N-type electrode connection pin 811A. Accordingly, the thickness dimension range of the P-type electrode 82A refers to the P-type The thickness dimension of the body portion of the electrode 82A, that is, the thickness dimension of the P-type electrode 82A does not include the extension length of the P-type electrode connection pin 821A.
  • the N-type electrode 81A and the P-type electrode 82A are laminated on the second separation portion 72A by using a negative adhesive peeling method. Specifically, first, a pattern of the N-type electrode 81A and the P-type electrode 82A to be deposited is formed in the second isolation portion 72A by using negative photoresist photolithography, and secondly, evaporation or The N-type electrode 81A and the P-type electrode 82A are deposited on the pattern by sputtering, so that the N-type electrode connection pin 811A of the N-type electrode 81A is held in the second isolation portion 72A.
  • the third channel 721A and the N-type extension electrode portion 61A extending through the third channel 721A, and the P-type electrode connection pin 821A of the P-type electrode 82A are maintained at the second isolation.
  • the fourth channel 722A of the portion 72A and the P-type extension electrode portion 62A extending through the fourth channel 722A are then stripped of excess metal using a blue film.
  • the photoresist layer is removed to form the photoresist layer.
  • the N-type electrode 81A and the P-type electrode 82A are reflective electrodes capable of reflecting light generated in the active region 22A.
  • the material forming the N-type electrode 81A and the P-type electrode 82A is selected from the group consisting of chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), and gold (Au). Material group, so that the N-type electrode 81A and the P-type electrode 82A have the function of reflecting light generated by the active region 22A.
  • the present invention further provides a method for manufacturing a semiconductor light emitting chip, wherein the manufacturing method includes the following steps:
  • the N-type electrode 81A is electrically connected to the N-type semiconductor layer 21A and the P-type electrode 82A is electrically connected to the anti-diffusion layer 50A to obtain the semiconductor light emitting chip.
  • the insulating layer 40A shown in FIGS. 8A to 15B all surrounds the inside and outside of the reflective layer 30A in a manner of growing from a part of the surface of the P-type semiconductor layer 23A.
  • the insulating layer 40A may also be grown from the active region 22A, the N-type semiconductor layer 21A, or the Substrate 10A.
  • the growth position of the insulating layer 40A is not limited in the manufacturing method and the semiconductor chip of the present invention, as long as it can surround the inside and outside of the reflective layer 30A and isolate the anti-diffusion layer 50A and the P-type semiconductor layer 23A may be sufficient.
  • the substrate 10A, the N-type semiconductor layer 21A, the active region 22A, and the P-type semiconductor layer 23A of the semiconductor light emitting chip shown in the drawings of the present invention The reflective layer 30A, the insulating layer 40A, the anti-diffusion layer 50A, the N-type extension electrode portion 61A, the P-type extension electrode portion 62A, the first isolation portion 71A, and the second isolation
  • the thickness of the portion 72A, the N-type electrode 81A, and the P-type electrode 82A is only an example, and it does not represent the substrate 10A, the N-type semiconductor layer 21A, the active region 22A, the P Type semiconductor layer 23A, the reflection layer 30A, the insulating layer 40A, the diffusion prevention layer 50A, the N-type extension electrode portion 61A, the P-type extension electrode portion 62A, the first isolation portion 71A,
  • the true scale is not as shown in the drawings.
  • the ratios of the sizes of the N-type electrode 81A and the P-type electrode 82A to the sizes of other layers of the semiconductor light emitting chip are not limited to those shown in the drawings.

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Abstract

本发明公开了一半导体发光芯片及其制造方法，其中所述半导体发光芯片包括一衬底和自所述衬底依次生长的一N型半导体层、一有源区、一P型半导体层、一反射层、至少两绝缘层、一防扩散层以及一电极组，其中一个所述绝缘层环绕在所述反射层的内侧，另一个所述绝缘层环绕在所述反射层的外侧，并且所述绝缘层隔离所述防扩散层和所述P型半导体层，其中所述电极组包括一N型电极和一P型电极，其中所述N型电极被电连接于所述N型半导体层，所述P型电极被电连接于所述P型半导体层。

Description

半导体发光芯片及其制造方法 技术领域
本发明涉及半导体发光二极管，特别涉及一半导体发光芯片及其制造方法。
背景技术
通常情况下，高亮度倒装芯片普遍采用金属银作为反射镜的材料，以形成层叠于P型氮化镓层的银镜，但是由于该P型氮化镓层的功函数为7.5eV，而该银镜的功函数为4.26eV，并且理论上只有当该银镜的功函数大于该P型氮化镓层的功函数时，该银镜才能与该P型氮化镓层之间形成低电阻的欧姆接触，但实际上，因为该银镜的功函数小于该P型氮化镓层的功函数，导致该银镜无法与该P型氮化镓层形成低电阻的欧姆接触。因为形成该银镜的金属银为活泼金属，在存在电势差、高湿度、高温度的条件下，该银镜容易出现金属迁移的不良现象，而一旦该银镜出现金属迁移的不良现象，则容易导致漏电、器件失效等异常情况出现，因此，采用该银镜的高亮度倒装芯片还需要提供一个包覆该银镜的防扩散层，即，该防扩散层需要与该P型氮化镓层直接接触(该防扩散层层叠于该P型氮化镓层)才能够完全包覆该银镜。也就是说，该防扩散层的长宽尺寸均需大于该银镜的长宽尺寸，这导致该防扩散层会直接以接触该P型氮化镓层的方式层叠于该P型氮化镓层。因为形成该防扩散层的材料通常是钛(Ti)、钛钨(TiW)、镍(Ni)等金属材料，在实际使用过程中，该防扩散层与该P型氮化镓层的接触电阻低于该银镜与该P型氮化镓层的接触电阻，这就容易导致从P型电极注入的电流聚集在该区域(该防扩散层与该P型氮化镓层接触的区域)内，从而导致该区域的电流密度过高，进而导致静电击穿异常。
发明内容
本发明的一个目的在于提供一半导体发光芯片及其制造方法，其中所述半导体发光芯片能够避免出现静电击穿的不良现象，以保证所述半导体芯片在被使用时的可靠性。
本发明的一个目的在于提供一半导体发光芯片及其制造方法，其中所述半导体发光芯片通过阻止一防扩散层直接接触一P型半导体层的方式避免电流聚集而导致的静电击穿异常，从而保证所述半导体发光芯片在被使用时的可靠性。
本发明的一个目的在于提供一半导体发光芯片及其制造方法，其中所述半导体发光芯片提供一绝缘层，以藉由所述绝缘层以隔离所述防扩散层和所述P型半导体层的方式阻止所述防扩散层直接接触所述P型半导体层。
本发明的一个目的在于提供一半导体发光芯片及其制造方法，其中所述绝缘层环绕在一反射层的四周，所述防扩散层以层叠于所述反射层和所述绝缘层的方式避免所述反射层出现金属迁移的不良现象，从而保证所述半导体发光芯片的稳定性。
本发明的一个目的在于提供一半导体发光芯片及其制造方法，其中在所述绝缘层层叠于所述P型半导体层之后，层叠所述防扩散层于所述绝缘层和所述反射层，通过这样的方式， 所述绝缘层不仅能够阻止所述防扩散层接触所述P型半导体层，而且所述绝缘层能够与所述防扩散层相互配合而包覆所述反射层，从而避免所述反射层出现金属迁移的不良现象。
依本发明的一个方面，本发明提供一半导体发光芯片，其包括：
一衬底；
一外延叠层，其中所述外延叠层包括一N型氮化镓层、一有源区以及一P型氮化镓层，其中所述衬底、所述N型氮化镓层、所述有源区和所述P型氮化镓层依次层叠；
至少一反射层，其中所述反射层层叠于所述P型氮化镓层的一部分表面；
至少两绝缘层，其中一个所述绝缘层以层叠于所述P型氮化镓层的一部分表面的方式环绕于所述反射层的内侧，另一个所述绝缘层以层叠于所述P型氮化镓层的一部分表面的方式环绕于所述反射层的外侧；
至少一防扩散层，其中所述防扩散层层叠于所述反射层和所述绝缘层；以及
一电极组，其中所述电极组包括一N型电极和一P型电极，其中所述N型电极被电连接于所述外延叠层的所述N型氮化镓层，所述P型电极被电连接于所述防扩散层。
依本发明的另一个方面，本发明进一步提供一半导体发光芯片的制造方法，其中所述制造方法包括如下步骤：
(a)自一衬底依次生长一N型氮化镓层、一有源区以及一P型氮化镓层；
(b)层叠一反射层于所述P型氮化镓层的一部分表面；
(c)分别环绕一绝缘层于所述反射层的内侧和外侧；
(d)自所述反射层和所述绝缘层生长一防扩散层；以及
(e)电连接一N型电极于所述N型氮化镓层和电连接一P型电极于所述防扩散层，以制得所述半导体发光芯片。
附图说明
图1A和图1B分别是依本发明的一较佳实施例的一半导体发光芯片的制作步骤之一的剖视示意图和俯视示意图。
图2A和图2B是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之二的剖视示意图和俯视示意图。
图3A和图3B分别是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之三的剖视示意图和俯视示意图。
图4A和图4B分别是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之四的剖视示意图和俯视示意图。
图5A和图5B分别是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之五的剖视示意图和俯视示意图。
图6A和图6B分别是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之六的剖视示意图和俯视示意图。
图7A和图7B分别是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之七的剖视示意图和俯视示意图，并且图7A示出了所述半导体发光芯片的剖视状态，图7B示出了所述半导体发光芯片的俯视状态。
图8A和图8B分别是依本发明的一较佳实施例的一半导体发光芯片的制作步骤之一的剖视示意图和俯视示意图。
图9A和图9B分别是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之二的剖视示意图和俯视示意图。
图10A和图10B分别是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之三的剖视示意图和俯视示意图。
图11A和图11B分别是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之四的剖视示意图和俯视示意图。
图12A和图12B分别是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之五的剖视示意图和俯视示意图。
图13A和图14B分别是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之六的剖视示意图和俯视示意图。
图14A和图14B分别是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之七的剖视示意图和俯视示意图。
图15A和图15B分别是依本发明的上述较佳实施例的所述半导体发光芯片的制作步骤之八的剖视示意图和俯视示意图，并且图15A示出了所述半导体发光芯片的剖视状态，图15B示出了所述半导体芯片的俯视状态。
具体实施方式
以下描述用于揭露本发明以使本领域技术人员能够实现本发明。以下描述中的优选实施例只作为举例，本领域技术人员可以想到其他显而易见的变型。在以下描述中界定的本发明的基本原理可以应用于其他实施方案、变形方案、改进方案、等同方案以及没有背离本发明的精神和范围的其他技术方案。
本领域技术人员应理解的是，在本发明的揭露中，术语“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系是基于附图所示的方位或位置关系，其仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此上述术语不能理解为对本发明的限制。
可以理解的是，术语“一”应理解为“至少一”或“一个或多个”，即在一个实施例中，一个元件的数量可以为一个，而在另外的实施例中，该元件的数量可以为多个，术语“一”不能理解为对数量的限制。
参考本发明的说明书附图之附图7A和图7B，依本发明的一较佳实施例的一半导体发光芯片在接下来的描述中将被揭露和被阐述，其中所述半导体发光芯片包括一衬底10、一外延叠层20、一反射层30、至少一绝缘层40、一防扩散层50、一扩展电极层60、一电流隔离层70以及一电极组80。
附图1A至图7B进一步示出了所述半导体发光芯片的制造过程，在接下来的描述中，将结合所述半导体发光芯片的制造过程进一步揭露和阐述所述半导体发光芯片的所述衬底10、所述外延叠层20、所述反射层30、所述绝缘层40、所述防扩散层50、所述扩展电极层 60、所述电流隔离层70和所述电极组80之间的关系。
参考附图1A和图1B，所述外延叠层20包括一N型半导体层21、一有源区22以及一P型半导体层23，其中所述N型半导体层21生长于所述衬底10，以使所述N型半导体层21层叠于所述衬底10，其中所述有源区22生长于所述N型半导体层21，以使所述有源区22层叠于所述N型半导体层21，其中所述P型半导体层23生长于所述有源区22，以使所述P型半导体层23层叠于所述有源区22。
优选地，在本发明的所述半导体发光芯片的这个较佳示例中，所述N型半导体层21和所述P型半导体层23均可以被实施为氮化镓层，即，所述外延叠层20包括层叠于所述衬底10的一N型氮化镓层、层叠于所述N型氮化镓层的所述有源区22以及层叠于所述有源区22的一P型氮化镓层。
值得一提的是，在本发明的所述半导体发光芯片中，在所述衬底10上层叠所述外延叠层20的方式不受限制，例如在附图1A至图7B示出的所述半导体发光芯片的这个较佳示例中，可以利用金属有机化合物化学气相沉淀设备(Metal-organic Chemical Vapor Deposition，MOCVD)自所述衬底10生长所述N型半导体层21、自所述N型半导体层21生长所述有源区22、自所述有源区22生长所述P型半导体层23。
值得一提的是，所述衬底10的类型在本发明的所述半导体发光芯片中不受限制，例如所述衬底10可以是但不限于氧化铝(Al2O3)衬底、碳化硅(SiC)衬底、硅(Si)衬底、氮化镓(GaN)衬底、砷化镓(GaAs)衬底和磷化镓(GaP)衬底。
继续参考附图1A和图1B，所述外延叠层20进一步具有至少一半导体裸露部24，其中所述半导体裸露部24自所述P型半导体层23经所述有源区22延伸至所述N型半导体层21，以使所述N型半导体层21的一部分表面被暴露在所述半导体裸露部24。
优选地，在所述外延叠层20层叠于所述衬底10之后，可以通过刻蚀所述外延叠层20的方式形成所述半导体裸露部24。具体地说，首先，使用正胶光刻胶对层叠于所述衬底10的所述外延叠层20进行光刻，以裸露出所述外延叠层20的需要被刻蚀的区域，设定光刻胶厚度为3μm-5μm(包括3μm和5μm)。其次，在烘烤光刻胶后，使用感应耦合等离子体机台(Inductively Coupled Plasma，ICP)对所述外延叠层20进行干法刻蚀，以使所述外延叠层20形成自所述P型半导体层23经所述有源区22延伸至所述N型半导体层21的所述半导体裸露部24。最后，去除所述P型半导体层23表面的光刻胶。在使用感应耦合等离子体机台对所述外延叠层20进行干法刻蚀时使用的气体为氯气(Cl2)、三氯化硼(BCl3)和氩气(Ar)。另外，使用感应耦合等离子体机台对所述外延叠层20蚀刻的深度范围为0.9μm-2μm(包括0.9μm和2μm)。也就是说，所述外延叠层20的所述半导体裸露部24的深度范围为0.9μm-2μm(包括0.9μm和2μm)。
在附图1A至图7B示出的所述半导体发光芯片的这个较佳示例中，所述N型半导体层21的一部分厚度也被刻蚀，以使所述半导体裸露部24自所述P型半导体层23经所述有源区22延伸至所述N型半导体层21的中部，从而使得所述N型半导体层21的对应于所述半导体裸露部24的厚度尺寸小于所述N型半导体层21的其他部分的厚度尺寸。
值得一提的是，所述外延叠层20的所述半导体裸露部24的数量和类型在本发明的所述 半导体发光芯片中不受限制，例如在附图1B示出的具体示例中，所述半导体裸露部24的数量可以有四个，其中两个所述半导体裸露部24呈圆形并位于所述半导体发光芯片的一个端部，另外两个所述半导体裸露部24分别具有一个位于所述半导体裸露部芯片的中部的焊盘裸露部和一个自所述焊盘裸露部向所述半导体发光芯片的另一个端部延伸的扩展条裸露部。当然，本领域技术人员应当理解，附图1B示出的所述半导体裸露部24的类型仅为示例，其并不应被视为对本发明的所述半导体发光芯片的内容和范围的限制。
参考附图2A和图2B，自所述外延叠层20的所述P型半导体层23生长所述反射层30，以使所述反射层30层叠于所述外延叠层20的所述P型半导体层23的一部分表面。
具体地说，首先，在所述外延叠层20的所述P型半导体层23的表面使用负胶光刻胶光刻出需要沉积的所述反射层30的图形，其次，使用蒸镀或者溅射镀膜的方式沉积所述反射层30于该图形，最后，去除负胶光刻胶。优选地，所述反射层30采用层叠结构，例如，所述反射层30可以是银(Ag)和钛钨(TiW)的层叠结构，其中银层的厚度尺寸范围为1000埃-3000埃(包括1000埃和3000埃)，钛钨层的厚度尺寸范围为200埃-2000埃(包括200埃和2000埃)。优选地，因为所述反射层30是通过蒸镀或者溅射镀膜的方式沉积在所述P型半导体层23的一部分表面的，因此，在去除负胶光刻胶之前，需要使用蓝膜剥离掉多余的金属层。
所述反射层30具有至少一反射层穿孔31，其中所述外延叠层20的所述半导体裸露部24对应于所述反射层30的所述反射层穿孔31，以使所述外延叠层20的所述半导体裸露部24和所述反射层30的所述反射层穿孔31相连通。优选地，所述反射层30的所述反射层穿孔31的形状与所述外延叠层20的所述半导体裸露部24的形状一致，并且所述反射层30的所述反射层穿孔31的尺寸大于所述外延叠层20的所述半导体裸露部24的尺寸，通过这样的方式，在所述反射层30层叠于所述外延叠层20的所述P型半导体层23之后，所述P型半导体层23的一部分表面被暴露在所述反射层30的所述反射层穿孔31。另外，所述反射层30的长宽尺寸小于所述外延叠层20的所述P型半导体层23的长宽尺寸，这样，在所述反射层30层叠于所述外延叠层20的所述P型半导体层23之后，所述外延叠层20的周缘表面因为没有被所述反射层30覆盖而被暴露。
也就是说，所述外延叠层20的所述P型半导体层23的表面具有至少一第一区域231和至少二第二区域232，其中任意一个所述第一区域231的外侧和内侧分别设有一个所述第二区域232。例如，在附图2B示出的具体示例中，所述外延叠层20的所述P型半导体层23的表面具有一个所述第一区域231和两个所述第二区域232，其中一个所述第二区域232以环绕在所述半导体裸露部24的方式形成于所述P型半导体层23的中部，另外一个所述第二区域232形成于所述P型半导体层23的周缘表面，所述第一区域231形成于两个所述第二区域232之前，其中所述反射层30以自所述P型半导体层23的所述第一区域231生长的方式层叠于所述P型半导体层23。也就是说，所述P型半导体层23的一个所述第二区域232是所述P型半导体层23的被暴露在所述反射层30的所述反射层穿孔31的区域，所述P型半导体层23的另一个所述第二区域232是所述P型半导体层23的没有被所述反射层30覆盖的周缘表面。
参考附图3A和图3B，自所述外延叠层20的所述P型半导体层23的所述第二区域232 的至少一部分表面生长所述绝缘层40，以使所述绝缘层40环绕在所述反射层30的外侧和内侧，其中所述绝缘层40能够以环绕在所述反射层30的外侧和内侧的方式阻止所述反射层30向外侧和内侧出现金属迁移的不良现象，从而保证所述反射层30的稳定性，进而保证所述半导体发光芯片的稳定性。
具体地说，在所述外延叠层20的所述P型半导体层23的所述第一区域231生长所述反射层30之后，使用蒸镀、溅镀或者等离子体增强化学的气相沉淀法(Plasma Enhanced Chemical Vapor Deposition，PECVD)的方式自所述P型半导体层23的所述第二区域232的至少一部分表面生长所述绝缘层40，从而使所述绝缘层40环绕在所述反射层30的外侧和内侧。优选地，所述绝缘层40层叠于所述P型半导体层23的所述第二区域232的全部区域。值得一提的是，所述绝缘层40能够进一步覆盖所述反射层30的至少一部分表面。优选地，所述绝缘层40可以使用但不限于负胶剥离或者正胶蚀刻的方式制作。
优选地，形成所述绝缘层40的材料为二氧化硅(SiO2)，从而所述绝缘层40为层叠于所述P型半导体层23和环绕在所述反射层30的内侧和外侧的二氧化硅层。优选地，所述绝缘层40的厚度尺寸范围为100埃-5000埃(包括100埃和5000埃)。
值得一提的是，尽管在附图3A和图3B示出的具体示例中，所述绝缘层40的厚度尺寸与所述反射层30的厚度尺寸一致，但是本领域技术人员应当理解的是，在本发明的所述半导体发光芯片的其他可能的示例中，所述绝缘层40的厚度尺寸可以大于所述反射层30的厚度尺寸，从而使得所述绝缘层40高出所述反射层30，或者所述绝缘层40的厚度尺寸可以小于所述反射层30的厚度尺寸，从而使得所述绝缘层40低于所述反射层30。
参考附图4A和图4B，自所述反射层30和所述绝缘层40生长所述防扩散层50，以使所述防扩散层50层叠于所述反射层30和层叠于所述绝缘层40，其中所述防扩散层50能够以层叠于所述反射层30的表面的方式阻止所述反射层30的表面出现金属迁移的不良现象。因为所述绝缘层40环绕在所述反射层30的内侧和外侧以藉由所述绝缘层40阻止所述反射层30向内侧和外侧出现金属迁移的不良现象，和所述防扩散层50层叠于所述反射层30的表面以藉由所述防扩散层50阻止所述反射层30的表面出现金属迁移的不良现象，因此，所述反射层30被所述绝缘层40和所述防扩散层50共同包覆以避免出现金属迁移的不良现象，这样的方式能够保证所述反射层30的稳定性，进而保证所述半导体发光芯片的稳定性。
因为所述防扩散层50层叠于所述反射层30和所述绝缘层40，从而所述绝缘层40能够隔离所述防扩散层50和所述P型半导体层23，以藉由所述绝缘层40阻止所述防扩散层50直接接触所述P型半导体层23，通过这样的方式，能够避免所述半导体发光芯片在被通电后电流聚集而导致的静电击穿异常，从而保证所述半导体发光芯片在被使用时的可靠性。
所述防扩散层50具有至少一防扩散层穿孔51，其中所述外延叠层20的所述半导体裸露部24对应于所述防扩散层50的所述防扩散层穿孔51，以使所述外延叠层20的所述半导体裸露部24和所述防扩散层50的所述防扩散层穿孔51相连通。优选地，所述防扩散层50的所述防扩散层穿孔51的形状和所述外延叠层20的所述半导体裸露部24的形状一致。
优选地，在所述防扩散层50自所述反射层30和所述绝缘层40生长的同时形成所述防扩散层50的所述防扩散层穿孔51。具体地说，首先，在所述绝缘层40的外侧表面使用负胶光刻胶光刻的方式制作出需要沉积的所述防扩散层50的图形，其次，使用蒸镀或者溅镀 的方式沉积所述防扩散层50于该图形，以使所述防扩散层50层叠于所述反射层30和所述绝缘层40的内侧表面，接着，使用蓝膜剥离掉多余的金属层，最后，去除所述绝缘层40的表面的光刻胶层，以形成所述防扩散层50的所述防扩散层穿孔51。
优选地，所述防扩散层50采用层叠结构，例如，所述防扩散层50是钛钨(TiW)和铂(Pt)的层叠结构。
参考附图5A和图5B，所述扩展电极层60包括至少一N型扩展电极部61，其中所述N型扩展电极部61以被保持在所述外延叠层20的所述半导体裸露部24的方式层叠于所述N型半导体层21。
优选地，所述N型扩展电极部61的尺寸和形状与所述外延叠层20的所述半导体裸露部24的尺寸和形状一致。具体地说，当所述外延叠层20的所述半导体裸露部24的形状是圆形时，所述N型扩展电极部61的形状相应地为圆形，当所述外延叠层20的所述半导体裸露部24由所述焊盘裸露部和所述扩展条裸露部形成时，所述N型扩展电极部61相应地包括焊盘和自所述焊盘延伸的扩展条。所述N型扩展电极部61的尺寸与所述外延叠层20的所述半导体裸露部24的尺寸一致是指所述N型扩展电极部61的尺寸稍小于所述外延叠层20的所述半导体裸露部24的尺寸，以避免所述N型扩展电极部61接触用于形成所述半导体裸露部24的所述有源区22和所述P型半导体层23。
所述N型扩展电极部61使用负胶剥离的方式层叠于所述N型半导体层21。具体地说，首先，在所述外延叠层20的所述半导体裸露部24使用负胶光刻胶光刻的方式制作需要沉积所述N型扩展电极部61的图形，其次，使用蒸镀或者溅镀的方式沉积所述N型扩展电极部61于该图形，以使所述N型扩展电极部61以被保持在所述半导体裸露部24的方式层叠于所述N型半导体层21，接着，使用蓝膜剥离掉多余的金属层，最后，去除光刻胶层，以形成所述N型扩展电极部61。
优选地，所述N型扩展电极部61是反射扩展电极部，其能够反射所述有源区22产生的光线。优选地，形成所述N型扩展电极部61的材料选自：铬(Cr)、铝(Al)、钛(Ti)、铂(Pt)和金(Au)组成的材料组，从而使得所述N型扩展电极部61具有反射所述有源区22产生的光线的作用。
参考附图6A和图6B，所述电流隔离层70包括一第一隔离部71，其中所述第一隔离部71生长自所述绝缘层40、所述防扩散层50、所述外延叠层20和所述N型扩展电极部61，即，所述第一隔离部71依次经所述防扩散层50的所述防扩散层穿孔51和所述外延叠层20的所述半导体裸露部24延伸至所述N型半导体层21，从而使得所述第一隔离部71隔离所述N型扩展电极部61和所述有源区22以及隔离所述N型扩展电极部61和所述P型半导体层23。所述第一隔离部71具有至少一第一通道711和至少一第二通道712，其中所述第一通道711延伸至所述N型扩展电极部61，以暴露所述N型扩展电极部61于所述第一通道711，其中所述第二通道712延伸至所述防扩散层50，以暴露所述防扩散层50于所述第二通道712。
具体地说，首先，自所述绝缘层40、所述防扩散层50、所述外延叠层20和所述N型扩展电极部61生长一第一隔离部基层，其中所述第一隔离部基层依次经所述防扩散层50的所述防扩散层穿孔51和所述外延叠层20的所述半导体裸露部24延伸至所述N型半导体层21， 从而使得所述第一隔离部基层隔离所述N型扩展电极部61和所述有源区22以及隔离所述N型扩展电极部61和所述P型半导体层23。其次，使用光刻胶光刻的方式确定所述第一隔离部基层的被蚀刻位置，然后使用感应耦合等离子体机台(Inductively Coupled Plasma，ICP)对所述第一隔离部基层进行蚀刻，以形成延伸至所述N型扩展电极部61的所述第一通道711和延伸至所述防扩散层50的所述第二通道712，并且所述第一隔离部基层形成所述第一隔离部71。
优选地，所述第一隔离部71是分布式布拉格反射镜结构(Distributed Bragg Reflection，DBR)，其中所述第一隔离部71使用氧化硅和氧化钛交叠结构，并且所述第一隔离部71针对不同的波长设计不同的反射层对，例如，在本发明的所述半导体发光芯片的一个较佳示例中，所述第一隔离部71的反射层对的对数范围为20对-50对(包括20对和50对)。
参考附图7A和图7B，所述电极组80包括一N型电极81和一P型电极82，其中所述N型电极81和所述P型电极82以相互间隔的方式层叠于所述第一隔离部71，并且所述N型电极81经所述第一隔离部71的所述第一通道711延伸至所述N型扩展电极部61，所述P型电极82经所述第一隔离部71的所述第二通道712延伸至所述防扩散层50。
具体地说，所述N型电极81进一步具有至少一N型电极连接针811，其中在所述N型电极81层叠于所述第一隔离部71时，所述N型电极连接针811形成于和被保持在所述第一隔离部71的所述第一通道711，从而使得所述N型电极81的所述N型电极连接针811经所述第一隔离部71的所述第一通道711延伸至所述N型扩展电极部61。相应地，所述P型电极82进一步具有至少一P型电极连接针821，其中在所述P型电极82层叠于所述第一隔离部71时，所述P型电极连接针821形成于和被保持在所述第一隔离部71的所述第二通道712，从而使得所述P型电极82的所述P型电极连接针821经所述第一隔离部71的所述第二通道712延伸至所述防扩散层50。
优选地，所述N型电极81和所述P型电极82的厚度尺寸范围是1μm-5μm(包括1μm和5μm)，其中所述N型电极81的厚度尺寸是指所述N型电极81的主体部分的厚度尺寸，即，所述N型电极81的厚度尺寸不包括所述N型电极连接针811的延伸长度，相应地，所述P型电极82的厚度尺寸范围是指所述P型电极82的主体部分的厚度尺寸，即，所述P型电极82的厚度尺寸不包括所述P型电极连接针821的延伸长度。
所述N型电极81和所述P型电极82使用负胶剥离的方式层叠于所述第一隔离部71。具体地说，首先，在所述第一隔离部71使用负胶光刻胶光刻的方式制作需要沉积的所述N型电极81和所述P型电极82的图形，其次，使用蒸镀或者溅镀的方式沉积所述N型电极81和所述P型电极82于该图形，以使所述N型电极81的所述N型电极连接针811被保持在所述第一隔离部71的所述第一通道711和经所述第一通道711延伸至所述N型扩展电极部61，和使所述P型电极82的所述P型电极连接针821被保持在所述第一隔离部71的所述第二通道712和经所述第二通道712延伸至所述防扩散层50，接着，使用蓝膜剥离掉多余的金属，最后，去除光刻胶层，以形成所述N型电极81和所述P型电极82。优选地，所述N型电极81和所述P型电极82是反射电极，其能够反射所述有源区22产生的光线。与偶选地，形成所述N型电极81和所述P型电极82的材料选自：铬(Cr)、铝(Al)、钛(Ti)、 铂(Pt)和金(Au)组成的材料组，从而使得所述N型电极81和所述P型电极82具有反射所述有源区22产生的光线的作用。
依本发明的另一个方面，本发明进一步提供一半导体发光芯片的制造方法，其中所述制造方法包括如下步骤：
(a)自所述衬底10依次生长所述N型半导体层21、所述有源区22以及所述P型半导体层23；
(b)层叠所述反射层30于所述P型半导体层23的一部分表面；
(c)分别环绕所述绝缘层40于所述反射层30的内侧和外侧；
(d)自所述反射层30和所述绝缘层40生长所述防扩散层50；以及
(e)电连接所述N型电极81于所述N型半导体层21和电连接所述P型电极82于所述防扩散层50，以制得所述半导体发光芯片。
值得注意的是，在本发明的附图中示出的所述半导体发光芯片的所述衬底10、所述N型半导体层21、所述有源区22、所述P型半导体层23、所述反射层30、所述绝缘层40、所述防扩散层50、所述N型扩展电极部61、所述第一隔离部71、所述N型电极81和所述P型电极82的厚度仅为示例，其并不表示所述衬底10、所述N型半导体层21、所述有源区22、所述P型半导体层23、所述反射层30、所述绝缘层40、所述防扩散层50、所述N型扩展电极部61、所述第一隔离部71、所述N型电极81和所述P型电极82的真实厚度。并且，所述衬底10、所述N型半导体层21、所述有源区22、所述P型半导体层23、所述反射层30、所述绝缘层40、所述防扩散层50、所述N型扩展电极部61、所述第一隔离部71、所述N型电极81和所述P型电极82之间的真实比例也不像附图中示出的那样。另外，所述N型电极81和所述P型电极82的尺寸与所述半导体发光芯片的其他层的尺寸比例也不受限于附图中示出的那样。
参考本发明的说明书附图之附图15A和图15B，依本发明的另一较佳实施例的一半导体发光芯片在接下来的描述中将被揭露和被阐述，其中所述半导体发光芯片包括一衬底10A、一外延叠层20A、一反射层30A、至少一绝缘层40A、一防扩散层50A、一扩展电极层60A、一电流隔离层70A以及一电极组80A。
附图8A至图15B进一步示出了所述半导体发光芯片的制造过程，在接下来的描述中，将结合所述半导体发光芯片的制造过程进一步揭露和阐述所述半导体发光芯片的所述衬底10A、所述外延叠层20A、所述反射层30A、所述绝缘层40A、所述防扩散层50A、所述扩展电极层60A、所述电流隔离层70A和所述电极组80A之间的关系。
参考附图8A和图8B，所述外延叠层20A包括一N型半导体层21A、一有源区22A以及一P型半导体层23A，其中所述N型半导体层21A生长于所述衬底10A，以使所述N型半导体层21A层叠于所述衬底10A，其中所述有源区22A生长于所述N型半导体层21A，以使所述有源区22A层叠于所述N型半导体层21A，其中所述P型半导体层23A生长于所述有源区22A，以使所述P型半导体层23A层叠于所述有源区22A。
优选地，在本发明的所述半导体发光芯片的这个较佳示例中，所述N型半导体层21A和所述P型半导体层23A均可以被实施为氮化镓层，即，所述外延叠层20A包括层叠于所述衬底10A的一N型氮化镓层、层叠于所述N型氮化镓层的所述有源区22A以及层叠于所述有 源区22A的一P型氮化镓层。
值得一提的是，在本发明的所述半导体发光芯片中，在所述衬底10A上层叠所述外延叠层20A的方式不受限制，例如在附图8A至图8B示出的所述半导体发光芯片的这个较佳示例中，可以利用金属有机化合物化学气相沉淀设备(Metal-organic Chemical Vapor Deposition，MOCVD)自所述衬底10A生长所述N型半导体层21A、自所述N型半导体层21A生长所述有源区22A、自所述有源区22A生长所述P型半导体层23A。
值得一提的是，所述衬底10A的类型在本发明的所述半导体发光芯片中不受限制，例如所述衬底10A可以是但不限于氧化铝(Al2O3)衬底、碳化硅(SiC)衬底、硅(Si)衬底、氮化镓(GaN)衬底、砷化镓(GaAs)衬底和磷化镓(GaP)衬底。
继续参考附图8A和图8B，所述外延叠层20A进一步具有至少一半导体裸露部24A，其中所述半导体裸露部24A自所述P型半导体层23A经所述有源区22A延伸至所述N型半导体层21A，以使所述N型半导体层21A的一部分表面被暴露在所述半导体裸露部24A。
优选地，在所述外延叠层20A层叠于所述衬底10A之后，可以通过刻蚀所述外延叠层20A的方式形成所述半导体裸露部24A。具体地说，首先，使用正胶光刻胶对层叠于所述衬底10A的所述外延叠层20A进行光刻，以裸露出所述外延叠层20A的需要被刻蚀的区域，设定光刻胶厚度为3μm-5μm(包括3μm和5μm)。其次，在烘烤光刻胶后，使用感应耦合等离子体机台(Inductively Coupled Plasma，ICP)对所述外延叠层20A进行干法刻蚀，以使所述外延叠层20A形成自所述P型半导体层23A经所述有源区22A延伸至所述N型半导体层21A的所述半导体裸露部24A。最后，去除所述P型半导体层23A表面的光刻胶。在使用感应耦合等离子体机台对所述外延叠层20A进行干法刻蚀时使用的气体为氯气(Cl2)、三氯化硼(BCl3)和氩气(Ar)。另外，使用感应耦合等离子体机台对所述外延叠层20A蚀刻的深度范围为0.9μm-2μm(包括0.9μm和2μm)。也就是说，所述外延叠层20A的所述半导体裸露部24A的深度范围为0.9μm-2μm(包括0.9μm和2μm)。
在附图8A至图15B示出的所述半导体发光芯片的这个较佳示例中，所述N型半导体层21A的一部分厚度也被刻蚀，以使所述半导体裸露部24A自所述P型半导体层23A经所述有源区22A延伸至所述N型半导体层21A的中部，从而使得所述N型半导体层21A的对应于所述半导体裸露部24A的厚度尺寸小于所述N型半导体层21A的其他部分的厚度尺寸。
值得一提的是，所述外延叠层20A的所述半导体裸露部24A的数量和类型在本发明的所述半导体发光芯片中不受限制，附图8B示出的所述外延叠层20A的具体示例仅为举例，其并不构成对本发明的所述半导体发光芯片的内容和范围的限制。
参考附图9A和图9B，自所述外延叠层20A的所述P型半导体层23A生长所述反射层30A，以使所述反射层30A层叠于所述外延叠层20A的所述P型半导体层23A的一部分表面。
具体地说，首先，在所述外延叠层20A的所述P型半导体层23A的表面使用负胶光刻胶光刻出需要沉积的所述反射层30A的图形，其次，使用蒸镀或者溅射镀膜的方式沉积所述反射层30A于该图形，最后，去除负胶光刻胶。优选地，所述反射层30A采用层叠结构，例如，所述反射层30A可以是银(Ag)和钛钨(TiW)的层叠结构，其中银层的厚度尺寸范围为1000埃-3000埃(包括1000埃和3000埃)，钛钨层的厚度尺寸范围为200埃-2000埃(包括200 埃和2000埃)。优选地，因为所述反射层30A是通过蒸镀或者溅射镀膜的方式沉积在所述P型半导体层23A的一部分表面的，因此，在去除负胶光刻胶之前，需要使用蓝膜剥离掉多余的金属层。
所述反射层30A具有至少一反射层穿孔31A，其中所述外延叠层20A的所述半导体裸露部24A对应于所述反射层30A的所述反射层穿孔31A，以使所述外延叠层20A的所述半导体裸露部24A和所述反射层30A的所述反射层穿孔31A相连通。优选地，所述反射层30A的所述反射层穿孔31A的形状与所述外延叠层20A的所述半导体裸露部24A的形状一致，并且所述反射层30A的所述反射层穿孔31A的尺寸大于所述外延叠层20A的所述半导体裸露部24A的尺寸，通过这样的方式，在所述反射层30A层叠于所述外延叠层20A的所述P型半导体层23A之后，所述P型半导体层23A的一部分表面被暴露在所述反射层30A的所述反射层穿孔31A。另外，所述反射层30A的长宽尺寸小于所述外延叠层20A的所述P型半导体层23A的长宽尺寸，这样，在所述反射层30A层叠于所述外延叠层20A的所述P型半导体层23A之后，所述外延叠层20A的周缘表面因为没有被所述反射层30A覆盖而被暴露。
也就是说，所述外延叠层20A的所述P型半导体层23A的表面具有至少一第一区域231A和至少二第二区域232A，其中任意一个所述第一区域231A的外侧和内侧分别设有一个所述第二区域232A。例如，在附图9B示出的具体示例中，所述外延叠层20A的所述P型半导体层23A的表面具有一个所述第一区域231A和两个所述第二区域232A，其中一个所述第二区域232A以环绕在所述半导体裸露部24A的方式形成于所述P型半导体层23A的中部，另外一个所述第二区域232A形成于所述P型半导体层23A的周缘表面，所述第一区域231A形成于两个所述第二区域232A之前，其中所述反射层30A以自所述P型半导体层23A的所述第一区域231A生长的方式层叠于所述P型半导体层23A。也就是说，所述P型半导体层23A的一个所述第二区域232A是所述P型半导体层23A的被暴露在所述反射层30A的所述反射层穿孔31A的区域，所述P型半导体层23A的另一个所述第二区域232A是所述P型半导体层23A的没有被所述反射层30A覆盖的周缘表面。
参考附图10A和图10B，自所述外延叠层20A的所述P型半导体层23A的所述第二区域232A的至少一部分表面生长所述绝缘层40A，以使所述绝缘层40A环绕在所述反射层30A的外侧和内侧，其中所述绝缘层40A能够以环绕在所述反射层30A的外侧和内侧的方式阻止所述反射层30A向外侧和内侧出现金属迁移的不良现象，从而保证所述反射层30A的稳定性，进而保证所述半导体发光芯片的稳定性。
具体地说，在所述外延叠层20A的所述P型半导体层23A的所述第一区域231A生长所述反射层30A之后，使用蒸镀、溅镀或者等离子体增强化学的气相沉淀法(Plasma Enhanced Chemical Vapor Deposition，PECVD)的方式自所述P型半导体层23A的所述第二区域232A的至少一部分表面生长所述绝缘层40A，从而使所述绝缘层40A环绕在所述反射层30A的外侧和内侧。优选地，所述绝缘层40A层叠于所述P型半导体层23A的所述第二区域232A的全部区域。值得一提的是，所述绝缘层40A能够进一步覆盖所述反射层30A的至少一部分表面。优选地，所述绝缘层40A可以使用但不限于负胶剥离或者正胶蚀刻的方式制作。
优选地，形成所述绝缘层40A的材料为二氧化硅(SiO2)，从而所述绝缘层40A为层叠于所述P型半导体层23A和环绕在所述反射层30A的内侧和外侧的二氧化硅层。优选地，所 述绝缘层40A的厚度尺寸范围为100埃-5000埃(包括100埃和5000埃)。
值得一提的是，尽管在附图10A和图10B示出的具体示例中，所述绝缘层40A的厚度尺寸与所述反射层30A的厚度尺寸一致，但是本领域技术人员应当理解的是，在本发明的所述半导体发光芯片的其他可能的示例中，所述绝缘层40A的厚度尺寸可以大于所述反射层30A的厚度尺寸，从而使得所述绝缘层40A高出所述反射层30A，或者所述绝缘层40A的厚度尺寸可以小于所述反射层30A的厚度尺寸，从而使得所述绝缘层40A低于所述反射层30A。
参考附图11A和图11B，自所述反射层30A和所述绝缘层40A生长所述防扩散层50A，以使所述防扩散层50A层叠于所述反射层30A和层叠于所述绝缘层40A，其中所述防扩散层50A能够以层叠于所述反射层30A的表面的方式阻止所述反射层30A的表面出现金属迁移的不良现象。因为所述绝缘层40A环绕在所述反射层30A的内侧和外侧以藉由所述绝缘层40A阻止所述反射层30A向内侧和外侧出现金属迁移的不良现象，和所述防扩散层50A层叠于所述反射层30A的表面以藉由所述防扩散层50A阻止所述反射层30A的表面出现金属迁移的不良现象，因此，所述反射层30A被所述绝缘层40A和所述防扩散层50A共同包覆以避免出现金属迁移的不良现象，这样的方式能够保证所述反射层30A的稳定性，进而保证所述半导体发光芯片的稳定性。
因为所述防扩散层50A层叠于所述反射层30A和所述绝缘层40A，从而所述绝缘层40A能够隔离所述防扩散层50A和所述P型半导体层23A，以藉由所述绝缘层40A阻止所述防扩散层50A直接接触所述P型半导体层23A，通过这样的方式，能够避免所述半导体发光芯片在被通电后电流聚集而导致的静电击穿异常，从而保证所述半导体发光芯片在被使用时的可靠性。
所述防扩散层50A具有至少一防扩散层穿孔51A，其中所述外延叠层20A的所述半导体裸露部24A对应于所述防扩散层50A的所述防扩散层穿孔51A，以使所述外延叠层20A的所述半导体裸露部24A和所述防扩散层50A的所述防扩散层穿孔51A相连通。优选地，所述防扩散层50A的所述防扩散层穿孔51A的形状和所述外延叠层20A的所述半导体裸露部24A的形状一致。
优选地，在所述防扩散层50A自所述反射层30A和所述绝缘层40A生长的同时形成所述防扩散层50A的所述防扩散层穿孔51A。具体地说，首先，在所述绝缘层40A的外侧表面使用负胶光刻胶光刻的方式制作出需要沉积的所述防扩散层50A的图形，其次，使用蒸镀或者溅镀的方式沉积所述防扩散层50A于该图形，以使所述防扩散层50A层叠于所述反射层30A和所述绝缘层40A的内侧表面，接着，使用蓝膜剥离掉多余的金属层，最后，去除所述绝缘层40A的表面的光刻胶层，以形成所述防扩散层50A的所述防扩散层穿孔51A。
优选地，所述防扩散层50A采用层叠结构，例如，所述防扩散层50A是钛钨(TiW)和铂(Pt)的层叠结构。
参附图12A和图12B，所述电流隔离层70A包括一第一隔离部71A，其中所述第一隔离部71A生长自所述绝缘层40A、所述防扩散层50A和所述外延叠层20A，即，所述第一隔离部71A依次经所述防扩散层50A的所述防扩散层穿孔51A和所述外延叠层20A的所述半导体裸露部24A延伸至所述N型半导体层21A。所述第一隔离部71A具有至少一第一通道711A和至少一第二通道712A，其中所述第一通道711A延伸至所述外延叠层20A的所述N型半导 体层21A，以暴露所述N型半导体层21A的一部分表面于所述第一通道711A，其中所述第二通道712A延伸至所述防扩散层50A，以暴露所述防扩散层50A的一部分表面于所述第二通道712A。
具体地说，首先，自所述绝缘层40A、所述防扩散层50A和所述外延叠层20A生长一第一隔离部基层，其中所述第一隔离部基层依次经所述防扩散层50A的所述防扩散层穿孔51A和所述外延叠层20A的所述半导体裸露部24A延伸至所述N型半导体层21A。其次，使用光刻胶光刻的方式确定所述第一隔离部基层的被蚀刻位置，然后使用感应耦合等离子体机台(Inductively Coupled Plasma，ICP)对所述第一隔离部基层进行蚀刻，以形成延伸至所述外延叠层20A的所述N型半导体层21A的所述第一通道711A和延伸至所述防扩散层50A的所述第二通道712A，并且所述第一隔离部基层形成所述第一隔离部71A。
优选地，所述第一隔离部71A是分布式布拉格反射镜结构(Distributed Bragg Reflection，DBR)，其中所述第一隔离部71A使用氧化硅和氧化钛交叠结构，并且所述第一隔离部71A针对不同的波长设计不同的反射层对，例如，在本发明的所述半导体发光芯片的一个较佳示例中，所述第一隔离部71A的反射层对的对数范围为20对-50对(包括20对和50对)。
参考附图13A和图13B，所述扩展电极层60A包括至少一N型扩展电极部61A和至少一P型扩展电极部62A，其中所述N型扩展电极部61A和所述P型扩展电极部62A以相互间隔的方式分别层叠于所述第一隔离部71A，并且所述N型扩展电极部61A经所述第一隔离部71A的所述第一通道711A延伸至所述外延叠层20A的所述N型半导体层21A，所述P型扩展电极部62A经所述第一隔离部71A的所述第二通道712A延伸至所述防扩散层50A。
具体地说，所述N型扩展电极部61A具有至少一N型扩展电极针611A，其中在所述N型扩展电极部61A层叠于所述第一隔离部71A时，所述N型扩展电极针611A形成于和被保持在所述第一隔离部71A的所述第一通道711A，从而使得所述N型扩展电极部61A经所述第一隔离部71A的所述第一通道711A延伸至所述外延叠层20A的所述N型半导体层21A。相应地，所述P型扩展电极部62A具有至少一P型扩展电极针621A，其中在所述P型扩展电极部62A层叠于所述第一隔离部71A时，所述P型扩展电极针621A形成于和被保持在所述第一隔离部71A的所述第二通道712A，从而使得所述P型扩展电极部62A经所述第一隔离部71A的所述第二通道712A延伸至所述防扩散层50A。
所述N型扩展电极部61A和所述P型扩展电极部62A使用负胶剥离的方式层叠于所述第一隔离部71A。具体地说，首先，在所述第一隔离部71A使用负胶光刻胶光刻的方式制作需要沉积所述N型扩展电极部61A和所述P型扩展电极部62A的图形，其次，使用蒸镀或者溅镀的方式沉积所述N型扩展电极部61A和所述P型扩展电极部62A于该图形，以使所述N型扩展电极部61A的所述N型扩展电极针611A被保持在所述第一隔离部71A的所述第一通道711A和经所述第一通道711A延伸至所述外延叠层20A的所述N型半导体层21A，和使所述P型扩展电极部62A的所述P型扩展电极针621A被保持在所述第一隔离部71A的所述第二通道712A和经所述第二通道712A延伸至所述防扩散层50A。
优选地，所述N型扩展电极部61A和所述P型扩展电极部62A是反射扩展电极部，其能够反射所述有源区22A产生的光线。优选地，形成所述N型扩展电极部61A和所述P型扩展 电极部62A的材料选自：铬(Cr)、铝(Al)、钛(Ti)、铂(Pt)和金(Au)组成的材料组，从而使得所述N型扩展电极部61A和所述P型扩展电极部62A具有反射所述有源区22A产生的光线的作用。
参考附图14A和图14B，所述电流隔离层70A包括一第二隔离部72A，其中所述第二隔离部72A生长自所述N型扩展电极部61A、所述P型扩展电极部62A和所述第一隔离部71A，即，所述第二隔离部72A填充在形成于所述N型扩展电极部61A和所述P型扩展电极部62A之间的间隔缝隙。所述第二隔离部72A具有至少一第三通道721A和至少一第四通道722A，其中所述第三通道721A延伸至所述N型扩展电极部61A，以使所述N型扩展电极部61A的一部分表面被暴露在所述第三通道721A，其中所述第四通道722A延伸至所述P型扩展电极部62A，以使所述P型扩展电极部62A的一部分表面被暴露在所述第四通道722A。
具体地说，首先，自所述N型扩展电极部61A、所述P型扩展电极部62A和所述第一隔离部71A生长一第二隔离部基层，其中所述第二隔离部基层填充在形成于所述N型扩展电极部61A和所述P型扩展电极部62A之间的间隔缝隙。其次，使用正胶光刻胶的方式确定所述第二隔离部基层的被蚀刻位置，然后使用干法蚀刻的方式蚀刻所述第二隔离部基层的被蚀刻位置，以形成延伸至所述N型扩展电极部61A的所述第三通道721A和形成延伸至所述P型扩展电极部62A的所述第四通道722A。优选地，所述第二隔离部基层被使用等离子体增强化学的气相沉淀法(Plasma Enhanced Chemical Vapor Deposition，PECVD)的方式生长于所述N型扩展电极部61A、所述P型扩展电极部62A和所述第一隔离部71A，其中在使用等离子体增强化学的气相沉淀法(Plasma Enhanced Chemical Vapor Deposition，PECVD)的方式沉积所述第二隔离部基层时使用的气体为硅烷(SiH4)、一氧化二氮(N2O)和氮气(N2)，所述第二隔离部基层的厚度尺寸范围为5000埃-20000埃(包括5000埃和20000埃)。
参考附图15A和图15B，所述电极组80A包括一N型电极81A和一P型电极82A，其中所述N型电极81A和所述P型电极82A以相互间隔的方式层叠于所述第二隔离部72A，并且所述N型电极81A经所述第二隔离部72A的所述第三通道721A延伸至所述N型扩展电极部61A，所述P型电极82A经所述第二隔离部72A的所述第四通道722A延伸至所述P型扩展电极部62A。
具体地说，所述N型电极81A进一步具有至少一N型电极连接针811A，其中在所述N型电极81A层叠于所述第一隔离部71A时，所述N型电极连接针811A形成于和被保持在所述第二隔离部72A的所述第三通道721A，从而使得所述N型电极81A的所述N型电极连接针811A经所述第二隔离部72A的所述第三通道721A延伸至所述N型扩展电极部61A。相应地，所述P型电极82A进一步具有至少一P型电极连接针821A，其中在所述P型电极82A层叠于所述第一隔离部71A时，所述P型电极连接针821A形成于和被保持在所述第二隔离部72A的所述第四通道722A，从而使得所述P型电极82A的所述P型电极连接针821A经所述第二隔离部72A的所述第四通道722A延伸至所述P型扩展电极部62A。
优选地，所述N型电极81A和所述P型电极82A的厚度尺寸范围是1μm-5μm(包括1μm和5μm)，其中所述N型电极81A的厚度尺寸是指所述N型电极81A的主体部分的厚度尺寸，即，所述N型电极81A的厚度尺寸不包括所述N型电极连接针811A的延伸长度，相 应地，所述P型电极82A的厚度尺寸范围是指所述P型电极82A的主体部分的厚度尺寸，即，所述P型电极82A的厚度尺寸不包括所述P型电极连接针821A的延伸长度。
所述N型电极81A和所述P型电极82A使用负胶剥离的方式层叠于所述第二隔离部72A。具体地说，首先，在所述第二隔离部72A使用负胶光刻胶光刻的方式制作需要沉积的所述N型电极81A和所述P型电极82A的图形，其次，使用蒸镀或者溅镀的方式沉积所述N型电极81A和所述P型电极82A于该图形，以使所述N型电极81A的所述N型电极连接针811A被保持在所述第二隔离部72A的所述第三通道721A和经所述第三通道721A延伸至所述N型扩展电极部61A，和使所述P型电极82A的所述P型电极连接针821A被保持在所述第二隔离部72A的所述第四通道722A和经所述第四通道722A延伸至所述P型扩展电极部62A，接着，使用蓝膜剥离掉多余的金属，最后，去除光刻胶层，以形成所述N型电极81A和所述P型电极82A。优选地，所述N型电极81A和所述P型电极82A是反射电极，其能够反射所述有源区22A产生的光线。与偶选地，形成所述N型电极81A和所述P型电极82A的材料选自：铬(Cr)、铝(Al)、钛(Ti)、铂(Pt)和金(Au)组成的材料组，从而使得所述N型电极81A和所述P型电极82A具有反射所述有源区22A产生的光线的作用。
依本发明的另一个方面，本发明进一步提供一半导体发光芯片的制造方法，其中所述制造方法包括如下步骤：
(a)自所述衬底10A依次生长所述N型半导体层21A、所述有源区22A以及所述P型半导体层23A；
(b)层叠所述反射层30A于所述P型半导体层23A的一部分表面；
(c)分别环绕所述绝缘层40A于所述反射层30A的内侧和外侧；
(d)自所述反射层30A和所述绝缘层40A生长所述防扩散层50A；以及
(e)电连接所述N型电极81A于所述N型半导体层21A和电连接所述P型电极82A于所述防扩散层50A，以制得所述半导体发光芯片。
值得一提的是，尽管在附图8A至图15B中示出的所述绝缘层40A均以自所述P型半导体层23A的一部分表面生长的方式环绕于所述反射层30A的内侧和外侧，但是本领域技术人员应当理解的是，在本发明的所述制造方法的其他示例中，所述绝缘层40A也可以生长自所述有源区22A、所述N型半导体层21A或者所述衬底10A。换言之，所述绝缘层40A的生长位置在本发明的所述制造方法和所述半导体芯片中均不受限制，其只要能够环绕在所述反射层30A的内侧和外侧以及隔离所述防扩散层50A和所述P型半导体层23A即可。
值得注意的是，在本发明的附图中示出的所述半导体发光芯片的所述衬底10A、所述N型半导体层21A、所述有源区22A、所述P型半导体层23A、所述反射层30A、所述绝缘层40A、所述防扩散层50A、所述N型扩展电极部61A、所述P型扩展电极部62A、所述第一隔离部71A、所述第二隔离部72A、所述N型电极81A和所述P型电极82A的厚度仅为示例，其并不表示所述衬底10A、所述N型半导体层21A、所述有源区22A、所述P型半导体层23A、所述反射层30A、所述绝缘层40A、所述防扩散层50A、所述N型扩展电极部61A、所述P型扩展电极部62A、所述第一隔离部71A、所述第二隔离部72A、所述N型电极81A和所述P型电极82A的真实厚度。并且，所述衬底10A、所述N型半导体层21A、所述有源区22A、所述P型半导体层23A、所述反射层30A、所述绝缘层40A、所述防扩散层50A、所述N型扩 展电极部61A、所述P型扩展电极部62A、所述第一隔离部71A、所述第二隔离部72A、所述N型电极81A和所述P型电极82A之间的真实比例也不像附图中示出的那样。另外，所述N型电极81A和所述P型电极82A的尺寸与所述半导体发光芯片的其他层的尺寸比例也不受限于附图中示出的那样。
本领域的技术人员可以理解的是，以上实施例仅为举例，其中不同实施例的特征可以相互组合，以得到根据本发明揭露的内容很容易想到但是在附图中没有明确指出的实施方式。
本领域的技术人员应理解，上述描述及附图中所示的本发明的实施例只作为举例而并不限制本发明。本发明的目的已经完整并有效地实现。本发明的功能及结构原理已在实施例中展示和说明，在没有背离所述原理下，本发明的实施方式可以有任何变形或修改。

Claims (53)

  1. 一半导体发光芯片，其特征在于，包括：
    一衬底；
    一外延叠层，其中所述外延叠层包括一N型氮化镓层、一有源区以及一P型氮化镓层，其中所述衬底、所述N型氮化镓层、所述有源区和所述P型氮化镓层依次层叠；
    至少一反射层，其中所述反射层层叠于所述P型氮化镓层的一部分表面；
    至少两绝缘层，其中一个所述绝缘层以层叠于所述P型氮化镓层的一部分表面的方式环绕于所述反射层的内侧，另一个所述绝缘层以层叠于所述P型氮化镓层的一部分表面的方式环绕于所述反射层的外侧；
    至少一防扩散层，其中所述防扩散层层叠于所述反射层和所述绝缘层；以及
    一电极组，其中所述电极组包括一N型电极和一P型电极，其中所述N型电极被电连接于所述外延叠层的所述N型氮化镓层，所述P型电极被电连接于所述防扩散层。
  2. 根据权利要求1所述的半导体发光芯片，其中所述外延叠层具有至少一半导体裸露部，所述半导体裸露部自所述P型氮化镓层经所述有源区延伸至所述N型氮化镓层，其中所述防扩散层具有至少一防扩散层穿孔，所述外延叠层的所述半导体裸露部对应于所述防扩散层的所述防扩散层穿孔，其中所述N型电极依次经所述防扩散层的所述防扩散层穿孔和所述外延叠层的所述半导体裸露部被电连接于所述N型氮化镓层。
  3. 根据权利要求2所述的半导体发光芯片，进一步包括至少一N型扩展电极部，其中所述N型扩展电极部以被保持在所述外延叠层的所述半导体裸露部的方式层叠于所述N型氮化镓层，其中所述N型电极被电连接于所述N扩展电极部。
  4. 根据权利要求3所述的半导体发光芯片，进一步包括一第一隔离部，其中所述第一隔离部以所述第一隔离部经所述防扩散层的所述防扩散层通道和所述外延叠层的所述半导体裸露部延伸至所述N型氮化镓层的方式层叠于所述防扩散层，其中所述第一隔离部具有至少一第一通道和至少一第二通道，其中所述第一通道延伸至所述N型扩展电极部，所述N型电极经所述第一通道被电连接于所述N型扩展电极部，其中所述第二通道延伸至所述防扩散层，所述P型电极经所述第二通道被电连接于所述防扩散层。
  5. 根据权利要求4所述的半导体发光芯片，其中所述第一隔离部进一步层叠于所述绝缘层。
  6. 根据权利要求4所述的半导体发光芯片，其中所述第一隔离部进一步层叠所述N型扩展电极部。
  7. 根据权利要求4至6中任一所述的半导体发光芯片，其中所述N型电极具有至少一N型电极连接针，其中在所述N型电极层叠于所述第一隔离部时，所述N型电极连接针形成于和被保持在所述第一隔离部的所述第一通道，并且所述N型电极连接针延伸至和被电连接于所述N型扩展电极部，相应地，所述P型电极具有至少一P型电极连接针，其中在所述P型电极层叠于所述第一隔离部时，所述P型电极连接针形成于和被保持在所述第一隔离部的所述第二通道，并且所述P型电极连接针延伸至和被电连接于所述防扩散层。
  8. 根据权利要求2所述的半导体发光芯片，进一步包括一第一隔离部，其中所述第一隔离部以所述第一隔离部经所述防扩散层的所述防扩散层穿孔和所述外延叠层的所述半导体裸露部延伸至所述N型氮化镓层的方式层叠于所述防扩散层，其中所述第一隔离部具有至少一第一通道和至少一第二通道，其中所述第一通道延伸至所述N型氮化镓层，所述N型电极经所述第一通道被电连接于所述N型氮化镓层，其中所述第二通道延伸至所述P型氮化镓层，所述P型电极经所述第二通道被电连接于所述防扩散层。
  9. 根据权利要求8所述的半导体发光芯片，其中所述第一隔离部进一步层叠所述绝缘层。
  10. 根据权利要求8或9所述的半导体发光芯片，进一步包括一扩展电极层，其中所述扩展电极层包括至少一N型扩展电极部和至少一P型扩展电极部，所述N型扩展电极部和所述P型扩展电极部以相互间隔的方式层叠于所述第一隔离部，其中所述N型扩展电极部具有至少一N型扩展电极针，其经所述第一隔离部的所述第一通道延伸至和被电连接于所述N型氮化镓层，其中所述P型扩展电极部具有至少一P型扩展电极针，其经所述第一隔离部的所述第二通道延伸至和被电连接于所述P型氮化镓层，其中所述N型电极被电连接于所述N型扩展电极部，所述P型电极被电连接于所述P型扩展电极部。
  11. 根据权利要求10所述的半导体发光芯片，进一步包括一第二隔离部，其中所述第二隔离部层叠于所述N型扩展电极部、所述第一隔离部和所述P型扩展电极部，其中所述第二隔离部具有至少一第三通道和至少一第四通道，其中所述第三通道延伸至所述N型扩展电极部，所述N型电极经所述第三通道被电连接于所述N型扩展电极部，其中所述第四通道延伸至所述P型扩展电极部，所述P型电极经所述第四通道被电连接于所述P型扩展电极部。
  12. 根据权利要求11所述的半导体发光芯片，其中所述N型电极具有至少一N型扩展连接针，其中在所述N型电极层叠于所述第二隔离部时，所述N型电极连接针形成于和被保持在所述第二隔离部的所述第三通道，并且所述N型电极连接针延伸至和被电连接于所述N型电极连接部，相应地，所述P型电极具有至少一P型电极连接针，其中在所述P型电极层叠于所述第二隔离部时，所述P型电极连接针形成于和被保持在所述第二隔离部的所述第四通道，并且所述P型电极连接针延伸至和被电连接于所述P型扩展电极部。
  13. 根据权利要求1至6、8和9中任一所述的半导体发光芯片，其中所述反射层的厚度尺寸和所述绝缘层的厚度尺寸一致。
  14. 根据权利要求7所述的半导体发光芯片，其中所述反射层的厚度尺寸和所述绝缘层的厚度尺寸一致。
  15. 根据权利要求10所述的半导体发光芯片，其中所述反射层的厚度尺寸和所述绝缘层的厚度尺寸一致。
  16. 根据权利要求11所述的半导体发光芯片，其中所述反射层的厚度尺寸和所述绝缘层的厚度尺寸一致。
  17. 根据权利要求12所述的半导体发光芯片，其中所述反射层的厚度尺寸和所述绝缘层的厚度尺寸一致。
  18. 根据权利要求1至6、8和9中任一所述的半导体发光芯片，其中所述绝缘层的材 料为二氧化硅。
  19. 根据权利要求7所述的半导体发光芯片，其中所述绝缘层的材料为二氧化硅。
  20. 根据权利要求10所述的半导体发光芯片，其中所述绝缘层的材料为二氧化硅。
  21. 根据权利要求11所述的半导体发光芯片，其中所述绝缘层的材料为二氧化硅。
  22. 根据权利要求12所述的半导体发光芯片，其中所述绝缘层的材料为二氧化硅。
  23. 根据权利要求1至6、8和9中任一所述的半导体发光芯片，其中所述绝缘层的厚度尺寸范围为100埃-5000埃。
  24. 根据权利要求7所述的半导体发光芯片，其中所述绝缘层的厚度尺寸范围为100埃-5000埃。
  25. 根据权利要求10所述的半导体发光芯片，其中所述绝缘层的厚度尺寸范围为100埃-5000埃。
  26. 根据权利要求11所述的半导体发光芯片，其中所述绝缘层的厚度尺寸范围为100埃-5000埃。
  27. 根据权利要求12所述的半导体发光芯片，其中所述绝缘层的厚度尺寸范围为100埃-5000埃。
  28. 一半导体发光芯片的制造方法，其特征在于，所述制造方法包括如下步骤：
    (a)自一衬底依次生长一N型氮化镓层、一有源区以及一P型氮化镓层；
    (b)层叠一反射层于所述P型氮化镓层的一部分表面；
    (c)分别环绕一绝缘层于所述反射层的内侧和外侧；
    (d)自所述反射层和所述绝缘层生长一防扩散层；以及
    (e)电连接一N型电极于所述N型氮化镓层和电连接一P型电极于所述防扩散层，以制得所述半导体发光芯片。
  29. 根据权利要求28所述的制造方法，其中在所述步骤(c)中，自所述P型氮化镓层生长所述绝缘层，以使所述绝缘层环绕于所述反射层。
  30. 根据权利要求28所述的制造方法，其中在所述步骤(c)中，自所述有源区生长所述绝缘层，以使所述绝缘层环绕于所述反射层。
  31. 根据权利要求28所述的制造方法，其中在所述步骤(c)中，自所述N型氮化镓层生长所述绝缘层，以使所述绝缘层环绕于所述反射层。
  32. 根据权利要求28所述的制造方法，其中在所述步骤(c)中，自所述衬底生长所述绝缘层，以使所述绝缘环绕于所述反射层。
  33. 根据权利要求28至32中任一所述的制造方法，其中在所述步骤(c)之前，所述制造方法进一步包括步骤：依次刻蚀所述P型氮化镓层和所述有源区，以形成自所述P型氮化镓层经所述有源区延伸至所述N型氮化镓层的至少一半导体裸露部，其中在所述步骤(d)中，在所述防扩散层生长于所述反射层和所述绝缘层时形成至少一防扩散层穿孔，其中所述半导体裸露部对应于所述防扩散层穿孔，以在所述步骤(e)中，允许所述N型电极依次经所述防扩散层穿孔和所述半导体裸露部被电连接于所述N型氮化镓层。
  34. 根据权利要求29至32中任一所述的制造方法，其中在所述步骤(c)之前，所述制造方法进一步包括步骤：依次刻蚀所述P型氮化镓层、所述有源区和所述N型氮化镓层， 以形成自所述P型氮化镓层经所述有源区延伸至所述N型氮化镓层的至少一半导体裸露部，其中在所述步骤(d)中，在所述防扩散层生长于所述反射层和所述绝缘层时形成至少一防扩散层穿孔，其中所述半导体裸露部对应于所述防扩散层穿孔，以在所述步骤(e)中，允许所述N型电极依次经所述防扩散层穿孔和所述半导体裸露部被电连接于所述N型氮化镓层。
  35. 根据权利要求34所述的制造方法，其中在所述步骤(e)之前，所述制造方法进一步包括步骤：生长至少一N型扩展电极部于所述N型氮化镓层，以在所述步骤(e)中，所述N型电极以被电连接于所述N型扩展电极部的方式被电连接于所述N型氮化镓层。
  36. 根据权利要求34所述的制造方法，其中在所述步骤(e)之前，所述制造方法进一步包括步骤：生长一第一隔离部于所述防扩散层，并且所述第一隔离部经所述防扩散层穿孔和所述半导体裸露部延伸至所述N型氮化镓层，其中所述第一隔离部具有至少一第一通道和至少一第二通道，其中所述第一通道延伸至所述N型扩展电极部，所述N型电极经所述第一通道被电连接于所述N型扩展电极部，其中所述第二通道延伸至所述防扩散层，所述P型电极经所述第二通道被电连接于所述防扩散层。
  37. 根据权利要求36所述的制造方法，其中在生长所述第一隔离部于所述防扩散层的步骤中，进一步包括步骤：
    生长一第一隔离部基层于所述防扩散层；和
    蚀刻所述第一隔离部基层，以形成延伸至所述N型扩展电极部的所述第一通道和延伸至所述防扩散层的所述第二通道，其中所述第一隔离部基层形成所述第一隔离部。
  38. 根据权利要求36所述的制造方法，其中在上述方法中，所述第一隔离部层叠所述绝缘层。
  39. 根据权利要求38所述的制造方法，其中在上述方法中，所述第一隔离部层叠所述N型扩展电极部。
  40. 根据权利要求34所述的制造方法，其中在所述步骤(e)中，进一步包括步骤：
    (e.1)自所述第一隔离部生长所述N型电极，其中在生长所述N型电极的过程中，所述N型电极的一N型电极连接针形成于所述第一隔离部的所述第一通道和经所述第一通道延伸至和被电连接于所述N型扩展电极部；和
    (e.2)自所述第一隔离部生长所述P型电极，其中在生长所述P型电极的过程中，所述P型电极的一P型电极连接针形成于所述第一隔离部的所述第二通道和经所述第二通道延伸至和被电连接于所述防扩散层。
  41. 根据权利要求35所述的制造方法，其中在所述步骤(e)中，进一步包括步骤：
    (e.1)自所述第一隔离部生长所述N型电极，其中在生长所述N型电极的过程中，所述N型电极的一N型电极连接针形成于所述第一隔离部的所述第一通道和经所述第一通道延伸至和被电连接于所述N型扩展电极部；和
    (e.2)自所述第一隔离部生长所述P型电极，其中在生长所述P型电极的过程中，所述P型电极的一P型电极连接针形成于所述第一隔离部的所述第二通道和经所述第二通道延伸至和被电连接于所述防扩散层。
  42. 根据权利要求36所述的制造方法，其中在所述步骤(e)中，进一步包括步骤：
    (e.1)自所述第一隔离部生长所述N型电极，其中在生长所述N型电极的过程中，所述N型电极的一N型电极连接针形成于所述第一隔离部的所述第一通道和经所述第一通道延伸至和被电连接于所述N型扩展电极部；和
    (e.2)自所述第一隔离部生长所述P型电极，其中在生长所述P型电极的过程中，所述P型电极的一P型电极连接针形成于所述第一隔离部的所述第二通道和经所述第二通道延伸至和被电连接于所述防扩散层。
  43. 根据权利要求37所述的制造方法，其中在所述步骤(e)中，进一步包括步骤：
    (e.1)自所述第一隔离部生长所述N型电极，其中在生长所述N型电极的过程中，所述N型电极的一N型电极连接针形成于所述第一隔离部的所述第一通道和经所述第一通道延伸至和被电连接于所述N型扩展电极部；和
    (e.2)自所述第一隔离部生长所述P型电极，其中在生长所述P型电极的过程中，所述P型电极的一P型电极连接针形成于所述第一隔离部的所述第二通道和经所述第二通道延伸至和被电连接于所述防扩散层。
  44. 根据权利要求38所述的制造方法，其中在所述步骤(e)中，进一步包括步骤：
    (e.1)自所述第一隔离部生长所述N型电极，其中在生长所述N型电极的过程中，所述N型电极的一N型电极连接针形成于所述第一隔离部的所述第一通道和经所述第一通道延伸至和被电连接于所述N型扩展电极部；和
    (e.2)自所述第一隔离部生长所述P型电极，其中在生长所述P型电极的过程中，所述P型电极的一P型电极连接针形成于所述第一隔离部的所述第二通道和经所述第二通道延伸至和被电连接于所述防扩散层。
  45. 根据权利要求39所述的制造方法，其中在所述步骤(e)中，进一步包括步骤：
    (e.1)自所述第一隔离部生长所述N型电极，其中在生长所述N型电极的过程中，所述N型电极的一N型电极连接针形成于所述第一隔离部的所述第一通道和经所述第一通道延伸至和被电连接于所述N型扩展电极部；和
    (e.2)自所述第一隔离部生长所述P型电极，其中在生长所述P型电极的过程中，所述P型电极的一P型电极连接针形成于所述第一隔离部的所述第二通道和经所述第二通道延伸至和被电连接于所述防扩散层。
  46. 根据权利要求34所述的制造方法，其中在所述步骤(e)之前，所述制造方法进一步包括步骤：生长一第一隔离部于所述防扩散层，并且所述第一隔离部经所述防扩散层穿孔和所述半导体裸露部延伸至所述N型氮化镓层，其中所述第一隔离部具有至少一第一通道和至少一第二通道，其中所述第一通道延伸至所述N型氮化镓层，所述N型电极经所述第一通道被电连接于所述N型氮化镓层，其中所述第二通道延伸至所述防扩散层，所述P型电极经所述第二通道被电连接于所述防扩散层。
  47. 根据权利要求46所述的制造方法，其中在生长所述第一隔离部于所述防扩散层的步骤中，进一步包括步骤：
    生长一第一隔离部基层于所述防扩散层；和
    蚀刻所述第一隔离部基层，以形成延伸至所述N型扩展电极部的所述第一通道和延伸至所述防扩散层的所述第二通道，其中所述第一隔离部基层形成所述第一隔离部。
  48. 根据权利要求46所述的制造方法，其中在上述方法中，所述第一隔离部层叠所述绝缘层。
  49. 根据权利要求46所述的制造方法，其中在生长所述第一隔离部于所述防扩散层之后，所述制造方法进一步包括步骤：
    自所述第一隔离部生长一N型扩展电极部，其中在生长所述N型扩展电极部的过程中，所述N型扩展电极部的一N型扩展电极针形成于所述第一隔离部的所述第一通道和经所述第一通道延伸至所述N型氮化镓层；和
    自所述第一隔离部生长一P型扩展电极部，其中在生长所述P型扩展电极部的过程中，所述P型扩展电极部的一P型扩展电极针形成于所述第一隔离部的所述第二通道和经所述第二通道延伸至所述防扩散层。
  50. 根据权利要求49所述的制造方法，其中在生长所述N型扩展电极部和所述P型扩展电极部于所述第一隔离部之后，所述制造方法进一步包括步骤：生长一第二隔离部于所述N型扩展电极部、所述第一隔离部和所述P型扩展电极部，其中所述第二隔离部具有至少一第三通道和至少一第四通道，其中所述第三通道延伸至所述N型扩展电极部，所述N型电极经所述第三通道被电连接于所述N型扩展电极部，其中所述第四通道延伸至所述P型扩展电极部，所述P型电极经所述第四通道被电连接于所述P型扩展电极部。
  51. 根据权利要求50所述的制造方法，其中在生长所述第二隔离部于所述N型扩展电极部、所述第一隔离部和所述P型扩展电极部的步骤中，进一步包括步骤：
    生长一第二隔离部基层于所述N型扩展电极部、所述第一隔离部和所述P型扩展电极部；
    蚀刻所述第二隔离部基层，以形成延伸至所述N型扩展电极部的所述第三通道和延伸至所述P型扩展电极部的所述第四通道，其中所述第二隔离部基层形成所述第二隔离部。
  52. 根据权利要求50所述的制造方法，其中在所述步骤(e)中，进一步包括步骤：
    (e.1)自所述第二隔离部生长所述N型电极，其中在生长所述N型电极的过程中，所述N型电极的一N型电极连接针形成于所述第二隔离部的所述第三通道和经所述第三通道延伸至和被电连接于所述N型扩展电极部；和
    (e.2)自所述第二隔离部生长所述P型电极，其中在生长所述P型电极的过程中，所述P型电极的一P型电极连接针形成于所述第二隔离部的所述第四通道和经所述第四通道延伸至和被电连接于所述P型扩展电极部。
  53. 根据权利要求51根据权利要求50所述的制造方法，其中在所述步骤(e)中，进一步包括步骤：
    (e.1)自所述第二隔离部生长所述N型电极，其中在生长所述N型电极的过程中，所述N型电极的一N型电极连接针形成于所述第二隔离部的所述第三通道和经所述第三通道延伸至和被电连接于所述N型扩展电极部；和
    (e.2)自所述第二隔离部生长所述P型电极，其中在生长所述P型电极的过程中，所述P型电极的一P型电极连接针形成于所述第二隔离部的所述第四通道和经所述第四通道延伸至和被电连接于所述P型扩展电极部。
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