WO2017167189A1 - 半导体发光器件及其制造方法 - Google Patents

半导体发光器件及其制造方法 Download PDF

Info

Publication number
WO2017167189A1
WO2017167189A1 PCT/CN2017/078474 CN2017078474W WO2017167189A1 WO 2017167189 A1 WO2017167189 A1 WO 2017167189A1 CN 2017078474 W CN2017078474 W CN 2017078474W WO 2017167189 A1 WO2017167189 A1 WO 2017167189A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode
semiconductor layer
semiconductor
light emitting
Prior art date
Application number
PCT/CN2017/078474
Other languages
English (en)
French (fr)
Inventor
张丽旸
程凯
Original Assignee
苏州晶湛半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州晶湛半导体有限公司 filed Critical 苏州晶湛半导体有限公司
Publication of WO2017167189A1 publication Critical patent/WO2017167189A1/zh
Priority to US16/148,989 priority Critical patent/US10636836B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0025—Processes relating to coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials

Definitions

  • the present invention relates to the field of semiconductors, and in particular to a semiconductor light emitting device and a method of fabricating the same.
  • one method currently used is to connect a plurality of LEDs in series and parallel, and one uses a high voltage LED (HV LED).
  • HV LED high voltage LED
  • the chip-level realizes the serial-parallel connection of micro-grains.
  • high-voltage LEDs with micro-die series and parallel connection at the chip level have the advantages of low packaging cost, low line loss, and avoidance of consistency problems caused by wavelength, voltage and brightness span.
  • the existing high-voltage LEDs usually adopt an opposite-side vertical structure, and the two electrodes are on both sides of the epitaxial layer of the LED.
  • the pre-voltage of the package of the LED of the opposite-side vertical structure is high, which tends to cause the temperature of the LED to be too high.
  • a semiconductor light emitting device includes: an insulating substrate; a current spreading layer disposed on the insulating substrate, the current diffusing layer comprising: a first electrode connecting portion, a second electrode connecting portion, and a location N contact portions between the first electrode connecting portion and the second electrode connecting portion, and between the first electrode connecting portion and the contact portion, between the N contact portions, and a flat portion between the second electrode connecting portion and the contact portion, the number of flat portions is N+1, N is a natural number; corresponding to N+1 light rays disposed on the N+1 flat portions a structural layer, each of the light emitting structure layers comprising: a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the corresponding flat portion, wherein the second semiconductor layer is formed away from one side of the active layer Having at least N trenches mated with the N contact portions, the at least N trenches having a depth less than a thickness of the second semiconductor layer, the at least N contacts and at least N of the trench
  • a portion of the second electrode connection portion away from the end surface of the insulating substrate is connected to a second semiconductor layer of the adjacent light emitting structure layer, and each of the contact portions is located adjacent to the first electrode at the contact portion
  • the insulating layer is disposed between a side surface of the active layer of the light emitting structure layer on the side of the connecting portion, a side surface of the first semiconductor layer, and a side surface of the flat portion, and the second electrode connecting portion is located at the contact portion
  • the insulating layer is disposed between sides of the light emitting structure layer on one side, and each of the contact portions is away from an end surface of the insulating substrate and a side of the contact portion adjacent to the first electrode connecting portion
  • the second semiconductor layer of the light emitting structure layer is connected to the first semiconductor layer on the flat portion by a flat portion on the side of the contact portion close to the second electrode connecting portion.
  • the insulating substrate includes a first substrate and a first bonding metal layer, a second bonding metal layer, and an insulating substrate layer sequentially laminated on the first substrate, wherein the insulating substrate layer is disposed at Between the second bonding metal layer and the current spreading layer.
  • the method further includes a first electrode formed on the first electrode connection portion, and a second electrode formed on the second electrode connection portion.
  • a reflective metal layer is formed between the first semiconductor layer and the current diffusion layer.
  • a portion of the at least N contact portions that is electrically connected to the second semiconductor layer from an end surface of the insulating substrate is formed with a conductive metal layer.
  • the second semiconductor layer has a pattern or a rough surface away from the surface of the first semiconductor layer.
  • the second semiconductor layer is formed with a passivation layer away from the surface of the first semiconductor layer and the bottom of the groove.
  • the current diffusion layer further includes at least one first tunnel electrode and a second tunnel electrode, and the first tunnel electrode is located between the first electrode connection portion and the contact portion or two adjacent contacts
  • the second tunnel electrode is located between the contact portion and the second electrode connecting portion, and the insulating layer is disposed on both sides of the first tunnel electrode and the second tunnel electrode.
  • An end surface of the first tunnel electrode and the second tunnel electrode adjacent to the insulating substrate is connected to the insulating substrate, and the first tunnel electrode and the second tunnel electrode are away from an end surface of the insulating substrate and a corresponding light emitting structure layer.
  • the second semiconductor layer is electrically connected.
  • a method of fabricating a semiconductor light emitting device includes: providing a semiconductor light emitting substrate, the semiconductor light emitting substrate comprising a first substrate, the second semiconductor layer sequentially formed on the first substrate, and the active a layer and the first semiconductor layer; forming a filling groove corresponding to the first electrode connection portion, the second electrode connection portion, and at least N contact portions respectively on a surface of the first semiconductor layer away from the first substrate
  • the filling trench extends from the surface of the first semiconductor layer away from the first substrate toward the second semiconductor layer, the second semiconductor layer is exposed to the filling trench; in each of the filling trenches a sidewall and a bottom wall of the filling trench corresponding to the first electrode connection portion form a first insulating layer; the current diffusion layer is formed on a surface of the first semiconductor layer away from the second semiconductor layer, the current
  • the diffusion layer includes the first electrode connection portion, the second electrode connection portion, the N contact portions, and the flattening connecting the first electrode connection portion, the second electrode connection portion, and the contact portion
  • the method further includes: processing the first insulating layer to move the first semiconductor layer away from the first substrate a surface exposed by the first insulating layer; a portion of the first semiconductor layer exposed by the first insulating layer to form the reflective metal layer; and a bottom wall of the filling trench
  • the first insulating layer on the other bottom wall except the bottom wall of the corresponding filling groove of the first electrode connecting portion is etched away, and the first insulating layer on the bottom wall of the filling groove corresponding to the first electrode connecting portion is left. .
  • the method further comprises: forming the conductive metal layer in a portion where the first insulating layer is etched away.
  • the method further includes: roughening a surface of the second semiconductor layer away from the insulating substrate or Graphical.
  • the method further includes forming a passivation layer on a portion of the second semiconductor layer away from the surface of the first semiconductor layer, a bottom of the trench, and a portion where the current diffusion layer is exposed.
  • the method further includes: first, connecting the first electrode connection portion Forming the first electrode after etching the portion of the insulating layer, the first electrode is electrically connected to the first electrode connecting portion, and etching the metal conductive layer and the passivation layer on the second electrode connecting portion to form a portion Said second electrode.
  • the semiconductor light emitting device and the method for fabricating the same according to the embodiments of the present invention have higher integration density, smaller size, less wire bonding, and higher reliability than high voltage LEDs in which a plurality of semiconductor light emitting devices are connected in series and in parallel.
  • FIG. 1 is a top plan view of a semiconductor light emitting device according to a preferred embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the semiconductor light emitting device according to the preferred embodiment of the present invention taken along line A-A of FIG. 1.
  • FIG. 3 is a cross-sectional view showing the semiconductor light emitting device shown in FIG. 2 with a passivation layer and an electrode added thereto.
  • FIG. 4 is a top plan view of a semiconductor light emitting device in accordance with a preferred embodiment of the present invention.
  • Figure 5 is a cross-sectional view taken along line B-B of Figure 4 .
  • Figure 6 is a top plan view of a semiconductor light emitting device in accordance with a preferred embodiment of the present invention in another embodiment.
  • Figure 7 is a top plan view of a semiconductor light emitting device in accordance with a preferred embodiment of the present invention in yet another embodiment.
  • Figure 8 is a top plan view of a semiconductor light emitting device in accordance with a preferred embodiment of the present invention in yet another embodiment.
  • FIG. 9 is a top plan view of a semiconductor light emitting device according to another preferred embodiment of the present invention.
  • Figure 10 is a cross-sectional view taken along line C-C of Figure 9.
  • FIG. 11 is a top plan view of another embodiment of a semiconductor light emitting device according to another preferred embodiment of the present invention.
  • Figure 12 is a schematic cross-sectional view taken along line D-D of Figure 11 .
  • FIG. 13 is a top plan view of a semiconductor light emitting device according to another embodiment of the present invention.
  • FIG. 14 is a top plan view of another embodiment of a semiconductor light emitting device according to another preferred embodiment of the present invention.
  • FIG. 15 is a top plan view of another embodiment of a semiconductor light emitting device according to another preferred embodiment of the present invention.
  • FIG. 16 is a top plan view of another embodiment of a semiconductor light emitting device according to another preferred embodiment of the present invention.
  • 17 is a process flow diagram of a method of fabricating a semiconductor light emitting device according to a preferred embodiment of the present invention.
  • FIG. 18 to FIG. 36 are schematic diagrams showing the structures of the respective components of the semiconductor light-emitting device in each process step of the method for fabricating a semiconductor light-emitting device according to a preferred embodiment of the present invention.
  • 37 to 38 are structural diagrams showing the respective components of the semiconductor light emitting device in each process step of the method for fabricating a semiconductor light emitting device according to another preferred embodiment of the present invention.
  • FIG. 1 is a plan view of a semiconductor light emitting device according to a preferred embodiment of the present invention
  • FIG. 2 is a cross-sectional view of the semiconductor light emitting device according to a preferred embodiment of the present invention taken along line AA of FIG. 3 is a schematic cross-sectional view of the semiconductor light emitting device shown in FIG. 2 after the passivation layer and the electrode are added.
  • a semiconductor light emitting device 100A according to a preferred embodiment of the present invention includes an insulating substrate 110, a current spreading layer 120, an insulating layer 130, a light emitting structure layer 230, and first electrodes 170 and a second disposed on the insulating substrate 110. Electrode 180.
  • the first electrode 170 and the second electrode 180 are not shown in FIGS. 1 and 2, and FIG. 3 shows that the first electrode 170 and the second electrode are formed. 180 device structure.
  • the insulating substrate 110 may include a first substrate 111 and a first bonding metal layer 112, a second bonding metal layer 113, and an insulating substrate layer 114 which are sequentially stacked on the first substrate 111.
  • the first substrate 111 is preferably a silicon substrate.
  • the material of the first substrate 111 is not limited in the embodiment of the present invention, and may be other, such as sapphire, silicon carbide or gallium arsenide.
  • the material of the first bonding metal layer 112 and the second bonding metal layer 113 may be one of metals such as titanium, gold, nickel, tin, platinum, or the like, or an alloy or a plurality of metals.
  • Floor may be one of metals such as titanium, gold, nickel, tin, platinum, or the like, or an alloy or a plurality of metals.
  • the first bonding metal layer 112 and the second bonding metal layer 113 may be bonded to each other.
  • the material of the insulating base layer 114 may be silicon dioxide or silicon nitride. Of course, the material of the insulating base layer 114 is not limited, and may be other.
  • the insulating base layer 114 is formed on a surface of the current diffusion layer 120 away from the first semiconductor layer 140 to break the current diffusion layer 120 and the second bonding metal layer 113.
  • the current diffusion layer 120 is directly disposed on the insulating substrate 110.
  • the current diffusion layer 120 includes a first electrode connection portion 121, a second electrode connection portion 122, and at least N contact portions 123 (one contact portion 123 is taken as an example in FIGS. 1 to 3), and the first electrode is connected
  • the first electrode connecting portion 121, the second electrode connecting portion 122, the contact portion 123, and the flat portion 124 are all part of the current diffusion layer 120, but the current diffusion layer 120 is divided into different regions for convenience of description.
  • the first electrode connecting portion 121, the second electrode connecting portion 122, the contact portion 123, and the flat portion 124 (separated by a broken line in Fig. 2).
  • Each of the flat portions 124 is provided with a light emitting structure layer 230, that is, N+1 flat portions 124 correspond to N+1 light emitting structure layers 230.
  • Each of the light emitting structure layers 230 includes a first semiconductor layer 140, an active layer 150, and a second semiconductor layer 160 which are sequentially stacked on the flat portion 124.
  • At least N trenches 161 are formed on the one surface of the second semiconductor layer 160 away from the active layer 150, and the N contact portions 123 are matched.
  • the depth of the at least N trenches 161 is smaller than the thickness of the second semiconductor layer 160, and the at least N contact portions 123 correspond to at least N of the trenches 161.
  • the second semiconductor layer 160 may have n-type conductivity, and the first semiconductor layer 140 may have p-type conductivity. Alternatively, the second semiconductor layer 160 may have p-type conductivity, and the first semiconductor layer 140 may have n-type conductivity.
  • the active layer 150 is located between the second semiconductor layer 160 and the first semiconductor layer 140.
  • the active layer 150 may have, for example, a multiple quantum well structure.
  • the multiple quantum well structure includes a plurality of quantum well layers and a plurality of quantum barrier layers formed between the quantum well layers.
  • the quantum well layer and the quantum barrier layer may be composed of Al x In y Ga 1-xy N(0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1), but need to satisfy the quantum barrier layer.
  • the energy band is wider than the quantum well layer.
  • the second semiconductor layer 160 may be formed of GaN doped with an n-type impurity
  • the first semiconductor layer 140 may be formed of GaN doped with a p-type impurity, and is active
  • the layer 150 may be formed by alternately stacking quantum well layers formed of Al x In y Ga 1-xy N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1) and having a wider energy band
  • a quantum barrier layer formed of AlInGaN is formed.
  • the electrons and holes injected through the second semiconductor layer 160 and the first semiconductor layer 140 are combined with each other in the active layer 150 to emit light.
  • the emitted light exits through the second semiconductor layer 160.
  • the second semiconductor layer 160 is formed with at least N (N is a natural number) trenches 161 away from the surface of the active layer 150 (one trench 161 is taken as an example in FIGS. 1 to 3), and the trench 161 is The depth is less than the thickness of the second semiconductor 160.
  • the first electrode connecting portion 121 and the second connecting portion 122 are located at two sides of the contact portion 123.
  • the flat portion 124 is located between the first electrode connecting portion 121 and the contact portion 123 and between the contact portion 123 and the second electrode connecting portion 122. If the number of the contact portions 123 is two or more, the flat portion 124 is also located between the plurality of contact portions 123.
  • the material of the current diffusion layer 120 may be, for example, Indium Tin Oxides (ITO), or a combination of one or more metals such as aluminum, copper, gold, tungsten, or the like. An alloy of metals. Of course, the material of the current diffusion layer 120 is not limited, and may be other.
  • the first electrode connection portion 121 is protruded from a side of the current diffusion layer 120 close to the insulating substrate 110 toward a side away from the insulating substrate 110.
  • the insulating layer 130 is disposed between the first electrode connecting portion 121 and a side surface of the first semiconductor layer 140, a side surface of the active layer 150, and a side surface of the second semiconductor layer 160.
  • the first electrode connecting portion 121 is connected to the first semiconductor layer 140 of the light emitting structure layer 230 disposed on the flat portion 124 by a flat portion 124 adjacent thereto.
  • the second electrode connecting portion 122 is protruded from a side of the current diffusion layer 120 close to the insulating substrate 110 toward a side away from the insulating substrate 110.
  • the insulating layer 130 is disposed between the second electrode connecting portion 122 and a side surface of the active layer 150, a side surface of the first semiconductor layer 140, and a side surface of the flat portion 124 connected to the second electrode connecting portion 122.
  • a portion of the second electrode connecting portion 122 that is away from the end surface of the insulating substrate 110 is connected to the second semiconductor layer 160 of the light emitting structure layer 230 adjacent thereto.
  • the contact portion 123 is protruded from a side of the current diffusion layer 120 close to the insulating substrate 110 toward a side away from the insulating substrate 110.
  • the contact portion 123 and the side surface of the active layer 150 on the side of the contact portion 123 (on the side close to the first electrode 170 in FIG. 2), the side surface of the first semiconductor layer 140, and the side surface of the flat portion 124 The insulating layer 130 is disposed therebetween.
  • the contact portion 123 is provided with the insulation between a side surface of the first semiconductor layer 140 on the other side of the contact portion 123 (on the side close to the second electrode 180 in FIG. 2) and a side surface of the active layer 150.
  • each of the contact portions 123 away from the insulating substrate 110 is connected to the second semiconductor layer 160 of the light emitting structure layer 230 on the side of the contact portion 123 close to the first electrode connecting portion 121, and the contact portion is located at the contact portion
  • the flat portion 124 on the side of the second electrode connecting portion 122 is connected to the first semiconductor layer 140 on the flat portion 124.
  • the insulating layer 130 may be disposed between the first electrode connection portion 121 and the side surface of the second semiconductor layer 160, the side surface of the active layer 150, and the side surface of the first semiconductor layer 140. Said absolutely The edge layer 130 may be disposed between the second electrode connection portion 122 and a side surface of the active layer 150, a side surface of the first semiconductor layer 140, and a side surface of the flat portion 124 connected to the second electrode connection portion 122. The insulating layer 130 may be disposed between the contact portion 123 and a side surface of the active layer 150 on the side of the contact portion 123, a side surface of the first semiconductor layer 140, and a side surface of the flat portion 124.
  • the side faces of the first semiconductor layer 140, the active layer 150, the second semiconductor layer 160, and the flat portion 124 in the embodiment of the present invention are connected to the first semiconductor layer 140, the active layer 150, and the second semiconductor.
  • the surface between the layer 160 and the flat portion 124 is a surface between the top surface (the side away from the insulating substrate 110) and the bottom surface (the side close to the insulating substrate 110).
  • the material of the insulating layer 130 may be an insulating material such as silicon dioxide or silicon nitride.
  • the material of the insulating layer 130 is not limited, and may be other.
  • a reflective metal layer 190 may be further formed between the first semiconductor layer 140 and the current diffusion layer 120.
  • the reflective metal layer 190 may cause a portion of the light emitted from the active layer 150 to be reflected and then emitted from the second semiconductor layer 160.
  • the material of the reflective metal layer 190 is not limited, and may be one of a metal that reflects light such as silver (Ag), aluminum (Al), or nickel (Ni), or a plurality of metals.
  • a conductive metal layer 200 may be formed between the end surface of the contact portion 123 away from the insulating substrate 110 and the second semiconductor layer 160.
  • the conductive metal layer 200 is located between the corresponding contact portion 123 and the second semiconductor layer 160, and the conductivity between the second semiconductor layer 160 and the current diffusion layer 120 may be increased. Further, the conductive metal layer 200 may be formed on the end surface of the second electrode connecting portion away from the insulating substrate 110.
  • the surface of the second semiconductor layer 160 away from the insulating substrate 110 may be roughened or patterned, and the surface of the second semiconductor layer 160 away from the surface of the first semiconductor layer 140 may be roughened or patterned to further enhance the semiconductor.
  • the light extraction rate of the light emitting device 100 may be roughened or patterned.
  • FIG. 3 is a schematic cross-sectional view showing the surface of the semiconductor light emitting device shown in FIG. 2 after the passivation layer and the electrode are formed, and the second semiconductor layer 160 may be away from the first semiconductor layer 140.
  • the surface, the bottom of the trench 161, and the portion of the current diffusion layer 120 exposed to the outside form a passivation layer 210.
  • the passivation layer 210 can prevent oxidation of the second semiconductor layer 160 and the current diffusion layer 120.
  • the passivation layer 210 may be directly plated on the corresponding surface.
  • the material of the passivation layer 210 is not limited, and may be a material such as silicon oxide or silicon nitride. Since the refractive index of the passivation layer is between the second semiconductor layer 160 and the air, it is also advantageous to increase the light extraction rate.
  • the first electrode 170 is formed on the first electrode connecting portion 121
  • the second electrode 180 is formed on the second electrode connecting portion 122 .
  • the first lead 171 may be soldered on the first electrode 170
  • the second lead 181 may be soldered on the second electrode 180.
  • the portion of the second semiconductor layer 160 corresponding to the first electrode connection portion 121 may be etched away, and the first electrode 170 may be formed at the etched portion.
  • a portion corresponding to the second semiconductor layer 160 and the second electrode connection portion 122 may be etched away, and the second electrode 180 may be formed at the etched portion.
  • the first electrode 170 may sequentially pass through the first electrode connecting portion 121, the flat portion 124 adjacent to the first electrode connecting portion 121, and the first semiconductor layer near the light emitting structure layer 230 of the first electrode connecting portion 121. 140, the active layer 150 and the second semiconductor layer 160, the contact portion 123, the flat portion 124 close to the second electrode connecting portion 122, the first semiconductor layer 140 near the light emitting structure layer 230 of the second electrode connecting portion 122, and the active layer 150
  • the second semiconductor layer 160 and the second electrode connection portion 122 are electrically connected to the second electrode 180.
  • the first electrode 170 and the second electrode 180 are both located on the same side of the active layer 150, which avoids the problem that the conventional vertical electrode different-side structure packaging process introduces a large pre-voltage.
  • FIG. 4 is A top view of a semiconductor light emitting device in another embodiment of the preferred embodiment of the invention
  • FIG. 5 is a cross-sectional view taken along line B-B of FIG.
  • the number of the trenches 161 may be two, and the contact portions 123 are also two.
  • the two trenches 161 and the two contact portions 123 will be the first semiconductor layer 140, the active layer 150, and the second semiconductor.
  • Layer 160 is divided into three light emitting structure layers 230. The portion enclosed by the broken line in Fig. 5 represents a light emitting structure layer 230.
  • the number of the grooves 161 and the contact portions 123 may be more, and the arrangement may not be limited to a straight type.
  • the number of the grooves 161 and the contact portions 123 is eight, and the arrangement manner is It is serpentine. That is to say, the number of the light-emitting structure layers 230 is flexible and the design is flexible, and the number of rows and the number of columns of the light-emitting structure layer 230 can be limited.
  • first electrode 170 and the second electrode 180 can also be flexibly set.
  • they can be symmetrically disposed on both sides of the groove 161 as shown in FIG. 1 , respectively located at the center of the two sides, or as As shown in Fig. 7, diagonally opposite sides of the groove 161 are separately provided.
  • the positions of the first electrode 170 and the second electrode 180 can also be flexibly set, for example, symmetrically disposed in two trenches as shown in FIG.
  • the two sides of the 161 are respectively located at the center of the two side edges, and may also be disposed at the opposite corners. Alternatively, as shown in FIG. 8, they may be disposed at two vertex angles perpendicular to one side of the groove 161.
  • FIG. 9 is a plan view of a semiconductor light emitting device according to another preferred embodiment of the present invention
  • FIG. 10 is a cross-sectional view taken along line C-C of FIG.
  • the current diffusion layer 120 of the semiconductor light emitting device 100B may further include one or more first tunnel electrodes 125 electrically connected to the contact portion 123 and one or more
  • the second tunnel electrode 126 is electrically connected to the second tunnel electrode 126.
  • the first tunnel electrode 125 is disposed between the first electrode connecting portion 121 and the contact portion 123, and the second tunnel electrode 126 is disposed at the second electrode connecting portion 122. Between the contact portion 123, it is possible to help spread the current.
  • the first tunnel electrode 125 and the second tunnel electrode 126 may adopt a finger-shaped electrode, and may also adopt other shapes of electrodes.
  • the design is flexible, and the number thereof is not limited.
  • the number of electrodes may be one or more, and is not affected by limit.
  • the first tunnel electrode 125 may be disposed between the first electrode connecting portion 121 and the contact portion 123 .
  • the first tunnel electrode 125 is protruded from a side of the current diffusion layer 120 close to the insulating substrate 110 toward a side away from the insulating substrate 110, but does not pass through the second semiconductor layer 160.
  • An insulating layer 130 is disposed on both sides of the first tunnel electrode 125, and the first tunnel electrode 125 is electrically connected to the contact portion 123.
  • the end surface of the first tunnel electrode 125 adjacent to the insulating substrate 110 is connected to the insulating substrate 110.
  • the first tunnel electrode 125 is electrically away from the end surface of the insulating substrate 110 and the second semiconductor layer 160 of the corresponding light emitting structure layer 230. connection.
  • the second tunnel electrode 126 may be disposed between the second electrode connecting portion 122 and the contact portion 123.
  • the second tunnel electrode 126 is protruded from a side of the current diffusion layer 120 close to the insulating substrate 110 toward a side away from the insulating substrate 110, but does not pass through the second semiconductor layer 160, and both sides of the second tunnel electrode 126
  • An insulating layer 130 is provided.
  • An insulating layer 130 is disposed on both sides of the second tunnel electrode 126 , and the second tunnel electrode 126 is electrically connected to the second electrode 180 .
  • the second tunnel electrode 126 is connected to the insulating substrate 110 near the end surface of the insulating substrate 110, and the second tunnel electrode 126 is electrically away from the end surface of the insulating substrate 110 and the second semiconductor layer 160 of the corresponding light emitting structure layer 230. connection.
  • each of the light emitting structure layers 230 can also add a tunnel electrode, as shown in FIG. 11 and FIG. 12, and FIG. 11 is another preferred embodiment of the present invention.
  • FIG. 12 is a cross-sectional view taken along line DD of FIG. 11 in a top view of a semiconductor light emitting device provided in another embodiment.
  • the specific number and arrangement of the tunnel electrodes are not limited. The use of tunnel electrodes helps to spread the current. When the size of the semiconductor light emitting element is increased, the tunnel electrode diffusion effect is better.
  • FIG. 9 and FIG. 10 are only one embodiment of the first tunnel electrode 125 and the second tunnel electrode 126.
  • the first tunnel electrode 125 and the second tunnel electrode 126 are
  • the finger portion may also be plural, may be parallel to the groove 161, or may be perpendicular to the groove 161. For example, it can be as shown in FIGS. 13 and 14.
  • FIG. 13 and FIG. 14 are only one embodiment of the first tunnel electrode 125 and the second tunnel electrode 126.
  • the finger portions of the first tunnel electrode 125 and the second tunnel electrode 126 may also be A plurality of electrodes may be parallel to the trench 161 or may be perpendicular to the trench 161.
  • the first electrode 170 and the second electrode 180 may be disposed at different positions. For example, it can be as shown in FIGS. 15 and 16.
  • Figure 17 is a process flow diagram showing a method of fabricating the semiconductor light emitting device 100 in accordance with a preferred embodiment of the present invention. The flowchart will be described in detail below with reference to Figs. 18 to 36. It should be noted that the method of the present invention is not limited to the specific order described in FIG. 17 and the following. It should be understood that in other embodiments, the order of some of the steps in the method of the present invention may be interchanged according to actual needs, or some of the steps may be omitted or deleted.
  • a semiconductor light-emitting base layer 220 is provided.
  • the semiconductor light-emitting base layer 220 includes a first substrate 221, the second semiconductor layer 160 sequentially formed on the first substrate 221, the active layer 150, and The first semiconductor layer 140.
  • the second semiconductor layer 160, the active layer 150, and the first semiconductor layer 140 may be sequentially grown on the surface of the first substrate 221.
  • the first substrate 221 may include a second substrate 222 and a buffer layer 223 grown on the second substrate 222.
  • the second semiconductor layer 160, the active layer 150, and the first semiconductor layer 140 may be grown on the buffer layer 223. .
  • Step S302 forming a filling groove 141 corresponding to the first electrode connecting portion 121, the second electrode connecting portion 122, and the contact portion 123 of FIG. 2, respectively, on a surface of the first semiconductor layer 140 away from the first substrate 221,
  • the filling trench 141 extends from the surface of the first semiconductor layer 140 away from the first substrate 221 toward the second semiconductor layer 160, and the second semiconductor layer 160 is exposed to the filling trench 141.
  • three filling slots 141 are arranged at intervals on the surface of the first semiconductor layer 140 away from the first substrate 221 , and the three filling slots 141 respectively correspond to FIG. 2 .
  • the second semiconductor layer 160 is exposed by the filling trench 141.
  • the etching depth of the second semiconductor layer 160 is smaller than the thickness of the second semiconductor layer 160.
  • a first insulating layer 131 is formed on the sidewall 142 of each of the filling grooves 141 and the bottom wall 143 of the filling groove 141 corresponding to the first electrode connecting portion 121.
  • the first semiconductor layer 140 may be away from the surface of the first substrate 221, the sidewall 142 of each of the filling trenches 141, and the bottom of the filling trench 141 by chemical vapor deposition (CVD) or the like.
  • the wall 143 forms a first insulating layer 131.
  • the material of the first insulating layer 131 may be an insulating material such as silicon dioxide or silicon nitride. Of course, the material of the first insulating layer 131 is not limited, and may be other.
  • the first semiconductor layer 140 may be exposed from the first insulating layer 131 by a process such as photo, deposition, etching, come out.
  • the reflective metal layer 190 may be formed on a portion of the first semiconductor layer 140 exposed by the first insulating layer 131.
  • the reflective metal layer 190 may cause a portion of the light emitted from the active layer 150 to be reflected and then emitted from the second semiconductor layer 160.
  • the material of the reflective metal layer 190 is not limited, and may be one of a metal that reflects light such as silver (Ag), aluminum (Al), or nickel (Ni), or a plurality of metals.
  • the first insulating layer on the bottom wall 143 of the filling groove 141 except the bottom wall 143 of the filling groove 141 corresponding to the first electrode connecting portion 121 is used.
  • the first insulating layer 131 on the bottom wall 143 of the filling trench 141 corresponding to the first electrode connecting portion 121 is left to be etched away, in preparation for the subsequent fabrication of the first electrode 170.
  • a conductive gold may be formed in a portion where the first insulating layer 131 is etched away.
  • Layer 200 is added to increase conductivity.
  • Step S304 forming the current diffusion layer 120 on a surface of the first semiconductor layer 140 away from the second semiconductor layer 160, the current diffusion layer 120 including the first electrode connection portion 121 and the second electrode connection portion 122 and a flat portion 124 of the contact portion 123.
  • a surface of the first semiconductor layer 140 away from the second semiconductor layer 160 is plated with a current diffusion layer 120, and the current diffusion layer 120 is filled in a filling groove corresponding to the first electrode connection portion 121.
  • a portion of the portion 141 forms a first electrode connection portion 121
  • a portion of the current diffusion layer 120 filled in the filling groove 141 corresponding to the second electrode connection portion 122 forms a second electrode connection portion 122
  • the current diffusion layer 120 is filled in correspondence with the contact portion 123.
  • a portion of the filling groove 141 forms a contact portion 123.
  • the flat portion 124 is connected to the first electrode connecting portion 121 and the contact portion 123, the contact portion 123, and the second electrode connecting portion 122.
  • the maximum thickness of the current diffusion layer 120 is greater than the distance from the reflective metal layer 190 to the bottom of the filling trench 141. Therefore, the surface of the current diffusion layer 120 away from the second semiconductor layer 160 is a flat surface.
  • Step S305 etching the flat portion 124 of the current diffusion layer 120 to form a second insulating layer 132, and forming the second portion between the flat portion 124 connected to the first electrode connecting portion 121 and the contact portion 123.
  • the insulating layer 132, the second insulating layer 132 is formed between the flat portion 124 connected to the contact portion 123 and the second electrode connecting portion 122.
  • the patterning portion 124 of the selective current diffusion layer 120 may be etched, and then the second insulating layer 132 may be plated in the etched pattern.
  • the second insulating layer 132 functions as a resistor and can be electrically disconnected at a position where electrical communication is not required.
  • Step S306 forming the insulating substrate 110 on a surface of the current diffusion layer 120 away from the second semiconductor layer 160.
  • the insulating base layer 114 may be formed on the surface of the current diffusion layer 120 away from the second semiconductor layer 160, and then the second bonding metal layer 113 is plated on the insulating base layer 114. As shown in Figure 28.
  • the first substrate 111 plated with the first bonding metal layer 112 is prepared, and then the first bonding metal layer 112 is bonded to the second bonding metal layer 113 as shown in FIG.
  • Step S307 removing the first substrate 221, forming the trench 161 on a surface of the second semiconductor layer 160 away from the first semiconductor layer 140, so that the contact portion 123 is exposed to the trench 161.
  • the depth of the trench 161 is smaller than the thickness of the second semiconductor layer 160.
  • FIG. 31 is a schematic diagram showing the overall structure after the bonding is reversed.
  • the first substrate 221 is removed.
  • a trench 161 is formed on the surface of the second semiconductor layer 160 away from the first semiconductor layer 140, and the contact portion 123 is exposed to the trench 161.
  • the portion of the second semiconductor layer 160 corresponding to the first electrode connection portion 121 and the second electrode connection portion 122 may be etched away to expose the first electrode connection portion 121 and the second electrode connection portion 122, specifically The first insulating layer 131 on the first electrode connecting portion 121 and the metal conductive layer 200 on the second electrode connecting portion 122 are exposed.
  • Step S308 forming the first electrode 170 and the second electrode 180, the first electrode 170 is electrically connected to the first electrode connecting portion 121, and the second electrode 180 is connected to the second electrode 122 electrical connection.
  • the surface of the second semiconductor layer 160 may be roughened or patterned to form a semiconductor light emitting device 100A as shown in FIG. 34 (illustrated by taking a pattern in FIG. 34), in the second semiconductor layer.
  • the surface away from the surface of the first semiconductor layer 140 is roughened or has a pattern, and the light extraction rate of the semiconductor light emitting device 100 can be further improved.
  • a passivation layer may be formed on a portion of the second semiconductor layer 160 away from the surface of the first semiconductor layer 140, the bottom of the trench 161, and the portion where the current diffusion layer 120 is exposed outside. 210.
  • the passivation layer 210 can prevent oxidation of the second semiconductor layer 160 and the current diffusion layer 120, and increase the light extraction rate.
  • the first insulating layer 131 on the first electrode connecting portion 121 may be etched away to form a first electrode 170 electrically connected to the first electrode connecting portion 121.
  • the metal conductive layer 200 and the passivation layer 210 on the second electrode connecting portion 122 are etched away to form a second electrode 180 electrically connected to the second electrode connecting portion 122.
  • the specific connecting method is not limited.
  • the first electrode 170 may be formed on the etched portion of the second semiconductor layer 160 corresponding to the first electrode connection portion 121, and the second semiconductor layer 160 corresponds to the second electrode connection portion 122. The portion that is etched away forms the second electrode 180.
  • the filling trench 141 when the filling trench 141 is formed, the filling trenches 141 corresponding to the first tunnel electrode 125 and the second tunnel electrode 126 respectively shown in FIG. 12 are formed, after etching The second semiconductor layer 160 is exposed by the filling trench.
  • One end of the filling groove 141 corresponding to the first tunnel electrode 125 and the filling groove 141 corresponding to the contact portion 123 are electrically connected, and one end of the filling groove 141 corresponding to the second tunnel electrode 126 and the contact
  • the filling grooves 141 corresponding to the portions 123 are electrically connected.
  • the first insulating layer 131 is formed on the side wall 142 of each of the filling grooves 141 and the bottom wall 143 of the filling groove 141 corresponding to the first electrode connecting portion 121.
  • the current diffusion layer 120 when the current diffusion layer 120 is formed, the current diffusion layer 120 is filled in the filling trench 141 corresponding to the first tunnel electrode 125 and the second tunnel electrode 126, and one end of the first tunnel electrode 125 is The contact portion 123 is electrically connected, and one end of the second tunnel electrode 126 is electrically connected to the second electrode 180.
  • the insulating layer 130 is disposed on both sides of the first tunnel electrode 125 and the second tunnel electrode 126.
  • the first tunnel electrode 125 and the second tunnel electrode 126 can help to diffuse current, and the structure thereof can adopt a finger-shaped electrode, and the design is flexible, wherein the number of the finger portions can be one or more, and is not limited.
  • the semiconductor light emitting device and the method for fabricating the same have higher integration density, smaller size, and less wiring, and are more reliable than high voltage LEDs in which a plurality of semiconductor light emitting devices are connected in series and in parallel.
  • the first electrode 170 and the second electrode 180 are disposed on the same side, thereby avoiding the problem that the conventional vertical electrode different-side structure packaging process introduces a pre-voltage.
  • the terms “set”, “install”, “connected”, and “connected” are to be understood broadly, and may be a fixed connection, for example, unless otherwise specifically defined and defined. It can also be a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be internal communication between the two elements.
  • the specific meaning of the above terms in the present invention can be understood in a specific case by those skilled in the art.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)

Abstract

一种半导体发光器件（100A）及制造方法，半导体发光器件（100A）包括绝缘基底（110）、电流扩散层（120）、发光结构层（230）以及绝缘层（130）。电流扩散层（120）包括第一电极连接部（121）、第二电极连接部（122）、位于第一电极连接部（121）与第二电极连接部（122）之间的N个接触部（123）、以及连接于第一电极连接部（121）与接触部（123）之间、N个接触部（123）之间以及第二电极连接部（122）与接触部（123）之间的N+1个平展部（124），N为自然数。N+1个发光结构层（230）对应设置在N+1个平展部（124）上，每个发光结构层（230）包括：依次层叠在对应的平展部（124）上的第一半导体层（140）、活性层（150）以及第二半导体层（160），第二半导体层（160）远离活性层（150）的一面形成有与N个接触部（123）配合的至少N个沟槽（161），至少N个沟槽（161）的深度小于第二半导体层（160）的厚度，至少N个接触部（123）与至少N个沟槽（161）相对应。

Description

半导体发光器件及其制造方法
本申请要求于2016年03月29日提交中国专利局的申请号为CN201610187812.0、名称为“半导体发光器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体领域，具体而言，涉及一种半导体发光器件及其制造方法。
背景技术
为使发光二极管(light emitting diode,简称LED)能在较高的电压下工作，目前使用的一种方式是将多颗LED进行串并联，一种则是使用高压LED(HV LED)，其在芯片级就实现了微晶粒的串并联。相比于将多颗LED进行串并联，在芯片级实现微晶粒串并联的高压LED具有封装成本低、线路损耗低以及避免波长、电压、亮度跨度带来的一致性问题等优势。
现有的高压LED通常采用异侧垂直结构，其两个电极在LED外延层的两侧，但是，异侧垂直结构的LED的封装的前置电压较高，容易导致LED的温度过高。
发明内容
本发明实施例的目的在于提供一种半导体发光器件及其制造方法，以改善上述的问题。
本发明实施例提供的一种半导体发光器件，包括：绝缘基底；设置在所述绝缘基底上的电流扩散层，所述电流扩散层包括：第一电极连接部、第二电极连接部、位于所述第一电极连接部与所述第二电极连接部之间的N个接触部、以及连接于所述第一电极连接部与所述接触部之间、所述N个接触部之间以及所述第二电极连接部与所述接触部之间的平展部，平展部的个数为N+1个，N为自然数；对应设置在所述N+1个平展部上的N+1个发光结构层，每个所述发光结构层包括：依次层叠在对应的所述平展部上的第一半导体层、活性层以及第二半导体层，所述第二半导体层远离所述活性层的一面形成有与所述N个接触部配合的至少N个沟槽，所述至少N个沟槽的深度小于所述第二半导体层的厚度，所述至少N个接触部与至少N个所述沟槽相对应；以及绝缘层；其中，所述第一电极连接部和与其相邻的所述发光结构层的侧面之间设置有所述绝缘层，所述第一电极连接部通过与其相邻的平展部与设置在该平展部上的发光结构层的第一半导体层连接，所述第二电极连接部和与其相邻的所述发光结构层的活性层的侧面、第一半导体层的侧面以及与平展部的侧面之间设置有所述绝缘层，所述第二电极连接部的远离所述绝缘基板的端面的一部分和与其相邻的发光结构层的第二半导体层连接，每个所述接触部与位于所述接触部靠近所述第一电极连接部一侧的发光结构层的活性层的侧面、第一半导体层的侧面以及所述平展部的侧面之间设置有所述绝缘层，与位于所述接触部靠近所述第二电极连接部一侧的发光结构层的侧面之间设置有所述绝缘层，每个所述接触部远离所述绝缘基板的端面与位于该接触部靠近所述第一电极连接部一侧的发光结构层的第二半导体层连接，通过位于该接触部靠近所述第二电极连接部一侧的平展部与该平展部上的第一半导体层连接。
进一步的，所述绝缘基底包括第一衬底以及依次层叠在所述第一衬底上的第一键合金属层、第二键合金属层以及绝缘基底层，所述绝缘基底层设置在所述第二键合金属层与所述电流扩散层之间。
进一步的，还包括形成于所述第一电极连接部上的第一电极，以及形成于所述第二电极连接部上的第二电极。
进一步的，所述第一半导体层与所述电流扩散层之间形成有反射金属层。
进一步的，所述至少N个接触部远离所述绝缘基底的端面与所述第二半导体层电连接的部分形成有导电金属层。
进一步的，所述第二半导体层远离所述第一半导体层的表面具有图形或者为粗糙表面。
进一步的，所述第二半导体层远离所述第一半导体层的表面以及所述凹槽的底部形成有钝化层。
进一步的，所述电流扩散层还包括至少一个第一隧道电极以及第二隧道电极，所述第一隧道电极位于所述第一电极连接部与所述接触部之间或者相邻的两个接触部之间，所述第二隧道电极位于所述接触部与所述第二电极连接部之间，所述第一隧道电极与所述第二隧道电极的两侧均设置有所述绝缘层，所述第一隧道电极以及第二隧道电极靠近所述绝缘基底的端面与所述绝缘基底连接，所述第一隧道电极以及第二隧道电极远离所述绝缘基底的端面与对应的发光结构层的第二半导体层电连接。
本发明实施例提供的一种半导体发光器件的制造方法，包括：提供半导体发光基层，所述半导体发光基层包括第一基底、依次形成在第一基底上的所述第二半导体层、所述活性层以及所述第一半导体层；在所述第一半导体层远离所述第一基底的表面形成分别对应于所述第一电极连接部、第二电极连接部以及至少N个接触部的填充槽，所述填充槽由所述第一半导体层远离所述第一基底的表面向所述第二半导体层延伸，所述第二半导体层曝露于所述填充槽；在每个所述填充槽的侧壁以及与所述第一电极连接部对应的填充槽的底壁形成第一绝缘层；在所述第一半导体层远离所述第二半导体层的表面形成所述电流扩散层，所述电流扩散层包括所述第一电极连接部、第二电极连接部、N个接触部以及连接所述第一电极连接部、第二电极连接部以及接触部的平展部；对所述电流扩散层的平展部蚀刻并形成第二绝缘层，其中，与所述第一电极连接部连接的平展部与所述接触部之间形成所述第二绝缘层，与所述接触部连接的平展部与所述第二电极连接部之间形成所述第二绝缘层；在所述电流扩散层远离所述第二半导体层的表面形成所述绝缘基底；去除所述第一基底，在所述第二半导体层远离所述第一半导体层的表面形成所述至少N个沟槽，使得所述至少N个接触部对应的曝露于所述至少N个沟槽。
进一步的，在所述第一半导体层远离所述第二半导体层的表面形成所述电流扩散层之前还包括：对所述第一绝缘层进行处理，使所述第一半导体层远离第一基底的表面由所述第一绝缘层曝露出来；在所述第一半导体层由所述第一绝缘层曝露出来的部分形成所述反射金属层；将所述填充槽的底壁中除与所述第一电极连接部对应的填充槽的底壁之外的其他底壁上的第一绝缘层刻蚀掉，保留与所述第一电极连接部对应的填充槽的底壁上的第一绝缘层。
进一步的，在所述第一半导体层远离所述第二半导体层的表面形成所述电流扩散层之前，还包括：在第一绝缘层被蚀刻掉的部分形成所述导电金属层。
进一步的，在所述第二半导体层远离所述第一半导体层的表面形成所述至少N个沟槽之后，还包括：对所述第二半导体层远离所述绝缘基底的表面进行粗糙化或者图形化。
进一步的，所述方法还包括在所述第二半导体层远离所述第一半导体层的表面、所述沟槽的底部以及所述电流扩散层曝露在外面的部分均形成钝化层。
进一步的，在形成所述钝化层之后，还包括：将所述第一电极连接部上的第一 绝缘层蚀刻掉部分后形成所述第一电极，所述第一电极与所述第一电极连接部电连接，将第二电极连接部上的金属导电层及钝化层蚀刻掉部分后形成所述第二电极。
本发明实施例提供的半导体发光器件及其制造方法，与将多个半导体发光器件进行串并联的高压LED相比，集成密度更高，尺寸更小，且打线少，可靠性高。
为使本发明的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本发明的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1是本发明较佳实施例提供的半导体发光器件的俯视图。
图2是本发明较佳实施例提供的半导体发光器件沿图1中A-A线的剖面示意图。
图3是图2所示的半导体发光器件增加钝化层和电极后的剖面示意图。
图4是本发明较佳实施例的半导体发光器件在一种具体实施方式中的俯视图。
图5是沿图4中B-B线的剖面示意图。
图6是本发明较佳实施例的中半导体发光器件在另一种具体实施方式中的俯视图。
图7是本发明较佳实施例的中半导体发光器件在又一种具体实施方式中的俯视图。
图8是本发明较佳实施例的中半导体发光器件在再一种具体实施方式中的俯视图。
图9是本发明另一较佳实施例提供的半导体发光器件的俯视图。
图10是沿图9中C-C线的剖面示意图。
图11是本发明另一较佳实施例提供的半导体发光器件在再一种具体实施方式中的俯视图。
图12是沿图11的D-D线的剖面示意图。
图13是本发明另一较佳实施例提供的半导体发光器件在一种具体实施方式中的俯视图。
图14是本发明另一较佳实施例提供的半导体发光器件在又一种具体实施方式中的俯视图。
图15是本发明另一较佳实施例提供的半导体发光器件在另一种具体实施方式中的俯视图。
图16是本发明另一较佳实施例提供的半导体发光器件在再一种具体实施方式中的俯视图。
图17是本发明较佳实施例提供的半导体发光器件制造方法的工艺流程图。
图18至图36是本发明一种较佳实施例的半导体发光器件制造方法各工艺流程步骤中分别制造所述半导体发光器件各组成部分的结构示意图。
图37至图38是本发明另一种较佳实施例的半导体发光器件制造方法各工艺流程步骤中分别制造所述半导体发光器件各组成部分的结构示意图。
其中，附图标记汇总如下：
半导体发光器件100A、100B，绝缘基底110，电流扩散层120，绝缘层130，发光结构层230，第一半导体层140，活性层150，第二半导体层160，第一电极170，第一引线171，第二电极180，第二引线181，第一衬底111，第一键合金属 层112，第二键合金属层113，绝缘基底层114，沟槽161，第一电极连接部121、第二电极连接部122以及接触部123，平展部124，第一隧道电极125，第二隧道电极126，反射金属层190，导电金属层200，钝化层210，半导体发光基层220，第一基底221，第二衬底222，缓冲层223，填充槽141，填充槽141的侧壁142，填充槽141的底壁143，第一绝缘层131，第二绝缘层132。
具体实施方式
下面将结合本发明实施例中附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围，而是仅仅表示本发明的选定实施例。基于本发明的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
请参阅图1及图3，图1是本发明较佳实施例提供的半导体发光器件的俯视图，图2是本发明较佳实施例提供的半导体发光器件沿图1中A-A线的剖面示意图，图3是图2所示的半导体发光器件增加钝化层和电极后的剖面示意图。本发明较佳实施例提供的一种半导体发光器件100A包括绝缘基底110，设置在所述绝缘基底110上的电流扩散层120、绝缘层130、发光结构层230、以及第一电极170和第二电极180。为了更清楚的说明本发明实施例中半导体发光器件的结构，图1及图2中未示出第一电极170和第二电极180，图3示出了形成了第一电极170及第二电极180的器件结构。
具体的，所述绝缘基底110可以包括第一衬底111以及依次层叠在第一衬底111上的第一键合金属层112、第二键合金属层113以及绝缘基底层114。其中，第一衬底111优选的为硅衬底，当然，第一衬底111的材料在本发明实施例中并不作为限制，也可以是其他，如蓝宝石、碳化硅或者砷化镓中的一种或多种。第一键合金属层112和第二键合金属层113的材料可以为钛、金、镍、锡、铂等金属中的一种金属，又或是多种金属组合而成的合金或多金属层。所述第一键合金属层112和所述第二键合金属层113可以相互键合。所述绝缘基底层114的材料可以是二氧化硅或者氮化硅等，当然，绝缘基底层114的材料并不作为限制，也可以是其他。绝缘基底层114形成于所述电流扩散层120远离所述第一半导体层140的表面，使电流扩散层120与第二键合金属层113断路。
所述电流扩散层120直接设置于所述绝缘基底110上。所述电流扩散层120包括第一电极连接部121、第二电极连接部122以及至少N个接触部123(图1至图3中以一个接触部123为例)，以及连接所述第一电极连接部121与所述接触部123、所述第二电极连接部122与所述接触部123的N+1个平展部124。可以理解的是，第一电极连接部121、第二电极连接部122、接触部123以及平展部124都是电流扩散层120的一部分，只是为了方便描述，将电流扩散层120划分为不同的区域：第一电极连接部121、第二电极连接部122、接触部123以及平展部124(图2中用虚线进行了区隔)。
每个平展部124上均设置有一个发光结构层230，也就是说N+1个平展部124对应有N+1个发光结构层230。每个发光结构层230均包括依次层叠在平展部124上的第一半导体层140、活性层150以及第二半导体层160。所述第二半导体层160远离所述活性层150的一面形成有与所述N个接触部123配合的至少N个沟槽161， 所述至少N个沟槽161的深度小于所述第二半导体层160的厚度，所述至少N个接触部123与至少N个所述沟槽161相对应。
第二半导体层160可以具有n型导电性，第一半导体层140可以具有p型导电性。可选地，第二半导体层160可以具有p型导电性，第一半导体层140可以具有n型导电性。
活性层150位于第二半导体层160和第一半导体层140之间。活性层150可以具有例如多量子阱结构。多量子阱结构包括多个量子阱层和形成在量子阱层之间的多个量子垒层。量子阱层和量子垒层较佳的可由AlxInyGa1-x-yN(0≦x≦1,0≦y≦1,0<x+y≦1)组成，但需满足量子垒层的能带比量子阱层宽。举例来说，如果为氮化镓基发光二极管，则第二半导体层160可以由掺杂有n型杂质的GaN形成，第一半导体层140可以由掺杂有p型杂质的GaN形成，并且活性层150可以通过交替地堆叠由AlxInyGa1-x-yN(0≦x≦1,0≦y≦1,0<x+y≦1)形成的量子阱层和由具有更宽能带的AlInGaN形成的量子垒层来形成。
通过第二半导体层160和第一半导体层140注入的电子和空穴在活性层150中彼此结合而发射光。发射的光穿过第二半导体层160出射。
所述第二半导体层160远离所述活性层150的表面形成有至少N(N为自然数)个沟槽161(图1至图3中以一个沟槽161为例)，所述沟槽161的深度小于所述第二半导体160的厚度。
其中，具体的，所述第一电极连接部121与所述第二连接部122位于所述接触部123的两侧。所述平展部124位于所述第一电极连接部121与所述接触部123之间，以及所述接触部123与第二电极连接部122之间。如果接触部123的个数是两个以上，则平展部124还位于多个接触部123之间。所述电流扩散层120的材料例如可以是氧化铟锡(Indium Tin Oxides，简称ITO)，也可以是铝、铜、金、钨等金属中的一种或多种金属的组合层亦或是多种金属的合金。当然，所述电流扩散层120的材料并不作为限制，也可以是其他。
所述第一电极连接部121由电流扩散层120靠近所述绝缘基底110的一侧向远离所述绝缘基底110的一侧凸起。所述第一电极连接部121与所述第一半导体层140的侧面、活性层150的侧面和第二半导体层160的侧面之间设置有所述绝缘层130。所述第一电极连接部121通过与其相邻的平展部124与设置在该平展部124上的发光结构层230的第一半导体层140连接。
所述第二电极连接部122由电流扩散层120靠近所述绝缘基底110的一侧向远离所述绝缘基底110的一侧凸起。所述第二电极连接部122与所述活性层150的侧面、第一半导体层140的侧面以及与所述第二电极连接部122连接的平展部124的侧面之间设置有所述绝缘层130。所述第二电极连接部122的远离所述绝缘基板110的端面的一部分和与其相邻的发光结构层230的第二半导体层160连接。
所述接触部123由电流扩散层120靠近所述绝缘基底110的一侧向远离所述绝缘基底110的一侧凸起。所述接触部123与位于接触部123一侧(图2中靠近所述第一电极170一侧)的活性层150的侧面、第一半导体层140的侧面以及与所述平展部124的侧面之间设置有所述绝缘层130。所述接触部123与位于所述接触部123另一侧(图2中靠近所述第二电极180一侧)的第一半导体层140的侧面和活性层150的侧面之间设置有所述绝缘层130。每个所述接触部123远离所述绝缘基板110的端面与位于该接触部123靠近所述第一电极连接部121一侧的发光结构层230的第二半导体层160连接，通过位于该接触部123靠近所述第二电极连接部122一侧的平展部124与该平展部124上的第一半导体层140连接。
也就是说，所述绝缘层130可以设置于所述第一电极连接部121与所述第二半导体层160的侧面、活性层150的侧面以及第一半导体层140的侧面之间。所述绝 缘层130可以设置于第二电极连接部122与活性层150的侧面、第一半导体层140的侧面以及与第二电极连接部122连接的平展部124的侧面之间。所述绝缘层130可以设置于所述接触部123与位于接触部123一侧的活性层150的侧面、第一半导体层140的侧面以及平展部124的侧面之间。可以理解的，本发明实施例中的第一半导体层140、活性层150、第二半导体层160以及平展部124的侧面，指的是连接于第一半导体层140、活性层150、第二半导体层160以及平展部124各自顶面(远离绝缘基底110的一面)与底面(靠近绝缘基底110的一面)之间的面。
在本实施例中，所述绝缘层130的材料可以是二氧化硅或者氮化硅等绝缘材料，当然，所述绝缘层130的材料并不作为限制，也可以是其他。
另外，所述第一半导体层140与所述电流扩散层120之间可以进一步形成有反射金属层190。该反射金属层190可以使活性层150发出的部分光经反射后从第二半导体层160方向出射。在本实施例中，反射金属层190的材料并不作为限制，可以是银(Ag)、铝(Al)、镍(Ni)等对光有反射作用的金属中的一种，或多种金属组成的金属合金或者金属组合层，亦或是合金超晶格结构。
另外，可选的，所述接触部123远离所述绝缘基底110的端面与所述第二半导体层160之间可以形成有导电金属层200。导电金属层200位于相应的接触部123与第二半导体层160之间，可以增加第二半导体层160与电流扩散层120之间的导电性。进一步的，还可以在第二电极连接部远离绝缘基板110的端面形成导电金属层200。
可选的，可以对第二半导体层160远离所述绝缘基底110的表面进行粗糙化或者图形化，在第二半导体层160远离第一半导体层140的表面粗糙化或者具有图形，可以进一步提升半导体发光器件100的光提取率。
进一步的，请参照图3，图3是图2所示的半导体发光器件的表面形成钝化层及电极后的剖面示意图，可以在所述第二半导体层160远离所述第一半导体层140的表面、沟槽161的底部以及电流扩散层120曝露在外面的部分均形成钝化层210。所述钝化层210可以防止第二半导体层160以及电流扩散层120的氧化。在本实施例中，钝化层210可以是直接镀在相应的表面，钝化层210的材料并不作为限制，可以是氧化硅、氮化硅等材料。由于钝化层的折射率介于第二半导体层160与空气之间，还可以有利于提高光提取率。
请参照图3，所述第一电极170形成于所述第一电极连接部121上，所述第二电极180形成于所述第二电极连接部122上。进一步的，第一电极170上可以焊接第一引线171，第二电极180上还可以焊接第二引线181。进一步的，在一种具体实施方式中，可以将第二半导体层160与第一电极连接部121对应的部分蚀刻掉，并在蚀刻掉的部分形成第一电极170。进一步的，在一种具体实施方式中，可以将在第二半导体层160与第二电极连接部122对应的部分蚀刻掉，并在蚀刻掉的部分形成第二电极180。
作为一种具体实施方式，第一电极170可以依次通过第一电极连接部121、靠近第一电极连接部121的平展部124、靠近第一电极连接部121的发光结构层230的第一半导体层140、活性层150以及第二半导体层160、接触部123、靠近第二电极连接部122的平展部124、靠近第二电极连接部122的发光结构层230的第一半导体层140、活性层150以及第二半导体层160、第二电极连接部122，与第二电极180电连接。
在本实施例中，第一电极170与第二电极180都位于活性层150的同一侧，避免传统垂直电极异侧结构封装工艺引入前置电压变大的问题。
当然，可以理解的，在本实施例中，N个沟槽161以及N个接触部123的数量并不作为限制，可以根据实际需求进行设定。例如，如图4及图5所示，图4是本 发明较佳实施例的另一种具体实施方式中半导体发光器件的俯视图，图5是沿图4中B-B线的剖面示意图。在该具体实施方式中，沟槽161可以为两个，接触部123对应的也为两个，两个沟槽161和两个接触部123将第一半导体层140、活性层150以及第二半导体层160分割为3个发光结构层230。图5中的虚线框住的部分表示一个发光结构层230。
可以理解的，沟槽161以及接触部123的数量还可以更多，排列方式也可以不局限于直线型，例如在图6中，沟槽161和接触部123的个数为8个，排列方式为蛇形。也就是说，发光结构层230的数量灵活，设计灵活，发光结构层230的排数、列数可以不限。
可以理解的，第一电极170和第二电极180的位置也可以灵活设置，例如可以如图1所示对称的设置在沟槽161的两侧，分别位于两个侧边的中央，也可以如图7所示，分别设置的沟槽161两侧的对角。
可以理解的是，在有3个以上发光结构层230的结构中，第一电极170和第二电极180的位置也是可以灵活设置的，例如可以如图4所示对称的设置在两个沟槽161的两侧，分别位于两个侧边的中央，也可以设置在对角，还可以如图8所示，设置在垂直于沟槽161的一个侧边的两个顶角处。
请参照图9及图10，图9是本发明另一较佳实施例提供的半导体发光器件的俯视图，图10是沿图9中C-C线的剖面示意图。可以理解的是，于本发明的其他实施方式中，半导体发光器件100B的所述电流扩散层120还可以包括一个或多个与接触部123电连接的第一隧道电极125以及一个或多个与第二电极180电连接的第二隧道电极126，所述第一隧道电极125设置在第一电极连接部121与接触部123之间，所述第二隧道电极126设置在第二电极连接部122与接触部123之间，可以帮助扩散电流。第一隧道电极125和第二隧道电极126可采用手指形状的电极，也可采用其他形状的电极，设计灵活，其数目也不作限制，例如电极的个数可以是一个或者多个，都不受限制。
以图9及图10为例，所述第一隧道电极125可以设置于所述第一电极连接部121与接触部123的中间。第一隧道电极125由电流扩散层120靠近所述绝缘基底110的一侧向远离所述绝缘基底110的一侧凸起，但是未穿过所述第二半导体层160。第一隧道电极125的两侧均设置有绝缘层130，所述第一隧道电极125与所述接触部123电连接。第一隧道电极125靠近所述绝缘基底110的端面与所述绝缘基底110连接，所述第一隧道电极125远离所述绝缘基底110的端面与对应的发光结构层230的第二半导体层160电连接。
所述第二隧道电极126可以设置于所述第二电极连接部122与接触部123的中间。第二隧道电极126由电流扩散层120靠近所述绝缘基底110的一侧向远离所述绝缘基底110的一侧凸起，但是未穿过第二半导体层160，第二隧道电极126的两侧均设置有绝缘层130。第二隧道电极126的两侧均设置有绝缘层130，所述第二隧道电极126与所述第二电极180电连接。第二隧道电极126靠近所述绝缘基底110的端面与所述绝缘基底110连接，所述第二隧道电极126远离所述绝缘基底110的端面与对应的发光结构层230的第二半导体层160电连接。
可以理解的是，在如图4及图5所示的实施方式中，每个发光结构层230也可以增加隧道电极，如图11及图12所示，图11是本发明另一较佳实施例提供的半导体发光器件在再一种具体实施方式中的俯视图，图12是沿图11的D-D线的剖面示意图。隧道电极的具体个数及排列方式不限。采用隧道电极，可以帮助扩散电流。当半导体发光元件的尺寸增大时，采用隧道电极扩散效果更好。
可以理解的是，图9及图10只是关于第一隧道电极125与第二隧道电极126的一种实施方式，在其他实施方式中，第一隧道电极125与第二隧道电极126中的 手指部还可以为多个，可以与沟槽161平行，也可以与沟槽161垂直。例如，可以如图13及图14所示。
同样的，图13及图14只是关于第一隧道电极125与第二隧道电极126的一种实施方式，在其他实施方式中，第一隧道电极125与第二隧道电极126中的手指部还可以为多个，可以与沟槽161平行，也可以与沟槽161垂直，同时，第一电极170和第二电极180也可以设置在不同的位置。例如，可以如图15及图16所示。
图17示出了本发明较佳实施例中所述半导体发光器件100的制造方法的工艺流程图。下面结合图18至图36对该流程图进行详细的说明。所应说明的是，本发明所述的方法并不以图17以及以下所述的具体顺序为限制。应当理解，在其它实施例中，本发明所述的方法其中部分步骤的顺序可以根据实际需要相互交换，或者其中的部分步骤也可以省略或删除。
步骤S301，请同时参照图18，提供半导体发光基层220，所述半导体发光基层220包括第一基底221、依次形成在第一基底221上的所述第二半导体层160、所述活性层150以及所述第一半导体层140。
可以在第一基底221的表面依次生长第二半导体层160、活性层150和第一半导体层140。优选的，第一基底221可以包括第二衬底222以及生长在第二衬底222上的缓冲层223，第二半导体层160、活性层150以及第一半导体层140可以生长在缓冲层223上。
步骤S302，在所述第一半导体层140远离所述第一基底221的表面形成分别对应于图2所述第一电极连接部121、第二电极连接部122以及接触部123的填充槽141，所述填充槽141由所述第一半导体层140远离所述第一基底221的表面向所述第二半导体层160延伸，所述第二半导体层160曝露于所述填充槽141。
具体的，请参照图19，在此步骤中，在所述第一半导体层140远离所述第一基底221的表面刻蚀间隔排列的三个填充槽141，三个填充槽141分别对应图2所示的半导体发光器件中的第一电极连接部121、第二电极连接部122以及接触部123。经过刻蚀后，第二半导体层160由填充槽141处曝露出来。于第二半导体层160的刻蚀深度小于第二半导体层160的厚度。
步骤S303，在每个所述填充槽141的侧壁142以及与所述第一电极连接部121对应的填充槽141的底壁143形成第一绝缘层131。
具体的，请参照图20，可以通过化学气相沉积法(CVD)等方式在第一半导体层140远离第一基底221的表面、每个所述填充槽141的侧壁142以及填充槽141的底壁143形成第一绝缘层131。第一绝缘层131的材料可以是二氧化硅或者氮化硅等绝缘材料，当然，所述第一绝缘层131的材料并不作为限制，也可以是其他。
进一步的，请参照图21，可以通过光刻(photo)、沉积(Depositing)、蚀刻(etching)、等工艺使第一半导体层140远离第一基底221的表面由所述第一绝缘层131曝露出来。
进一步的，请参照图22，可以在第一半导体层140由第一绝缘层131曝露出来的部分形成反射金属层190。该反射金属层190可以使活性层150发出的部分光经反射后从第二半导体层160方向出射。在本实施例中，反射金属层190的材料并不作为限制，可以是银(Ag)、铝(Al)、镍(Ni)等对光有反射作用的金属中一种，或多种金属组成的金属合金或者金属组合层，亦或是合金超晶格结构。
进一步的，请参照图23，将填充槽141的底壁143中，除与所述第一电极连接部121对应的填充槽141的底壁143之外的其他底壁143上的第一绝缘层131刻蚀掉，保留与所述第一电极连接部121对应的填充槽141的底壁143上的第一绝缘层131，为后续制作第一电极170做准备。
可选的，请参照图24，还可以在第一绝缘层131被蚀刻掉的部分形成导电金 属层200，以增加导电性。
步骤S304，在所述第一半导体层140远离所述第二半导体层160的表面形成所述电流扩散层120，所述电流扩散层120包括所述第一电极连接部121、第二电极连接部122以及接触部123的平展部124。
请参照图25，于此步骤中，在第一半导体层140远离第二半导体层160的表面镀上一层电流扩散层120，电流扩散层120填充在与第一电极连接部121对应的填充槽141的部分形成第一电极连接部121，电流扩散层120填充在与第二电极连接部122对应的填充槽141的部分形成第二电极连接部122，电流扩散层120填充在与接触部123对应的填充槽141的部分形成接触部123。连接第一电极连接部121与接触部123、接触部123与第二电极连接部122的是平展部124。电流扩散层120最大厚度大于反射金属层190至填充槽141底部的距离，因此，电流扩散层120远离所述第二半导体层160的表面是平整表面。
步骤S305，对所述电流扩散层120的平展部124蚀刻并形成第二绝缘层132，与所述第一电极连接部121连接的平展部124与所述接触部123之间形成所述第二绝缘层132，与所述接触部123连接的平展部124与所述第二电极连接部122之间形成所述第二绝缘层132。
请参照图26，在此步骤中，可以选择性的电流扩散层120的平展部124刻蚀出图形，然后在所刻蚀的图形中镀上第二绝缘层132。第二绝缘层132起到电阻断的作用，可以对不需要电连通的位置进行电阻断。
步骤S306，在所述电流扩散层120远离所述第二半导体层160的表面形成所述绝缘基底110。
在一种具体实施方式中，请参照图27，可以在电流扩散层120远离第二半导体层160的表面形成绝缘基底层114，然后，在绝缘基底层114上镀第二键合金属层113，如图28所示。
如图29所示，准备镀有第一键合金属层112的第一衬底111，然后将第一键合金属层112键合在第二键合金属层113上，如图30所示。
步骤S307，去除所述第一基底221，在所述第二半导体层160远离所述第一半导体层140的表面形成所述沟槽161，使得所述接触部123曝露于所述沟槽161，所述沟槽161的深度小于所述第二半导体层160的厚度。
请参照图31，图31所示为键合后的整体结构进行翻转后的示意图。接着如图32所示，去掉第一基底221。请参照图33，在第二半导体层160远离第一半导体层140的表面形成沟槽161，使接触部123曝露于沟槽161。优选的，可以将第二半导体层160与第一电极连接部121和第二电极连接部122对应的部分蚀刻掉，以将第一电极连接部121与第二电极连接部122曝露出来，具体的，将第一电极连接部121上的第一绝缘层131以及第二电极连接部122上的金属导电层200曝露出来。
步骤S308，形成所述第一电极170与所述第二电极180，所述第一电极170与所述第一电极连接部121电连接，所述第二电极180与所述第二电极连接部122电连接。
优选的，可以先在对第二半导体层160的表面进行粗糙化或者图形化，形成如图34所示的半导体发光器件100A(图34中以图形化为例进行说明)，在第二半导体层160远离第一半导体层140的表面粗糙化或者具有图形，可以进一步提升半导体发光器件100的光提取率。
进一步的，请参照图35，还可以在所述第二半导体层160远离所述第一半导体层140的表面、沟槽161的底部以及电流扩散层120曝露在外面的部分均可以形成钝化层210。所述钝化层210可以防止第二半导体层160以及电流扩散层120的氧化，并且提高光提取率。
进一步的，请参照图36，可以将第一电极连接部121上的第一绝缘层131蚀刻掉部分后形成与第一电极连接部121电连接的第一电极170。将第二电极连接部122上的金属导电层200及钝化层210蚀刻掉部分后形成与第二电极连接部122电连接的第二电极180，具体的连接方法不限。在一种具体实施方式中，可以在第二半导体层160与第一电极连接部121对应的被蚀刻掉的部分形成第一电极170，在第二半导体层160与第二电极连接部122对应的被蚀刻掉的部分形成第二电极180。
可以理解的是，于本发明的其他实施方式中，在形成填充槽141时，形成分别对应于图12所示的第一隧道电极125以及第二隧道电极126的填充槽141，经过刻蚀后，第二半导体层160由填充槽处曝露出来。与所述第一隧道电极125对应的填充槽141的一端和与所述接触部123对应的填充槽141电连接，与所述第二隧道电极126对应的填充槽141的一端和与所述接触部123对应的填充槽141电连接。在每个填充槽141的侧壁142以及与第一电极连接部121对应的填充槽141的底壁143形成第一绝缘层131。
请参照图37，在形成电流扩散层120时，电流扩散层120填充在与第一隧道电极125及第二隧道电极126对应的填充槽141中，所述第一隧道电极125的一端与所述接触部123电连接，所述第二隧道电极126的一端与所述第二电极180电连接。
请参照图38，在形成第二绝缘层132时，使得第一隧道电极125和第二隧道电极126的两侧均设置有绝缘层130。第一隧道电极125和第二隧道电极126可以帮助扩散电流，其结构可采用手指形状的电极，设计灵活，其中手指部的个数可以是一个或者多个，都不受限制。
综上所述，本发明实施例提供的半导体发光器件及其制造方法，与将多个半导体发光器件进行串并联的高压LED相比，集成密度更高，尺寸更小，且打线少，可靠性高，并且，第一电极170与第二电极180设置于同一侧，避免传统垂直电极异侧结构封装工艺引入前置电压变大的问题。
还需要说明的是，在本发明的描述中，除非另有明确的规定和限定，术语“设置”、“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本发明的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种半导体发光器件，其特征在于，所述半导体发光器件包括：
    绝缘基底；设置在所述绝缘基底上的电流扩散层，所述电流扩散层包括：第一电极连接部，第二电极连接部，位于所述第一电极连接部与所述第二电极连接部之间的N个接触部，以及连接于所述第一电极连接部与所述接触部之间、所述N个接触部之间以及所述第二电极连接部与所述接触部之间的平展部，所述平展部的个数为N+1个，N为自然数；
    对应设置在所述N+1个平展部上的N+1个发光结构层，每个所述发光结构层包括：依次层叠在对应的所述平展部上的第一半导体层、活性层以及第二半导体层，所述第二半导体层远离所述活性层的一面形成有与所述N个接触部配合的至少N个沟槽，所述至少N个沟槽的深度小于所述第二半导体层的厚度，所述至少N个接触部与至少N个所述沟槽相对应；
    以及绝缘层；
    其中，所述第一电极连接部和与其相邻的所述发光结构层的侧面之间设置有所述绝缘层，所述第一电极连接部通过与其相邻的平展部与设置在该平展部上的发光结构层的第一半导体层连接，所述第二电极连接部和与其相邻的所述发光结构层的活性层的侧面、第一半导体层的侧面以及与平展部的侧面之间设置有所述绝缘层，所述第二电极连接部的远离所述绝缘基板的端面的一部分和与其相邻的发光结构层的第二半导体层连接，每个所述接触部与位于所述接触部靠近所述第一电极连接部一侧的发光结构层的活性层的侧面、第一半导体层的侧面以及所述平展部的侧面之间设置有所述绝缘层，与位于所述接触部靠近所述第二电极连接部一侧的发光结构层的侧面之间设置有所述绝缘层，每个所述接触部远离所述绝缘基板的端面与位于该接触部靠近所述第一电极连接部一侧的发光结构层的第二半导体层连接，通过位于该接触部靠近所述第二电极连接部一侧的平展部与该平展部上的第一半导体层连接。
  2. 根据权利要求1所述的半导体发光器件，其特征在于，所述绝缘基底包括第一衬底以及依次层叠在所述第一衬底上的第一键合金属层、第二键合金属层以及绝缘基底层，所述绝缘基底层设置在所述第二键合金属层与所述电流扩散层之间。
  3. 根据权利要求1所述的半导体发光器件，其特征在于，所述半导体发光器件还包括形成于所述第一电极连接部上的第一电极，以及形成于所述第二电极连接部上的第二电极。
  4. 根据权利要求1所述的半导体发光器件，其特征在于，所述第一半导体层与所述电流扩散层之间形成有反射金属层。
  5. 根据权利要求1所述的半导体发光器件，其特征在于，所述至少N个接触部远离所述绝缘基底的端面与所述第二半导体层电连接的部分形成有导电金属层。
  6. 根据权利要求1所述的半导体发光器件，其特征在于，所述第二半导体层远离所述第一半导体层的表面具有图形或者为粗糙表面。
  7. 根据权利要求1所述的半导体发光器件，其特征在于，所述第二半导体层远离所述第一半导体层的表面以及所述凹槽的底部形成有钝化层。
  8. 根据权利要求1所述的半导体发光器件，其特征在于，所述电流扩散层还包括至少一个第一隧道电极以及第二隧道电极，所述第一隧道电极位于所述第一电极连接部与所述接触部之间或者相邻的两个接触部之间，所述第二隧道电极位于所述接触部与所述第二电极连接部之间，所述第一隧道电极与所述第二隧道电极的两侧均设置有所述绝缘层，所述第一隧道电极以及第二隧道电极靠近所述绝缘基底的 端面与所述绝缘基底连接，所述第一隧道电极以及第二隧道电极远离所述绝缘基底的端面与对应的发光结构层的第二半导体层电连接。
  9. 一种制造如权利要求1至8中任一项所述半导体发光器件的制造方法，其特征在于，所述方法包括步骤：
    提供半导体发光基层，所述半导体发光基层包括第一基底、依次形成在第一基底上的所述第二半导体层、所述活性层以及所述第一半导体层；
    在所述第一半导体层远离所述第一基底的表面形成分别对应于所述第一电极连接部、第二电极连接部以及至少N个接触部的填充槽，所述填充槽由所述第一半导体层远离所述第一基底的表面向所述第二半导体层延伸，所述第二半导体层曝露于所述填充槽；
    在每个所述填充槽的侧壁以及与所述第一电极连接部对应的填充槽的底壁形成第一绝缘层；
    在所述第一半导体层远离所述第二半导体层的表面形成所述电流扩散层，所述电流扩散层包括所述第一电极连接部、第二电极连接部、N个接触部以及连接所述第一电极连接部、第二电极连接部以及接触部的平展部；
    对所述电流扩散层的平展部蚀刻并形成第二绝缘层，其中，与所述第一电极连接部连接的平展部与所述接触部之间形成所述第二绝缘层，与所述接触部连接的平展部与所述第二电极连接部之间形成所述第二绝缘层；
    在所述电流扩散层远离所述第二半导体层的表面形成所述绝缘基底；
    去除所述第一基底，在所述第二半导体层远离所述第一半导体层的表面形成所述至少N个沟槽，使得所述至少N个接触部对应的曝露于所述至少N个沟槽。
  10. 如权利要求9所述的方法，其特征在于，在所述第一半导体层远离所述第二半导体层的表面形成所述电流扩散层的步骤之前还包括步骤：
    对所述第一绝缘层进行处理，使所述第一半导体层远离第一基底的表面由所述第一绝缘层曝露出来；
    在所述第一半导体层由所述第一绝缘层曝露出来的部分形成所述反射金属层；
    将所述填充槽的底壁中除与所述第一电极连接部对应的填充槽的底壁之外的其他底壁上的第一绝缘层刻蚀掉，保留与所述第一电极连接部对应的填充槽的底壁上的第一绝缘层。
  11. 如权利要求10所述的方法，其特征在于，在所述第一半导体层远离所述第二半导体层的表面形成所述电流扩散层的步骤之前，还包括步骤：
    在第一绝缘层被蚀刻掉的部分形成所述导电金属层。
  12. 如权利要求11所述的方法，其特征在于，在所述第二半导体层远离所述第一半导体层的表面形成所述至少N个沟槽的步骤之后，还包括步骤：
    对所述第二半导体层远离所述绝缘基底的表面进行粗糙化或者图形化。
  13. 如权利要求12所述的方法，其特征在于，所述方法还包括步骤：
    在所述第二半导体层远离所述第一半导体层的表面、所述沟槽的底部以及所述电流扩散层曝露在外面的部分均形成钝化层。
  14. 如权利要求13所述的方法，其特征在于，在形成所述钝化层的步骤之后，还包括步骤：
    将所述第一电极连接部上的第一绝缘层蚀刻掉部分后形成所述第一电极，所述第一电极与所述第一电极连接部电连接，将第二电极连接部上的金属导电层及钝化层蚀刻掉部分后形成所述第二电极。
PCT/CN2017/078474 2016-03-29 2017-03-28 半导体发光器件及其制造方法 WO2017167189A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/148,989 US10636836B2 (en) 2016-03-29 2018-10-01 Semiconductor light-emitting device and manufacturing method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610187812.0A CN105702821B (zh) 2016-03-29 2016-03-29 半导体发光器件及其制造方法
CN201610187812.0 2016-03-29

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/148,989 Continuation US10636836B2 (en) 2016-03-29 2018-10-01 Semiconductor light-emitting device and manufacturing method therefor

Publications (1)

Publication Number Publication Date
WO2017167189A1 true WO2017167189A1 (zh) 2017-10-05

Family

ID=56231775

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/078474 WO2017167189A1 (zh) 2016-03-29 2017-03-28 半导体发光器件及其制造方法

Country Status (4)

Country Link
US (1) US10636836B2 (zh)
CN (1) CN105702821B (zh)
TW (1) TWI712184B (zh)
WO (1) WO2017167189A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105702821B (zh) * 2016-03-29 2018-01-30 苏州晶湛半导体有限公司 半导体发光器件及其制造方法
CN106409997A (zh) * 2016-11-23 2017-02-15 映瑞光电科技(上海)有限公司 Led芯片及其形成方法
WO2018129696A1 (zh) * 2017-01-12 2018-07-19 苏州晶湛半导体有限公司 半导体器件及其制造方法
CN107768491B (zh) * 2017-10-31 2019-11-22 江苏新广联半导体有限公司 用于手环的MicroLED显示模块制作方法
CN111933771B (zh) * 2018-07-28 2023-02-17 厦门三安光电有限公司 微发光二极管及其显示装置
WO2020155176A1 (zh) * 2019-02-03 2020-08-06 泉州三安半导体科技有限公司 发光装置
CN112713228B (zh) * 2021-03-23 2021-07-06 北京芯海视界三维科技有限公司 发光单元、发光器件及显示器件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102939794A (zh) * 2010-06-10 2013-02-20 欧司朗光电半导体有限公司 发光二极管装置和尤其带有这种发光二极管装置的发光机构
CN103140927A (zh) * 2010-10-11 2013-06-05 奥斯兰姆奥普托半导体有限责任公司 发光二极管芯片
US20130214247A1 (en) * 2012-02-22 2013-08-22 Jianhua Hu Ac led device and its manufacturing process for general lighting applications
CN105702821A (zh) * 2016-03-29 2016-06-22 苏州晶湛半导体有限公司 半导体发光器件及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2733744A1 (en) * 2004-06-30 2014-05-21 Seoul Viosys Co., Ltd Light emitting element comprising a plurality of vertical-type LEDs connected in series on the same carrier substrate
KR101533817B1 (ko) * 2008-12-31 2015-07-09 서울바이오시스 주식회사 복수개의 비극성 발광셀들을 갖는 발광 소자 및 그것을 제조하는 방법
KR100986570B1 (ko) * 2009-08-31 2010-10-07 엘지이노텍 주식회사 반도체 발광소자 및 그 제조방법
TWI533473B (zh) * 2009-12-16 2016-05-11 晶元光電股份有限公司 發光元件及其製造方法
KR101106151B1 (ko) * 2009-12-31 2012-01-20 서울옵토디바이스주식회사 발광 소자 및 그것을 제조하는 방법
US8084775B2 (en) * 2010-03-16 2011-12-27 Bridgelux, Inc. Light sources with serially connected LED segments including current blocking diodes
CN102709423B (zh) * 2012-05-15 2014-12-31 北京工业大学 一种具有电荷输运限制的高压发光二极管
CN102723415A (zh) * 2012-06-25 2012-10-10 钟伟荣 一种倒装型高压交/直流发光二极管及其制作方法
US20140091330A1 (en) * 2012-10-02 2014-04-03 Helio Optoelectronics Corporation Led package structure with transparent electrodes
CN104425537A (zh) * 2013-09-02 2015-03-18 晶元光电股份有限公司 发光二极管元件
CN103715086A (zh) * 2013-12-27 2014-04-09 苏州晶湛半导体有限公司 一种增强型器件的制造方法
JP6302303B2 (ja) * 2014-03-17 2018-03-28 株式会社東芝 半導体発光素子
CN104051522B (zh) * 2014-07-02 2018-05-11 苏州晶湛半导体有限公司 一种增强型氮化物半导体器件及其制造方法
JP6637703B2 (ja) * 2015-09-10 2020-01-29 アルパッド株式会社 半導体発光装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102939794A (zh) * 2010-06-10 2013-02-20 欧司朗光电半导体有限公司 发光二极管装置和尤其带有这种发光二极管装置的发光机构
CN103140927A (zh) * 2010-10-11 2013-06-05 奥斯兰姆奥普托半导体有限责任公司 发光二极管芯片
US20130214247A1 (en) * 2012-02-22 2013-08-22 Jianhua Hu Ac led device and its manufacturing process for general lighting applications
CN105702821A (zh) * 2016-03-29 2016-06-22 苏州晶湛半导体有限公司 半导体发光器件及其制造方法

Also Published As

Publication number Publication date
TWI712184B (zh) 2020-12-01
CN105702821B (zh) 2018-01-30
US20190035845A1 (en) 2019-01-31
CN105702821A (zh) 2016-06-22
US10636836B2 (en) 2020-04-28
TW201810720A (zh) 2018-03-16

Similar Documents

Publication Publication Date Title
WO2017167189A1 (zh) 半导体发光器件及其制造方法
JP6485019B2 (ja) 半導体発光素子
JP5304563B2 (ja) Ｉｉｉ族窒化物半導体発光素子
KR20120107874A (ko) 발광 다이오드 패키지 및 그의 제조 방법
JP5056799B2 (ja) Ｉｉｉ族窒化物半導体発光素子およびその製造方法
JP2011029612A (ja) Ｉｉｉ族窒化物半導体発光素子
KR102588170B1 (ko) 다층 구조의 반사막을 구비한 반도체 발광 소자
JPWO2013161208A1 (ja) 発光素子
KR20140006485A (ko) 멀티셀 어레이를 갖는 반도체 발광장치 및 그 제조 방법
JP2011198997A (ja) Ｉｉｉ族窒化物半導体発光素子
CN108040503A (zh) 发光元件和具有该发光元件的发光元件封装
US9698305B2 (en) High voltage LED flip chip
CN113169253A (zh) 微型发光二极管以及微型发光二极管的制造方法
KR102477250B1 (ko) 발광 소자
US20210336090A1 (en) Light-emitting device and manufacturing method thereof
CN112750931B (zh) 微发光二极管、微发光二极管阵列基板及其制作方法
KR102075059B1 (ko) 발광 소자 및 발광 소자 패키지
KR100891800B1 (ko) 발광소자 어레이 제조방법 및 발광소자 어레이
CN106159045A (zh) 倒装led芯片及其制造方法
TWI779378B (zh) 微型發光二極體
US10868216B2 (en) Display devices, light emitting diode chips and methods for manufacturing the same
US20230154902A1 (en) Semiconductor structure and manufacturing method therefor
KR102619665B1 (ko) 발광 장치
CN116960249A (zh) 发光二极管及发光装置
CN116960250A (zh) 发光二极管及发光装置

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17773219

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 17773219

Country of ref document: EP

Kind code of ref document: A1