WO2020019364A1 - 薄膜晶体管的制备方法 - Google Patents

薄膜晶体管的制备方法 Download PDF

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WO2020019364A1
WO2020019364A1 PCT/CN2018/098269 CN2018098269W WO2020019364A1 WO 2020019364 A1 WO2020019364 A1 WO 2020019364A1 CN 2018098269 W CN2018098269 W CN 2018098269W WO 2020019364 A1 WO2020019364 A1 WO 2020019364A1
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layer
film
ohmic contact
passivation
gate
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PCT/CN2018/098269
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English (en)
French (fr)
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谢华飞
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/080,620 priority Critical patent/US11121228B2/en
Publication of WO2020019364A1 publication Critical patent/WO2020019364A1/zh

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Definitions

  • the invention relates to the technical field of semiconductor manufacturing, and in particular, to a method for manufacturing a thin film transistor.
  • a high-concentration doped conductive layer is usually patterned with a dry etch, the dry etch will affect graphene, carbon nanotubes,
  • the active layer of semiconductor materials such as silicon carbide causes damage, so it is of great significance to develop a transistor fabrication process that protects new semiconductor materials.
  • the present invention provides a method for manufacturing a thin film transistor, which can avoid damage to the active layer by dry etching and improve the performance of the transistor.
  • a method for preparing a thin film transistor includes:
  • the etch stop layer is removed by a wet etching process.
  • fabricating a gate on the substrate specifically includes:
  • the conductive thin film not covered by the first photoresist pattern is removed by wet etching and elution with an acid solution to obtain a patterned gate.
  • the conductive film is ITO, Mo / Al, Ti / Cu, Cr / Au, or Ag.
  • making an etch stop layer on the active layer specifically includes:
  • the etching stopper film not covered by the second photoresist pattern is removed by wet etching and elution with an acid solution to obtain a patterned etching stopper layer.
  • the etching stopper film is ITO (Indium Tin Oxide), Mo / Al, Ti / Cu, metal oxide, or Ag.
  • the ohmic contact layer film is phosphorus-doped silicon, boron-doped silicon, arsenic-doped silicon, nitrogen-doped silicon, or aluminum-doped silicon.
  • the method for manufacturing a thin film transistor further includes: after removing the etching stop layer, forming a passivation layer in a channel region between the source electrode and the drain electrode.
  • making the passivation layer specifically includes:
  • the passivation protection film is patterned, and only the passivation protection film that is directly opposite to the gate electrode is retained to obtain a passivation layer.
  • the passivation protection film is an organic insulating material, SiN x , SiO 2 , HfO 2, or Al 2 O 3 .
  • the thin film transistor of the present invention is provided with an etch barrier layer above the transistor channel before the ohmic contact layer is manufactured, which can effectively prevent the dry etched ohmic contact layer from damaging the active layer and improve the electrical performance of the transistor.
  • the photomask used to make the etch stop layer can be used as the photomask for making the passivation layer, which realizes the reuse of the photomask and saves the cost of designing an additional photomask.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention
  • 3a to 3l are schematic structural diagrams of each step of a thin film transistor manufacturing process according to an embodiment of the present invention.
  • a thin film transistor mainly includes a substrate 10, a gate 20, a gate insulating layer 30, an active layer 40, an ohmic contact layer 60, and a source on the ohmic contact layer 60 which are sequentially formed on the substrate 10. ⁇ 71 ⁇ ticle 72.
  • the ohmic contact layer 60 is located between the active layer 40 and the source 71 / drain 72, and the upper and lower surfaces are in contact with the active layer 40 and the source 71 / drain 72, respectively, which can effectively reduce the active layer 40 and the source 71,
  • the contact resistance between the drains 72 is beneficial to improve the electrical performance of the transistor.
  • the substrate 10 may be made of materials such as PI (Polyimide), PET (Polyethylene terephthalate), quartz, SiO 2 , and glass
  • the gate 20 may be made of ITO, made of Mo / Al, Ti / Cu, Cr / Au, Ag and other materials
  • a gate insulating layer 30 may be used an organic insulating material, SiN x, SiO 2, is made of HfO 2, Al 2 O 3 and other materials
  • the active layer 40 can be made of graphene, SiC, MoS 2 , organic semiconductors, carbon nanotubes and other materials.
  • the ohmic contact layer 60 is a doped conductive layer.
  • Phosphorus-doped silicon, boron-doped silicon, arsenic-doped silicon, and nitrogen can be used.
  • the doped silicon, aluminum doped silicon, and other materials are used.
  • the source 71 and the drain 72 may be ITO, Mo / Al, Ti / Cu, Cr / Au, Ag, or the like.
  • a passivation layer 80 may also be formed in the channel region between the source 71 and the drain 72 on the ohmic contact layer 60.
  • the passivation layer 80 fills the channel and plays a certain role in the bottom active layer 40. Protective effects.
  • the passivation layer 80 may be formed of an organic insulating material, SiN x , SiO 2 , HfO 2 , Al 2 O 3, or the like.
  • this embodiment provides a method for preparing a thin film transistor, which mainly includes:
  • a substrate 10 is provided.
  • the substrate 10 can be made of materials such as PI, PET, quartz, SiO 2 and glass;
  • S02, a gate 20, a gate insulating layer 30, and an active layer 40 are sequentially formed on the substrate 10 (as shown in Figs. 3a, 3b, and 3c);
  • the process of fabricating the gate 20 on the substrate 10 specifically includes:
  • the conductive film may be ITO, Mo / Al, Ti / Cu, Cr / Au or Ag;
  • the unexposed photoresist is removed, leaving only the photocured photoresist to form the first photoresist pattern, and then wet-etched and eluted with an acid
  • the remaining conductive thin film material not covered by the photoresist pattern is removed by a photolithography process to obtain a patterned gate electrode 20.
  • the process of manufacturing the gate insulating layer 30 on the substrate 10 specifically includes: after cleaning the substrate 10 after the gate 20 is manufactured, the surface of the substrate 10 is further subjected to atomic layer deposition (ALD) or chemical vapor deposition (CVD) to prepare the entire surface A gate insulating layer 30 that covers the substrate 10 and the gate 20 at the same time.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the process of making the active layer 40 on the substrate 10 specifically includes: after cleaning the substrate 10 on which the gate insulating layer 30 has been prepared, manufacturing a semiconductor thin film by a solution process or a transfer process, and then coating a photoresist on the surface of the semiconductor thin film The photoresist is exposed and developed to remove the residual photoresist to form a patterned photoresist. Then, the semiconductor thin film is subjected to plasma dry etching, and the residual semiconductor thin film material is eluted to pattern the semiconductor thin film to obtain a channel active. Layer 40.
  • An etch stop layer 50 is formed on the active layer 40 that has the same pattern as the gate electrode 20 and is opposite to the pattern of the gate electrode 20 (see FIGS. 3d and 3e).
  • making the etch stop layer 50 on the active layer 40 specifically includes:
  • the entire surface of the etch stop layer film 5 is deposited on the active layer 40 by physical vapor deposition (PVD) or evaporation, and the etch stop layer film 5 is a metal or metal oxide film, such as ITO, Mo / Al, Ti / Cu, metal oxide or Ag;
  • a second photoresist pattern is obtained, and an etching barrier film not covered by the second photoresist pattern is removed by a photolithography process such as wet etching and elution of an acid solution. 5.
  • a patterned etch stop layer 50 is obtained. After the etch stop layer 50 is manufactured, it can be used to protect the underlying active layer 40 to avoid damage to specific areas of the active layer in subsequent processing processes.
  • the ohmic contact layer film 6 is phosphorus-doped silicon, boron-doped silicon, arsenic-doped silicon, nitrogen-doped silicon, or aluminum-doped silicon.
  • CVD chemical vapor deposition
  • the ohmic contact layer thin film 6 is prepared by a method, and the source and drain conductive films 7 are ITO, Mo / Al, Ti / Cu, Cr / Au, Ag, etc., and are deposited on the substrate 10 by physical vapor deposition (PVD) or evaporation. .
  • the source and drain conductive film 7 is processed by a wet etching process to form a patterned source 71 and drain 72 (as shown in FIG. 3h).
  • the source and drain conductive film 7 is coated on the surface first.
  • the photoresist is patterned by exposing and developing the photoresist, and then wet-etching the source-drain conductive film 7 through the patterned photoresist, and the source-drain conductive film blocked by the photoresist.
  • the material is protected, and the source and drain conductive film materials that are not covered by the photoresist pattern are exposed and etched and removed, and then the remaining materials are dried to form patterned source 71 and drain 72;
  • the ohmic contact layer film 6 is processed by a dry etching process to form a patterned ohmic contact layer 60 to remove the ohmic contact layer film 6 in the channel region between the source 71 and the drain 72 (see FIG. 3i). ;
  • the ohmic contact layer film 6 under the source-drain conductive film 7 is dry-etched by plasma, so that the ohmic contact layer film under the channel region between the source 71 and the drain 72 is penetrated to expose the etching barrier below.
  • the layer 50 is then washed to remove the remaining ohmic contact layer film material. It is precisely because the etch stop layer 50 is located above the active layer 40 opposite to the channel region between the source 71 and the drain 72.
  • the etch stop layer 50 The layer 50 can be used as a protection layer to avoid damage to the active layer 40 by the dry etching process.
  • a passivation layer 80 is formed in the channel region between the source 71 and the drain 72 on the ohmic contact layer 60 (as shown in FIGS. 3k and 3l), so that the passivation layer 80 is opposed to the active layer 40 below the channel. Cover protection is performed.
  • the steps of manufacturing the passivation layer 80 include:
  • Atomic layer deposition or chemical vapor deposition (CVD) is used to prepare the entire passivation protective film 8 on the surface of the source 71, the drain 72, and the active layer 40;
  • the passivation protection film 8 is patterned, and only the passivation protection film 8 opposite to the gate electrode 20 is retained to obtain a passivation layer.
  • the passivation protection film 8 is an organic insulating material, SiN x , SiO 2 , HfO. 2 or Al 2 O 3 .
  • the pattern of the passivation layer 80 is the same as the pattern of the etch stop layer 50, and the two can share the same photomask, which realizes the reuse of the photomask, thus saving one time of the photomask. Design and production costs.
  • the thin film transistor of the present invention is provided with an etching barrier layer above the transistor channel before the ohmic contact layer is manufactured, which can effectively prevent the dry etched ohmic contact layer from damaging the active layer and improve the electrical performance of the transistor;
  • the photomask used to make the etch stop layer can be used as the photomask for the passivation layer, which realizes the reuse of the photomask and saves the cost of additional photomask design.

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Abstract

本发明公开了一种薄膜晶体管的制备方法，包括：在基板上依次制作栅极、栅极绝缘层、有源层；在有源层上制作蚀刻阻挡层；在蚀刻阻挡层及有源层上沉积欧姆接触层薄膜，及在欧姆接触层薄膜上沉积源漏极导电膜；处理源漏极导电膜形成图形化的源极、漏极，通过干法刻蚀工艺处理欧姆接触层薄膜形成图形化的欧姆接触层；欧姆接触层制作完成后，去除蚀刻阻挡层。由于本发明在欧姆接触层制作之前在晶体管沟道上方设置有蚀刻阻挡层，可以有效避免干刻欧姆接触层对于有源层的损伤，提高了晶体管的性能。

Description

薄膜晶体管的制备方法 技术领域
本发明涉及半导体制备技术领域，尤其涉及一种薄膜晶体管的制备方法。
背景技术
石墨烯、碳纳米管、碳化硅、二硫化钼、有机化合物等新型半导体材料的发现为晶体管的制备提供了新的研究方向。然而这些半导体材料都具有一个共同的特征，在制备晶体管的时候，通过干刻来进行图形化得到有源层，但以传统非晶硅工艺为例，在有源层与源漏极之间需加入高浓度掺杂的导电层以减少有源层与金属层的接触电阻形成欧姆接触，由于高浓度掺杂导电层通常以干刻进行图形化，而干刻会对石墨烯、碳纳米管、碳化硅等半导体材料有源层造成损伤，因此开发一种保护新型半导体材料的晶体管制备工艺具有非常重要的意义。
发明内容
鉴于现有技术存在的不足，本发明提供了一种薄膜晶体管的制备方法，可以避免干刻对于有源层的损伤，提高了晶体管的性能。
为了实现上述的目的，本发明采用了如下的技术方案：
一种薄膜晶体管的制备方法，包括：
提供一基板；
在所述基板上依次制作栅极、栅极绝缘层、有源层；
在所述有源层上制作一层与所述栅极图案相同并与所述栅极的图案正对的蚀刻阻挡层；
在所述蚀刻阻挡层及有源层上沉积欧姆接触层薄膜，及在所述欧姆接触层薄膜上沉积源漏极导电膜；
通过湿法刻蚀工艺处理所述源漏极导电膜形成图形化的源极、漏极；
通过干法刻蚀工艺处理所述欧姆接触层薄膜形成图形化的欧姆接触层，以去除位于所述源极、所述漏极之间的沟道区域的所述欧姆接触层薄膜；
通过湿法刻蚀工艺去除所述蚀刻阻挡层。
作为其中一种实施方式，在所述基板上制作栅极，具体包括：
在所述基板上沉积整面覆盖的导电薄膜；
在所述导电薄膜上沉积第一光刻胶薄膜；
对所述第一光刻胶薄膜进行曝光、显影，得到第一光刻胶图案；
利用酸液湿刻、洗脱去除未被所述第一光刻胶图案覆盖的所述导电薄膜，得到图形化的栅极。
作为其中一种实施方式，所述导电薄膜为ITO、Mo/Al、Ti/Cu、Cr/Au或Ag。
作为其中一种实施方式，在所述有源层上制作蚀刻阻挡层，具体包括：
在所述有源层上沉积整面覆盖的蚀刻阻挡层薄膜；
在所述蚀刻阻挡层薄膜上沉积第二光刻胶薄膜；
对所述第二光刻胶薄膜进行曝光、显影，得到第二光刻胶图案；
利用酸液湿刻、洗脱去除未被所述第二光刻胶图案覆盖的蚀刻阻挡层薄膜，得到图形化的蚀刻阻挡层。
作为其中一种实施方式，所述蚀刻阻挡层薄膜为ITO(氧化铟锡)、Mo/Al、Ti/Cu、金属氧化物或Ag。
作为其中一种实施方式，所述欧姆接触层薄膜为磷掺杂硅、硼掺杂硅、砷掺杂硅、氮掺杂硅或铝掺杂硅。
作为其中一种实施方式，所述的薄膜晶体管的制备方法还包括：在去除所述蚀刻阻挡层后，在所述源极、所述漏极之间的沟道区域内制作钝化层。
作为其中一种实施方式，制作钝化层具体包括：
以原子层沉积或化学气相沉积在所述源极、所述漏极、所述有源层表面制备整面的钝化保护膜；
对所述钝化保护膜图形化处理，仅保留与所述栅极正对的所述钝化保护膜， 得到钝化层。
作为其中一种实施方式，所述钝化保护膜为有机绝缘材料、SiN x、SiO 2、HfO 2或Al 2O 3。
本发明的薄膜晶体管在欧姆接触层制作之前在晶体管沟道上方设置有蚀刻阻挡层，能有效避免干刻欧姆接触层对于有源层的损伤，提高了晶体管的电学性能。同时，在制作钝化层的过程中，可以将原本制作蚀刻阻挡层的光罩作为制作钝化层的光罩，实现了光罩的重复利用，也节省了额外设计光罩的成本。
附图说明
图1为本发明实施例的薄膜晶体管的结构示意图；
图2为本发明实施例的薄膜晶体管的制备方法流程图；
图3a～3l为本发明实施例的薄膜晶体管的制程的各步骤执行后的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
参阅图1，本发明实施例的薄膜晶体管主要包括基板10、依次形成在基板10上方的栅极20、栅极绝缘层30、有源层40、欧姆接触层60以及欧姆接触层60上的源极71、漏极72。
欧姆接触层60位于有源层40与源极71/漏极72之间，上下表面分别与有源层40、源极71/漏极72接触，可有效降低有源层40与源极71、漏极72之间的接触电阻，有利于提高晶体管电学性能。其中，基板10可以采用PI(Polyimide，聚酰亚胺)、PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)、石英、SiO 2、玻璃等材料制成，栅极20可以采用ITO、Mo/Al、Ti/Cu、Cr/Au、Ag等材料制成，栅极绝缘层30可以采用有机绝缘材料、SiN x、SiO 2、HfO 2、Al 2O 3等材料制成，有源层40可以采用石墨烯、SiC、MoS 2、有机半导体、碳纳米管等材料制成，欧姆接触层60为掺杂导电层，可以采用磷掺杂硅、硼掺杂硅、砷掺杂硅、氮掺杂硅、铝掺杂硅等材料制成，源极71、漏极72可以是ITO、Mo/Al、Ti/Cu、Cr/Au、Ag等。
在欧姆接触层60上的源极71、漏极72之间的沟道区域内还可以制作有钝化层80，钝化层80填充在沟道内，对底部的有源层40起到一定的保护作用。钝化层80可以采用有机绝缘材料、SiN x、SiO 2、HfO 2、Al 2O 3等材料形成。
如图2～图3l，本实施例提供了一种薄膜晶体管的制备方法，主要包括：
S01、提供一基板10，该基板10可以采用PI、PET、石英、SiO 2、玻璃等材料制成；
S02、在基板10上依次制作栅极20、栅极绝缘层30、有源层40(如图3a、3b、3c)；
其中，在基板10上制作栅极20的过程具体包括：
清洗基板10，并以物理气相沉积(PVD)或蒸镀的方式在基板10上沉积整面覆盖的导电薄膜；
在导电薄膜上沉积形成第一光刻胶薄膜，该导电薄膜可以为ITO、Mo/Al、Ti/Cu、Cr/Au或Ag；
对第一光刻胶薄膜进行曝光、显影后，未被曝光的光刻胶被去除，仅留下光照固化的光刻胶，形成第一光刻胶图案，然后利用酸液湿刻、洗脱等光刻工艺去除未被光刻胶图案覆盖的残留的导电薄膜材料，得到图形化的栅极20。
在基板10上制作栅极绝缘层30的过程具体包括：对栅极20制作后的基板10清洗后，继续在基板10表面进行原子层沉积(ALD)或化学气相沉积(CVD)制备整面的栅极绝缘层30，该栅极绝缘层30同时覆盖基板10和栅极20。
在基板10上制作有源层40的过程具体包括：对制作好栅极绝缘层30的基板10清洗后，以溶液制程或转印工艺制作半导体薄膜，然后通过在半导体薄膜表面涂布光刻胶，利用光罩曝光、显影以去除残留光刻胶，形成图案化的光刻胶，再对半导体薄膜进行等离子体干刻、洗脱残留半导体薄膜材料后使半导体薄膜图形化，得到沟道有源层40。
S03、在有源层40上制作一层与栅极20图案相同并与栅极20的图案正对的蚀刻阻挡层50(如图3d、3e)；
其中，在有源层40上制作蚀刻阻挡层50具体包括：
以物理气相沉积(PVD)或蒸镀等方式在有源层40上沉积整面覆盖的蚀刻 阻挡层薄膜5，该蚀刻阻挡层薄膜5为金属或金属氧化物膜，例如ITO、Mo/Al、Ti/Cu、金属氧化物或Ag；
在蚀刻阻挡层薄膜5上沉积第二光刻胶薄膜；
对第二光刻胶薄膜进行曝光、显影后，得到第二光刻胶图案，利用酸液湿刻、洗脱等光刻工艺去除未被所述第二光刻胶图案覆盖的蚀刻阻挡层薄膜5，得到图形化的蚀刻阻挡层50，蚀刻阻挡层50制作完成后，可以用来保护下方的有源层40，避免后续制程工艺对有源层的特定区域造成损害。
S04、在有源层40和蚀刻阻挡层50表面沉积欧姆接触层薄膜6(如图3f)，并在欧姆接触层薄膜6表面沉积源漏极导电膜7(如图3g)；
作为其中一种实施方式，欧姆接触层薄膜6为磷掺杂硅、硼掺杂硅、砷掺杂硅、氮掺杂硅或铝掺杂硅，上述步骤S04中，采用化学气相沉积(CVD)法制备欧姆接触层薄膜6，源漏极导电膜7为ITO、Mo/Al、Ti/Cu、Cr/Au、Ag等，以物理气相沉积(PVD)或蒸镀的方式在基板10上沉积形成。
S05、通过湿法刻蚀工艺处理源漏极导电膜7形成图形化的源极71、漏极72(如图3h)，本实施例中，具体是先在源漏极导电膜7表面涂布光刻胶，通过对光刻胶曝光、显影后形成使其图案化，然后透过图案化的光刻胶对源漏极导电膜7酸液湿刻，被光刻胶遮挡的源漏导电膜材料受到保护，而未被光刻胶图案遮挡的源漏极导电膜材料则裸露而被腐蚀、去除，然后对剩余材料进行干燥后，即可形成图案化的源极71、漏极72；
S06、通过干法刻蚀工艺处理欧姆接触层薄膜6形成图形化的欧姆接触层60，以去除位于源极71、漏极72之间的沟道区域的欧姆接触层薄膜6(如图3i)；
该步骤具体是用等离子体干刻源漏极导电膜7下方的欧姆接触层薄膜6，使得源极71、漏极72之间的沟道区域下方的欧姆接触层薄膜贯穿，露出下方的蚀刻阻挡层50，然后清洗，去除残留的欧姆接触层薄膜材料。正是由于蚀刻阻挡层50位于源极71、漏极72之间的沟道区域正对的有源层40上方，当对沟道区域下方的欧姆接触层薄膜进行干刻的过程中，蚀刻阻挡层50可以作为保护层，避免了干刻工艺对于有源层40的损伤。
S07、通过湿法刻蚀工艺，利用酸液去除蚀刻阻挡层50(如图3j)，露出沟道内的有源层40；
S08、在欧姆接触层60上的源极71、漏极72之间的沟道区域内制作钝化层 80(如图3k、3l)，使得钝化层80对沟道下方的有源层40进行覆盖保护，其中，制作钝化层80的步骤具体包括：
以原子层沉积(ALD)或化学气相沉积(CVD)在源极71、漏极72、有源层40表面制备整面的钝化保护膜8；
对钝化保护膜8图形化处理，仅保留与栅极20正对的钝化保护膜8，得到钝化层，这里，该钝化保护膜8为有机绝缘材料、SiN x、SiO 2、HfO 2或Al 2O 3。
在制作钝化层80的过程中，其钝化层80的图案与蚀刻阻挡层50的图案一致，二者可以共用同一个光罩，实现了光罩的重复利用，因此可以节省一次光罩的设计和制作成本。
本发明的薄膜晶体管在欧姆接触层制作之前在晶体管沟道上方设置有蚀刻阻挡层，能有效避免干刻欧姆接触层对有源层的损伤，提高了晶体管的电学性能；同时，在制作钝化层的过程中，可以将原本制作蚀刻阻挡层的光罩作为制作钝化层的光罩，实现了光罩的重复利用，也节省了额外设计光罩的成本。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (19)

  1. 一种薄膜晶体管的制备方法，其中，包括：
    提供一基板；
    在所述基板上依次制作栅极、栅极绝缘层、有源层；
    在所述有源层上制作一层与所述栅极图案相同并与所述栅极的图案正对的蚀刻阻挡层；
    在所述蚀刻阻挡层及所述有源层上沉积欧姆接触层薄膜，及在所述欧姆接触层薄膜上沉积源漏极导电膜；
    通过湿法刻蚀工艺处理所述源漏极导电膜形成图形化的源极、漏极；
    通过干法刻蚀工艺处理所述欧姆接触层薄膜形成图形化的欧姆接触层，以去除位于所述源极、所述漏极之间的沟道区域的所述欧姆接触层薄膜；
    通过湿法刻蚀工艺去除所述蚀刻阻挡层。
  2. 根据权利要求1所述的薄膜晶体管的制备方法，其中，在所述基板上制作栅极，具体包括：
    在所述基板上沉积整面覆盖的导电薄膜；
    在所述导电薄膜上沉积第一光刻胶薄膜；
    对所述第一光刻胶薄膜进行曝光、显影，得到第一光刻胶图案；
    利用酸液湿刻、洗脱去除未被所述第一光刻胶图案覆盖的所述导电薄膜，得到图形化的栅极。
  3. 根据权利要求2所述的薄膜晶体管的制备方法，其中，所述导电薄膜为ITO、Mo/Al、Ti/Cu、Cr/Au或Ag。
  4. 根据权利要求1所述的薄膜晶体管的制备方法，其中，在所述有源层上制作蚀刻阻挡层，具体包括：
    在所述有源层上沉积整面覆盖的蚀刻阻挡层薄膜；
    在所述蚀刻阻挡层薄膜上沉积第二光刻胶薄膜；
    对所述第二光刻胶薄膜进行曝光、显影，得到第二光刻胶图案；
    利用酸液湿刻、洗脱去除未被所述第二光刻胶图案覆盖的蚀刻阻挡层薄膜，得到图形化的蚀刻阻挡层。
  5. 根据权利要求4所述的薄膜晶体管的制备方法，其中，所述蚀刻阻挡层薄膜为ITO、Mo/Al、Ti/Cu、金属氧化物或Ag。
  6. 根据权利要求1所述的薄膜晶体管的制备方法，其中，所述欧姆接触层薄膜为磷掺杂硅、硼掺杂硅、砷掺杂硅、氮掺杂硅或铝掺杂硅。
  7. 根据权利要求1所述的薄膜晶体管的制备方法，其中，还包括：在去除所述蚀刻阻挡层后，在所述源极、所述漏极之间的沟道区域内制作钝化层。
  8. 根据权利要求7所述的薄膜晶体管的制备方法，其中，制作钝化层具体包括：
    以原子层沉积或化学气相沉积在所述源极、所述漏极、所述有源层表面制备整面的钝化保护膜；
    对所述钝化保护膜图形化处理，仅保留与所述栅极正对的所述钝化保护膜，得到钝化层。
  9. 根据权利要求8所述的薄膜晶体管的制备方法，其中，所述钝化保护膜为有机绝缘材料、SiN x、SiO 2、HfO 2或Al 2O 3。
  10. 根据权利要求2所述的薄膜晶体管的制备方法，其中，还包括：在去除所述蚀刻阻挡层后，在所述源极、所述漏极之间的沟道区域内制作钝化层。
  11. 根据权利要求10所述的薄膜晶体管的制备方法，其中，制作钝化层具体包括：
    以原子层沉积或化学气相沉积在所述源极、所述漏极、所述有源层表面制备整面的钝化保护膜；
    对所述钝化保护膜图形化处理，仅保留与所述栅极正对的所述钝化保护膜，得到钝化层。
  12. 根据权利要求11所述的薄膜晶体管的制备方法，其中，所述钝化保护膜为有机绝缘材料、SiN x、SiO 2、HfO 2或Al 2O 3。
  13. 根据权利要求3所述的薄膜晶体管的制备方法，其中，还包括：在去 除所述蚀刻阻挡层后，在所述源极、所述漏极之间的沟道区域内制作钝化层。
  14. 根据权利要求13所述的薄膜晶体管的制备方法，其中，制作钝化层具体包括：
    以原子层沉积或化学气相沉积在所述源极、所述漏极、所述有源层表面制备整面的钝化保护膜；
    对所述钝化保护膜图形化处理，仅保留与所述栅极正对的所述钝化保护膜，得到钝化层。
  15. 根据权利要求14所述的薄膜晶体管的制备方法，其中，所述钝化保护膜为有机绝缘材料、SiN x、SiO 2、HfO 2或Al 2O 3。
  16. 根据权利要求4所述的薄膜晶体管的制备方法，其中，还包括：在去除所述蚀刻阻挡层后，在所述源极、所述漏极之间的沟道区域内制作钝化层。
  17. 根据权利要求16所述的薄膜晶体管的制备方法，其中，制作钝化层具体包括：
    以原子层沉积或化学气相沉积在所述源极、所述漏极、所述有源层表面制备整面的钝化保护膜；
    对所述钝化保护膜图形化处理，仅保留与所述栅极正对的所述钝化保护膜，得到钝化层。
  18. 根据权利要求17所述的薄膜晶体管的制备方法，其中，所述钝化保护膜为有机绝缘材料、SiN x、SiO 2、HfO 2或Al 2O 3。
  19. 一种薄膜晶体管的制备方法，其中，包括：
    提供一基板；
    在所述基板上依次制作栅极、栅极绝缘层、有源层，在所述基板上制作栅极，具体包括：
    在所述基板上沉积整面覆盖的导电薄膜；
    在所述导电薄膜上沉积第一光刻胶薄膜；
    对所述第一光刻胶薄膜进行曝光、显影，得到第一光刻胶图案；
    利用酸液湿刻、洗脱去除未被所述第一光刻胶图案覆盖的所述导电薄 膜，得到图形化的栅极；
    在所述有源层上制作一层与所述栅极图案相同并与所述栅极的图案正对的蚀刻阻挡层，具体包括：
    在所述有源层上沉积整面覆盖的蚀刻阻挡层薄膜；
    在所述蚀刻阻挡层薄膜上沉积第二光刻胶薄膜；
    对所述第二光刻胶薄膜进行曝光、显影，得到第二光刻胶图案；
    利用酸液湿刻、洗脱去除未被所述第二光刻胶图案覆盖的蚀刻阻挡层薄膜，得到图形化的蚀刻阻挡层；
    在所述蚀刻阻挡层及所述有源层上沉积欧姆接触层薄膜，及在所述欧姆接触层薄膜上沉积源漏极导电膜；
    通过湿法刻蚀工艺处理所述源漏极导电膜形成图形化的源极、漏极；
    通过干法刻蚀工艺处理所述欧姆接触层薄膜形成图形化的欧姆接触层，以去除位于所述源极、所述漏极之间的沟道区域的所述欧姆接触层薄膜；
    通过湿法刻蚀工艺去除所述蚀刻阻挡层。
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