WO2019237809A1 - 子像素电路、像素电路及其驱动方法、显示模组和显示装置 - Google Patents

子像素电路、像素电路及其驱动方法、显示模组和显示装置 Download PDF

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Publication number
WO2019237809A1
WO2019237809A1 PCT/CN2019/082199 CN2019082199W WO2019237809A1 WO 2019237809 A1 WO2019237809 A1 WO 2019237809A1 CN 2019082199 W CN2019082199 W CN 2019082199W WO 2019237809 A1 WO2019237809 A1 WO 2019237809A1
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Prior art keywords
control
circuit
light
terminal
light emission
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PCT/CN2019/082199
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English (en)
French (fr)
Inventor
岳晗
玄明花
丛宁
张粲
王灿
赵德涛
陈小川
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京东方科技集团股份有限公司
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Priority to US16/612,887 priority Critical patent/US11335241B2/en
Publication of WO2019237809A1 publication Critical patent/WO2019237809A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a sub-pixel circuit, a pixel circuit and a driving method thereof, a display module, and a display device.
  • MicroLED microwave-light-emitting diode
  • its luminous efficiency will decrease as the current density decreases at low current density.
  • Different gray-scale displays are achieved by driving light-emitting elements with different current densities and emitting light of different brightness.
  • An object of the present disclosure is to provide a sub-pixel circuit, a pixel circuit and a driving method thereof, a display module, and a display device.
  • the present disclosure provides a sub-pixel circuit.
  • the sub-pixel circuit includes a data voltage writing circuit, a driving circuit, a storage circuit, a light emitting time control circuit, a light emitting control circuit, and a light emitting element, wherein the data voltage writing circuit, the voltage writing control terminal, and a first data signal.
  • the terminal is connected to the control terminal of the driving circuit, and is used for writing data voltage from the first data signal terminal to the control of the driving circuit in the data voltage writing stage under the control of the voltage writing control terminal.
  • the light-emitting time control circuit is connected to the light-emitting time control terminal, the second data signal terminal, and the control terminal of the light-emitting control circuit, and is configured to emit light during the light-emitting time control stage under the control of the light-emitting time control terminal.
  • a control signal is written from the second data signal terminal to the control terminal of the light-emitting control circuit; a first terminal of the driving circuit is connected to a first voltage input terminal, and a second terminal of the driving circuit is connected to the light-emitting control.
  • the first end of the circuit is connected, and the second end of the light-emitting control circuit is connected to the first pole of the light-emitting element, and the second pole of the light-emitting element is connected to the second electrode.
  • the input end is connected; the first end of the storage circuit is connected to the control end of the driving circuit, the second end of the storage circuit is connected to the first voltage input end, and the storage circuit is used to control the driving The potential of the control terminal of the circuit; the light-emitting control circuit is used for a light-emitting time period included in the light-emitting time control stage, and under the control of the light-emitting control signal, the second terminal of the driving circuit is turned on with the light-emitting The first poles of the elements are connected so that the driving circuit drives the light emitting element to emit light according to the data voltage.
  • the light emission time control circuit includes a light emission time control transistor, a gate of the light emission time control transistor is connected to the light emission time control terminal, a first pole is connected to the second data signal terminal, and a second electrode Connected to the control end of the light emission control circuit.
  • the light emission control circuit includes a light emission control transistor; a gate of the light emission control transistor is a control end of the light emission control circuit, a first end of the light emission control transistor is a first end of the light emission control circuit, A second terminal of the light emission control transistor is a second terminal of the light emission control circuit.
  • the data voltage writing circuit includes a data voltage writing transistor, a gate of the data voltage writing transistor is connected to the voltage writing control terminal, and a first electrode is connected to the first data signal terminal.
  • the second pole is connected to the control terminal of the driving circuit.
  • the driving circuit includes a driving transistor; a gate of the driving transistor is a control terminal of the driving circuit, a first terminal of the driving transistor is a first terminal of the driving circuit, and a first terminal of the driving transistor is The second terminal is a second terminal of the driving circuit; the storage circuit includes a storage capacitor, a first terminal of the storage capacitor is connected to a control terminal of the driving circuit, and a second terminal is connected to the first voltage input terminal.
  • the present disclosure provides a driving method of a sub-pixel circuit, which is applied to the sub-pixel circuit according to the first aspect, and a display period of the sub-pixel circuit includes a data voltage writing phase and a light emitting time control phase which are sequentially set.
  • the driving method of the sub-pixel circuit includes:
  • the data voltage writing circuit writes the data voltage from the first data signal terminal to the control terminal of the driving circuit under the control of the voltage writing control terminal;
  • the storage circuit maintains a potential of a control terminal of the driving circuit;
  • the storage circuit maintains the potential of the control terminal of the driving circuit; the light emission time control circuit controls the light emission control signal from the second data signal terminal under the control of the light emission time control terminal.
  • the light-emitting control circuit under the control of the light-emitting control signal, turns on the second end of the driving circuit and the first pole of the light-emitting element. Connection such that the driving circuit drives the light emitting element to emit light according to the data voltage.
  • the present disclosure provides a pixel circuit.
  • the pixel circuit is connected to N data lines and includes: a light-emission time control circuit and N sub-pixel circuits; N is an integer greater than or equal to 2; the light-emission time control circuit, the light-emission time control gate line, and the N sub-pixels
  • the control end of the light-emitting control circuit included in the circuit is connected to one of the N data lines, and is used to control the one data line in the light-emitting time control stage under the control of the light-emitting time control grid line.
  • the n-th sub-pixel circuit includes an n-th data voltage writing circuit, an n-th driving circuit, an n-th storage circuit, and an n-th A light-emitting control circuit and an n-th light-emitting element;
  • n is a positive integer less than or equal to N;
  • the n-th data line connection in the data line is used to write the n-th data voltage on the n-th data line to the n-th data line under the control of the voltage-write control gate line in the data voltage writing stage.
  • the first end of the n-th drive circuit is connected to a first voltage input end, the second end of the n-th drive circuit is connected to the first end of the n-th light-emitting control circuit, and the first The second end of the n light-emitting control circuit is connected to the first pole of the n-th light-emitting element, and the second pole of the n-th light-emitting element is connected to the second voltage input terminal; the first end of the n-th memory circuit is connected to The control terminal of the n-th driving circuit is connected, the second terminal of the n-th storage circuit is connected to the first voltage input terminal, and the n-th storage circuit is used to control the potential of the control terminal of the n-th driving circuit.
  • the n-th light emission control circuit is configured to emit light during the light-emission time control phase, and under the control of the light-emission control signal, turn on the second end of the n-th drive circuit and the n-th drive circuit
  • the first poles of the light emitting elements are connected such that the nth driving circuit drives the nth light emitting element to emit light according to the nth data voltage.
  • the light emission time control circuit includes a light emission time control transistor; a gate of the light emission time control transistor is connected to the light emission time control gate line, and a first pole of the light emission time control transistor is connected to the N One of the data lines is connected, and a second pole of the light-emission time control transistor is connected to a control terminal of the light-emission control circuit.
  • the nth emission control circuit includes an nth emission control transistor; a gate of the nth emission control transistor is a control terminal of the nth emission control circuit, and a first terminal of the nth emission control circuit A first end of the n-th emission control circuit, a second end of the n-th emission control circuit, and a second end of the n-th emission control circuit.
  • the n-th data voltage writing circuit includes an n-th data voltage writing transistor, a gate is connected to the voltage writing control gate line, a first pole is connected to the n-th data line, and a second pole It is connected to the control terminal of the n-th driving circuit.
  • the n-th driving circuit includes an n-th driving transistor; a gate of the n-th driving transistor is a control terminal of the n-th driving circuit, and a first pole of the n-th driving transistor is the n-th driving A first end of the circuit, a second end of the n-th drive transistor, and a second end of the n-th drive circuit; the n-th storage circuit includes: an n-th storage capacitor, a first end and the n-th drive circuit The control terminal is connected, and the second terminal is connected to the first voltage input terminal.
  • the present disclosure provides a driving method of a pixel circuit.
  • the method is applied to the pixel circuit according to the third aspect, wherein a display cycle of the pixel circuit includes a data voltage writing phase and a light emitting time control phase which are sequentially set; and the driving method of the pixel circuit includes: In the voltage writing stage, the n-th data voltage writing circuit writes the n-th data voltage on the n-th data line to the control end of the n-th driving circuit under the control of the voltage writing control gate line; the n-th storage circuit The potential of the control terminal of the nth driving circuit is maintained; in the light emission time control stage, the light emission time control circuit controls the light emission of one of the N data lines under the control of the light emission time control gate line.
  • the signals are written into the control ends of the light emission control circuits included in the N sub-pixel circuits; during the light emission time period included in the light emission time control stage, the nth light emission control circuit turns on the nth light under the control of the light emission control signal.
  • a connection between the second end of the driving circuit and the first pole of the n-th light-emitting element, so that the n-th driving circuit drives the n-th light-emitting according to the n-th data voltage A light emitting member; N is an integer greater than or equal to 2, n is a positive integer less than or equal to the N.
  • the present disclosure provides a pixel circuit that is connected to N data lines.
  • the pixel circuit includes: N sub-pixel circuits according to the first aspect, where N is an integer greater than or equal to 2, wherein the light emission time control circuit in each of the N sub-pixel circuits is respectively associated with A corresponding one of the N data lines is connected.
  • the present disclosure provides a display module that is connected to N data lines.
  • the display module includes: N pixel circuits according to the third aspect, where N is an integer greater than or equal to 2, wherein a light emitting time control circuit in each pixel circuit of the N pixel circuits and the A corresponding one of the N data lines is connected, and different light emitting time control circuits in the N pixel circuits are connected to different data lines in the N data lines.
  • the present disclosure provides a display device.
  • the display device includes the pixel circuit according to the third or fifth aspect, or the display module according to the sixth aspect.
  • FIG. 1 is a structural diagram of a sub-pixel circuit according to some embodiments of the present disclosure.
  • FIG. 2 is a graph showing a relationship between a current density flowing through the micro light emitting diode and a light emitting efficiency of the micro light emitting diode;
  • FIG. 3 is a circuit diagram of a specific example of a sub-pixel circuit according to the present disclosure.
  • FIG. 4 is a structural diagram of a pixel circuit according to some embodiments of the present disclosure.
  • FIG. 5 is a circuit diagram of a specific example of a pixel circuit according to the present disclosure.
  • FIG. 6 is a schematic diagram of a specific example of a display module including three pixel circuits when three data lines can be accommodated in one pixel circuit;
  • FIG. 7 is a working timing diagram of a specific example of the display module shown in FIG. 6;
  • FIG. 8 is a circuit diagram of another specific example of a pixel circuit according to the present disclosure.
  • FIG. 9 is a flowchart of a driving method of the sub-pixel circuit shown in FIG. 1;
  • FIG. 10 is a flowchart of a driving method of the sub-pixel circuit shown in FIG. 5;
  • FIG. 11 is a flowchart of a driving method of a pixel circuit of the present disclosure.
  • MicroLED displays use different current levels to achieve different gray levels of brightness. MicroLEDs have a lower current density at low gray levels, resulting in lower luminous efficiency and higher luminous power consumption.
  • the sub-pixel circuit, the pixel circuit and the driving method, the display module and the display device provided by the present disclosure can solve the related art because the light-emitting elements are driven to emit different brightness through different current densities, resulting in low light-emitting efficiency and low power consumption at low gray levels. High problem.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the poles in order to distinguish the two poles of the transistor other than the gate, one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • the first pole may be a drain
  • the second pole may be a source
  • the first pole may be a source
  • the second pole may be a drain.
  • the present disclosure provides a sub-pixel circuit, as shown in FIG. 1.
  • the sub-pixel circuit includes a data voltage writing circuit 11, a driving circuit 12, a storage circuit 13, a light emission time control circuit 14, a light emission control circuit 15, and a light emitting element EL.
  • the data voltage writing circuit 11 is connected to the voltage writing control gate line V-GATE, the data line DATA, and the control terminal CON1 of the driving circuit 12, and is used to control the voltage writing during the data voltage writing stage. Under the control of the gate line V-GATE, the data voltage on the data line DATA is written into the control terminal CON1 of the driving circuit 12.
  • the light emission time control circuit 14 is respectively connected to the light emission time control gate line T-GATE, the data line DATA, and the control terminal CON2 of the light emission control circuit 15 for controlling the light emission time during the light emission time control stage. Under the control of the gate line T-GATE, the light emission control signal on the data line DATA is written into the control terminal CON2 of the light emission control circuit 15.
  • a first terminal TER1 of the driving circuit 12 is connected to a first voltage input terminal, a second terminal TER2 of the driving circuit 12 is connected to a first terminal TER3 of the lighting control circuit 15,
  • the two terminals TER4 are connected to the first pole of the light-emitting element EL, and the second pole of the light-emitting element EL is connected to the second voltage input terminal;
  • the first voltage input terminal is used to input the first voltage V1 and the second voltage
  • the input terminal is used for inputting the second voltage V2.
  • a first terminal of the storage circuit 13 is connected to the control terminal CON1 of the driving circuit 12, a second terminal of the storage circuit 13 is connected to the first voltage input terminal TER1, and the storage circuit 13 is used to control all The potential of the control terminal CON1 of the driving circuit 12 is described.
  • the light emission control circuit 15 is used for a light emission time period included in the light emission time control stage. Under the control of the light emission control signal, the second end of the driving circuit 12 and the first end of the light emitting element EL are turned on. One pole is connected so that the driving circuit 12 drives the light emitting element EL to emit light according to the data voltage.
  • the sub-pixel circuit accesses a light-emission control signal through a light-emission time control circuit to control the light-emission time, and combines the data voltage and the light-emission time to control the light-emitting brightness of the light-emitting element, thereby improving light-emitting efficiency and reducing Power consumption and enable more gray levels.
  • the light-emitting element EL may be a MicroLED (micro-light-emitting diode).
  • the first pole of the light-emitting element EL is the anode, and the second pole of the light-emitting element is the cathode, but not limited thereto.
  • the light-emitting element EL may also be an OLED (Organic Light-Emitting Diode) or another kind of light-emitting element.
  • the first voltage V1 may be a high voltage
  • the second voltage V2 may be a low voltage, but is not limited thereto.
  • the high voltage may be a positive voltage with a voltage value greater than 3V, but is not limited thereto; the low voltage may be a zero voltage or a negative voltage, but is not limited thereto.
  • MicroLED is a kind of self-luminous device.
  • the relationship between its luminous efficiency and current density is shown in Figure 2 (the horizontal axis is the current density, and the vertical axis is the luminous efficiency).
  • the luminous efficiency of MicroLED will decrease as the current density decreases. Therefore, if the current density is used to modulate the gray scale of the display, since the low gray scale will correspond to the low current density, the luminous efficiency of the MicroLED will decrease.
  • the reference numeral J1 is a first current density
  • the reference numeral J2 is a second current density.
  • the MicroLED is controlled to work in the region with the highest luminous efficiency, that is, the current density of the MicroLED is between J1 and J2, and the grayscale is modulated by the current and the light emission time.
  • the grayscale is modulated by the current and the light emission time.
  • the gray level modulation is performed by adjusting the current density.
  • the second current density J2 corresponds to L255
  • the first current density J1 corresponds to L120
  • the light emission time The ratios are all 100%.
  • At low gray levels (such as below L120), keep the current density J1 unchanged and adjust the gray level by adjusting the light emission time.
  • the current density corresponding to L40 is the first current density J1, and the light emission time ratio corresponding to L40 is 4.7. %.
  • L120 is the 120th gray level
  • L255 is the 255th gray level
  • L40 is the 40th gray level.
  • Some embodiments of the present disclosure provide a driving scheme suitable for MicroLED.
  • the gray scale is adjusted by the current and the light emission time at the same time, so that the MicroLED works in a region with high light emission efficiency.
  • High gray levels are achieved by adjusting the drive current, and low gray levels are achieved by adjusting the light emission time.
  • a display period of the sub-pixel circuit includes a data voltage writing phase and a light emitting time control phase which are sequentially set.
  • the data voltage writing circuit 11 writes the data voltage on the data line DATA to the control terminal CON1 of the driving circuit 12 under the control of the voltage writing control gate line V-GATE; the storage circuit 13 maintains the The potential of the control terminal CON1 of the driving circuit 12 is described.
  • the storage circuit 13 maintains the potential of the control terminal CON1 of the driving circuit 12.
  • the light emission time control circuit 14 writes the light emission control signal on the data line DATA into the control terminal CON2 of the light emission control circuit 15 under the control of the light emission time control gate line T-GATE.
  • the light emission control circuit 15 controls the connection between the second terminal TER2 of the driving circuit 12 and the first electrode TER5 of the light emitting element EL under the control of the light emission control signal. It is connected so that the driving circuit 12 drives the light emitting element EL to emit light according to the data voltage.
  • the light emission time control circuit 14 may include: a light emission time control transistor, a gate of which is connected to the light emission time control gate line, a first electrode connected to the data line, and a second electrode connected to the light emission control circuit. Control terminal connection.
  • the light emission control circuit may include a light emission control transistor; a gate of the light emission control transistor is a control terminal of the light emission control circuit, a first end of the light emission control transistor is a first end of the light emission control circuit, A second terminal of the light emission control transistor is a second terminal of the light emission control circuit.
  • the data voltage writing circuit may include a data voltage writing transistor, a gate is connected to the voltage writing control gate line, a first pole is connected to the data line, and a second pole is connected to the driving circuit. Control terminal connection.
  • the driving circuit may include a driving transistor; a gate of the driving transistor is a control terminal of the driving circuit, a first terminal of the driving transistor is a first terminal of the driving circuit, and the driving transistor The second terminal is the second terminal of the driving circuit.
  • the storage circuit may include a storage capacitor, a first terminal of which is connected to a control terminal of the driving circuit, and a second terminal of which is connected to the first voltage input terminal.
  • specific examples of the sub-pixel circuit according to the present disclosure include a data voltage writing circuit 11, a driving circuit 12, a storage circuit 13, a light emitting time control circuit 14, a light emitting control circuit 15, and a micro light emitting diode MLED.
  • the driving circuit 12 includes a driving transistor T2
  • the light-emitting control circuit 15 includes a light-emitting control transistor T3.
  • the light emission time control circuit 14 includes a light emission time control transistor T4, a gate is connected to the light emission time control gate line T-GATE, a source is connected to the data line DATA, and a drain is connected to the gate of the light emission control transistor T3. connection.
  • a source of the light emitting control transistor T3 is connected to a drain of the driving transistor T2, and a drain of the light emitting control transistor T3 is connected to an anode of the micro light emitting diode MLED.
  • the data voltage writing circuit 11 includes a data voltage writing transistor T1, a gate is connected to the voltage writing control gate line V-GATE, a source is connected to the data line DATA, and a drain is connected to the driving transistor T2. Gate connection.
  • V1 is a high voltage VDD.
  • the storage circuit 13 includes a storage capacitor C, a first terminal of which is connected to the gate of the driving transistor T2, and a second terminal of which is connected to the first voltage V1.
  • V2 is a low voltage VSS.
  • T1, T2, T3, and T4 are all p-type transistors, but not limited to this; in actual operation, the above-mentioned transistors can also be replaced with n-type transistors.
  • a specific embodiment of the sub-pixel circuit shown in FIG. 3 of the present disclosure is a 4T1C sub-pixel circuit.
  • T2 is a driving transistor
  • T1, T3, and T4 are switching transistors.
  • T1 When the V-GATE input is low and the T-GATE input is high, T1 is turned on and T4 is turned off. Pole connected node), and stored in the storage capacitor C;
  • T4 When the T-GATE input is low and the V-GATE input is high, T4 is turned on, T1 is turned off, and the light emission control signal on the DATA that controls the T3 switch is transmitted to the gate of T3 via T4.
  • T3 When the light emission control signal is at a low level, T3 is turned on and the MLED can emit light; when the light emission control signal is at a high level, T3 is turned off and the MLED is not lighted.
  • Some embodiments of the present disclosure provide a driving method of the sub-pixel circuit.
  • the driving method of the sub-pixel circuit is applied to the above-mentioned sub-pixel circuit.
  • the display period of the sub-pixel circuit includes a data voltage writing phase and a light emitting time control phase which are sequentially set.
  • the driving method of the sub-pixel circuit includes steps S11-S13.
  • the data voltage writing circuit controls the data voltage on the data line to be written to the control terminal of the driving circuit under the control of the voltage writing control gate line; the storage circuit maintains the control terminal of the driving circuit. Potential.
  • the storage circuit maintains the potential of the control terminal of the driving circuit; the light emission time control circuit writes the light emission control signal on the data line into the light emission control under the control of the light emission time control gate line. Control terminal of the circuit.
  • the light emission control circuit In the light emission time period included in the light emission time control stage, the light emission control circuit, under the control of the light emission control signal, turns on the connection between the second end of the driving circuit and the first pole of the light emitting element, so that The driving circuit drives the light emitting element to emit light according to the data voltage.
  • the driving method of the sub-pixel circuit first writes the data voltage in the data voltage writing stage, and then writes the light emission control signal on the data line to the control terminal of the light emission control circuit in the light emission time control stage. To control the light-emitting element to emit light during the light-emitting period.
  • the pixel circuit according to some embodiments of the present disclosure is connected to N data lines and includes a light emitting time control circuit and N sub-pixel circuits; N is an integer greater than or equal to 2.
  • the light emission time control circuit is connected to a light emission time control gate line, and a control end of the light emission control circuit is connected to one of the N data lines for controlling the light emission time during the light emission time control stage. Under the control of the gate lines, the light emission control signals on the data lines are written into the control terminals of the light emission control circuits included in the N sub-pixel circuits.
  • the n-th sub-pixel circuit includes an n-th data voltage writing circuit, an n-th driving circuit, an n-th storage circuit, an n-th light-emitting control circuit, and an n-th light-emitting element; n is a positive integer less than or equal to N.
  • the n-th data voltage writing circuit is connected to a voltage writing control gate line, a control terminal of the n-th driving circuit, and an n-th data line of the N data lines, and is used in a data voltage writing stage, Under the control of the voltage writing control gate line, the n-th data voltage on the n-th data line is written into a control terminal of the n-th driving circuit.
  • a first terminal of the n-th driving circuit is connected to a first voltage input terminal, a second terminal of the n-th driving circuit is connected to a first terminal of the n-th lighting control circuit, and the The second terminal is connected to the first electrode of the n-th light-emitting element, and the second electrode of the n-th light-emitting element is connected to the second voltage input terminal.
  • a first terminal of the n-th memory circuit is connected to a control terminal of the n-th drive circuit, a second terminal of the n-th memory circuit is connected to the first voltage input terminal, and the n-th memory circuit is used for Controlling a potential of a control terminal of the n-th driving circuit.
  • the n-th light emission control circuit is configured to emit light during the light-emission time control stage, and under the control of the light-emission control signal, the second end of the n-th drive circuit is turned on and the n-th light is emitted.
  • the first poles of the elements are connected such that the n-th driving circuit drives the n-th light-emitting element to emit light according to the n-th data voltage.
  • the pixel circuit includes N sub-pixel circuits and a light-emission time control circuit.
  • the N sub-pixel circuits each control the light-emission time by the light-emission time control circuit, so that one including N can be controlled through one data line.
  • the use of N data lines can control the light-emitting times of the above N pixel circuits, which can improve the light-emitting efficiency, reduce power consumption, and achieve more gray levels while reducing the use of transistors. And the number of data lines.
  • N 3 as an example.
  • the pixel circuit includes a light emitting time control circuit 40, a first sub-pixel circuit P1, a second sub-pixel circuit P2, and a third sub-pixel circuit P3.
  • the first subpixel circuit P1 is any one of a red subpixel circuit, a blue subpixel circuit, or a green subpixel circuit
  • the second subpixel circuit P2 is a red subpixel circuit, a blue subpixel circuit, or Any one of a green sub-pixel circuit
  • the third sub-pixel circuit P3 is any one of a red sub-pixel circuit, a blue sub-pixel circuit, or a green sub-pixel circuit.
  • the first sub-pixel circuit P1 is a red sub-pixel circuit
  • the second sub-pixel circuit P2 is a blue sub-pixel circuit
  • the third sub-pixel circuit P3 is a green sub-pixel circuit.
  • the first sub-pixel circuit P1 includes a first data voltage writing circuit 411, a first driving circuit 412, a first storage circuit 413, a first light emitting control circuit 414, and a first light emitting element EL1.
  • the second sub-pixel circuit P2 includes a second data voltage writing circuit 421, a second driving circuit 422, a second storage circuit 423, a second light emitting control circuit 424, and a second light emitting element EL2.
  • the third sub-pixel circuit P3 includes a third data voltage writing circuit 431, a third driving circuit 432, a third storage circuit 433, a third light emitting control circuit 434, and a third light emitting element EL3.
  • the control end is connected to the first data line DATA1, and is used to control the light-emission control signals on the first data line DATA1 respectively under the control of the light-emission time control grid line T-GATE.
  • the control terminal of the first light emission control circuit 414, the control terminal of the second light emission control circuit 424, and the control terminal of the third light emission control circuit 434 are written.
  • the first data voltage writing circuit 411 is respectively connected to a voltage writing control gate line V-GATE, a control terminal of the first driving circuit 412, and a first data line DATA1. Under the control of the voltage writing control gate line V-GATE, a first data voltage on the first data line DATA1 is written into a control terminal of the first driving circuit 412.
  • a first terminal of the first driving circuit 412 is connected to a first voltage V1
  • a second terminal of the first driving circuit 412 is connected to a first terminal of the first light emitting control circuit 414
  • the first light emitting control A second terminal of the circuit 414 is connected to a first pole of the first light emitting element EL1
  • a second pole of the first light emitting element EL1 is connected to a second voltage V2.
  • a first terminal of the first storage circuit 413 is connected to a control terminal of the first driving circuit 412, a second terminal of the first storage circuit 413 is connected to a first voltage V1, and the first storage circuit 413 is used for For controlling a potential of a control terminal of the first driving circuit 412.
  • the first light emission control circuit 414 is configured to emit light during the light emission time control period. Under the control of the light emission control signal, the second terminal of the first driving circuit 412 and the first light emitting circuit are turned on. The first poles of a light-emitting element EL1 are connected so that the first driving circuit 412 drives the first light-emitting element EL1 to emit light according to the first data voltage.
  • the second data voltage writing circuit 421 is connected to a voltage writing control gate line V-GATE, a control terminal of the second driving circuit 422, and a second data line DATA2. Under the control of the voltage writing control gate line V-GATE, a second data voltage on the second data line DATA2 is written into a control terminal of the second driving circuit 422.
  • a first terminal of the second driving circuit 422 is connected to a first voltage V1
  • a second terminal of the second driving circuit 422 is connected to a first terminal of the second light emitting control circuit 424, and the second light emitting control
  • the second end of the circuit 424 is connected to the first pole of the second light-emitting element EL2, and the second pole of the second light-emitting element EL2 is connected to the second voltage V2.
  • a first terminal of the second storage circuit 423 is connected to a control terminal of the second driving circuit 422, a second terminal of the second storage circuit 423 is connected to a first voltage V1, and the second storage circuit 423 is used for For controlling a potential of a control terminal of the second driving circuit 422.
  • the second light-emitting control circuit 424 is configured to emit light during the light-emitting time control phase. Under the control of the light-emitting control signal, the second terminal of the second driving circuit 422 and the first driving circuit are turned on. The two light emitting elements EL2 are connected between the first poles so that the second driving circuit 422 drives the second light emitting element EL2 to emit light according to the second data voltage.
  • the third data voltage writing circuit 431 is connected to a voltage writing control gate line V-GATE, a control terminal of the third driving circuit 432, and a third data line DATA3. Under the control of the voltage writing control gate line V-GATE, a second data voltage on the third data line DATA3 is written into a control terminal of the third driving circuit 432.
  • a first terminal of the third driving circuit 432 is connected to a first voltage V1
  • a second terminal of the third driving circuit 432 is connected to a first terminal of the third light-emitting control circuit 434
  • the third light-emitting control The second terminal of the circuit 434 is connected to the first pole of the third light-emitting element EL3, and the second pole of the third light-emitting element EL3 is connected to the second voltage V2.
  • a first terminal of the third storage circuit 433 is connected to a control terminal of the third driving circuit 432, a second terminal of the third storage circuit 433 is connected to a first voltage V1, and the third storage circuit 433 is used for For controlling a potential of a control terminal of the third driving circuit 432.
  • the third light-emitting control circuit 434 is configured to emit light during the light-emitting time control phase. Under the control of the light-emitting control signal, the second terminal of the third driving circuit 432 and the first driving circuit are turned on. The first electrodes of the three light-emitting elements EL3 are connected so that the third driving circuit 432 drives the third light-emitting element EL3 to emit light according to the third data voltage.
  • DATA1 is used to provide corresponding light emission control signals for the first subpixel circuit P1, the second subpixel circuit P2, and the third subpixel circuit P3, that is, the same pixel
  • the red sub-pixel circuit, the green sub-pixel circuit, and the blue sub-pixel circuit in the circuit use a data line (in the specific embodiment shown in FIG. 4, the data line is the first data line DATA1) to control the light emission time.
  • the three data lines can support three rows of pixel circuits to be lighted at the same time. If one pixel circuit can accommodate three data lines, the three rows of pixel circuits can be lighted at the same time.
  • the pixel circuit according to some embodiments of the present disclosure can modulate more grayscales on the premise of ensuring light emission efficiency. For example, when the current density of the driving current flowing through each light-emitting element is greater than or equal to the first current density J1 and less than or equal to the second current density J2, the light-emitting efficiency of each light-emitting element is the highest, and the highest grayscale is the second current density J2 and The combination of the highest light emission time ratio and the lowest gray scale is the combination of the first current density J1 and the minimum light emission time ratio.
  • This method can expand the ratio of the highest gray scale to the lowest gray scale and achieve more gray scales.
  • the display period of the pixel circuit includes a data voltage writing phase and a light emitting time control phase which are sequentially set.
  • the first data voltage writing circuit 411 writes the first data voltage on the first data line DATA1 to the first driving circuit 412 under the control of the voltage writing control gate line V-GATE.
  • the first storage circuit 413 controls the potential of the control terminal of the first driving circuit 412 to be maintained.
  • the second data voltage writing circuit 421 controls the writing of the second data voltage on the second data line DATA2 to the control terminal of the second driving circuit 422 and the second storage circuit 423 under the control of the voltage writing control gate line V-GATE. The control maintains the potential of the control terminal of the second driving circuit 422.
  • the third data voltage writing circuit 431 controls the third data voltage on the third data line DATA3 to be written to the control terminal of the third driving circuit 432 and the third storage circuit 433 under the control of the voltage writing control gate line V-GATE.
  • the control maintains the potential of the control terminal of the third driving circuit 432.
  • the light emission time control circuit 40 controls the light emission control signals on the first data line DATA1 to be written to the control terminals of the first light emission control circuit 414 under the control of the light emission time control grid line T-GATE.
  • the first light emission control circuit 414 Under the control of the light emission control signal, turns on the second end of the first driving circuit 412 and the first end of the first light emitting element EL1.
  • the second light-emitting control circuit 424 guides the light-emitting control circuit 424 under the control of the light-emitting control signal Through the connection between the second end of the second driving circuit 422 and the first pole of the second light emitting element EL2, so that the second driving circuit 422 drives the second light emitting element according to the second data voltage EL2 emits light;
  • the third light-emitting control circuit 434 controls the connection between the second end of the third driving circuit 432 and the first pole of the third light-emitting element EL3 under the control of the light-emitting control signal, so that The third driving circuit 432 drives the third light emitting element
  • the light emission time control circuit may include a light emission time control transistor.
  • a gate of the light emission time control transistor is connected to the light emission time control gate line, a first electrode of the light emission time control transistor is connected to one of the N data lines, and a light emission time control transistor The second pole is connected to a control terminal of the light emitting control circuit.
  • the n-th emission control circuit may include an n-th emission control transistor
  • the gate of the n-th emission control transistor is a control terminal of the n-th emission control circuit
  • the first pole of the n-th emission control circuit is the first end of the n-th emission control circuit
  • the second pole of the circuit is the second end of the n-th light emitting control circuit.
  • the n-th data voltage writing circuit may include: an n-th data voltage writing transistor, a gate connected to the voltage writing control gate line, and a first pole connected to the n-th data line, The second pole is connected to the control terminal of the n-th driving circuit.
  • the n-th driving circuit may include an n-th driving transistor; the gate of the n-th driving transistor is a control terminal of the n-th driving circuit, and the first pole of the n-th driving transistor is the first A first end of the n-th drive circuit, a second end of the n-th drive transistor, and a second end of the n-th drive circuit.
  • the n-th storage circuit includes an n-th storage capacitor, a first end of which is connected to a control end of the n-th drive circuit, and a second end of which is connected to the first voltage input end.
  • specific examples of the pixel circuit according to the present disclosure include a light emission time control circuit 40, a first sub-pixel circuit P1, a second sub-pixel circuit P2, and a third sub-pixel circuit P3.
  • the light emission time control circuit 40 includes a light emission time control transistor T4.
  • the first sub-pixel circuit P1 includes a first data voltage writing circuit, a first driving circuit, a first storage circuit, a first light emitting control circuit, and a first micro light emitting diode MLED1.
  • the second sub-pixel circuit P2 includes a second data voltage writing circuit, a second driving circuit, a second storage circuit, a second light emitting control circuit, and a second micro light emitting diode MLED2.
  • the third sub-pixel circuit P3 includes a third data voltage writing circuit, a third driving circuit, a third storage circuit, a third light emitting control circuit, and a third micro light emitting diode MLED3.
  • the first light emitting control circuit includes a first light emitting control transistor T13
  • the first data voltage writing circuit includes a first data voltage writing transistor T11
  • the first driving circuit includes a first driving transistor T12
  • the first A storage circuit includes a first storage capacitor C1.
  • the second light emission control circuit includes a second light emission control transistor T23
  • the second data voltage writing circuit includes a second data voltage writing transistor T21
  • the second driving circuit includes a second driving transistor T22
  • the first The two storage circuits include a second storage capacitor C2.
  • the third light emitting control circuit includes a third light emitting control transistor T33, the third data voltage writing circuit includes a third data voltage writing transistor T31, the third driving circuit includes a third driving transistor T32, and the first
  • the three storage circuits include a third storage capacitor C3.
  • the gate of the light emission time control transistor T4 is connected to the light emission time control gate line T-GATE, the source of the light emission time control transistor T4 is connected to the first data line DATA1, and the drain of the light emission time control transistor T4 is A pole is connected to a gate of the first light emission control transistor T13, a gate of the second light emission control transistor T23, and a gate of the third light emission control transistor T33.
  • a gate of the first data voltage writing transistor T11 is connected to a voltage writing control gate line V-GATE, a source of the first data voltage writing transistor T11 is connected to a first data line DATA1, and the first The drain of the data voltage writing transistor T11 is connected to the gate of the first driving transistor T12.
  • the source of the first driving transistor T12 is connected to a first voltage V1, and the drain of the first driving transistor T12 is connected to the source of the first light-emitting control transistor T13; in this specific example, V1 is high
  • V1 is high
  • the voltage VDD is not limited to this.
  • a drain of the first light emitting control transistor T13 is connected to an anode of the first micro light emitting diode MLED1, and a cathode of the first micro light emitting diode MLED1 is connected to a second voltage V2.
  • V2 is a low voltage VSS, but not limited to this.
  • a first terminal of the first storage capacitor C1 is connected to a gate of the first driving transistor T12, and a second terminal of the first storage capacitor C1 is connected to the first voltage V1.
  • a gate of the second data voltage writing transistor T21 is connected to a voltage writing control gate line V-GATE, a source of the second data voltage writing transistor T21 is connected to a second data line DATA2, and the second A drain of the data voltage writing transistor T21 is connected to a gate of the second driving transistor T22.
  • the source of the second driving transistor T22 is connected to a first voltage V1, and the drain of the second driving transistor T22 is connected to the source of the second light-emitting control transistor T23; in this specific example, V1 is high
  • V1 is high
  • the voltage VDD is not limited to this.
  • the drain of the second light-emitting control transistor T23 is connected to the anode of the second micro-light-emitting diode MLED2, and the cathode of the second micro-light-emitting diode MLED2 is connected to the second voltage V2; in this specific example, V2 is low
  • V2 is low
  • the voltage VSS is not limited to this.
  • a first terminal of the second storage capacitor C2 is connected to a gate of the second driving transistor T22, and a second terminal of the second storage capacitor C2 is connected to the first voltage V1.
  • a gate of the third data voltage writing transistor T31 is connected to a voltage writing control gate line V-GATE, a source of the third data voltage writing transistor T31 is connected to a third data line DATA3, and the third A drain of the data voltage writing transistor T31 is connected to a gate of the third driving transistor T32.
  • a source of the third driving transistor T32 is connected to a first voltage V1, and a drain of the third driving transistor T32 is connected to a source of the third light-emitting control transistor T33.
  • V1 is High voltage VDD, but not limited to this.
  • the drain of the third light-emitting control transistor T33 is connected to the anode of the third micro-light-emitting diode MLED3, and the cathode of the third micro-light-emitting diode MLED3 is connected to the second voltage V2; in this specific example, V2 is low
  • V2 is low
  • the voltage VSS is not limited to this.
  • a first terminal of the third storage capacitor C3 is connected to a gate of the third driving transistor T32, and a second terminal of the third storage capacitor C3 is connected to the first voltage V1.
  • all the transistors are p-type transistors, but not limited thereto.
  • the P-type transistor can also be replaced with an N-type transistor as needed.
  • a driving method of a specific example of the pixel circuit shown in FIG. 5 of the present disclosure includes the following steps S21-S23.
  • V-GATE In the data voltage writing stage, V-GATE outputs a low level, T-GATE outputs a high level, DATA1 outputs a first data voltage, DATA2 outputs a second data voltage, and DATA3 outputs a third data voltage, T11, T21, and T31 is turned on, T4 is turned off, the first data voltage is written to the gate of T12, the second data voltage is written to the gate of T22, the third data voltage is written to the gate of T32, and C1 maintains the gate of T12. Potential, C2 maintains the potential of the gate of T22, and C3 maintains the potential of the gate of T32.
  • V-GATE In the lighting time control stage, V-GATE outputs a high level, T-GATE outputs a low level, DATA1 inputs a lighting control signal, T11, T21, and T31 are all turned off, T4 is turned on, and the lighting control signals are written respectively The gate of T13, the gate of T23 and the gate of T33.
  • S23 The lighting time period included in the lighting time control phase, the lighting control signal is low level, T13, T23, and T33 are turned on, T12 drives MLED1 to emit light, T22 drives MLED2 to emit light, and T23 drives MLED3 to emit light.
  • the pulse width of the light emission control signal determines the length of the light emission time, and each data voltage together with the light emission time determines the light emission brightness of each micro light emitting diode.
  • FIG. 6 is a schematic diagram of a specific example of a display module including three pixel circuits when three data lines can be accommodated in one pixel circuit.
  • the reference numeral V-GATE (M) is the M-th row voltage write control gate line
  • the reference numeral T-GATE (M) is the M-th row light-emission time control gate line
  • the reference numeral V-GATE (M + 1) is the M + 1 row voltage write control gate line
  • the label is T-GATE (M + 1) is M + 1 row light-emission time control gate line
  • the label is V-GATE (M + 2) is a voltage writing control gate line for the M + 2th row
  • T-GATE (M + 2) is a light emitting time control gate line for the M + 2th row
  • M is a positive integer.
  • the reference numeral T14 is a first light emission time control transistor
  • the reference numeral T24 is a second light emission time control transistor
  • the T34 is a third light emission time control transistor.
  • the source of T14 is connected to the first data line DATA1, the source of T24 is connected to the second data line DATA2, and the source of T34 is connected to the third data line DATA3.
  • the reference number T11 is the Mth row and first column data voltage writing transistor
  • the reference number T12 is the Mth row and first column drive transistor
  • the reference number T13 is the Mth row and first column light-emitting control transistor
  • the reference number is C1. Is the storage capacitor for the Mth row and the first column
  • the reference number T21 is the data voltage writing transistor in the Mth row and the second column
  • the reference number T22 is the Mth row and the second column drive transistor
  • the reference number T23 is the Mth row and the first column.
  • Two-column light-emitting control transistor the storage capacitor of the M-th row and the second column is labeled C2; the data voltage writing transistor of the M-th row and the third column is labeled T31, and the drive transistor of the M-th row and the third column is labeled T32
  • the reference numeral T33 is the M-th row and third column light-emitting control transistor, and the reference numeral C3 is the M-th row and third column storage capacitor.
  • the reference number T41 is the M + 1 row first column data voltage writing transistor
  • the reference number T42 is the M + 1 row first column drive transistor
  • the reference number T43 is the M + 1 row first column drive control.
  • Transistor, C4 is M + 1 row and first column storage capacitor
  • T51 is M + 1 row and second column data voltage writing transistor
  • T52 is M + 1 row and second column Drive transistor.
  • the code for T53 is the M + 1 row and the second column light-emission control transistor.
  • the code for C5 is the M + 1 row and the second column storage capacitor.
  • the code for T61 is the M + 1 row and the third column.
  • Voltage writing transistor, T62 is the M + 1 row and the third column drive transistor
  • T63 is the M + 1 row and the third column light-emission control transistor
  • C6 is the M + 1 row and the third column. Column storage capacitor.
  • the reference number T71 is the M + 2 row and first column data voltage writing transistor
  • the reference number T72 is the M + 2 row and first column drive transistor
  • the reference number T73 is the M + 2 row and first column light emitting control.
  • Transistor, C7 is M + 2 row and first column storage capacitor
  • T81 is M + 2 row and second column data voltage writing transistor
  • T82 is M + 2 row and second column Driving transistor
  • T83 is the M + 2 row and second column light-emission control transistor
  • C8 is the M + 2 row and second column storage capacitor
  • T91 is M + 2 row and third column data Voltage writing transistor
  • T92 is the M + 2 row and third column drive transistor
  • T93 is the M + 2 row and third column light-emitting control transistor
  • C9 is the M + 2 row and third column. Column storage capacitor.
  • T-GATE (M), T-GATE (M + 1), and T-GATE (M + 2) all output a high level.
  • V-GATE (M) outputs a low level
  • both V-GATE (M + 1) and V-GATE (M + 2) output a high level.
  • the first data voltage output from DATA1 is written to the gate of T12 through the conductive T11
  • the second data voltage output from DATA2 is written to the gate of T22 through the conductive T21
  • the third data voltage output from DATA3 is passed through the conductive Pass T31 to the gate of T32.
  • V-GATE (M + 1) outputs a low level
  • both V-GATE (M) and V-GATE (M + 2) output a high level.
  • the first data voltage output from DATA1 is written to the gate of T42 through T41 that is turned on
  • the second data voltage output from DATA2 is written to the gate of T52 through T51 that is turned on
  • the third data voltage output from DATA3 is passed to T61 that is turned on Write to the gate of T62.
  • V-GATE (M + 2) outputs a low level
  • both V-GATE (M) and V-GATE (M + 1) output a high level.
  • the first data voltage output from DATA1 is written to the gate of T72 through T71 that is turned on
  • the second data voltage output from DATA2 is written to the gate of T82 through T81 that is turned on
  • the third data voltage output from DATA3 is passed to T91 that is turned on Write to the gate of T92.
  • V-GATE (M), V-GATE (M + 1) and V-GATE (M + 2) all output high level, T-GATE (M), T-GATE (M + 1) and T-GATE (M + 2) both output a low level to write the first light-emitting control signal on DATA1 to the gates of T12, T22, and T32, respectively, so that MLED1, MLED2 And MLED3 emit light in the first light emitting time period included in S2 (the duration of the first light emitting time period is the time when the first light emitting control signal is low level); write the second light emitting control signal on DATA2 separately Into the gate of T42, the gate of T52, and the gate of T62, so that MLED4, MLED5, and MLED6 emit light during the second light emission period included in S2 (the second light emission period lasts for the second light emission period) The time when the control signal is low level); the third light-emitting control signal on DATA3 is written into the gate
  • the driving method of a pixel circuit is applied to the above-mentioned pixel circuit, and a display period of the pixel circuit includes a data voltage writing phase and a light emitting time control phase which are sequentially set.
  • the driving method of the pixel circuit includes steps S31-S33.
  • the nth data voltage writing circuit controls the nth data voltage on the nth data line to write to the control terminal of the nth driving circuit; the nth The storage circuit controls to maintain the potential of the control terminal of the n-th driving circuit.
  • the light emission time control circuit In the light emission time control stage, the light emission time control circuit, under the control of the light emission time control grid line, controls writing the light emission control signal of one of the N data lines into the light emission control included in the N sub-pixel circuits. Control terminal of the circuit.
  • the nth light emission control circuit controls the second end of the nth drive circuit and the nth light emitting element to be turned on under the control of the light emission control signal.
  • the pixel circuit according to some embodiments of the present disclosure is connected to N data lines and includes N above-mentioned sub-pixel circuits; N is an integer greater than or equal to 2; and the light-emitting time in each of the sub-pixel circuits
  • the control circuit is correspondingly connected to one of the N data lines.
  • FIG. 8 another specific example of the pixel circuit according to the present disclosure includes a first sub-pixel circuit P4, a second sub-pixel circuit P5, and a third sub-pixel circuit P6.
  • Each of the first, second, and third sub-pixel circuits P4, P5, or P6 may be one of a red sub-pixel circuit, a green sub-pixel circuit, or a blue sub-pixel.
  • the first sub-pixel circuit P4 may be a red sub-pixel circuit
  • the second sub-pixel circuit P5 may be a green sub-pixel circuit
  • the third sub-pixel circuit P6 may be a blue sub-pixel circuit.
  • the structure of the first sub-pixel circuit P4, the structure of the second sub-pixel circuit P5, and the structure of the third sub-pixel circuit P6 are the same as those of the sub-pixel circuit shown in FIG.
  • the first sub-pixel circuit P4 includes a first data voltage writing transistor T11, a first driving transistor T12, a first storage capacitor C1, a first light emitting time control transistor T14, and a first light emitting control transistor T13; a source of T14 and The first data line DATA1 is connected.
  • the second sub-pixel circuit P5 includes a second data voltage writing transistor T21, a second driving transistor T22, a second storage capacitor C2, a second light-emission time control transistor T24, and a second light-emission control transistor T23; the source of T24 and The second data line DATA2 is connected.
  • the third sub-pixel circuit P6 includes a third data voltage writing transistor T31, a third driving transistor T32, a third storage capacitor C3, a third light emitting time control transistor T34, and a third light emitting control transistor T33.
  • the source of T34 is The third data line DATA3 is connected.
  • the reference numeral MLED1 is a first micro light emitting diode
  • the reference numeral MLED2 is a second micro light emitting diode
  • the reference numeral MLED3 is a third micro light emitting diode
  • the reference numeral DATA1 is a first data line
  • the reference numeral is DATA2 is a second data line
  • DATA3 is a third data line
  • V-GATE is a voltage write control gate line
  • T-GATE is a light emission time control gate line.
  • all transistors are p-type transistors, but not limited to this; in actual operation, the above-mentioned transistors can also be replaced with n-type transistors.
  • the display device includes the pixel circuit described above.
  • the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the sub-pixel circuit, the pixel circuit, the driving method thereof, and the display device of the present disclosure access a light-emitting control signal through a light-emitting time control circuit to control the light-emitting time, and control the light-emitting element in combination with the data voltage and the light-emitting time.
  • Light emission brightness which can improve light emission efficiency and reduce power consumption.

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Abstract

一种子像素电路、像素电路及其驱动方法、显示模组和显示装置。该子像素电路包括数据电压写入电路（11）、驱动电路（12）、存储电路（13）、发光时间控制电路（14）、发光控制电路（15）和发光元件；发光时间控制电路（14）用于在发光时间控制阶段，在发光时间控制端的控制下，将发光控制信号写入发光控制电路（15）的控制端；发光控制电路（15）在发光时间控制阶段包括的发光时间段，在发光控制信号的控制下，导通驱动电路（12）的第二端与发光元件的第一极之间的连接，以使得驱动电路（12）根据数据电压驱动发光元件发光。

Description

子像素电路、像素电路及其驱动方法、显示模组和显示装置
相关申请的交叉引用
本申请主张在2018年6月14日在中国提交的中国专利申请号No.201810613582.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种子像素电路、像素电路及其驱动方法、显示模组和显示装置。
背景技术
MicroLED(微型发光二极管)作为一种自发光器件，其发光效率会在低电流密度下随着电流密度降低而降低。不同灰阶显示是采用不同电流密度来驱动发光元件而发出不同亮度的光来实现的。
发明内容
本公开的目的在于提供一种子像素电路、像素电路及其驱动方法、显示模组和显示装置。
第一方面，本公开提供一种子像素电路。该子像素电路包括：数据电压写入电路、驱动电路、存储电路、发光时间控制电路、发光控制电路和发光元件，其中，所述数据电压写入电路与电压写入控制端、第一数据信号端和所述驱动电路的控制端连接，用于在数据电压写入阶段，在所述电压写入控制端的控制下，将数据电压从所述第一数据信号端写入所述驱动电路的控制端；所述发光时间控制电路与发光时间控制端、第二数据信号端和所述发光控制电路的控制端连接，用于在发光时间控制阶段，在所述发光时间控制端的控制下，将发光控制信号从所述第二数据信号端写入所述发光控制电路的控制端；所述驱动电路的第一端与第一电压输入端连接，所述驱动电路的第二端与所述发光控制电路的第一端连接，所述发光控制电路的第二端与发光元件的第一极连接，所述发光元件的第二极与第二电压输入端连接；所述存 储电路的第一端与所述驱动电路的控制端连接，所述存储电路的第二端与所述第一电压输入端连接，所述存储电路用于控制所述驱动电路的控制端的电位；所述发光控制电路用于在所述发光时间控制阶段包括的发光时间段，在所述发光控制信号的控制下，导通所述驱动电路的第二端与所述发光元件的第一极之间的连接，以使得所述驱动电路根据所述数据电压驱动所述发光元件发光。
可选地，所述发光时间控制电路包括发光时间控制晶体管，所述发光时间控制晶体管的栅极与所述发光时间控制端连接，第一极与所述第二数据信号端连接，第二极与所述发光控制电路的控制端连接。
可选地，所述发光控制电路包括发光控制晶体管；所述发光控制晶体管的栅极为所述发光控制电路的控制端，所述发光控制晶体管的第一极为所述发光控制电路的第一端，所述发光控制晶体管的第二极为所述发光控制电路的第二端。
可选地，所述数据电压写入电路包括数据电压写入晶体管，所述数据电压写入晶体管的栅极与所述电压写入控制端连接，第一极与所述第一数据信号端连接，第二极与所述驱动电路的控制端连接。
可选地，所述驱动电路包括驱动晶体管；所述驱动晶体管的栅极为所述驱动电路的控制端，所述驱动晶体管的第一极为所述驱动电路的第一端，所述驱动晶体管的第二极为所述驱动电路的第二端；所述存储电路包括存储电容，所述存储电容的第一端与所述驱动电路的控制端连接，第二端与所述第一电压输入端连接。
第二方面，本公开提供一种子像素电路的驱动方法，应用于第一方面所述的子像素电路，所述子像素电路的显示周期包括依次设置的数据电压写入阶段和发光时间控制阶段。所述子像素电路的驱动方法包括：
在所述数据电压写入阶段，所述数据电压写入电路在所述电压写入控制端的控制下，将所述数据电压从所述第一数据信号端写入所述驱动电路的控制端；所述存储电路维持所述驱动电路的控制端的电位；
在所述发光时间控制阶段，所述存储电路维持所述驱动电路的控制端的电位；发光时间控制电路在所述发光时间控制端的控制下，将所述发光控制 信号从所述第二数据信号端写入所述发光控制电路的控制端；
在所述发光时间控制阶段包括的所述发光时间段，所述发光控制电路在所述发光控制信号的控制下，导通所述驱动电路的第二端与所述发光元件的第一极之间的连接，以使得所述驱动电路根据所述数据电压驱动所述发光元件发光。
第三方面，本公开提供一种像素电路。该像素电路与N条数据线连接且包括：一个发光时间控制电路和N个子像素电路；N为大于或等于2的整数；所述发光时间控制电路与发光时间控制栅线、所述N个子像素电路包括的发光控制电路的控制端和所述N条数据线中的一条数据线连接，用于在发光时间控制阶段，在所述发光时间控制栅线的控制下，将该所述一条数据线上的发光控制信号写入所述N个子像素电路包括的所述发光控制电路的控制端；第n子像素电路包括第n数据电压写入电路、第n驱动电路、第n存储电路、第n发光控制电路和第n发光元件；n为小于或等于N的正整数；所述第n数据电压写入电路与电压写入控制栅线、所述第n驱动电路的控制端和所述N条数据线中的第n数据线连接，用于在数据电压写入阶段，在所述电压写入控制栅线的控制下，将所述第n数据线上的第n数据电压写入所述第n驱动电路的控制端；所述第n驱动电路的第一端与第一电压输入端连接，所述第n驱动电路的第二端与所述第n发光控制电路的第一端连接，所述第n发光控制电路的第二端与所述第n发光元件的第一极连接，所述第n发光元件的第二极与第二电压输入端连接；所述第n存储电路的第一端与所述第n驱动电路的控制端连接，所述第n存储电路的第二端与所述第一电压输入端连接，所述第n存储电路用于控制所述第n驱动电路的控制端的电位；所述第n发光控制电路用于在所述发光时间控制阶段包括的发光时间段，在所述发光控制信号的控制下，导通所述第n驱动电路的第二端与所述第n发光元件的第一极之间的连接，以使得所述第n驱动电路根据所述第n数据电压驱动所述第n发光元件发光。
可选地，所述发光时间控制电路包括发光时间控制晶体管；所述发光时间控制晶体管的栅极与所述发光时间控制栅线连接，所述发光时间控制晶体管的第一极与所述N条数据线中的所述一条数据线连接，所述发光时间控制 晶体管的第二极与所述发光控制电路的控制端连接。
可选地，所述第n发光控制电路包括第n发光控制晶体管；所述第n发光控制晶体管的栅极为所述第n发光控制电路的控制端，所述第n发光控制电路的第一极为所述第n发光控制电路的第一端，所述第n发光控制电路的第二极为所述第n发光控制电路的第二端。
可选地，所述第n数据电压写入电路包括第n数据电压写入晶体管，栅极与所述电压写入控制栅线连接，第一极与所述第n数据线连接，第二极与所述第n驱动电路的控制端连接。
可选地，所述第n驱动电路包括第n驱动晶体管；所述第n驱动晶体管的栅极为所述第n驱动电路的控制端，所述第n驱动晶体管的第一极为所述第n驱动电路的第一端，所述第n驱动晶体管的第二极为所述第n驱动电路的第二端；所述第n存储电路包括：第n存储电容，第一端与所述第n驱动电路的控制端连接，第二端与所述第一电压输入端连接。
第四方面，本公开提供一种像素电路的驱动方法。该方法应用于第三方面所述的像素电路，其中，所述像素电路的显示周期包括依次设置的数据电压写入阶段和发光时间控制阶段；所述像素电路的驱动方法包括：在所述数据电压写入阶段，第n数据电压写入电路在所述电压写入控制栅线的控制下，将第n数据线上的第n数据电压写入第n驱动电路的控制端；第n存储电路维持第n驱动电路的控制端的电位；在所述发光时间控制阶段，所述发光时间控制电路在所述发光时间控制栅线的控制下，将N条数据线中的一条数据线上的发光控制信号写入N个子像素电路包括的发光控制电路的控制端；在所述发光时间控制阶段包括的发光时间段，第n发光控制电路在所述发光控制信号的控制下，导通所述第n驱动电路的第二端与第n发光元件的第一极之间的连接，以使得所述第n驱动电路根据所述第n数据电压驱动所述第n发光元件发光；N为大于或等于2的整数，n为小于或等于N的正整数。
第五方面，本公开提供一种像素电路，该像素电路与N条数据线连接。该像素电路包括：N个如第一方面所述的子像素电路，N为大于或等于2的整数，其中，所述N个子像素电路中的每个子像素电路中所述发光时间控制电路分别与所述N条数据线中对应的一条数据线连接。
第六方面，本公开提供一种显示模组，该显示模组与N条数据线连接。该显示模组包括：N个如第三方面所述的像素电路，N为大于或等于2的整数，其中，所述N个像素电路中的每个像素电路中的发光时间控制电路与所述N条数据线中对应的一条数据线连接，所述N个像素电路中不同的发光时间控制电路与所述N条数据线中不同的数据线连接。
第七方面，本公开提供一种显示装置。该显示装置包括：如第三方面或第五方面所述的像素电路，或者如第六方面所述的显示模组。
附图说明
图1本公开的一些实施例所述的子像素电路的结构图；
图2是流过微型发光二极管的电流密度与微型发光二极管的发光效率之间的关系曲线图；
图3是本公开所述的子像素电路的具体示例的电路图；
图4是本公开的一些实施例所述的像素电路的结构图；
图5是本公开所述的像素电路的具体示例的电路图；
图6是当一个像素电路内可以容纳三条数据线时，包括三个像素电路的显示模组的具体示例的示意图；
图7是图6所示的显示模组的具体示例的工作时序图；
图8是本公开所述的像素电路的另一具体示例的电路图；
图9是图1所示的子像素电路的驱动方法的流程图；
图10是图5所示的子像素电路的驱动方法的流程图；以及
图11是本公开的像素电路的驱动方法的流程图。
具体实施方式
下面将结合本公开的一些实施例中的附图，对本公开的一些实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在相关技术中，MicroLED显示采用调节电流密度来实现不同灰阶的亮度。MicroLED在低灰阶时电流密度较低，导致发光效率也较低，进而导致发光功耗高。
本公开提供的子像素电路、像素电路及其驱动方法、显示模组和显示装置可以解决相关技术中由于通过不同电流密度驱动发光元件发出不同亮度，从而导致低灰阶时发光效率低并功耗高的问题。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开的一些实施例中，为区分晶体管的除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开提供一种子像素电路，如图1所示。本公开的一些实施例所述的子像素电路包括数据电压写入电路11、驱动电路12、存储电路13、发光时间控制电路14、发光控制电路15和发光元件EL。所述数据电压写入电路11与电压写入控制栅线V-GATE、数据线DATA和所述驱动电路12的控制端CON1连接，用于在数据电压写入阶段，在所述电压写入控制栅线V-GATE的控制下，将所述数据线DATA上的数据电压写入所述驱动电路12的控制端CON1。
所述发光时间控制电路14分别与发光时间控制栅线T-GATE、所述数据线DATA和所述发光控制电路15的控制端CON2连接，用于在发光时间控制阶段，在所述发光时间控制栅线T-GATE的控制下，将所述数据线DATA上的发光控制信号写入所述发光控制电路15的控制端CON2。
所述驱动电路12的第一端TER1与第一电压输入端连接，所述驱动电路12的第二端TER2与所述发光控制电路15的第一端TER3连接，所述发光控制电路15的第二端TER4与发光元件EL的第一极连接，所述发光元件EL的第二极与第二电压输入端连接；所述第一电压输入端用于输入第一电压V1，所述第二电压输入端用于输入第二电压V2。
所述存储电路13的第一端与所述驱动电路12的控制端CON1连接，所述存储电路13的第二端与所述第一电压输入端TER1连接，所述存储电路13 用于控制所述驱动电路12的控制端CON1的电位。
所述发光控制电路15用于在所述发光时间控制阶段包括的发光时间段，在所述发光控制信号的控制下，导通所述驱动电路12的第二端与所述发光元件EL的第一极之间的连接，以使得所述驱动电路12根据所述数据电压驱动所述发光元件EL发光。
本公开的一些实施例所述的子像素电路通过发光时间控制电路接入发光控制信号，以控制发光时间，结合数据电压和发光时间来控制发光元件的发光亮度，从而可以提升发光效率，减小功耗，并能够实现更多灰阶。
在实际操作时，所述发光元件EL可以为MicroLED(微型发光二极管)，此时，发光元件EL的第一极为阳极，发光元件的第二极为阴极，但不以此为限。在具体实施时，所述发光元件EL也可以为OLED(有机发光二极管)或其他种类的发光元件。
在实际操作时，所述第一电压V1可以为高电压，所述第二电压V2可以为低电压，但不以此为限。
在具体实施时，所述高电压可以为电压值大于3V的正电压，但不以此为限；所述低电压可以为零电压或负电压，但不以此为限。
MicroLED作为一种自发光器件，其发光效率与电流密度的关系如图2所示(横轴为电流密度，纵轴为发光效率)。在低电流密度下，MicroLED的发光效率会随着电流密度的降低而降低。因此如果采用电流密度来调制显示的灰阶，则由于低灰阶会对应低电流密度，那么MicroLED的发光效率会降低。在图2中，标号为J1的为第一电流密度，标号为J2的为第二电流密度。
在本公开的一些实施例中，控制MicroLED工作在发光效率最高区域，也即使得MicroLED的电流密度在J1和J2之间，通过电流和发光时间来共同调制灰阶。以256个灰阶为例，在高灰阶(比如L120-L255)下，通过调节电流密度来进行灰阶调制，比如，第二电流密度J2对应L255，第一电流密度J1对应L120，发光时间比例都为100％。在低灰阶(比如低于L120)下，保持电流密度J1不变，通过调节发光时间来调节灰阶，比如，L40对应的电流密度为第一电流密度J1，L40对应的发光时间比例为4.7％。其中，L120为第120灰阶，L255为第255灰阶，L40为第40灰阶。
本公开的一些实施例提供了一种适用于MicroLED的驱动方案。在该方案中，灰阶通过电流和发光时间同时调控，使得MicroLED工作在发光效率较高区间。高灰阶通过调控驱动电流实现，低灰阶通过调控发光时间实现。
本公开如图1所示的子像素电路在工作时，所述子像素电路的显示周期包括依次设置的数据电压写入阶段和发光时间控制阶段。
在数据电压写入阶段，数据电压写入电路11在电压写入控制栅线V-GATE的控制下，将数据线DATA上的数据电压写入驱动电路12的控制端CON1；存储电路13维持所述驱动电路12的控制端CON1的电位。
在发光时间控制阶段，所述存储电路13维持所述驱动电路12的控制端CON1的电位。发光时间控制电路14在发光时间控制栅线T-GATE的控制下，将所述数据线DATA上的发光控制信号写入发光控制电路15的控制端CON2。
在所述发光时间控制阶段包括的发光时间段，发光控制电路15在所述发光控制信号的控制下，控制导通驱动电路12的第二端TER2与发光元件EL的第一极TER5之间的连接，以使得所述驱动电路12根据所述数据电压驱动所述发光元件EL发光。
具体的，所述发光时间控制电路14可以包括：发光时间控制晶体管，栅极与所述发光时间控制栅线连接，第一极与所述数据线连接，第二极与所述发光控制电路的控制端连接。
具体的，所述发光控制电路可以包括发光控制晶体管；所述发光控制晶体管的栅极为所述发光控制电路的控制端，所述发光控制晶体管的第一极为所述发光控制电路的第一端，所述发光控制晶体管的第二极为所述发光控制电路的第二端。
具体的，所述数据电压写入电路可以包括数据电压写入晶体管，栅极与所述电压写入控制栅线连接，第一极与所述数据线连接，第二极与所述驱动电路的控制端连接。
在具体实施时，所述驱动电路可以包括驱动晶体管；所述驱动晶体管的栅极为所述驱动电路的控制端，所述驱动晶体管的第一极为所述驱动电路的第一端，所述驱动晶体管的第二极为所述驱动电路的第二端。
所述存储电路可以包括：存储电容，第一端与所述驱动电路的控制端连 接，第二端与所述第一电压输入端连接。
如图3所示，本公开所述的子像素电路的具体示例包括数据电压写入电路11、驱动电路12、存储电路13、发光时间控制电路14、发光控制电路15和微型发光二极管MLED。其中，所述驱动电路12包括驱动晶体管T2；所述发光控制电路15包括发光控制晶体管T3。
所述发光时间控制电路14包括：发光时间控制晶体管T4，栅极与所述发光时间控制栅线T-GATE连接，源极与数据线DATA连接，漏极与所述发光控制晶体管T3的栅极连接。
所述发光控制晶体管T3的源极与所述驱动晶体管T2的漏极连接，所述发光控制晶体管T3的漏极与所述微型发光二极管MLED的阳极连接。
所述数据电压写入电路11包括数据电压写入晶体管T1，栅极与所述电压写入控制栅线V-GATE连接，源极与所述数据线DATA连接，漏极与所述驱动晶体管T2的栅极连接。
所述驱动晶体管T2的源极接入第一电压V1。在图3所示的具体实施例中，V1为高电压VDD。
所述存储电路13包括：存储电容C，第一端与所述驱动晶体管T2的栅极连接，第二端接入所述第一电压V1。
所述微型发光二极管MLED的阴极接入第二电压V2。在图3所示的具体实施例中，V2为低电压VSS。
在图3所示的具体实施例中，T1、T2、T3和T4都为p型晶体管，但不以此为限；在实际操作时，如上晶体管也可以被替换为n型晶体管。
本公开如图3所示的子像素电路的具体实施例为4T1C子像素电路，在该电路中，T2为驱动晶体管，T1、T3和T4为开关晶体管。
当V-GATE输入低电平，T-GATE输入高电平时，T1打开，T4关闭，DATA上的控制驱动电流大小的数据电压写入N点(在图3中，N点为与T2的栅极连接的节点)，并存储于存储电容C中；
当T-GATE输入低电平，V-GATE输入高电平时，T4打开，T1关闭，DATA上的控制T3开关的发光控制信号经T4传输至T3的栅极。当所述发光控制信号为低电平时，T3打开，MLED可以发光；当所述发光控制信号为高电平 时，T3关闭，MLED不发光。
本公开的一些实施例提供一种所述子像素电路的驱动方法。该子像素电路的驱动方法应用于上述的子像素电路。所述子像素电路的显示周期包括依次设置的数据电压写入阶段和发光时间控制阶段。参考图9，所述子像素电路的驱动方法包括步骤S11-S13。
S11：在数据电压写入阶段，数据电压写入电路在电压写入控制栅线的控制下，控制数据线上的数据电压写入驱动电路的控制端；存储电路维持所述驱动电路的控制端的电位。
S12：在发光时间控制阶段，所述存储电路维持所述驱动电路的控制端的电位；发光时间控制电路在发光时间控制栅线的控制下，将所述数据线上的发光控制信号写入发光控制电路的控制端。
S13：在所述发光时间控制阶段包括的发光时间段，发光控制电路在所述发光控制信号的控制下，导通驱动电路的第二端与发光元件的第一极之间的连接，以使得所述驱动电路根据所述数据电压驱动所述发光元件发光。
本公开的一些实施例所述的子像素电路的驱动方法首先在数据电压写入阶段进行数据电压写入，再在发光时间控制阶段将数据线上的发光控制信号写入发光控制电路的控制端，以控制发光元件在发光时间段发光。
本公开的一些实施例所述的像素电路，与N条数据线连接，包括一个发光时间控制电路和N个子像素电路；N为大于或等于2的整数。
所述发光时间控制电路与发光时间控制栅线连接，所述发光控制电路的控制端和所述N条数据线中的一数据线连接，用于在发光时间控制阶段，在所述发光时间控制栅线的控制下，将该数据线上的发光控制信号写入所述N个子像素电路包括的发光控制电路的控制端。
第n子像素电路包括第n数据电压写入电路、第n驱动电路、第n存储电路、第n发光控制电路和第n发光元件；n为小于或等于N的正整数。
所述第n数据电压写入电路与电压写入控制栅线、所述第n驱动电路的控制端和所述N条数据线中的第n数据线连接，用于在数据电压写入阶段，在所述电压写入控制栅线的控制下，将所述第n数据线上的第n数据电压写入所述第n驱动电路的控制端。
所述第n驱动电路的第一端与第一电压输入端连接，所述第n驱动电路的第二端与所述第n发光控制电路的第一端连接，所述第n发光控制电路的第二端与所述第n发光元件的第一极连接，所述第n发光元件的第二极与第二电压输入端连接。
所述第n存储电路的第一端与所述第n驱动电路的控制端连接，所述第n存储电路的第二端与所述第一电压输入端连接，所述第n存储电路用于控制所述第n驱动电路的控制端的电位。
所述第n发光控制电路用于在所述发光时间控制阶段包括的发光时间段，在所述发光控制信号的控制下，导通所述第n驱动电路的第二端与所述第n发光元件的第一极之间的连接，以使得所述第n驱动电路根据所述第n数据电压驱动所述第n发光元件发光。
本公开的一些实施例所述的像素电路包括N个子像素电路以及一个发光时间控制电路，所述N个子像素电路都由该发光时间控制电路控制发光时间，从而通过一条数据线可以控制一个包括N个子像素电路的像素电路的发光时间，采用N条数据线可以控制N个上述像素电路的发光时间，可以在提升发光效率，减小功耗，并能够实现更多灰阶的同时，减少采用晶体管和数据线的个数。
下面以N等于3为例来说明本公开所述的像素电路。
如图4所示，本公开所述的像素电路包括一个发光时间控制电路40、第一子像素电路P1、第二子像素电路P2和第三子像素电路P3。
所述第一子像素电路P1为红色子像素电路、蓝色子像素电路或绿色子像素电路中的任一种，所述第二子像素电路P2为红色子像素电路、蓝色子像素电路或绿色子像素电路中的任一种，所述第三子像素电路P3为红色子像素电路、蓝色子像素电路或绿色子像素电路中的任一种。例如，所述第一子像素电路P1为红色子像素电路，所述第二子像素电路P2为蓝色子像素电路，所述第三子像素电路P3为绿色子像素电路。
所述第一子像素电路P1包括第一数据电压写入电路411、第一驱动电路412、第一存储电路413、第一发光控制电路414和第一发光元件EL1。
所述第二子像素电路P2包括第二数据电压写入电路421、第二驱动电路 422、第二存储电路423、第二发光控制电路424和第二发光元件EL2。
所述第三子像素电路P3包括第三数据电压写入电路431、第三驱动电路432、第三存储电路433、第三发光控制电路434和第三发光元件EL3。
所述发光时间控制电路40与发光时间控制栅线T-GATE、所述第一发光控制电路414的控制端、所述第二发光控制电路424的控制端、所述第三发光控制电路434的控制端和所述第一数据线DATA1连接，用于在发光时间控制阶段，在所述发光时间控制栅线T-GATE的控制下，控制将所述第一数据线DATA1上的发光控制信号分别写入所述第一发光控制电路414的控制端、所述第二发光控制电路424的控制端和所述第三发光控制电路434的控制端。
所述第一数据电压写入电路411分别与电压写入控制栅线V-GATE、所述第一驱动电路412的控制端和第一数据线DATA1连接，用于在数据电压写入阶段，在所述电压写入控制栅线V-GATE的控制下，将所述第一数据线DATA1上的第一数据电压写入所述第一驱动电路412的控制端。
所述第一驱动电路412的第一端接入第一电压V1，所述第一驱动电路412的第二端与所述第一发光控制电路414的第一端连接，所述第一发光控制电路414的第二端与所述第一发光元件EL1的第一极连接，所述第一发光元件EL1的第二极接入第二电压V2。
所述第一存储电路413的第一端与所述第一驱动电路412的控制端连接，所述第一存储电路413的第二端接入第一电压V1，所述第一存储电路413用于控制所述第一驱动电路412的控制端的电位。
所述第一发光控制电路414用于在所述发光时间控制阶段包括的发光时间段，在所述发光控制信号的控制下，导通所述第一驱动电路412的第二端与所述第一发光元件EL1的第一极之间的连接，以使得所述第一驱动电路412根据所述第一数据电压驱动所述第一发光元件EL1发光。
所述第二数据电压写入电路421与电压写入控制栅线V-GATE、所述第二驱动电路422的控制端和第二数据线DATA2连接，用于在数据电压写入阶段，在所述电压写入控制栅线V-GATE的控制下，将所述第二数据线DATA2上的第二数据电压写入所述第二驱动电路422的控制端。
所述第二驱动电路422的第一端接入第一电压V1，所述第二驱动电路 422的第二端与所述第二发光控制电路424的第一端连接，所述第二发光控制电路424的第二端与所述第二发光元件EL2的第一极连接，所述第二发光元件EL2的第二极接入第二电压V2。
所述第二存储电路423的第一端与所述第二驱动电路422的控制端连接，所述第二存储电路423的第二端接入第一电压V1，所述第二存储电路423用于控制所述第二驱动电路422的控制端的电位。
所述第二发光控制电路424用于在所述发光时间控制阶段包括的发光时间段，在所述发光控制信号的控制下，导通所述第二驱动电路422的第二端与所述第二发光元件EL2的第一极之间的连接，以使得所述第二驱动电路422根据所述第二数据电压驱动所述第二发光元件EL2发光。
所述第三数据电压写入电路431与电压写入控制栅线V-GATE、所述第三驱动电路432的控制端和第三数据线DATA3连接，用于在数据电压写入阶段，在所述电压写入控制栅线V-GATE的控制下，将所述第三数据线DATA3上的第二数据电压写入所述第三驱动电路432的控制端。
所述第三驱动电路432的第一端接入第一电压V1，所述第三驱动电路432的第二端与所述第三发光控制电路434的第一端连接，所述第三发光控制电路434的第二端与所述第三发光元件EL3的第一极连接，所述第三发光元件EL3的第二极接入第二电压V2。
所述第三存储电路433的第一端与所述第三驱动电路432的控制端连接，所述第三存储电路433的第二端接入第一电压V1，所述第三存储电路433用于控制所述第三驱动电路432的控制端的电位。
所述第三发光控制电路434用于在所述发光时间控制阶段包括的发光时间段，在所述发光控制信号的控制下，导通所述第三驱动电路432的第二端与所述第三发光元件EL3的第一极之间的连接，以使得所述第三驱动电路432根据所述第三数据电压驱动所述第三发光元件EL3发光。
在本公开如图4所示的像素电路的实施例中，采用DATA1为第一子像素电路P1、第二子像素电路P2和第三子像素电路P3提供相应的发光控制信号，也即同一像素电路中的红色子像素电路、绿色子像素电路和蓝色子像素电路采用一条数据线(在图4所示的具体实施例中，该数据线为第一数据线DATA1) 来控制发光时间，这样，三条数据线可以支持三行像素电路同时点亮，则如果一个像素电路可以容纳三条数据线，则可以同时点亮三行像素电路。
本公开的一些实施例所述的像素电路可以在保证发光效率的前提下调制出更多灰阶。例如，当流过各发光元件的驱动电流的电流密度大于等于第一电流密度J1而小于等于第二电流密度J2时，各发光元件的发光效率最高，则最高灰阶为第二电流密度J2与最高发光时间比例的结合，最低灰阶为第一电流密度J1与最少发光时间比例的结合，这种方式可以扩大最高灰阶与最低灰阶的比例，可以实现更多灰阶。
本公开如图4所示的像素电路的实施例在工作时，所述像素电路的显示周期包括依次设置的数据电压写入阶段和发光时间控制阶段。
在数据电压写入阶段，第一数据电压写入电路411在电压写入控制栅线V-GATE的控制下，将第一数据线DATA1上的第一数据电压写入第一驱动电路412的控制端，第一存储电路413控制维持第一驱动电路412的控制端的电位。第二数据电压写入电路421在电压写入控制栅线V-GATE的控制下，控制第二数据线DATA2上的第二数据电压写入第二驱动电路422的控制端，第二存储电路423控制维持第二驱动电路422的控制端的电位。第三数据电压写入电路431在电压写入控制栅线V-GATE的控制下，控制第三数据线DATA3上的第三数据电压写入第三驱动电路432的控制端，第三存储电路433控制维持第三驱动电路432的控制端的电位。
在发光时间控制阶段，所述发光时间控制电路40在发光时间控制栅线T-GATE的控制下，控制将第一数据线DATA1上的发光控制信号分别写入第一发光控制电路414的控制端、第二发光控制电路424的控制端和第三发光控制电路434的控制端。
在所述发光时间控制阶段包括的发光时间段，第一发光控制电路414在所述发光控制信号的控制下，导通所述第一驱动电路412的第二端与第一发光元件EL1的第一极之间的连接，以使得所述第一驱动电路412根据所述第一数据电压驱动所述第一发光元件EL1发光；第二发光控制电路424在所述发光控制信号的控制下，导通所述第二驱动电路422的第二端与第二发光元件EL2的第一极之间的连接，以使得所述第二驱动电路422根据所述第二数 据电压驱动所述第二发光元件EL2发光；第三发光控制电路434在所述发光控制信号的控制下，控制导通所述第三驱动电路432的第二端与第三发光元件EL3的第一极之间的连接，以使得所述第三驱动电路432根据所述第三数据电压驱动所述第三发光元件EL3发光。
具体的，所述发光时间控制电路可以包括发光时间控制晶体管。
所述发光时间控制晶体管的栅极与所述发光时间控制栅线连接，所述发光时间控制晶体管的第一极与所述N条数据线中的一数据线连接，所述发光时间控制晶体管的第二极与所述发光控制电路的控制端连接。
具体的，所述第n发光控制电路可以包括第n发光控制晶体管；
所述第n发光控制晶体管的栅极为所述第n发光控制电路的控制端，所述第n发光控制电路的第一极为所述第n发光控制电路的第一端，所述第n发光控制电路的第二极为所述第n发光控制电路的第二端。
在实际操作时，所述第n数据电压写入电路可以包括：第n数据电压写入晶体管，栅极与所述电压写入控制栅线连接，第一极与所述第n数据线连接，第二极与所述第n驱动电路的控制端连接。
在具体实施时，所述第n驱动电路可以包括第n驱动晶体管；所述第n驱动晶体管的栅极为所述第n驱动电路的控制端，所述第n驱动晶体管的第一极为所述第n驱动电路的第一端，所述第n驱动晶体管的第二极为所述第n驱动电路的第二端。
所述第n存储电路包括：第n存储电容，第一端与所述第n驱动电路的控制端连接，第二端与所述第一电压输入端连接。
如图5所示，本公开所述的像素电路的具体示例包括一个发光时间控制电路40、第一子像素电路P1、第二子像素电路P2和第三子像素电路P3。
所述发光时间控制电路40包括发光时间控制晶体管T4。
所述第一子像素电路P1包括第一数据电压写入电路、第一驱动电路、第一存储电路、第一发光控制电路和第一微型发光二极管MLED1。
所述第二子像素电路P2包括第二数据电压写入电路、第二驱动电路、第二存储电路、第二发光控制电路和第二微型发光二极管MLED2。
所述第三子像素电路P3包括第三数据电压写入电路、第三驱动电路、第 三存储电路、第三发光控制电路和第三微型发光二极管MLED3。
所述第一发光控制电路包括第一发光控制晶体管T13，所述第一数据电压写入电路包括第一数据电压写入晶体管T11，所述第一驱动电路包括第一驱动晶体管T12，所述第一存储电路包括第一存储电容C1。
所述第二发光控制电路包括第二发光控制晶体管T23，所述第二数据电压写入电路包括第二数据电压写入晶体管T21，所述第二驱动电路包括第二驱动晶体管T22，所述第二存储电路包括第二存储电容C2。
所述第三发光控制电路包括第三发光控制晶体管T33，所述第三数据电压写入电路包括第三数据电压写入晶体管T31，所述第三驱动电路包括第三驱动晶体管T32，所述第三存储电路包括第三存储电容C3。
所述发光时间控制晶体管T4的栅极与所述发光时间控制栅线T-GATE连接，所述发光时间控制晶体管T4的源极与第一数据线DATA1连接，所述发光时间控制晶体管T4的漏极与所述第一发光控制晶体管T13的栅极、所述第二发光控制晶体管T23的栅极和所述第三发光控制晶体管T33的栅极连接。
所述第一数据电压写入晶体管T11的栅极与电压写入控制栅线V-GATE连接，所述第一数据电压写入晶体管T11的源极与第一数据线DATA1连接，所述第一数据电压写入晶体管T11的漏极与所述第一驱动晶体管T12的栅极连接。
所述第一驱动晶体管T12的源极接入第一电压V1，所述第一驱动晶体管T12的漏极与所述第一发光控制晶体管T13的源极连接；在本具体示例中，V1为高电压VDD，但不以此为限。
所述第一发光控制晶体管T13的漏极与所述第一微型发光二极管MLED1的阳极连接，所述第一微型发光二极管MLED1的阴极接入第二电压V2。在本具体示例中，V2为低电压VSS，但不以此为限。
所述第一存储电容C1的第一端与所述第一驱动晶体管T12的栅极连接，所述第一存储电容C1的第二端接入所述第一电压V1。
所述第二数据电压写入晶体管T21的栅极与电压写入控制栅线V-GATE连接，所述第二数据电压写入晶体管T21的源极与第二数据线DATA2连接，所述第二数据电压写入晶体管T21的漏极与所述第二驱动晶体管T22的栅极 连接。
所述第二驱动晶体管T22的源极接入第一电压V1，所述第二驱动晶体管T22的漏极与所述第二发光控制晶体管T23的源极连接；在本具体示例中，V1为高电压VDD，但不以此为限。
所述第二发光控制晶体管T23的漏极与所述第二微型发光二极管MLED2的阳极连接，所述第二微型发光二极管MLED2的阴极接入第二电压V2；在本具体示例中，V2为低电压VSS，但不以此为限。
所述第二存储电容C2的第一端与所述第二驱动晶体管T22的栅极连接，所述第二存储电容C2的第二端接入所述第一电压V1。
所述第三数据电压写入晶体管T31的栅极与电压写入控制栅线V-GATE连接，所述第三数据电压写入晶体管T31的源极与第三数据线DATA3连接，所述第三数据电压写入晶体管T31的漏极与所述第三驱动晶体管T32的栅极连接。
所述第三驱动晶体管T32的源极接入第一电压V1，所述第三驱动晶体管T32的漏极与所述第三发光控制晶体管T33的源极连接；在本具体实施例中，V1为高电压VDD，但不以此为限。
所述第三发光控制晶体管T33的漏极与所述第三微型发光二极管MLED3的阳极连接，所述第三微型发光二极管MLED3的阴极接入第二电压V2；在本具体示例中，V2为低电压VSS，但不以此为限。
所述第三存储电容C3的第一端与所述第三驱动晶体管T32的栅极连接，所述第三存储电容C3的第二端接入所述第一电压V1。
在图5所示的像素电路的具体示例中，所有的晶体管都为p型晶体管，但不以此为限。也可以根据需要将P型晶体管替换为N型晶体管。
参考图10，本公开如图5所示的像素电路的具体示例的驱动方法包括以下步骤S21-S23。
S21：在数据电压写入阶段，V-GATE输出低电平，T-GATE输出高电平，DATA1输出第一数据电压，DATA2输出第二数据电压，DATA3输出第三数据电压，T11、T21和T31都打开，T4关闭，将第一数据电压写入T12的栅极，将第二数据电压写入T22的栅极，将第三数据电压写入T32的栅极，C1 维持T12的栅极的电位，C2维持T22的栅极的电位，C3维持T32的栅极的电位。
S22：在发光时间控制阶段，V-GATE输出高电平，T-GATE输出低电平，DATA1输入发光控制信号，T11、T21和T31都关闭，T4打开，将所述发光控制信号分别写入T13的栅极、T23的栅极和T33的栅极。
S23：在发光时间控制阶段包括的发光时间段，所述发光控制信号为低电平，T13、T23和T33打开，T12驱动MLED1发光，T22驱动MLED2发光，T23驱动MLED3发光。
发光控制信号的脉冲宽度决定了发光时间的长短，各数据电压与发光时间一起决定了各微型发光二极管的发光亮度。
图6示出了当一个像素电路内可以容纳三条数据线时，包括三个像素电路的显示模组的一具体示例的示意图。
如图6所示，标号为V-GATE(M)的为第M行电压写入控制栅线，标号为T-GATE(M)的为第M行发光时间控制栅线，标号为V-GATE(M+1)的为第M+1行电压写入控制栅线，标号为T-GATE(M+1)的为第M+1行发光时间控制栅线，标号为V-GATE(M+2)的为第M+2行电压写入控制栅线，标号为T-GATE(M+2)的为第M+2行发光时间控制栅线；M为正整数。
在图6中，标号为T14的为第一发光时间控制晶体管，标号为T24的为第二发光时间控制晶体管，T34的为第三发光时间控制晶体管。
T14的源极与第一数据线DATA1连接，T24的源极与第二数据线DATA2连接，T34的源极与第三数据线DATA3连接。
标号为T11的为第M行第一列数据电压写入晶体管，标号为T12的为第M行第一列驱动晶体管，标号为T13的为第M行第一列发光控制晶体管，标号为C1的为第M行第一列存储电容；标号为T21的为第M行第二列数据电压写入晶体管，标号为T22的为第M行第二列驱动晶体管，标号为T23的为第M行第二列发光控制晶体管，标号为C2的为第M行第二列存储电容；标号为T31的为第M行第三列数据电压写入晶体管，标号为T32的为第M行第三列驱动晶体管，标号为T33的为第M行第三列发光控制晶体管，标号为C3的为第M行第三列存储电容。
标号为T41的为第M+1行第一列数据电压写入晶体管，标号为T42的为第M+1行第一列驱动晶体管，标号为T43的为第M+1行第一列发光控制晶体管，标号为C4的为第M+1行第一列存储电容；标号为T51的为第M+1行第二列数据电压写入晶体管，标号为T52的为第M+1行第二列驱动晶体管，标号为T53的为第M+1行第二列发光控制晶体管，标号为C5的为第M+1行第二列存储电容；标号为T61的为第M+1行第三列数据电压写入晶体管，标号为T62的为第M+1行第三列驱动晶体管，标号为T63的为第M+1行第三列发光控制晶体管，标号为C6的为第M+1行第三列存储电容。
标号为T71的为第M+2行第一列数据电压写入晶体管，标号为T72的为第M+2行第一列驱动晶体管，标号为T73的为第M+2行第一列发光控制晶体管，标号为C7的为第M+2行第一列存储电容；标号为T81的为第M+2行第二列数据电压写入晶体管，标号为T82的为第M+2行第二列驱动晶体管，标号为T83的为第M+2行第二列发光控制晶体管，标号为C8的为第M+2行第二列存储电容；标号为T91的为第M+2行第三列数据电压写入晶体管，标号为T92的为第M+2行第三列驱动晶体管，标号为T93的为第M+2行第三列发光控制晶体管，标号为C9的为第M+2行第三列存储电容。
如图7所示，在数据电压写入阶段S1，T-GATE(M)、T-GATE(M+1)和T-GATE(M+2)都输出高电平。
在数据电压写入阶段S1包括的第M数据电压写入时间段t1，V-GATE(M)输出低电平，V-GATE(M+1)和V-GATE(M+2)都输出高电平，DATA1输出的第一数据电压通过导通的T11写入T12的栅极，DATA2输出的第二数据电压通过导通的T21写入T22的栅极，DATA3输出的第三数据电压通过导通的T31写入T32的栅极。
在S1包括的第M+1数据电压写入时间段t2，V-GATE(M+1)输出低电平，V-GATE(M)和V-GATE(M+2)都输出高电平，DATA1输出的第一数据电压通过导通的T41写入T42的栅极，DATA2输出的第二数据电压通过导通的T51写入T52的栅极，DATA3输出的第三数据电压通过导通的T61写入T62的栅极。
在S1包括的第M+2数据电压写入时间段t3，V-GATE(M+2)输出低电平， V-GATE(M)和V-GATE(M+1)都输出高电平，DATA1输出的第一数据电压通过导通的T71写入T72的栅极，DATA2输出的第二数据电压通过导通的T81写入T82的栅极，DATA3输出的第三数据电压通过导通的T91写入T92的栅极。
在发光时间控制阶段S2，V-GATE(M)、V-GATE(M+1)和V-GATE(M+2)都输出高电平，T-GATE(M)、T-GATE(M+1)和T-GATE(M+2)都输出低电平，以将DATA1上的第一发光控制信号分别写入T12的栅极、T22的栅极和T32的栅极，以使得MLED1、MLED2和MLED3在S2包括的第一发光时间段发光(所述第一发光时间段持续的时间为所述第一发光控制信号为低电平的时间)；将DATA2上的第二发光控制信号分别写入T42的栅极、T52的栅极和T62的栅极，以使得MLED4、MLED5和MLED6在S2包括的第二发光时间段发光(所述第二发光时间段持续的时间为所述第二发光控制信号为低电平的时间)；将DATA3上的第三发光控制信号分别写入T72的栅极、T82的栅极和T92的栅极，以使得MLED7、MLED8和MLED9在S2包括的第三发光时间段发光(所述第三发光时间段持续的时间为所述第三发光控制信号为低电平的时间)。
本公开的一些实施例所述的像素电路的驱动方法，应用于上述的像素电路，所述像素电路的显示周期包括依次设置的数据电压写入阶段和发光时间控制阶段。参考图11，所述像素电路的驱动方法包括步骤S31-S33。
S31：在数据电压写入阶段，第n数据电压写入电路在电压写入控制栅线的控制下，控制第n数据线上的第n数据电压写入第n驱动电路的控制端；第n存储电路控制维持第n驱动电路的控制端的电位。
S32：在发光时间控制阶段，所述发光时间控制电路在发光时间控制栅线的控制下，控制将N条数据线中的一条数据线上的发光控制信号写入N个子像素电路包括的发光控制电路的控制端。
S33：在所述发光时间控制阶段包括的发光时间段，第n发光控制电路在所述发光控制信号的控制下，控制导通所述第n驱动电路的第二端与第n发光元件的第一极之间的连接，以使得所述第n驱动电路根据所述第n数据电压驱动所述第n发光元件发光，其中N为大于或等于2的整数，n为小于或 等于N的正整数。
本公开的一些实施例所述的像素电路，与N条数据线连接，包括N个上述的子像素电路；N为大于或等于2的整数；每一所述子像素电路中的所述发光时间控制电路分别与所述N条数据线中的一条数据线对应连接。
如图8所示，本公开所述的像素电路的另一具体示例包括第一子像素电路P4、第二子像素电路P5和第三子像素电路P6。第一子像素电路P4、第二子像素电路P5或第三子像素电路P6中的每个可以是红色子像素电路、绿色子像素电路或蓝色子像素中的一个。例如，第一子像素电路P4可以是红色子像素电路，第二子像素电路P5可以是绿色子像素电路，第三子像素电路P6可以是蓝色子像素电路。
所述第一子像素电路P4的结构、所述第二子像素电路P5的结构和所述第三子像素电路P6的结构与图3所示的子像素电路的结构相同。
所述第一子像素电路P4包括第一数据电压写入晶体管T11、第一驱动晶体管T12、第一存储电容C1、第一发光时间控制晶体管T14和第一发光控制晶体管T13；T14的源极与第一数据线DATA1连接。
所述第二子像素电路P5包括第二数据电压写入晶体管T21、第二驱动晶体管T22、第二存储电容C2、第二发光时间控制晶体管T24和第二发光控制晶体管T23；T24的源极与第二数据线DATA2连接。
所述第三子像素电路P6包括第三数据电压写入晶体管T31、第三驱动晶体管T32、第三存储电容C3、第三发光时间控制晶体管T34和第三发光控制晶体管T33；T34的源极与第三数据线DATA3连接。
在图8中，标号为MLED1的为第一微型发光二极管，标号为MLED2的为第二微型发光二极管，标号为MLED3的为第三微型发光二极管，标号为DATA1的为第一数据线，标号为DATA2的为第二数据线，标号为DATA3的为第三数据线，标号为V-GATE的为电压写入控制栅线，标号为T-GATE的为发光时间控制栅线。
在图8所示的具体示例中，所有的晶体管都为p型晶体管，但不以此为限；在实际操作时，如上晶体管也可以被替换为n型晶体管。
本公开的一些实施例所述的显示装置包括上述的像素电路。
本公开的一些实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
与相关技术相比，本公开所述的子像素电路、像素电路及其驱动方法和显示装置通过发光时间控制电路接入发光控制信号，以控制发光时间，结合数据电压和发光时间来控制发光元件的发光亮度，从而可以提升发光效率，减小功耗。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种子像素电路，包括：
    数据电压写入电路、驱动电路、存储电路、发光时间控制电路、发光控制电路和发光元件，其中，
    所述数据电压写入电路与电压写入控制端、第一数据信号端和所述驱动电路的控制端连接，用于在数据电压写入阶段，在所述电压写入控制端的控制下，将数据电压从所述第一数据信号端写入所述驱动电路的控制端；
    所述发光时间控制电路与发光时间控制端、第二数据信号端和所述发光控制电路的控制端连接，用于在发光时间控制阶段，在所述发光时间控制端的控制下，将发光控制信号从所述第二数据信号端写入所述发光控制电路的控制端；
    所述驱动电路的第一端与第一电压输入端连接，所述驱动电路的第二端与所述发光控制电路的第一端连接，所述发光控制电路的第二端与发光元件的第一极连接，所述发光元件的第二极与第二电压输入端连接；
    所述存储电路的第一端与所述驱动电路的控制端连接，所述存储电路的第二端与所述第一电压输入端连接，所述存储电路用于控制所述驱动电路的控制端的电位；
    所述发光控制电路用于在所述发光时间控制阶段包括的发光时间段，在所述发光控制信号的控制下，导通所述驱动电路的第二端与所述发光元件的第一极之间的连接，以使得所述驱动电路根据所述数据电压驱动所述发光元件发光。
  2. 如权利要求1所述的子像素电路，其中，所述发光时间控制电路包括：发光时间控制晶体管，所述发光时间控制晶体管的栅极与所述发光时间控制端连接，第一极与所述第二数据信号端连接，第二极与所述发光控制电路的控制端连接。
  3. 如权利要求1或2所述的子像素电路，其中，所述发光控制电路包括发光控制晶体管；
    所述发光控制晶体管的栅极为所述发光控制电路的控制端，所述发光控 制晶体管的第一极为所述发光控制电路的第一端，所述发光控制晶体管的第二极为所述发光控制电路的第二端。
  4. 如权利要求1至3中任一项所述的子像素电路，其中，所述数据电压写入电路包括数据电压写入晶体管，所述数据电压写入晶体管的栅极与所述电压写入控制端连接，第一极与所述第一数据信号端连接，第二极与所述驱动电路的控制端连接。
  5. 如权利要求1至4中任一项所述的子像素电路，其中，所述驱动电路包括驱动晶体管；所述驱动晶体管的栅极为所述驱动电路的控制端，所述驱动晶体管的第一极为所述驱动电路的第一端，所述驱动晶体管的第二极为所述驱动电路的第二端；
    所述存储电路包括存储电容，所述存储电容的第一端与所述驱动电路的控制端连接，第二端与所述第一电压输入端连接。
  6. 一种子像素电路的驱动方法，应用于如权利要求1至5中任一权利要求所述的子像素电路，所述子像素电路的显示周期包括依次设置的数据电压写入阶段和发光时间控制阶段，所述子像素电路的驱动方法包括：
    在所述数据电压写入阶段，所述数据电压写入电路在所述电压写入控制端的控制下，将所述数据电压从所述第一数据信号端写入所述驱动电路的控制端；所述存储电路维持所述驱动电路的控制端的电位；
    在所述发光时间控制阶段，所述存储电路维持所述驱动电路的控制端的电位；发光时间控制电路在所述发光时间控制端的控制下，将所述发光控制信号从所述第二数据信号端写入所述发光控制电路的控制端；
    在所述发光时间控制阶段包括的所述发光时间段，所述发光控制电路在所述发光控制信号的控制下，导通所述驱动电路的第二端与所述发光元件的第一极之间的连接，以使得所述驱动电路根据所述数据电压驱动所述发光元件发光。
  7. 一种像素电路，与N条数据线连接，包括：
    一个发光时间控制电路和N个子像素电路；N为大于或等于2的整数；
    所述发光时间控制电路与发光时间控制栅线、所述N个子像素电路包括的发光控制电路的控制端和所述N条数据线中的一条数据线连接，用于在发 光时间控制阶段，在所述发光时间控制栅线的控制下，将该所述一条数据线上的发光控制信号写入所述N个子像素电路包括的所述发光控制电路的控制端；
    第n子像素电路包括第n数据电压写入电路、第n驱动电路、第n存储电路、第n发光控制电路和第n发光元件；n为小于或等于N的正整数；
    所述第n数据电压写入电路与电压写入控制栅线、所述第n驱动电路的控制端和所述N条数据线中的第n数据线连接，用于在数据电压写入阶段，在所述电压写入控制栅线的控制下，将所述第n数据线上的第n数据电压写入所述第n驱动电路的控制端；
    所述第n驱动电路的第一端与第一电压输入端连接，所述第n驱动电路的第二端与所述第n发光控制电路的第一端连接，所述第n发光控制电路的第二端与所述第n发光元件的第一极连接，所述第n发光元件的第二极与第二电压输入端连接；
    所述第n存储电路的第一端与所述第n驱动电路的控制端连接，所述第n存储电路的第二端与所述第一电压输入端连接，所述第n存储电路用于控制所述第n驱动电路的控制端的电位；
    所述第n发光控制电路用于在所述发光时间控制阶段包括的发光时间段，在所述发光控制信号的控制下，导通所述第n驱动电路的第二端与所述第n发光元件的第一极之间的连接，以使得所述第n驱动电路根据所述第n数据电压驱动所述第n发光元件发光。
  8. 如权利要求7所述的像素电路，其中，所述发光时间控制电路包括发光时间控制晶体管；
    所述发光时间控制晶体管的栅极与所述发光时间控制栅线连接，所述发光时间控制晶体管的第一极与所述N条数据线中的所述一条数据线连接，所述发光时间控制晶体管的第二极与所述发光控制电路的控制端连接。
  9. 如权利要求7或8所述的像素电路，其中，所述第n发光控制电路包括第n发光控制晶体管；
    所述第n发光控制晶体管的栅极为所述第n发光控制电路的控制端，所述第n发光控制电路的第一极为所述第n发光控制电路的第一端，所述第n 发光控制电路的第二极为所述第n发光控制电路的第二端。
  10. 如权利要求7-9中的任一项所述的像素电路，其中，所述第n数据电压写入电路包括第n数据电压写入晶体管，栅极与所述电压写入控制栅线连接，第一极与所述第n数据线连接，第二极与所述第n驱动电路的控制端连接。
  11. 如权利要求7-10中任一项所述的像素电路，其中，所述第n驱动电路包括第n驱动晶体管；
    所述第n驱动晶体管的栅极为所述第n驱动电路的控制端，所述第n驱动晶体管的第一极为所述第n驱动电路的第一端，所述第n驱动晶体管的第二极为所述第n驱动电路的第二端；
    所述第n存储电路包括：第n存储电容，第一端与所述第n驱动电路的控制端连接，第二端与所述第一电压输入端连接。
  12. 一种像素电路的驱动方法，应用于如权利要求7至11中任一项所述的像素电路，其中，所述像素电路的显示周期包括依次设置的数据电压写入阶段和发光时间控制阶段；所述像素电路的驱动方法包括：
    在所述数据电压写入阶段，第n数据电压写入电路在所述电压写入控制栅线的控制下，将第n数据线上的第n数据电压写入第n驱动电路的控制端；第n存储电路维持第n驱动电路的控制端的电位；
    在所述发光时间控制阶段，所述发光时间控制电路在所述发光时间控制栅线的控制下，将N条数据线中的一条数据线上的发光控制信号写入N个子像素电路包括的发光控制电路的控制端；
    在所述发光时间控制阶段包括的发光时间段，第n发光控制电路在所述发光控制信号的控制下，导通所述第n驱动电路的第二端与第n发光元件的第一极之间的连接，以使得所述第n驱动电路根据所述第n数据电压驱动所述第n发光元件发光；
    N为大于或等于2的整数，n为小于或等于N的正整数。
  13. 一种像素电路，与N条数据线连接，包括：
    N个如权利要求1至5中任一项所述的子像素电路，N为大于或等于2的整数，
    其中，所述N个子像素电路中的每个子像素电路中所述发光时间控制电路分别与所述N条数据线中对应的一条数据线连接。
  14. 一种显示模组，与N条数据线连接，包括：
    N个如权利要求7至11中任一项所述的像素电路，N为大于或等于2的整数，
    其中，所述N个像素电路中的每个像素电路中的发光时间控制电路与所述N条数据线中对应的一条数据线连接，所述N个像素电路中不同的发光时间控制电路与所述N条数据线中不同的数据线连接。
  15. 一种显示装置，包括：
    如权利要求7、8、9、10、11、13中任一项所述的像素电路，或者
    如权利要求14所述的显示模组。
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