WO2021102906A1 - 像素驱动电路及其驱动方法和显示装置 - Google Patents

像素驱动电路及其驱动方法和显示装置 Download PDF

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Publication number
WO2021102906A1
WO2021102906A1 PCT/CN2019/121957 CN2019121957W WO2021102906A1 WO 2021102906 A1 WO2021102906 A1 WO 2021102906A1 CN 2019121957 W CN2019121957 W CN 2019121957W WO 2021102906 A1 WO2021102906 A1 WO 2021102906A1
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Prior art keywords
circuit
control
sub
light
electrically connected
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PCT/CN2019/121957
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English (en)
French (fr)
Inventor
玄明花
陈小川
刘冬妮
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/121957 priority Critical patent/WO2021102906A1/zh
Priority to US16/977,220 priority patent/US11508289B2/en
Priority to KR1020217035404A priority patent/KR20220106678A/ko
Priority to JP2021564462A priority patent/JP7414204B2/ja
Priority to EP19945419.0A priority patent/EP4068257B1/en
Priority to CN201980002679.9A priority patent/CN113196372B/zh
Publication of WO2021102906A1 publication Critical patent/WO2021102906A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a driving method thereof, and a display device.
  • micro-light-emitting diodes are considered to be the next-generation display panel technology due to their low driving voltage, ultra-high brightness, long life, and high temperature resistance.
  • Related pixel driving circuits for driving micro-light-emitting diodes have the problems of color coordinate shift of micro-light-emitting diodes under different currents and unstable brightness at low current densities.
  • an embodiment of the present disclosure provides a pixel drive circuit.
  • the pixel drive circuit includes a light-emission time control sub-circuit, a first energy storage sub-circuit, a first reset sub-circuit, a first light-emission control sub-circuit, and a time Control data writing sub-circuit and data control sub-circuit;
  • the first reset sub-circuit is connected to the reset control line, the first initial voltage terminal, the first terminal of the light-emitting time control sub-circuit, the control terminal of the light-emitting time control sub-circuit and the light-emitting time control sub-circuit.
  • the second terminal is electrically connected, and is used to write the first initial voltage provided by the first initial voltage terminal into the first terminal of the light-emitting time control sub-circuit under the control of the reset control signal provided by the reset control line , And controlling the electrical connection between the control terminal of the light-emitting time control sub-circuit and the second terminal of the light-emitting time control sub-circuit under the control of the reset control signal;
  • the first end of the first energy storage sub-circuit is electrically connected to the control end of the light-emitting time control sub-circuit; the first energy storage sub-circuit is used for storing voltage;
  • the time control data writing sub-circuit is electrically connected to the first gate line, the time control data line, and the second end of the first energy storage sub-circuit, respectively, for the first gate line provided on the first gate line. Controlling the electrical connection between the time control data line and the second end of the first energy storage sub-circuit under the control of the pole drive signal;
  • the data control sub-circuit is electrically connected to the light-emitting control line, the time control data line, and the second end of the first energy storage sub-circuit, and is used to control the light-emitting control signal provided by the light-emitting control line. , Controlling the electrical connection between the time control data line and the second end of the first energy storage sub-circuit;
  • the first lighting control sub-circuit is electrically connected to the lighting control line, the first terminal and the first voltage terminal of the lighting time control sub-circuit, and is used to control the lighting control signal under the control of the lighting control signal.
  • the second terminal of the light-emitting time control sub-circuit is electrically connected to the output terminal, and the light-emitting time control sub-circuit is used to control the first terminal of the light-emitting time control sub-circuit and the output terminal under the control of the potential of the control terminal.
  • the second ends of the light-emitting time control sub-circuit are electrically connected.
  • the pixel driving circuit described in at least one embodiment of the present disclosure further includes a second light-emitting control sub-circuit;
  • the second lighting control sub-circuit is electrically connected to the lighting control line, the second terminal of the lighting time control sub-circuit, and the output terminal, respectively, for controlling the lighting control signal under the control of the lighting control signal.
  • the second terminal of the light-emitting time control sub-circuit is electrically connected to the output terminal.
  • the light-emitting time control sub-circuit includes a light-emitting time control transistor
  • the control terminal of the emission time control transistor is the control terminal of the emission time control sub-circuit
  • the first terminal of the emission time control transistor is the first terminal of the emission time control sub-circuit
  • the first terminal of the emission time control transistor is The second pole is the second end of the light-emitting time control sub-circuit.
  • the first reset sub-circuit includes a first reset transistor and a second reset transistor
  • the control electrode of the first reset transistor is electrically connected to the reset control line, the first electrode of the first reset transistor is electrically connected to the control terminal of the light-emitting time control sub-circuit, and the first electrode of the first reset transistor is electrically connected to the control terminal of the light-emitting time control sub-circuit.
  • the two poles are electrically connected to the second end of the light-emitting time control sub-circuit;
  • the control electrode of the second reset transistor is electrically connected to the reset control line
  • the first electrode of the second reset transistor is electrically connected to the first end of the light-emitting time control sub-circuit
  • the second reset transistor The second pole is connected to the first initial voltage terminal; the first initial voltage terminal is used to provide the first initial voltage.
  • the time control data writing sub-circuit includes a time control data writing transistor
  • the control electrode of the time control data writing transistor is electrically connected to the first gate line
  • the first electrode of the time control data writing transistor is electrically connected to the time control data line
  • the second pole of the transistor is electrically connected to the second end of the first energy storage sub-circuit.
  • the data control sub-circuit includes a data control transistor; the first energy storage sub-circuit includes a time control capacitor;
  • the control electrode of the data control transistor is electrically connected to the light-emitting control line, the first electrode of the data control transistor is electrically connected to the time control data line, and the second electrode of the data control transistor is electrically connected to the first The second end of the energy storage sub-circuit is electrically connected;
  • the first end of the first energy storage sub-circuit is the first end of the time control capacitor, and the second end of the first energy storage sub-circuit is the second end of the time control capacitor.
  • the first light emission control sub-circuit includes a first light emission control transistor
  • the control electrode of the first light emission control transistor is electrically connected to the light emission control line
  • the first electrode of the first light emission control transistor is electrically connected to the first voltage terminal
  • the second electrode of the first light emission control transistor is electrically connected to the first voltage terminal.
  • the pole is electrically connected to the first end of the light-emitting time control sub-circuit.
  • the second light-emission control sub-circuit includes a second light-emission control transistor
  • the control electrode of the second light emission control transistor is electrically connected to the light emission control line
  • the first electrode of the second light emission control transistor is electrically connected to the second end of the light emission time control sub-circuit
  • the second light emission The second pole of the control transistor is electrically connected to the output terminal.
  • the light-emitting time control sub-circuit includes a light-emitting time control transistor;
  • the first reset sub-circuit includes a first reset transistor and a second reset transistor;
  • the time control data writing sub-circuit includes a time control data writing A transistor;
  • the data control sub-circuit includes a data control transistor;
  • the first light-emission control sub-circuit includes a first light-emission control transistor;
  • the first energy storage sub-circuit includes a time control capacitor;
  • the control terminal of the emission time control transistor is the control terminal of the emission time control sub-circuit, the first terminal of the emission time control transistor is the first terminal of the emission time control sub-circuit, and the first terminal of the emission time control transistor is A second pole of the second end of the light-emitting time control sub-circuit;
  • the control electrode of the first reset transistor is electrically connected to the reset control line, the first electrode of the first reset transistor is electrically connected to the control terminal of the light-emitting time control sub-circuit, and the first electrode of the first reset transistor is electrically connected to the control terminal of the light-emitting time control sub-circuit.
  • the two poles are electrically connected to the second end of the light-emitting time control sub-circuit;
  • the control electrode of the second reset transistor is electrically connected to the reset control line
  • the first electrode of the second reset transistor is electrically connected to the first end of the light-emitting time control sub-circuit
  • the second reset transistor The second pole is connected to the first initial voltage terminal; the first initial voltage terminal is used to provide the first initial voltage;
  • the control electrode of the time control data writing transistor is electrically connected to the first gate line, the first electrode of the time control data writing transistor is electrically connected to the time control data line, and the time control data writing
  • the second electrode of the transistor is electrically connected to the second end of the first energy storage sub-circuit
  • the control electrode of the data control transistor is electrically connected to the light-emitting control line, the first electrode of the data control transistor is electrically connected to the time control data line, and the second electrode of the data control transistor is electrically connected to the first The second end of the energy storage sub-circuit is electrically connected;
  • the control electrode of the first light emission control transistor is electrically connected to the light emission control line, the first electrode of the first light emission control transistor is electrically connected to the first voltage terminal, and the second electrode of the first light emission control transistor is electrically connected to the first voltage terminal.
  • the pole is electrically connected to the first end of the light-emitting time control sub-circuit;
  • the first end of the first energy storage sub-circuit is the first end of the time control capacitor, and the second end of the first energy storage sub-circuit is the second end of the time control capacitor.
  • the pixel driving circuit described in at least one embodiment of the present disclosure further includes a second light-emitting control sub-circuit;
  • the second light-emission control sub-circuit includes a second light-emission control transistor
  • the control electrode of the second light emission control transistor is electrically connected to the light emission control line
  • the first electrode of the second light emission control transistor is electrically connected to the second end of the light emission time control sub-circuit
  • the second light emission The second pole of the control transistor is electrically connected to the output terminal.
  • the pixel driving circuit described in at least one embodiment of the present disclosure further includes a current driving sub-circuit
  • the current driving sub-circuit is connected between the second terminal of the light-emitting time control sub-circuit and the output terminal.
  • the current driving sub-circuit is also electrically connected to the current control data line and the output terminal, respectively.
  • the current driving sub-circuit is used to generate a driving current output to the output terminal according to the current control data voltage provided by the current control data line during the light-emitting phase.
  • the current driving sub-circuit includes a driving sub-circuit, a current control data writing sub-circuit, a second reset sub-circuit, a compensation sub-circuit, and a second energy storage sub-circuit;
  • the first end of the driving sub-circuit is electrically connected to the second end of the light-emitting time control sub-circuit, and the second end of the driving sub-circuit is electrically connected to the output end;
  • the driving sub-circuit is used for Controlling the electrical connection between the first end of the driving sub-circuit and the second end of the driving sub-circuit under the control of the potential of the control terminal;
  • the first end of the second energy storage sub-circuit is electrically connected to the control end of the driving sub-circuit, the second end of the second energy storage sub-circuit is electrically connected to the second voltage end, and the second energy storage sub-circuit is electrically connected to the second voltage end.
  • the sub-circuit is used to store voltage
  • the current control data writing sub-circuit is electrically connected to the first end of the second gate line, the current control data line, and the driving sub-circuit, respectively, for the second gate provided on the second gate line Under the control of the driving signal, controlling the electrical connection between the current control data line and the first end of the driving sub-circuit;
  • the second reset sub-circuit is electrically connected to the reset control line, the second initial voltage terminal, and the control terminal of the drive sub-circuit, and is used to control the reset control signal input by the reset control line.
  • the second initial voltage provided by the second initial voltage terminal is provided to the control terminal of the driving sub-circuit;
  • the compensation sub-circuit is electrically connected to the second gate line, the control terminal of the driving sub-circuit, and the second terminal of the driving sub-circuit, respectively, for under the control of the second gate driving signal, Control the electrical connection between the control terminal of the driver sub-circuit and the second terminal of the driver sub-circuit.
  • the pixel driving circuit further includes a second light-emitting control sub-circuit; the first terminal of the driving sub-circuit is electrically connected to the second terminal of the light-emitting time control sub-circuit through the second light-emitting control sub-circuit ;
  • the control terminal of the second lighting control sub-circuit is electrically connected to the lighting control line
  • the first terminal of the second lighting control sub-circuit is electrically connected to the second terminal of the lighting time control sub-circuit
  • the first terminal is electrically connected to the second terminal of the lighting time control sub-circuit.
  • the second end of the second light-emitting control sub-circuit is electrically connected to the driving sub-circuit; the second light-emitting control sub-circuit is used to control the light-emitting time control sub-circuit under the control of the light-emitting control signal provided by the light-emitting control line
  • the second end of the circuit is electrically connected to the driving sub-circuit.
  • the pixel driving circuit described in at least one embodiment of the present disclosure further includes a third light-emitting control sub-circuit;
  • the second end of the driving sub-circuit is electrically connected to the output end through the third light-emitting control sub-circuit;
  • the control terminal of the third lighting control sub-circuit is electrically connected to the lighting control line, and the third lighting control sub-circuit is used to control the driver under the control of the lighting control signal provided by the lighting control line.
  • the second end of the circuit is electrically connected to the output end.
  • the driving sub-circuit includes a driving transistor; the second energy storage sub-circuit includes a current control capacitor; the current-controlled data writing sub-circuit includes a current-controlled data writing transistor; the second reset sub-circuit Including a third reset transistor; the compensation sub-circuit includes a compensation transistor;
  • the control electrode of the drive transistor is electrically connected to the first end of the current control capacitor, the first electrode of the drive transistor is electrically connected to the second end of the light-emitting time control sub-circuit, and the second end of the drive transistor is electrically connected.
  • the pole is electrically connected to the output terminal;
  • the control electrode of the current control data writing transistor is electrically connected to the second gate line, the first electrode of the current control data writing transistor is electrically connected to the current control data line, and the current control data writing The second electrode of the transistor is electrically connected to the first end of the driving sub-circuit;
  • the control electrode of the third reset transistor is electrically connected to the reset control line, the first electrode of the third reset transistor is electrically connected to the second initial voltage terminal, and the second electrode of the third reset transistor is electrically connected to the The control terminal of the driving sub-circuit is electrically connected;
  • the control electrode of the compensation transistor is electrically connected to the second gate line
  • the first electrode of the compensation transistor is electrically connected to the control terminal of the driving sub-circuit
  • the second electrode of the compensation transistor is electrically connected to the control terminal of the driving sub-circuit. The second end is electrically connected.
  • the third light-emission control sub-circuit includes a third light-emission control transistor
  • the control electrode of the third light-emission control transistor is electrically connected to the light-emission control line
  • the first electrode of the third light-emission control transistor is electrically connected to the second end of the driving sub-circuit
  • the first electrode of the third light-emission control transistor The two poles are electrically connected to the output terminal.
  • the pixel driving circuit is used to drive a light-emitting element
  • the output terminal is electrically connected to the first pole of the light-emitting element
  • the second pole of the light-emitting element is electrically connected to the third voltage terminal.
  • the light emitting element is a micro light emitting diode.
  • the embodiments of the present disclosure also provide a pixel driving method, which is applied to the above-mentioned pixel driving circuit, and the pixel driving method includes:
  • An on signal is provided to the light-emitting control line, so that the first terminal of the light-emitting time control sub-circuit is electrically connected to the first voltage terminal, and the time control data line and the second terminal of the first energy storage sub-circuit are electrically connected. Is electrically connected to each other to change the voltage of the first terminal of the first energy storage sub-circuit accordingly, so that the first terminal of the light-emitting time control sub-circuit is electrically connected to the second terminal of the light-emitting time control sub-circuit. Connect or disconnect.
  • the pixel drive circuit further includes a current drive sub-circuit
  • the pixel driving method includes:
  • the current driving sub-circuit While providing the turn-on signal to the light-emitting control line, the current driving sub-circuit controls the data voltage according to the current provided by the current control data line to generate a driving current output to the output terminal.
  • the current driving sub-circuit includes a driving sub-circuit, a current control data writing sub-circuit, a second reset sub-circuit, a compensation sub-circuit, and a second energy storage sub-circuit; the output terminal is electrically connected to the light-emitting element;
  • the pixel driving method further includes:
  • the second initial voltage is written into the control terminal of the driver sub-circuit to disconnect the first terminal of the driver sub-circuit from the driver.
  • an open signal is provided to the second gate line, so that the predetermined current control data voltage VdI provided by the current control data line is written into the first end of the driving sub-circuit, and causes The control terminal of the driver sub-circuit is electrically connected to the second terminal of the driver sub-circuit, so that the first terminal of the driver sub-circuit and the second terminal of the driver sub-circuit are electrically connected to Correspondingly changing the potential of the control terminal of the driving sub-circuit until the driving sub-circuit is turned off;
  • the driving sub-circuit While providing an on signal to the light-emitting control line, the driving sub-circuit generates a driving current for driving the light-emitting element to emit light, so as to drive the light-emitting element to emit light.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned pixel driving circuit.
  • FIG. 1A is a structural diagram of a pixel driving circuit according to at least one embodiment of the present disclosure
  • FIG. 1B is a structural diagram of a pixel driving circuit according to at least one embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a pixel driving circuit according to at least one embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of a pixel driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 4 is a working timing diagram of at least one embodiment of the pixel driving circuit shown in FIG. 3 of the present disclosure
  • 5A is a schematic diagram of the working state of at least one embodiment of the pixel driving circuit shown in FIG. 3 of the present disclosure during the reset period t1;
  • 5B is a schematic diagram of the working state of at least one embodiment of the pixel driving circuit shown in FIG. 3 of the present disclosure during the compensation period t2;
  • 5C is a schematic diagram of the working state of at least one embodiment of the pixel driving circuit shown in FIG. 3 of the present disclosure during the light-emitting stage te;
  • FIG. 6 is a working timing diagram of at least one embodiment of a multi-row pixel driving circuit
  • FIG. 7 is a structural diagram of a pixel driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 8 is a structural diagram of a pixel driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 9 is a structural diagram of a pixel driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 10 is a circuit diagram of a pixel driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 11 is a working timing diagram of at least one embodiment of the pixel driving circuit shown in FIG. 10 of the present disclosure.
  • FIG. 12A is a schematic diagram of the working state of at least one embodiment of the pixel driving circuit shown in FIG. 10 of the present disclosure during the reset period t1;
  • FIG. 12B is a schematic diagram of the working state of at least one embodiment of the pixel driving circuit shown in FIG. 10 of the present disclosure during the compensation period t2;
  • FIG. 12C is a schematic diagram of the working state of at least one embodiment of the pixel driving circuit shown in FIG. 10 of the present disclosure during the light-emitting stage te;
  • FIG. 13 is a working timing diagram of at least one embodiment of a multi-row pixel driving circuit.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the poles is called the first pole, and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, can be a base electrode, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base.
  • the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • the pixel driving circuit includes a light-emission time control sub-circuit 11, a first reset sub-circuit 12, a first light-emission control sub-circuit 13, a time control data writing sub-circuit 14, The data control sub-circuit 15 and the first energy storage sub-circuit 1;
  • the first reset sub-circuit 12 is respectively connected to the reset control line R1, the first initial voltage terminal, the first terminal of the light-emitting time control sub-circuit 11, the control terminal of the light-emitting time control sub-circuit 11, and the light-emitting time
  • the second terminal of the control sub-circuit 11 is electrically connected for writing the first initial voltage Vi1 provided by the first initial voltage terminal into the light-emitting time control sub-circuit 11 under the control of the reset control signal provided by the reset control line R1 Under the control of the reset control signal, the control terminal of the light-emitting time control sub-circuit 11 is electrically connected to the second terminal of the light-emitting time control sub-circuit 11;
  • the first end of the first energy storage sub-circuit 1 is electrically connected to the control end of the light-emitting time control sub-circuit 11; the first energy storage sub-circuit 1 is used for storing voltage;
  • the time control data writing sub-circuit 14 is electrically connected to the first gate line G1, the time control data line DT, and the second end of the first energy storage sub-circuit 1 respectively, and is used for providing the data on the first gate line G1.
  • the control time control data line DT is electrically connected to the second end of the first energy storage sub-circuit 1;
  • the data control sub-circuit 15 is electrically connected to the light emission control line E1, the time control data line DT, and the second end of the first energy storage sub-circuit 1 respectively, and is used for the light emission provided on the light emission control line E1. Under the control of the control signal, controlling the electrical connection between the time control data line DT and the second end of the first energy storage sub-circuit 1;
  • the first lighting control sub-circuit 13 is electrically connected to the lighting control line E1, the first terminal of the lighting time control sub-circuit 11, and the first voltage terminal Vt1, respectively, for under the control of the lighting control signal , Controlling the electrical connection between the first terminal of the light-emitting time control sub-circuit 11 and the first voltage terminal Vt1;
  • the second end of the light-emitting time control sub-circuit 11 is electrically connected to the output terminal U1, and the light-emitting time control sub-circuit 11 is used to control the first light-emitting time control sub-circuit 11 under the control of the potential of its control terminal.
  • the terminal is electrically connected to the second terminal of the light-emitting time control sub-circuit 11.
  • the pixel driving circuit is used to drive a light-emitting element, and the output terminal U1 is electrically connected to the light-emitting element.
  • the pixel driving circuit described in at least one embodiment of the present disclosure can determine the light-emitting brightness by controlling the light-emitting time of the light-emitting element, and can solve the problem of color coordinate shift of the light-emitting element under different currents and unstable brightness under low current density.
  • the light-emitting brightness is adjusted by adjusting the light-emitting time of the light-emitting element at a fixed higher current density, and can compensate for the influence of the threshold voltage shift of the transistor caused by the low-temperature polysilicon technology on the light-emitting brightness adjustment.
  • the light-emitting element may be a Micro LED (micro light-emitting diode) or an organic light-emitting diode, but it is not limited thereto.
  • the voltage provided by the first voltage terminal Vt1 is related to the type of the light-emitting time control transistor included in the light-emitting time control sub-circuit 11;
  • the first voltage provided by the first voltage terminal Vt1 may be a 0V voltage or a negative voltage, but is not limited to this;
  • the first voltage provided by the first voltage terminal Vt1 may be a positive voltage, but is not limited to this.
  • the first energy storage sub-circuit 1 may include a time control capacitor, but it is not limited to this.
  • a light-emitting element 10 is added.
  • the first pole of the light-emitting element 10 is electrically connected to the output terminal U1.
  • the second electrode of the light emitting element 10 can be connected to the low voltage VSS, but it is not limited to this.
  • the first electrode of the light-emitting element 10 may be an anode, and the second electrode of the light-emitting element 10 may be a cathode, but it is not limited to this.
  • the display period may include a reset period, a compensation period, and a light-emitting period
  • the first reset sub-circuit 12 writes the first initial voltage Vi1 into the first terminal of the light-emitting time control sub-circuit 11, and controls the control of the light-emitting time control sub-circuit 11 Is electrically connected to the second terminal of the light-emitting time control sub-circuit 11, and the time control data writing sub-circuit 14 is controlled by the first gate drive signal to control the time control data line to write the predetermined time control data voltage VdT to VdT under the control of the first gate drive signal.
  • the second terminal of the first energy storage sub-circuit 1, the light-emitting time control sub-circuit 11, under the control of its control terminal, controls the first terminal of the light-emitting time control sub-circuit 11 and the second terminal of the light-emitting time control sub-circuit 11 Are electrically connected between the terminals, and correspondingly change the voltage of the first terminal of the first energy storage sub-circuit 1 until the light-emitting time control sub-circuit 11 is turned off;
  • the time control data writing sub-circuit 14 controls the time control data line DT to write the predetermined voltage V0 to the first gate drive signal under the control of the first gate drive signal provided by the first gate line G1.
  • a second end of the energy storage sub-circuit 1 to correspondingly change the voltage of the first end of the first energy storage sub-circuit 1;
  • the first light-emitting control sub-circuit 13 controls the electrical connection between the first terminal of the light-emitting time control sub-circuit 11 and the first voltage terminal Vt1 under the control of the light-emitting control signal, and the data control sub-circuit 15 is on the light-emitting control line.
  • the control time control data line DT is electrically connected to the second end of the first energy storage sub-circuit 1 to correspondingly change the first end of the first energy storage sub-circuit 1.
  • the light-emitting time control sub-circuit 11 controls the first terminal of the light-emitting time control sub-circuit 11 and the light-emitting time control sub-circuit under the control of the voltage of the first terminal of the first energy storage sub-circuit 1.
  • the second ends of the circuit 11 are electrically connected or disconnected.
  • the predetermined voltage V0 may be 0V, but is not limited to this. In actual operation, V0 can also be a positive voltage or a negative voltage, and V0 can be selected according to actual conditions.
  • turning off the light-emitting time control sub-circuit 11 refers to: the light-emitting time control sub-circuit 11 disconnects the connection between the first terminal and the second terminal thereof;
  • the conduction of the light-emitting time control sub-circuit 11 refers to that the light-emitting time control sub-circuit 11 controls the electrical connection between the first terminal and the second terminal thereof.
  • the time control data voltage provided by DT is changed to control the light-emitting time control sub-circuit 11 from on to off, or to control The light-emitting time control sub-circuit 11 is turned off to on to control the time for driving the light-emitting element 10 to emit light.
  • the time-controlled data voltage provided by the time-controlled data line may be equal to V0-Kt, and t is the time difference between the current time and the time when the light-emitting phase starts;
  • the light-emitting time control transistor included in the light-emitting time control sub-circuit is a p-type transistor, and K can be a positive number, but is not limited to this; or,
  • the light-emitting time control transistor included in the light-emitting time control sub-circuit is an n-type transistor, and K can be a negative number, but is not limited thereto.
  • the time control data voltage can also be changed according to other laws, and the light-emitting time of the light-emitting element can also be controlled.
  • the pixel driving circuit described in at least one embodiment of the present disclosure may further include a second light-emitting control sub-circuit;
  • the second lighting control sub-circuit is electrically connected to the lighting control line, the second terminal of the lighting time control sub-circuit, and the output terminal, respectively, for controlling the lighting control signal under the control of the lighting control signal.
  • the second end of the light-emitting time control sub-circuit is electrically connected to the light-emitting element.
  • the pixel driving circuit described in at least one embodiment of the present disclosure may further include a second light-emitting control sub-circuit 16;
  • the second lighting control sub-circuit 16 is electrically connected to the lighting control line E1, the second terminal of the lighting time control sub-circuit 11, and the output terminal U1, respectively, for under the control of the lighting control signal , Controlling the electrical connection between the second terminal of the light-emitting time control sub-circuit 11 and the output terminal U1.
  • the pixel driving circuit can control the second end of the light emission time control sub-circuit 11 and the light emission under the control of the light emission control signal by adding the second light emission control sub-circuit 16. Whether the first poles of the element 10 are electrically connected.
  • the light-emitting element 10 when VSS is greater than or equal to Vi1, the light-emitting element 10 is in a reverse bias state during the reset period, and the light-emitting element 10 can be omitted at this time.
  • the second light-emission control sub-circuit 16 when VSS is less than Vi1, the second light-emission control sub-circuit 16 needs to be provided.
  • the light-emitting time control sub-circuit may include a light-emitting time control transistor
  • the control terminal of the emission time control transistor is the control terminal of the emission time control sub-circuit
  • the first terminal of the emission time control transistor is the first terminal of the emission time control sub-circuit
  • the first terminal of the emission time control transistor is The second pole is the second end of the light-emitting time control sub-circuit.
  • the first reset sub-circuit may include a first reset transistor and a second reset transistor;
  • the control electrode of the first reset transistor is electrically connected to the reset control line, the first electrode of the first reset transistor is electrically connected to the control terminal of the light-emitting time control sub-circuit, and the first electrode of the first reset transistor is electrically connected to the control terminal of the light-emitting time control sub-circuit.
  • the two poles are electrically connected to the second end of the light-emitting time control sub-circuit;
  • the control electrode of the second reset transistor is electrically connected to the reset control line
  • the first electrode of the second reset transistor is electrically connected to the first end of the light-emitting time control sub-circuit
  • the second reset transistor The second pole is connected to the first initial voltage terminal; the first initial voltage terminal is used to provide the first initial voltage.
  • the time control data writing sub-circuit may include a time control data writing transistor
  • the control electrode of the time control data writing transistor is electrically connected to the first gate line
  • the first electrode of the time control data writing transistor is electrically connected to the time control data line
  • the second pole of the transistor is electrically connected to the second end of the first energy storage sub-circuit.
  • the data control sub-circuit may include a data control transistor
  • the control electrode of the data control transistor is electrically connected to the light-emitting control line
  • the first electrode of the data control transistor is electrically connected to the time control data line
  • the second electrode of the data control transistor is electrically connected to the first
  • the second end of the energy storage sub-circuit is electrically connected.
  • the first light-emission control sub-circuit may include a first light-emission control transistor
  • the control electrode of the first light emission control transistor is electrically connected to the light emission control line
  • the first electrode of the first light emission control transistor is electrically connected to the first voltage terminal
  • the second electrode of the first light emission control transistor is electrically connected to the first voltage terminal.
  • the pole is electrically connected to the first end of the light-emitting time control sub-circuit.
  • the second light-emission control sub-circuit may include a second light-emission control transistor
  • the control electrode of the second light emission control transistor is electrically connected to the light emission control line
  • the first electrode of the second light emission control transistor is electrically connected to the second end of the light emission time control sub-circuit
  • the second light emission The second pole of the control transistor is electrically connected to the output terminal.
  • the light-emitting time control sub-circuit may include a light-emitting time control transistor; the first reset sub-circuit may include a first reset transistor and a second reset transistor; the time control data writing sub-circuit
  • the circuit may include a time control data writing transistor; the data control sub-circuit may include a data control transistor; the first light-emission control sub-circuit may include a first light-emission control transistor; the first energy storage sub-circuit may include a time control capacitance;
  • the control terminal of the emission time control transistor is the control terminal of the emission time control sub-circuit, the first terminal of the emission time control transistor is the first terminal of the emission time control sub-circuit, and the first terminal of the emission time control transistor is A second pole of the second end of the light-emitting time control sub-circuit;
  • the control electrode of the first reset transistor is electrically connected to the reset control line, the first electrode of the first reset transistor is electrically connected to the control terminal of the light-emitting time control sub-circuit, and the first electrode of the first reset transistor is electrically connected to the control terminal of the light-emitting time control sub-circuit.
  • the two poles are electrically connected to the second end of the light-emitting time control sub-circuit;
  • the control electrode of the second reset transistor is electrically connected to the reset control line
  • the first electrode of the second reset transistor is electrically connected to the first end of the light-emitting time control sub-circuit
  • the second reset transistor The second pole is connected to the first initial voltage terminal; the first initial voltage terminal is used to provide the first initial voltage;
  • the control electrode of the time control data writing transistor is electrically connected to the first gate line, the first electrode of the time control data writing transistor is electrically connected to the time control data line, and the time control data writing
  • the second electrode of the transistor is electrically connected to the second end of the first energy storage sub-circuit
  • the control electrode of the data control transistor is electrically connected to the light-emitting control line, the first electrode of the data control transistor is electrically connected to the time control data line, and the second electrode of the data control transistor is electrically connected to the first The second end of the energy storage sub-circuit is electrically connected;
  • the control electrode of the first light emission control transistor is electrically connected to the light emission control line, the first electrode of the first light emission control transistor is electrically connected to the first voltage terminal, and the second electrode of the first light emission control transistor is electrically connected to the first voltage terminal.
  • the pole is electrically connected to the first end of the light-emitting time control sub-circuit;
  • the first end of the first energy storage sub-circuit is the first end of the time control capacitor, and the second end of the first energy storage sub-circuit is the second end of the time control capacitor.
  • the pixel driving circuit described in at least one embodiment of the present disclosure may further include a second light-emitting control sub-circuit;
  • the second light emission control sub-circuit may include a second light emission control transistor
  • the control electrode of the second light emission control transistor is electrically connected to the light emission control line
  • the first electrode of the second light emission control transistor is electrically connected to the second end of the light emission time control sub-circuit
  • the second light emission The second pole of the control transistor is electrically connected to the output terminal.
  • the pixel driving circuit As shown in FIG. 3, the pixel driving circuit according to at least one embodiment of the present disclosure is used to drive the micro light-emitting diode O1.
  • the pixel driving circuit includes a light-emitting time control sub-circuit 11, a first reset sub-circuit 12, and a first light-emitting control.
  • Sub-circuit 13 time control data writing sub-circuit 14, data control sub-circuit 15, second light-emission control sub-circuit 16, and first energy storage sub-circuit 1, wherein,
  • the light-emitting time control sub-circuit 11 includes a light-emitting time control transistor M4; the first reset sub-circuit 12 includes a first reset transistor M3 and a second reset transistor M5; the time control data writing sub-circuit 14 includes time control data Write transistor M1; the data control sub-circuit 15 includes a data control transistor M7; the first light-emission control sub-circuit 13 includes a first light-emission control transistor M2; the second light-emission control sub-circuit 16 includes a second light-emission control transistor M6;
  • the first energy storage sub-circuit 1 includes a time control capacitor C1;
  • the gate of M3 is electrically connected to the reset control line R1, the source of M3 is electrically connected to the gate of M4, and the drain of M3 is electrically connected to the drain of M4;
  • the gate of M5 is electrically connected to the reset control line R1, the source of the second reset transistor M5 is electrically connected to the source of M4, and the drain of M5 is connected to the first initial voltage terminal; the first initial voltage Terminal is used to provide the first initial voltage Vi1;
  • the gate of M1 is electrically connected to the first gate line G1, the source of M1 is electrically connected to the time control data line DT, and the drain of M1 is electrically connected to the second end of C1;
  • the gate of M7 is electrically connected to the light-emitting control line E1, the source of M7 is electrically connected to the time control data line DT, the drain of M7 is electrically connected to the second end of C1; the first end of C1 is electrically connected to the gate of M4 Electrical connection
  • the gate of M2 is electrically connected to the light-emitting control line E1, the source of M2 is connected to the first voltage VDD, and the drain of M2 is electrically connected to the source of M4;
  • the gate of M6 is electrically connected to the light-emitting control line E1, the source of M6 is electrically connected to the drain of M4, and the drain of M6 is electrically connected to the anode of O1;
  • the cathode of O1 is connected to the low voltage VSS.
  • all the transistors are p-type thin film transistors, but not limited to this.
  • N1 is the first node connected to the gate of M4, and N2 is the second node connected to the second end of C1.
  • Vi1 can be 0V, but it is not limited to this.
  • the value of Vi1 can be selected according to the actual situation.
  • the anode of O1 may be the first pole of the light-emitting element, and the cathode of O1 may be the second pole of the light-emitting element.
  • the pixel driving circuit shown in FIG. 3 when VSS is greater than or equal to Vi1, O1 is in the reverse bias state during the reset period, and M6 can be omitted at this time; when VSS is less than Vi1 When, you need to set M6.
  • the display period includes a reset period t1, a compensation period t2, and a light-emitting period te;
  • the gate-source voltage Vgs4 of M4 is equal to Vth4-VDD, and VDD is preferably set to 0V or lower. That is, Vgs4>Vth4, at this time M4 is turned on; that is, in the light-emitting stage te, M4 is turned off to on, the turn-on time of M4 depends on the value of VdT and the time control data voltage in the light-emitting stage te, the turn-on time of M4 The impact of Vth4.
  • M4 In the light-emitting stage te, M4 is in a fully-on state and is in the unsaturated zone.
  • Id is the driving current for driving O1 to emit light
  • Vn1 is the voltage of N1.
  • the display panel may include multiple rows and multiple columns of the aforementioned pixel driving circuit.
  • the display time F1 of one frame may include a preparation phase and a light-emitting phase te that are sequentially arranged;
  • the preparation phase may include a plurality of preparation time periods set in sequence, and each preparation time period includes a reset time period and a compensation time period set in sequence;
  • the one marked t1-1 is the first reset time period
  • the one marked t1-2 is the first compensation time period
  • the one marked t2-1 is the second reset time period
  • the one marked t2-2 It is the second compensation time period.
  • the one marked tn-1 is the nth reset time period
  • the one marked tn-2 is the nth compensation time period
  • the one marked E1 is the light-emitting control line
  • the one marked DTm is the m-th column.
  • label R11 is the reset control line of the first row
  • label G11 is the first gate line of the first row
  • label R12 is the reset control line of the second row
  • label G12 is the second row
  • the first gate line, labeled G1n is the first gate line of the nth row
  • labeled R1n is the reset control line of the nth row
  • labeled Vn11 is the first node N1 in the pixel driving circuit of the first row and mth column.
  • Vn12 is the potential of the first node N1 in the pixel driving circuit of the second row and mth column
  • the potential of Id1 is the driving current of the mth column of the first row
  • the one marked Id2 is the first
  • the one labeled Idn is the driving current of the micro-light-emitting diode in the nth row and the mth column, where m is a positive integer, and n is an integer greater than 2.
  • the pixel driving circuit in the first row and mth column is used to drive the micro light emitting diodes in the first row and mth column
  • the pixel driving circuit in the second row and mth column is used to drive the micro light emitting diodes in the second row and mth column.
  • Light emitting diodes, the pixel driving circuit in the nth row and mth column is used to drive the nth row and mth column micro light emitting diodes.
  • DTm writes the first time control data voltage VdT1, at t1-2, DTm writes 0V voltage; at t1-2, DTm writes the second time control data voltage VdT2, at t2-2, DTm writes 0V voltage; at t1-n, DTm writes the nth time control data voltage VdTn, at tn-2, DTm writes 0V voltage; at te, the data voltage on DTm changes from 0V with a fixed slope Decrease to control the light-emitting time of each row of micro light-emitting diodes.
  • micro-light-emitting diodes are considered to be the next-generation display panel technology due to their low driving voltage, ultra-high brightness, long life, high temperature resistance, etc., but their transfer bonding is immature and there is no corresponding glass-based driving backplane. , And it has been slow to push to the consumer market.
  • At least one embodiment of the present disclosure proposes a glass-based driving backplane solution, and the proposed pixel driving circuit mainly solves the problems of color coordinate deviation of micro light emitting diodes under different currents and unstable brightness at low current densities.
  • the reason why most of the pixel drive circuits of the micro light-emitting diodes are on the PCB (Printed Circuit Board) substrate is that low-temperature polysilicon technology is used to fabricate the pixel drive circuits on the glass substrate.
  • the threshold voltage shift of the transistor caused by the low-temperature polysilicon technology has an impact on the luminous brightness.
  • the pixel driving circuit described in at least one embodiment of the present disclosure can compensate for the deviation of the threshold voltage, and therefore can provide a glass-based driving backplane solution.
  • the pixel driving circuit controls the gray scale by controlling the light emission time under a fixed current or a fixed voltage, and takes into account the threshold voltage shift of the transistor caused by the use of low-temperature polysilicon, and compensates for the threshold voltage Offset, the controlled turn-on of the light-emitting time control transistor M4 is not affected by its threshold voltage, and the light-emitting time can be precisely controlled according to the time control data voltage to make more gray levels.
  • the pixel drive circuit of at least one embodiment of the present disclosure controls the turn-on time of M4 through the potential of N1, and determines the time when the current is conducted to the micro LED, that is, the time the micro LED emits light within one frame of display time. The brightness as seen by the eye.
  • At least one embodiment of the present disclosure proposes a glass-based driving backplane solution, and the proposed pixel driving circuit mainly solves the problems of color coordinate deviation of micro light emitting diodes under different currents and unstable brightness at low current densities.
  • At least one embodiment of the present disclosure proposes a new pixel driving circuit based on a glass-based micro-light-emitting diode display panel, which controls the gray-scale driving scheme by controlling the light-emitting time under a fixed current or a fixed voltage.
  • the pixel driving circuit As shown in FIG. 7, the pixel driving circuit according to at least one embodiment of the present disclosure is used to drive the light-emitting element 10 to emit light.
  • the pixel driving circuit includes a current driving sub-circuit 70, a light-emitting time control sub-circuit 11, and a first energy storage sub-circuit.
  • Circuit 1 a first reset sub-circuit 12, a first light-emitting control sub-circuit 13, a time control data writing sub-circuit 14 and a data control sub-circuit 15;
  • the first reset sub-circuit 12 is respectively connected to the reset control line R1, the first initial voltage terminal, the first terminal of the light-emitting time control sub-circuit 11, the control terminal of the light-emitting time control sub-circuit 11, and the light-emitting time
  • the second terminal of the control sub-circuit 11 is electrically connected for writing the first initial voltage Vi1 provided by the first initial voltage terminal into the light-emitting time control sub-circuit 11 under the control of the reset control signal input by the reset control line R1 And control the electrical connection between the control terminal of the light-emitting time control sub-circuit 11 and the second terminal 11 of the light-emitting time control sub-circuit;
  • the first end of the first energy storage sub-circuit 1 is electrically connected to the control end of the light-emitting time control sub-circuit 11;
  • the time control data writing sub-circuit 14 is electrically connected to the first gate line G1, the time control data line DT, and the second end of the first energy storage sub-circuit 1 respectively, and is used for providing the data on the first gate line G1.
  • the control time control data line DT is electrically connected to the second end of the first energy storage sub-circuit 1;
  • the data control sub-circuit 15 is electrically connected to the light emission control line E1, the time control data line DT, and the second end of the first energy storage sub-circuit 1 respectively, and is used for the light emission provided on the light emission control line E1. Under the control of the control signal, controlling the electrical connection between the time control data line DT and the second end of the first energy storage sub-circuit 1;
  • the first lighting control sub-circuit 13 is electrically connected to the lighting control line E1, the first terminal of the lighting time control sub-circuit 11, and the first voltage terminal Vt1, respectively, for under the control of the lighting control signal , Controlling the electrical connection between the first terminal of the light-emitting time control sub-circuit 11 and the first voltage terminal Vt1;
  • the second end of the light-emitting time control sub-circuit 11 is electrically connected to the first electrode of the light-emitting element 10, and the light-emitting time control sub-circuit 11 is used to control the light-emitting time control under the control of the potential of its control terminal.
  • the first end of the sub-circuit 11 is electrically connected to the second end of the light-emitting time control sub-circuit 11;
  • the current driving sub-circuit 70 is electrically connected to the current control data line DI, and the current driving sub-circuit 70 is connected between the second end of the light-emitting time control sub-circuit 11 and the first electrode of the light-emitting element 10 , Used to control the data voltage according to the current on the current control data line DI during the light-emitting phase to generate a driving current for driving the light-emitting element 10 to emit light;
  • the first pole of the light-emitting element 10 is electrically connected to the output terminal U1, and the second pole of the light-emitting element 10 is connected to a low voltage VSS.
  • the current driving sub-circuit 70 controls the magnitude of the driving current for driving the light-emitting element 10 to emit light
  • the light-emitting time control sub-circuit 11 controls the magnitude of the driving current for driving the light-emitting element 10 to emit light
  • the light-emitting time control sub-circuit 11 controls the magnitude of the driving current for driving the light-emitting element 10 to emit light
  • the light-emitting time control sub-circuit 11 controls the magnitude of the driving current for driving the light-emitting element 10 to emit light
  • the light-emitting time control sub-circuit 11 controls the magnitude of the driving current for driving the light-emitting element 10 to emit light
  • the light-emitting time control sub-circuit 11 controls the magnitude of the driving current for driving the light-emitting element 10 to emit light
  • the light-emitting time control sub-circuit 11 controls the magnitude of the driving current for driving the light-emitting element 10 to emit light
  • the light-emitting time control sub-circuit 11 controls
  • the display period may include a reset period, a compensation period, and a light-emitting period
  • the first reset sub-circuit 12 writes the first initial voltage Vi1 into the first terminal of the light-emitting time control sub-circuit 11, and controls the control of the light-emitting time control sub-circuit 11 Is electrically connected to the second terminal of the light-emitting time control sub-circuit 11, and the time control data writing sub-circuit 14 is controlled by the first gate drive signal to control the time control data line to write the predetermined time control data voltage VdT to VdT under the control of the first gate drive signal.
  • the second terminal of the first energy storage sub-circuit 1, the light-emitting time control sub-circuit 11, under the control of its control terminal, controls the first terminal of the light-emitting time control sub-circuit 11 and the second terminal of the light-emitting time control sub-circuit 11 Are electrically connected between the terminals, and correspondingly change the voltage of the first terminal of the first energy storage sub-circuit 1 until the light-emitting time control sub-circuit 11 is turned off;
  • the time control data writing sub-circuit 14 controls the time control data line DT to write a predetermined voltage V0 to the first storage under the control of the first gate driving signal provided by the first gate line G1.
  • the second end of the energy sub-circuit 1 to correspondingly change the voltage of the first end of the first energy storage sub-circuit 1;
  • the current driving sub-circuit 70 controls the data voltage according to the current on the current control data line DI to generate a driving current for driving the light-emitting element 10 to emit light; the first light-emitting control sub-circuit 13 controls the light-emitting element 10 under the control of the light-emitting control signal
  • the first terminal of the light-emitting time control sub-circuit 11 is electrically connected to the first voltage terminal Vt1.
  • the data control sub-circuit 15 controls the time control data line DT and the first voltage terminal Vt1 under the control of the light-emitting control signal provided by the light-emitting control line E1.
  • the second end of an energy storage sub-circuit 1 is electrically connected to correspondingly change the voltage of the first end of the first energy storage sub-circuit 1, and the light-emitting time control sub-circuit 11 is connected to the first energy storage sub-circuit 1 Under the control of the voltage of the first terminal of the control, the first terminal of the light-emitting time control sub-circuit 11 and the second terminal of the light-emitting time control sub-circuit 11 are controlled to be electrically connected or disconnected.
  • the current driving sub-circuit may include a driving sub-circuit, a current control data writing sub-circuit, a second reset sub-circuit, a compensation sub-circuit, and a second energy storage sub-circuit;
  • the first end of the driving sub-circuit is electrically connected to the second end of the light-emitting time control sub-circuit, and the second end of the driving sub-circuit is electrically connected to the output end;
  • the driving sub-circuit is used for Controlling the electrical connection between the first end of the driving sub-circuit and the second end of the driving sub-circuit under the control of the potential of the control terminal;
  • the first end of the second energy storage sub-circuit is electrically connected to the control end of the driving sub-circuit, the second end of the second energy storage sub-circuit is electrically connected to the second voltage end, and the second energy storage sub-circuit is electrically connected to the second voltage end.
  • the sub-circuit is used to store voltage
  • the current control data writing sub-circuit is electrically connected to the first end of the second gate line, the current control data line, and the driving sub-circuit, respectively, for the second gate provided on the second gate line Under the control of the driving signal, controlling the electrical connection between the current control data line and the first end of the driving sub-circuit;
  • the second reset sub-circuit is electrically connected to the reset control line, the second initial voltage terminal, and the control terminal of the drive sub-circuit, and is used to control the reset control signal input by the reset control line.
  • the second initial voltage provided by the second initial voltage terminal is provided to the control terminal of the driving sub-circuit;
  • the compensation sub-circuit is electrically connected to the second gate line, the control terminal of the driving sub-circuit, and the second terminal of the driving sub-circuit, respectively, for under the control of the second gate driving signal, Control the electrical connection between the control terminal of the driver sub-circuit and the second terminal of the driver sub-circuit.
  • the first energy storage sub-circuit may include a time control capacitor
  • the second energy storage sub-circuit may include a current control capacitor
  • the current driving sub-circuit may include a driving sub-circuit 71, a current control data writing sub-circuit 72, and a second reset sub-circuit. Circuit 73, compensation sub-circuit 74 and second energy storage sub-circuit 70;
  • the first end of the driving sub-circuit 71 is electrically connected to the second end of the light-emitting time control sub-circuit 11, and the second end of the driving sub-circuit 71 is electrically connected to the first electrode of the light-emitting element 10;
  • the driving sub-circuit 71 is used to control the electrical connection between the first end of the driving sub-circuit 71 and the second end of the driving sub-circuit 71 under the control of the potential of the control terminal thereof;
  • the first end of the second energy storage sub-circuit 70 is electrically connected to the control end of the driving sub-circuit 71, and the second end of the second energy storage sub-circuit 70 is electrically connected to the second voltage terminal Vt2;
  • the current control data writing sub-circuit 72 is electrically connected to the second gate line G2, the current control data line DI, and the first end of the driving sub-circuit 71, respectively, for the second gate line provided on the second gate line G2. Under the control of the pole drive signal, control the electrical connection between the current control data line DI and the first end of the drive sub-circuit 71;
  • the second reset sub-circuit 73 is electrically connected to the reset control line R1, the second initial voltage terminal, and the control terminal of the driving sub-circuit 71, respectively, and is used for under the control of the reset control signal input from the reset control line R1. , Providing a second initial voltage Vi2 to the control terminal of the driving sub-circuit 71; the second initial voltage terminal is used to provide a second initial voltage Vi2;
  • the compensation sub-circuit 74 is electrically connected to the second gate line G2, the control terminal of the driving sub-circuit 71, and the second terminal of the driving sub-circuit 71, respectively, for controlling the second gate driving signal Next, control the electrical connection between the control terminal of the driving sub-circuit 71 and the second terminal of the driving sub-circuit 71.
  • the second voltage terminal may be the same as the first voltage terminal, but it is not limited to this. In actual operation, the second voltage terminal may also be different from the first voltage terminal.
  • the second reset sub-circuit 73 provides a second initial voltage Vi2 to the control terminal of the driving sub-circuit 71 under the control of the reset control signal, so that the driving sub-circuit 71, under the control of the potential of its control terminal, disconnect the connection between the first terminal of the driving sub-circuit 71 and the second terminal of the driving sub-circuit 71;
  • the current control data writing sub-circuit 72 controls the current control data line DI to write the predetermined current control data voltage VdI to VdI under the control of the second gate drive signal provided by the second gate line G2.
  • the first end of the driving sub-circuit 71, the compensation sub-circuit 74 controls the control end of the driving sub-circuit 71 and the second end of the driving sub-circuit 71 under the control of the second gate driving signal.
  • the terminals are electrically connected, so that the driver sub-circuit 71 controls the electrical connection between the first terminal of the driver sub-circuit 71 and the second terminal of the driver sub-circuit 71 under the control of the potential of the control terminal thereof, To correspondingly change the potential of the control terminal of the driving sub-circuit 71 until the driving sub-circuit 71 is turned off;
  • the driving sub-circuit 71 In the light-emitting phase, the driving sub-circuit 71 generates a driving current for driving the light-emitting element 10 to emit light under the control of the potential of its control terminal, so as to drive the light-emitting element 10 to emit light.
  • the pixel driving circuit may further include a second light-emitting control sub-circuit; the first terminal of the driving sub-circuit is electrically connected through the second light-emitting control sub-circuit and the second terminal of the light-emitting time control sub-circuit. connection;
  • the control terminal of the second lighting control sub-circuit is electrically connected to the lighting control line
  • the first terminal of the second lighting control sub-circuit is electrically connected to the second terminal of the lighting time control sub-circuit
  • the second lighting The second end of the control sub-circuit is electrically connected to the drive sub-circuit
  • the second light-emission control sub-circuit is used to control the light-emitting time control sub-circuit under the control of the light-emission control signal provided by the light-emission control line
  • the second end is electrically connected to the driving sub-circuit.
  • the pixel driving circuit described in at least one embodiment of the present disclosure may further include a third light-emitting control sub-circuit;
  • the second end of the driving sub-circuit is electrically connected to the output end through the third light-emitting control sub-circuit;
  • the third lighting control sub-circuit is used for controlling the electrical connection between the second terminal of the driving sub-circuit and the output terminal under the control of the lighting control signal provided by the lighting control line.
  • the pixel driving circuit may further include a second light-emitting control sub-circuit 16 and a third light-emitting circuit.
  • the first end of the driving sub-circuit 71 is electrically connected to the second end of the light-emitting time control sub-circuit 11 through the second light-emitting control sub-circuit 16;
  • the control terminal of the second lighting control sub-circuit 16 is electrically connected to the lighting control line E1
  • the first terminal of the second lighting control sub-circuit 16 is electrically connected to the second terminal of the lighting time control sub-circuit 11, so
  • the second end of the second light-emission control sub-circuit 16 is electrically connected to the first end of the drive sub-circuit 71
  • the second light-emission control sub-circuit 16 is used to control the light-emission control signal provided on the light-emission control line E1. Under control, controlling the electrical connection between the second end of the light-emitting time control sub-circuit 11 and the first end of the driving sub-circuit 71;
  • the second terminal of the driving sub-circuit 71 is electrically connected to the first pole of the light-emitting element 10 through the third light-emitting control sub-circuit 75; the second pole of the light-emitting element 10 is connected to a low voltage VSS; The first pole of the light emitting element 10 is electrically connected to the output terminal U1;
  • the third light-emitting control sub-circuit 75 is electrically connected to the light-emitting control line E1, and is used for controlling the second end of the driving sub-circuit 71 and the light-emitting element 10 under the control of the light-emitting control signal provided by the light-emitting control line E1.
  • the first pole is electrically connected.
  • the second light-emitting control sub-circuit 16 controls the distance between the first terminal and the second terminal thereof.
  • the third light-emitting control sub-circuit 75 controls the electrical connection between the second end of the driving sub-circuit 71 and the first pole of the light-emitting element 10.
  • the second energy storage sub-circuit may include a current control capacitor, the first end of the second energy storage sub-circuit is the first end of the current control capacitor, and the second end of the second energy storage sub-circuit The second terminal is the second terminal of the current control capacitor, but it is not limited to this.
  • the driving sub-circuit may include a driving transistor
  • the control electrode of the drive transistor is electrically connected to the first end of the current control capacitor, the first electrode of the drive transistor is electrically connected to the second end of the light-emitting time control sub-circuit, and the second end of the drive transistor is electrically connected.
  • the pole is electrically connected to the output terminal.
  • the current control data writing sub-circuit may include a current control data writing transistor
  • the control electrode of the current control data writing transistor is electrically connected to the second gate line
  • the first electrode of the current control data writing transistor is electrically connected to the current control data line
  • the current control data writing The second pole of the transistor is electrically connected to the first end of the driving sub-circuit.
  • the second reset sub-circuit may include a third reset transistor
  • the control electrode of the third reset transistor is electrically connected to the reset control line
  • the first electrode of the third reset transistor is electrically connected to the second initial voltage terminal
  • the second electrode of the third reset transistor is electrically connected to the The control terminal of the driving sub-circuit is electrically connected.
  • the compensation sub-circuit may include a compensation transistor
  • the control electrode of the compensation transistor is electrically connected to the second gate line
  • the first electrode of the compensation transistor is electrically connected to the control terminal of the driving sub-circuit
  • the second electrode of the compensation transistor is electrically connected to the control terminal of the driving sub-circuit. The second end is electrically connected.
  • the third light-emission control sub-circuit may include a third light-emission control transistor
  • the control electrode of the third light-emission control transistor is electrically connected to the light-emission control line
  • the first electrode of the third light-emission control transistor is electrically connected to the second end of the driving sub-circuit
  • the first electrode of the third light-emission control transistor The two poles are electrically connected to the output terminal.
  • the pixel driving circuit described in at least one embodiment of the present disclosure is used to drive the micro light emitting diode O1 to emit light;
  • the pixel drive circuit includes a current drive sub-circuit, a light-emitting time control sub-circuit 11, a first energy storage sub-circuit 1, a first reset sub-circuit 12, a first light-emission control sub-circuit 13, and a time control data writing sub-circuit 14, The data control sub-circuit 15 and the second light-emission control sub-circuit 15, wherein,
  • the light-emitting time control sub-circuit 11 includes a light-emitting time control transistor M4; the first reset sub-circuit 12 includes a first reset transistor M3 and a second reset transistor M5; the time control data writing sub-circuit 14 includes time control data Write transistor M1; the data control sub-circuit 15 includes a data control transistor M7; the first light-emission control sub-circuit 13 includes a first light-emission control transistor M2; the second light-emission control sub-circuit 15 includes a second light-emission control transistor M6;
  • the first energy storage sub-circuit 1 includes a time control capacitor C1;
  • the gate of M3 is electrically connected to the reset control line R1, the source of M3 is electrically connected to the gate of M4, and the drain of M3 is electrically connected to the drain of M4;
  • the gate of M5 is electrically connected to the reset control line R1, the source of the second reset transistor M5 is electrically connected to the source of M4, and the drain of M5 is connected to the first initial voltage terminal; the first initial voltage Terminal is used to provide the first initial voltage Vi1;
  • the gate of M1 is electrically connected to the first gate line G1, the source of M1 is electrically connected to the time control data line DT, the drain of M1 is electrically connected to the second end of C1; the first end of C1 is electrically connected to M4
  • the grid is electrically connected;
  • the gate of M7 is electrically connected to the light-emitting control line E1, the source of M7 is electrically connected to the time control data line DT, and the drain of M7 is electrically connected to the second end of C1;
  • the gate of M2 is electrically connected to the light-emitting control line E1, the source of M2 is connected to the first voltage VDD, and the drain of M2 is electrically connected to the source of M4;
  • the gate of M6 is electrically connected to the light-emitting control line E1, and the source of M6 is electrically connected to the drain of M4;
  • the cathode of O1 is connected to the low voltage VSS;
  • the current driving sub-circuit includes a driving sub-circuit 71, a current control data writing sub-circuit 72, a second reset sub-circuit 73, a compensation sub-circuit 74, a third light-emitting control sub-circuit 75, and a second energy storage sub-circuit 70;
  • the second energy storage sub-circuit 70 includes a current control capacitor C2;
  • the driving sub-circuit 71 includes a driving transistor M9;
  • the gate of M9 is electrically connected to the first terminal of C2, and the source of M9 is electrically connected to the drain terminal of M6;
  • the current control data writing sub-circuit 72 includes a current control data writing transistor M8;
  • the gate of the current control data writing transistor M8 is electrically connected to the second gate line G2, the source of the current control data writing transistor M8 is electrically connected to the current control data line DI, and the current control The drain of the data writing transistor M8 is electrically connected to the source of M9;
  • the second reset sub-circuit 73 includes a third reset transistor M11;
  • the gate of M11 is electrically connected to the reset control line R1, the source of M11 is electrically connected to the second initial voltage terminal, and the drain of M11 is electrically connected to the gate of M9; the second initial voltage terminal is used to provide a first Two initial voltage Vi2;
  • the compensation sub-circuit 74 includes a compensation transistor M10;
  • the gate of the compensation transistor M10 is electrically connected to the second gate line G2, the source of the compensation transistor M10 is electrically connected to the gate of M9, and the drain of M10 is electrically connected to the drain of M9;
  • the third light emission control sub-circuit 75 includes a third light emission control transistor M12;
  • the gate of M12 is electrically connected to the light emitting control line E1, the source of M12 is electrically connected to the drain of M9, and the drain of M12 is electrically connected to the anode of the micro light emitting diode O1;
  • the first terminal of C2 is electrically connected to the gate of M9, and the second terminal of C2 is connected to the first voltage VDD.
  • all the transistors are p-type thin film transistors, and the first voltage terminal and the second voltage terminal are the same voltage terminal, but not limited to this.
  • the first node labeled N1 is the first node electrically connected to the gate of M4
  • the second node labeled N2 is the second node electrically connected to the second end of C1
  • the one labeled N3 is the gate of M9.
  • the third node that is electrically connected, N4 is the fourth node that is electrically connected to the source of M9.
  • M6 can be omitted;
  • VdI when VdI is less than or equal to VSS, M12 can be omitted; and when VdI is greater than VSS, M12 cannot be omitted.
  • VdI When VdI is greater than VSS, M12 cannot be omitted.
  • the display period may include a reset period t1, a compensation period t2, and a light-emitting period te;
  • E1 inputs high level, M2, M6, M7, M8, M9, M11 and M12 are closed, R1 and G1 input low level, M1, M3, M4, M5 and M11 Turn on;
  • DT inputs the predetermined time to control the data voltage VdT, the voltage of N2 is VdT, the voltage of the source of M4 is Vi1, then M4 is turned on to change the potential of the gate of M4, until the potential of N1 becomes Vi1+Vth4, Vth4 Is the threshold voltage of M4; Vi1 is set to 0V, then the potential of N1 is Vth4, and the potential of N2 is VdT; the voltage of N3 is Vi2; Vi2 can also be set to 0V;
  • N2 The voltage of N1 jumps from VdT to 0V, and the potential of N1 jumps from Vth4 to Vth4-VdT; at the same time, G2 inputs low level, M8 and M10 are turned on, and M9 is turned on to change the voltage of N3 until M9 is turned off and the voltage of N3 changes Is VdI+Vth9, and remains unchanged under the action of C2; Vth9 is the threshold voltage of M9;
  • the gate voltage of M4 jumps to the threshold voltage Vth4 of M4 according to the law of charge retention.
  • the gate-source voltage Vgs4 of M4 is equal to Vth4-VDD, and VDD is 0V.
  • M9 is in the saturation region.
  • M9 When at least one embodiment of the pixel driving circuit shown in FIG. 10 of the present disclosure is working, M9 generates a driving current, and M4 controls the light-emitting time. Different driving currents and different light-emitting times can achieve more gray levels and can compensate The threshold voltage is shifted so that the threshold voltage shift of M4 and the threshold voltage of M9 caused by low-temperature polysilicon technology will not affect the display effect.
  • Vn1 is the voltage of N1
  • Vn4 is the voltage of N4.
  • Vn4 is equal to the difference between the potential of N3 and Vth4.
  • the pixel driving circuit is used to drive a light-emitting element
  • the output terminal is electrically connected to the first pole of the light-emitting element
  • the second pole of the light-emitting element is electrically connected to the third voltage terminal.
  • the third voltage terminal may be a low voltage terminal, but is not limited to this.
  • the display panel may include multiple rows and multiple columns of the aforementioned pixel driving circuits.
  • the display time of one frame may include a preparation phase and a light-emitting phase te that are sequentially set;
  • the preparation phase may include a plurality of preparation time periods set in sequence, and each preparation time period includes a reset time period and a compensation time period set in sequence;
  • the one labeled F1 is the display time of one frame
  • the one labeled t1-1 is the first reset period
  • the one labeled t1-2 is the first compensation period
  • the one labeled t2-1 is the first compensation period.
  • Two reset time period, the second compensation time period marked t2-2, the nth reset time period marked tn-1, the nth compensation time period marked tn-2, and the light emission marked E1 Control line labeled DTm is the time control data line of the mth column
  • labeled R11 is the reset control line of the first row
  • labeled G11 is the first gate line of the first row
  • labeled R12 is the second row of reset Control line
  • G12 is the first gate line in the second row
  • G1n is the first gate in the nth row
  • G21 is the second gate in the first row
  • G22 is the second gate
  • the second gate line, labeled G2n is the second gate line of the nth row
  • N4(2) is the voltage of the fourth node in the pixel drive circuit in the second row and mth column
  • labeled N4(n) is the voltage of the pixel drive circuit in the nth row and mth column.
  • the potential of the first node N1 in the pixel driving circuit in the first row and mth column is marked by Vn11
  • the potential of the first node N1 in the pixel driving circuit in the second row and mth column is marked by Vn12.
  • DTm writes the first time control data voltage VdT1, at t1-2, DTm writes 0V voltage; at t1-2, DTm writes the second time control data voltage VdT2, t2-2, DTm writes 0V voltage; at t1-n, DTm writes the nth time control data voltage VdTn, at tn-2, DTm writes 0V voltage; at te, the data voltage on DTm changes from 0V with a fixed slope Decrease to control the light-emitting time of each row of micro-LEDs.
  • the pixel driving method described in at least one embodiment of the present disclosure is applied to the aforementioned pixel driving circuit, and the pixel driving method may include:
  • An on signal is provided to the light-emitting control line, so that the first terminal of the light-emitting time control sub-circuit is electrically connected to the first voltage terminal, and the time control data line and the second terminal of the first energy storage sub-circuit are electrically connected. Is electrically connected to each other to change the voltage of the first terminal of the first energy storage sub-circuit accordingly, so that the first terminal of the light-emitting time control sub-circuit is electrically connected to the second terminal of the light-emitting time control sub-circuit. Connect or disconnect.
  • the pixel driving method described in at least one embodiment of the present disclosure can determine the light-emitting brightness by controlling the light-emitting time of the light-emitting element, and can solve the problem of the color coordinate shift of the light-emitting element under different currents and the unstable brightness under low current density.
  • the light-emitting brightness can be adjusted by adjusting the light-emitting time of the light-emitting element at a fixed higher current density, and can compensate for the influence of the threshold voltage shift of the transistor caused by the low-temperature polysilicon technology on the light-emitting brightness adjustment.
  • the turn-on signal may be a signal capable of controlling the conduction of the corresponding sub-circuit; for example, when the transistor included in the sub-circuit is an n-type transistor, the turn-on signal may be a high voltage signal; When the transistor included in the sub-circuit is a p-type transistor, the open signal may be a low voltage signal; but it is not limited to this.
  • the data voltage provided by the time-controlled data line may be equal to V0-Kt, where t is the duration of the light-emitting phase;
  • the emission time control transistor included in the emission time control sub-circuit is a p-type transistor, and K is a positive number; or,
  • the light-emitting time control transistor included in the light-emitting time control sub-circuit is an n-type transistor, and K is a negative number.
  • the pixel driving circuit may further include a current driving sub-circuit
  • the pixel driving method may further include:
  • the current driving sub-circuit While providing the turn-on signal to the light-emitting control line, the current driving sub-circuit controls the data voltage according to the current provided by the current control data line to generate a driving current output to the output terminal.
  • the current driving sub-circuit controls the magnitude of the driving current for driving the light-emitting element to emit light
  • other sub-circuits included in the pixel driving circuit control the light-emitting time of the light-emitting element
  • the micro-light-emitting diode When the pixel driving method described in at least one embodiment of the present disclosure is used to drive micro-light-emitting diodes, the micro-light-emitting diode has low efficiency at low current density and main peak shift, and high efficiency at high current density. Under the density, the current drive is adopted, and under the low current density, the high current drive and the light-emitting time modulation are adopted to realize the display of each gray scale.
  • the second initial voltage is written into the control terminal of the driver sub-circuit to disconnect the first terminal of the driver sub-circuit from the driver.
  • an open signal is provided to the second gate line, so that the predetermined current control data voltage VdI provided by the current control data line is written into the first end of the driving sub-circuit, and causes The control terminal of the driver sub-circuit is electrically connected to the second terminal of the driver sub-circuit, so that the first terminal of the driver sub-circuit and the second terminal of the driver sub-circuit are electrically connected to Correspondingly changing the potential of the control terminal of the driving sub-circuit until the driving sub-circuit is turned off;
  • the driving sub-circuit While providing an on signal to the light-emitting control line, the driving sub-circuit generates a driving current for driving the light-emitting element to emit light, so as to drive the light-emitting element to emit light.
  • the display device includes the above-mentioned pixel driving circuit.
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

本公开提供一种像素驱动电路及其方法和显示装置。像素驱动电路包括发光时间控制子电路、第一储能子电路，第一复位子电路、第一发光控制子电路、时间控制数据写入子电路和数据控制子电路；时间控制数据写入子电路在第一栅极驱动信号的控制下，控制时间控制数据线与第一储能子电路的第二端之间电连接；发光时间控制子电路控制发光时间控制子电路的第一端与发光时间控制子电路的第二端之间电连接。本公开解决微发光二极管在不同电流下色坐标偏移以及低电流密度下亮度不稳定的问题。

Description

像素驱动电路及其驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法和显示装置。
背景技术
在相关技术中，微发光二极管因其低驱动电压、超高亮度、长寿命、耐高温等特点被认为是次世代显示面板技术。相关的用于驱动微发光二极管的像素驱动电路存在微发光二极管在不同电流下色坐标偏移以及低电流密度下亮度不稳定的问题。
发明内容
在一个方面中，本公开实施例提供了一种像素驱动电路，所述像素驱动电路包括发光时间控制子电路、第一储能子电路，第一复位子电路、第一发光控制子电路、时间控制数据写入子电路和数据控制子电路；
所述第一复位子电路分别与复位控制线、第一初始电压端、所述发光时间控制子电路的第一端、所述发光时间控制子电路的控制端与所述发光时间控制子电路的第二端电连接，用于在所述复位控制线提供的复位控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述发光时间控制子电路的第一端，并在所述复位控制信号的控制下控制所述发光时间控制子电路的控制端与所述发光时间控制子电路的第二端之间电连接；
所述第一储能子电路的第一端与所述发光时间控制子电路的控制端电连接；所述第一储能子电路用于存储电压；
所述时间控制数据写入子电路分别与第一栅线、时间控制数据线和所述第一储能子电路的第二端电连接，用于在所述第一栅线提供的第一栅极驱动信号的控制下，控制所述时间控制数据线与所述第一储能子电路的第二端之间电连接；
所述数据控制子电路分别与发光控制线、所述时间控制数据线和所述第一储能子电路的第二端电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述时间控制数据线与所述第一储能子电路的第二端之间电连接；
所述第一发光控制子电路分别与所述发光控制线、所述发光时间控制子电路的第一端和第一电压端电连接，用于在所述发光控制信号的控制下，控制所述发光时间控制子电路的第一端与所述第一电压端之间电连接；
所述发光时间控制子电路的第二端与输出端电连接，所述发光时间控制子电路用于在其控制端的电位的控制下，控制所述发光时间控制子电路的第一端与所述发光时间控制子电路的第二端之间电连接。
可选的，本公开至少一实施例所述的像素驱动电路还包括第二发光控制子电路；
所述第二发光控制子电路分别与所述发光控制线、所述发光时间控制子电路的第二端和所述输出端电连接，用于在所述发光控制信号的控制下，控制所述发光时间控制子电路的第二端与所述输出端之间电连接。
可选的，所述发光时间控制子电路包括发光时间控制晶体管；
所述发光时间控制晶体管的控制极为所述发光时间控制子电路的控制端，所述发光时间控制晶体管的第一极为所述发光时间控制子电路的第一端，所述发光时间控制晶体管的第二极为所述发光时间控制子电路的第二端。
可选的，所述第一复位子电路包括第一复位晶体管和第二复位晶体管；
所述第一复位晶体管的控制极与所述复位控制线电连接，所述第一复位晶体管的第一极与所述发光时间控制子电路的控制端电连接，所述第一复位晶体管的第二极与所述发光时间控制子电路的第二端电连接；
所述第二复位晶体管的控制极与所述复位控制线电连接，所述第二复位晶体管的第一极与所述发光时间控制子电路的第一端电连接，所述第二复位晶体管的第二极与第一初始电压端连接；所述第一初始电压端用于提供所述第一初始电压。
可选的，所述时间控制数据写入子电路包括时间控制数据写入晶体管；
所述时间控制数据写入晶体管的控制极与所述第一栅线电连接，所述时间控制数据写入晶体管的第一极与所述时间控制数据线电连接，所述时间控制数据写入晶体管的第二极与所述第一储能子电路的第二端电连接。
可选的，所述数据控制子电路包括数据控制晶体管；所述第一储能子电路包括时间控制电容；
所述数据控制晶体管的控制极与所述发光控制线电连接，所述数据控制晶体管的第一极与所述时间控制数据线电连接，所述数据控制晶体管的第二极与所述第一储能子电路的第二端电连接；
所述第一储能子电路的第一端为所述时间控制电容的第一端，所述第一储能子电路的第二端为所述时间控制电容的第二端。
可选的，所述第一发光控制子电路包括第一发光控制晶体管；
所述第一发光控制晶体管的控制极与所述发光控制线电连接，所述第一发光控制晶体管的第一极与所述第一电压端电连接，所述第一发光控制晶体管的第二极与所述发光时间控制子电路的第一端电连接。
可选的，所述第二发光控制子电路包括第二发光控制晶体管；
所述第二发光控制晶体管的控制极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述发光时间控制子电路的第二端电连接，所述第二发光控制晶体管的第二极与所述输出端电连接。
可选的，所述发光时间控制子电路包括发光时间控制晶体管；所述第一复位子电路包括第一复位晶体管和第二复位晶体管；所述时间控制数据写入子电路包括时间控制数据写入晶体管；所述数据控制子电路包括数据控制晶体管；所述第一发光控制子电路包括第一发光控制晶体管；所述第一储能子电路包括时间控制电容；
所述发光时间控制晶体管的控制极为所述发光时间控制子电路的控制端，所述发光时间控制晶体管的第一极为所述发光时间控制子电路的第一端，所述发光时间控制晶体管的第二极为所述发光时间控制子电路的第二端；
所述第一复位晶体管的控制极与所述复位控制线电连接，所述第一复位晶体管的第一极与所述发光时间控制子电路的控制端电连接，所述第一复位晶体管的第二极与所述发光时间控制子电路的第二端电连接；
所述第二复位晶体管的控制极与所述复位控制线电连接，所述第二复位晶体管的第一极与所述发光时间控制子电路的第一端电连接，所述第二复位晶体管的第二极与第一初始电压端连接；所述第一初始电压端用于提供所述第一初始电压；
所述时间控制数据写入晶体管的控制极与所述第一栅线电连接，所述时间控制数据写入晶体管的第一极与所述时间控制数据线电连接，所述时间控制数据写入晶体管的第二极与所述第一储能子电路的第二端电连接；
所述数据控制晶体管的控制极与所述发光控制线电连接，所述数据控制晶体管的第一极与所述时间控制数据线电连接，所述数据控制晶体管的第二极与所述第一储能子电路的第二端电连接；
所述第一发光控制晶体管的控制极与所述发光控制线电连接，所述第一发光控制晶体管的第一极与所述第一电压端电连接，所述第一发光控制晶体管的第二极与所述发光时间控制子电路的第一端电连接；
所述第一储能子电路的第一端为所述时间控制电容的第一端，所述第一储能子电路的第二端为所述时间控制电容的第二端。
可选的，本公开至少一实施例所述的像素驱动电路还包括第二发光控制子电路；
所述第二发光控制子电路包括第二发光控制晶体管；
所述第二发光控制晶体管的控制极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述发光时间控制子电路的第二端电连接，所述第二发光控制晶体管的第二极与所述输出端电连接。
可选的，本公开至少一实施例所述的像素驱动电路还包括电流驱动子电路；
所述电流驱动子电路连接于所述发光时间控制子电路的第二端和所述输出端之间，所述电流驱动子电路还分别与电流控制数据线和所述输出端电连接，所述电流驱动子电路用于在发光阶段，根据所述电流控制数据线提供的电流控制数据电压，产生输出至所述输出端的驱动电流。
可选的，所述电流驱动子电路包括驱动子电路、电流控制数据写入子电路、第二复位子电路、补偿子电路和第二储能子电路；
所述驱动子电路的第一端与所述发光时间控制子电路的第二端电连接，所述驱动子电路的第二端与所述输出端电连接；所述驱动子电路用于在其控制端的电位的控制下，控制所述驱动子电路的第一端和所述驱动子电路的第二端之间电连接；
所述第二储能子电路的第一端与所述驱动子电路的控制端电连接，所述第二储能子电路的第二端与第二电压端电连接，所述第二储能子电路用于存储电压；
所述电流控制数据写入子电路分别与第二栅线、所述电流控制数据线和所述驱动子电路的第一端电连接，用于在所述第二栅线提供的第二栅极驱动信号的控制下，控制所述电流控制数据线与所述驱动子电路的第一端之间电连接；
所述第二复位子电路分别与所述复位控制线、第二初始电压端和所述驱动子电路的控制端电连接，用于在所述复位控制线输入的复位控制信号的控制下，将所述第二初始电压端提供的第二初始电压提供至所述驱动子电路的控制端；
所述补偿子电路分别与所述第二栅线、所述驱动子电路的控制端和所述驱动子电路的第二端电连接，用于在所述第二栅极驱动信号的控制下，控制所述驱动子电路的控制端与所述驱动子电路的第二端之间电连接。
可选的，所述像素驱动电路还包括第二发光控制子电路；所述驱动子电路的第一端通过所述第二发光控制子电路与所述发光时间控制子电路的第二端电连接；
所述第二发光控制子电路的控制端与所述发光控制线电连接，所述第二发光控制子电路的第一端与所述发光时间控制子电路的第二端电连接，所述第二发光控制子电路的第二端与所述驱动子电路电连接；所述第二发光控制子电路用于在所述发光控制线提供的发光控制信号的控制下，控制所述发光时间控制子电路的第二端与所述驱动子电路之间电连接。
可选的，本公开至少一实施例所述的像素驱动电路还包括第三发光控制子电路；
所述驱动子电路的第二端通过所述第三发光控制子电路与所述输出端电连接；
所述第三发光控制子电路的控制端与所述发光控制线电连接，所述第三发光控制子电路用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动子电路的第二端与所述输出端之间电连接。
可选的，所述驱动子电路包括驱动晶体管；所述第二储能子电路包括电流控制电容；所述电流控制数据写入子电路包括电流控制数据写入晶体管；所述第二复位子电路包括第三复位晶体管；所述补偿子电路包括补偿晶体管；
所述驱动晶体管的控制极与所述电流控制电容的第一端电连接，所述驱动晶体管的第一极与所述发光时间控制子电路的第二端电连接，所述驱动晶体管的第二极与所述输出端电连接；
所述电流控制数据写入晶体管的控制极与所述第二栅线电连接，所述电流控制数据写入晶体管的第一极与所述电流控制数据线电连接，所述电流控制数据写入晶体管的第二极与所述驱动子电路的第一端电连接；
所述第三复位晶体管的控制极与所述复位控制线电连接，所述第三复位晶体管的第一极与第二初始电压端电连接，所述第三复位晶体管的第二极与所述驱动子电路的控制端电连接；
所述补偿晶体管的控制极与第二栅线电连接，所述补偿晶体管的第一极与所述驱动子电路的控制端电连接，所述补偿晶体管的第二极与所述驱动子电路的第二端电连接。
可选的，所述第三发光控制子电路包括第三发光控制晶体管；
所述第三发光控制晶体管的控制极与发光控制线电连接，所述第三发光控制晶体管的第一极与所述驱动子电路的第二端电连接，所述第三发光控制晶体管的第二极与所述输出端电连接。
可选的，所述像素驱动电路用于驱动发光元件；
所述输出端与所述发光元件的第一极电连接；
所述发光元件的第二极与第三电压端电连接。
可选的，所述发光元件为微发光二极管。
在第二个方面中，本公开实施例还提供了一种像素驱动方法，应用于上述的像素驱动电路，所述像素驱动方法包括：
分别向复位控制线和第一栅线提供打开信号，使得第一初始电压Vi1写入发光时间控制子电路的第一端，使得发光时间控制子电路的控制端与发光时间控制子电路的第二端之间电连接，使得时间控制数据线提供的预定时间控制数据电压VdT写入第一储能子电路的第二端，并使得所述发光时间控制子电路的第一端与所述发光时间控制子电路的第二端之间电连接，相应改变所述第一储能子电路的第一端的电压，直至所述发光时间控制子电路关断；
向所述第一栅线提供打开信号，使得时间控制数据线提供的预定电压V0写入所述第一储能子电路的第二端，以相应改变所述第一储能子电路的第一端的电压；
向发光控制线提供打开信号，使得发光时间控制子电路的第一端与第一电压端之间电连接，并使得所述时间控制数据线与所述第一储能子电路的第二端之间电连接，以相应改变所述第一储能子电路的第一端的电压，以使得所述发光时间控制子电路的第一端与所述发光时间控制子电路的第二端之间电连接或断开。
可选的，所述像素驱动电路还包括电流驱动子电路；
所述像素驱动方法包括：
在向发光控制线提供打开信号的同时，电流驱动子电路根据电流控制数据线提供的电流控制数据电压，产生输出至输出端的驱动电流。
可选的，所述电流驱动子电路包括驱动子电路、电流控制数据写入子电路、第二复位子电路、补偿子电路和第二储能子电路；所述输出端与发光元件电连接；所述像素驱动方法还包括：
在分别向复位控制线和第一栅线提供打开信号的同时，使得第二初始电压写入所述驱动子电路的控制端，以断开所述驱动子电路的第一端与所述驱动子电路的第二端之间的连接；
在向所述第一栅线提供打开信号的同时，向第二栅线提供打开信号，使得电流控制数据线提供的预定电流控制数据电压VdI写入所述驱动子电路的第一端，并使得所述驱动子电路的控制端与所述驱动子电路的第二端之间电 连接，以使得所述驱动子电路的第一端与所述驱动子电路的第二端之间电连接，以相应改变所述驱动子电路的控制端的电位，直至所述驱动子电路关断；
在向发光控制线提供打开信号的同时，驱动子电路产生驱动所述发光元件发光的驱动电流，以驱动发光元件发光。
在第三个方面中，本公开实施例还提供了一种显示装置，包括上述的像素驱动电路。
附图说明
图1A是本公开至少一实施例所述的像素驱动电路的结构图；
图1B是本公开至少一实施例所述的像素驱动电路的结构图；
图2是本公开至少一实施例所述的像素驱动电路的结构图；
图3是本公开至少一实施例所述的像素驱动电路的电路图；
图4是本公开如图3所示的像素驱动电路的至少一实施例的工作时序图；
图5A是本公开如图3所示的像素驱动电路的至少一实施例在复位时间段t1的工作状态示意图；
图5B是本公开如图3所示的像素驱动电路的至少一实施例在补偿时间段t2的工作状态示意图；
图5C是本公开如图3所示的像素驱动电路的至少一实施例在发光阶段te的工作状态示意图；
图6是多行像素驱动电路的至少一实施例的工作时序图；
图7是本公开至少一实施例所述的像素驱动电路的结构图；
图8是本公开至少一实施例所述的像素驱动电路的结构图；
图9是本公开至少一实施例所述的像素驱动电路的结构图；
图10是本公开至少一实施例所述的像素驱动电路的电路图；
图11是本公开如图10所示的像素驱动电路的至少一实施例的工作时序图；
图12A是本公开如图10所示的像素驱动电路的至少一实施例在复位时间段t1的工作状态示意图；
图12B是本公开如图10所示的像素驱动电路的至少一实施例在补偿时间 段t2的工作状态示意图；
图12C是本公开如图10所示的像素驱动电路的至少一实施例在发光阶段te的工作状态示意图；
图13是多行像素驱动电路的至少一实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
如图1A所示，本公开至少一实施例所述的像素驱动电路包括发光时间控制子电路11、第一复位子电路12、第一发光控制子电路13、时间控制数据写入子电路14、数据控制子电路15和第一储能子电路1；
所述第一复位子电路12分别与复位控制线R1、第一初始电压端、所述发光时间控制子电路11的第一端、所述发光时间控制子电路11的控制端和所述发光时间控制子电路11的第二端电连接，用于在复位控制线R1提供的复位控制信号的控制下，将第一初始电压端提供的第一初始电压Vi1写入所述发光时间控制子电路11的第一端，并在所述复位控制信号的控制下，控制所述发光时间控制子电路11的控制端与所述发光时间控制子电路11的第二端之间电连接；
所述第一储能子电路1的第一端与所述发光时间控制子电路11的控制端电连接；所述第一储能子电路1用于存储电压；
所述时间控制数据写入子电路14分别与第一栅线G1、时间控制数据线DT和所述第一储能子电路1的第二端电连接，用于在第一栅线G1提供的第一栅极驱动信号的控制下，控制时间控制数据线DT与所述第一储能子电路1的第二端之间电连接；
所述数据控制子电路15分别与发光控制线E1、所述时间控制数据线DT和所述第一储能子电路1的第二端电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述时间控制数据线DT与所述第一储能子电路1的第二端之间电连接；
所述第一发光控制子电路13分别与所述发光控制线E1、所述发光时间控制子电路11的第一端和第一电压端Vt1电连接，用于在所述发光控制信号的控制下，控制所述发光时间控制子电路11的第一端与第一电压端Vt1之间电连接；
所述发光时间控制子电路11的第二端与输出端U1电连接，所述发光时间控制子电路11用于在其控制端的电位的控制下，控制所述发光时间控制子电路11的第一端与所述发光时间控制子电路11的第二端之间电连接。
在本公开至少一实施例中，所述像素驱动电路用于驱动发光元件，所述输出端U1与所述发光元件电连接。
本公开至少一实施例所述的像素驱动电路能够通过控制发光元件的发光时间来确定发光亮度，可以解决发光元件在不同电流下色坐标偏移以及低电流密度下亮度不稳定的问题，可以在固定的较高电流密度下通过调节发光元件的发光时间来调节发光亮度，并能够补偿采用低温多晶硅技术而引起的晶体管的阈值电压偏移对发光亮度调节的影响。
在本公开至少一实施例中，所述发光元件可以为Micro LED(微发光二极管)或有机发光二极管，但不以此为限。
在本公开至少一实施例中，所述第一电压端Vt1提供的电压根据所述发光时间控制子电路11包括的发光时间控制晶体管的类型有关；
当所述发光时间控制晶体管为p型晶体管时，所述第一电压端Vt1提供的第一电压可以为0V电压或负电压，但不以此为限；
当所述发光时间控制晶体管为n型晶体管时，所述第一电压端Vt1提供的第一电压可以为正电压，但不以此为限。
在本公开实施例中，所述第一储能子电路1可以包括时间控制电容，但不以此为限。
如图1B所示，在图1A所示的像素驱动电路的至少一实施例的基础上，增加了发光元件10，所述发光元件10的第一极与所述输出端U1电连接，所述发光元件10的第二极可以接入低电压VSS，但不以此为限。
在本公开至少一实施例中，所述发光元件10的第一极可以为阳极，所述发光元件10的第二极可以为阴极，但不以此为限。
本公开至少一实施例所述的像素驱动电路在工作时，显示周期可以包括复位时间段、补偿时间段和发光阶段；
在所述复位时间段，第一复位子电路12在复位控制信号的控制下，将第一初始电压Vi1写入发光时间控制子电路11的第一端，并控制发光时间控制子电路11的控制端与发光时间控制子电路11的第二端之间电连接，时间控制数据写入子电路14在第一栅极驱动信号的控制下，控制时间控制数据线写入预定时间控制数据电压VdT至第一储能子电路1的第二端，发光时间控制子电路11在其控制端的控制下，控制所述发光时间控制子电路11的第一端与所述发光时间控制子电路11的第二端之间电连接，相应改变所述第一储能子电路1的第一端的电压，直至所述发光时间控制子电路11关断；
在所述补偿时间段，所述时间控制数据写入子电路14在第一栅线G1提供的第一栅极驱动信号的控制下，控制时间控制数据线DT写入预定电压V0至所述第一储能子电路1的第二端，以相应改变所述第一储能子电路1的第一端的电压；
在发光阶段，第一发光控制子电路13在发光控制信号的控制下，控制发光时间控制子电路11的第一端与第一电压端Vt1之间电连接，数据控制子电路15在发光控制线E1提供的发光控制信号的控制下，控制时间控制数据线DT与所述第一储能子电路1的第二端之间电连接，以相应改变所述第一储能 子电路1的第一端的电压，发光时间控制子电路11在所述第一储能子电路1的第一端的电压的控制下，控制所述发光时间控制子电路11的第一端与所述发光时间控制子电路11的第二端之间电连接或断开。
在本公开至少一实施例中，所述预定电压V0可以为0V，但不以此为限。在实际操作是，V0也可以为正电压或负电压，V0可以根据实际情况选定。
在本公开至少一实施例中，所述发光时间控制子电路11关断指的是：所述发光时间控制子电路11断开其第一端与第二端之间的连接；
所述发光时间控制子电路11导通指的是：所述发光时间控制子电路11控制其第一端与第二端之间电连接。
本公开至少一实施例所述的像素驱动电路在工作时，在发光阶段，DT提供的时间控制数据电压是变化的，以控制所述发光时间控制子电路11从导通至关断，或控制所述发光时间控制子电路11从关断至导通，以控制驱动发光元件10发光的时间。
在所述发光阶段，所述时间控制数据线提供的时间控制数据电压可以等于V0-Kt，t为当前时间与所述发光阶段开始的时间之间的时间差值；
所述发光时间控制子电路包括的发光时间控制晶体管为p型晶体管，K可以为正数，但不以此为限；或者，
所述发光时间控制子电路包括的发光时间控制晶体管为n型晶体管，K可以为负数，但不以此为限。
在所述发光阶段，所述时间控制数据电压也可以根据其他规律变化，也可控制发光元件的发光时间。
在具体实施时，本公开至少一实施例所述的像素驱动电路还可以包括第二发光控制子电路；
所述第二发光控制子电路分别与所述发光控制线、所述发光时间控制子电路的第二端和所述输出端电连接，用于在所述发光控制信号的控制下，控制所述发光时间控制子电路的第二端与所述发光元件之间电连接。
如图2所示，在图1B所示的像素驱动电路的至少一实施例的基础上，本公开至少一实施例所述的像素驱动电路可以还包括第二发光控制子电路16；
所述第二发光控制子电路16分别与所述发光控制线E1、所述发光时间控制子电路11的第二端和所述输出端U1电连接，用于在所述发光控制信号的控制下，控制所述发光时间控制子电路11的第二端与所述输出端U1之间电连接。
本公开至少一实施例所述的像素驱动电路通过增加所述第二发光控制子电路16，能够在发光控制信号的控制下，控制所述发光时间控制子电路11的第二端与所述发光元件10的第一极之间是否电连接。
在图2所示的像素驱动电路的至少一实施例中，当VSS大于或等于Vi1时，则在复位时间段，所述发光元件10处于反向偏置状态，此时才可以省去所述第二发光控制子电路16；当VSS小于Vi1时，需要设置所述第二发光控制子电路16。
可选的，所述发光时间控制子电路可以包括发光时间控制晶体管；
所述发光时间控制晶体管的控制极为所述发光时间控制子电路的控制端，所述发光时间控制晶体管的第一极为所述发光时间控制子电路的第一端，所述发光时间控制晶体管的第二极为所述发光时间控制子电路的第二端。
可选的，所述第一复位子电路可以包括第一复位晶体管和第二复位晶体管；
所述第一复位晶体管的控制极与所述复位控制线电连接，所述第一复位晶体管的第一极与所述发光时间控制子电路的控制端电连接，所述第一复位晶体管的第二极与所述发光时间控制子电路的第二端电连接；
所述第二复位晶体管的控制极与所述复位控制线电连接，所述第二复位晶体管的第一极与所述发光时间控制子电路的第一端电连接，所述第二复位晶体管的第二极与第一初始电压端连接；所述第一初始电压端用于提供所述第一初始电压。
可选的，所述时间控制数据写入子电路可以包括时间控制数据写入晶体管；
所述时间控制数据写入晶体管的控制极与所述第一栅线电连接，所述时间控制数据写入晶体管的第一极与所述时间控制数据线电连接，所述时间控制数据写入晶体管的第二极与所述第一储能子电路的第二端电连接。
可选的，所述数据控制子电路可以包括数据控制晶体管；
所述数据控制晶体管的控制极与所述发光控制线电连接，所述数据控制晶体管的第一极与所述时间控制数据线电连接，所述数据控制晶体管的第二极与所述第一储能子电路的第二端电连接。
可选的，所述第一发光控制子电路可以包括第一发光控制晶体管；
所述第一发光控制晶体管的控制极与所述发光控制线电连接，所述第一发光控制晶体管的第一极与所述第一电压端电连接，所述第一发光控制晶体管的第二极与所述发光时间控制子电路的第一端电连接。
可选的，所述第二发光控制子电路可以包括第二发光控制晶体管；
所述第二发光控制晶体管的控制极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述发光时间控制子电路的第二端电连接，所述第二发光控制晶体管的第二极与所述输出端电连接。
在本公开至少一实施例中，所述发光时间控制子电路可以包括发光时间控制晶体管；所述第一复位子电路可以包括第一复位晶体管和第二复位晶体管；所述时间控制数据写入子电路可以包括时间控制数据写入晶体管；所述数据控制子电路可以包括数据控制晶体管；所述第一发光控制子电路可以包括第一发光控制晶体管；所述第一储能子电路可以包括时间控制电容；
所述发光时间控制晶体管的控制极为所述发光时间控制子电路的控制端，所述发光时间控制晶体管的第一极为所述发光时间控制子电路的第一端，所述发光时间控制晶体管的第二极为所述发光时间控制子电路的第二端；
所述第一复位晶体管的控制极与所述复位控制线电连接，所述第一复位晶体管的第一极与所述发光时间控制子电路的控制端电连接，所述第一复位晶体管的第二极与所述发光时间控制子电路的第二端电连接；
所述第二复位晶体管的控制极与所述复位控制线电连接，所述第二复位晶体管的第一极与所述发光时间控制子电路的第一端电连接，所述第二复位晶体管的第二极与第一初始电压端连接；所述第一初始电压端用于提供所述第一初始电压；
所述时间控制数据写入晶体管的控制极与所述第一栅线电连接，所述时间控制数据写入晶体管的第一极与所述时间控制数据线电连接，所述时间控制数据写入晶体管的第二极与所述第一储能子电路的第二端电连接；
所述数据控制晶体管的控制极与所述发光控制线电连接，所述数据控制晶体管的第一极与所述时间控制数据线电连接，所述数据控制晶体管的第二极与所述第一储能子电路的第二端电连接；
所述第一发光控制晶体管的控制极与所述发光控制线电连接，所述第一发光控制晶体管的第一极与所述第一电压端电连接，所述第一发光控制晶体管的第二极与所述发光时间控制子电路的第一端电连接；
所述第一储能子电路的第一端为所述时间控制电容的第一端，所述第一储能子电路的第二端为所述时间控制电容的第二端。
可选的，本公开至少一实施例所述的像素驱动电路还可以包括第二发光控制子电路；
所述第二发光控制子电路可以包括第二发光控制晶体管；
所述第二发光控制晶体管的控制极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述发光时间控制子电路的第二端电连接，所述第二发光控制晶体管的第二极与所述输出端电连接。
如图3所示，本公开至少一实施例所述的像素驱动电路用于驱动微发光二极管O1，所述像素驱动电路包括发光时间控制子电路11、第一复位子电路12、第一发光控制子电路13、时间控制数据写入子电路14、数据控制子电路15、第二发光控制子电路16和第一储能子电路1，其中，
所述发光时间控制子电路11包括发光时间控制晶体管M4；所述第一复位子电路12包括第一复位晶体管M3和第二复位晶体管M5；所述时间控制数据写入子电路14包括时间控制数据写入晶体管M1；所述数据控制子电路15包括数据控制晶体管M7；所述第一发光控制子电路13包括第一发光控制晶体管M2；所述第二发光控制子电路16包括第二发光控制晶体管M6；第一储能子电路1包括时间控制电容C1；
M3的栅极与所述复位控制线R1电连接，M3的源极与M4的栅极电连接，M3的漏极与M4的漏极电连接；
M5的栅极与所述复位控制线R1电连接，所述第二复位晶体管M5的源极与M4的源极电连接，M5的漏极与第一初始电压端连接；所述第一初始电压端用于提供所述第一初始电压Vi1；
M1的栅极与所述第一栅线G1电连接，M1的源极与所述时间控制数据线DT电连接，M1的漏极与C1的第二端电连接；
M7的栅极与发光控制线E1电连接，M7的源极与所述时间控制数据线DT电连接，M7的漏极与C1的第二端电连接；C1的第一端与M4的栅极电连接；
M2的栅极与所述发光控制线E1电连接，M2的源极接入第一电压VDD，M2的漏极与M4的源极电连接；
M6的栅极与所述发光控制线E1电连接，M6的源极与M4的漏极电连接，M6的漏极与O1的阳极电连接；
O1的阴极接入低电压VSS。
在图3所示的至少一实施例中，所有的晶体管都为p型薄膜晶体管，但不以此为限。
在图3中，N1为与M4的栅极连接的第一节点，N2为与C1的第二端连接的第二节点。
在图3所示的至少一实施例中，Vi1可以为0V，但不以此为限。Vi1的取值可以根据实际情况选定。
在图3所示的至少一实施例中，O1的阳极可以为发光元件的第一极，O1的阴极可以为发光元件的第二极。在图3所示的像素驱动电路的至少一实施例中，当VSS大于或等于Vi1时，则在复位时间段，O1处于反向偏置状态，此时才可以省去M6；当VSS小于Vi1时，需要设置M6。
如图4所示，如图3所示的像素驱动电路的至少一实施例在工作时，显示周期包括复位时间段t1、补偿时间段t2和发光阶段te；
在复位时间段t1，如图5A所示，E1输入高电平，M2、M6和M7关闭，R1和G1都输入低电平，M1、M3、M4和M5开启；DT输入预定时间控制数据电压VdT，则N2的电压等于VdT，M4的源极的电压为Vi1，则M4导 通以改变M4的栅极的电位，直至N1的电位变为Vi1+Vth4，Vth4为M4的阈值电压；Vi1被设置为0V，则N1的电位为Vth4，N2的电位为VdT；
在补偿时间段t2，如图5B所示，E1输入高电平，M2、M6和M7关闭，R1输入高电平，M3和M5关闭，DT输入0V数据电压；根据电荷保持定律，N2的电位从VdT跳变为0V，则N1的电位会从Vth4跳变为Vth4-VdT；在N1的电位的控制下，M4关断；
在发光阶段te，如图5C所示，G1输入高电平，M1关闭，R1输入高电平，M3和M5保持关闭，E1输入低电平，M2、M6和M7开启；此时DT提供的时间控制数据电压的波形如图4中所示，即时间控制数据电压从补偿时间段t2的0V电压按着固定的斜率往下降，直至下一帧显示时间开始，所述时间控制数据电压的电压值为预定电压；
在发光阶段te，所述时间控制数据电压从0V降至VdT时，N1的电位根据电荷保持定律跳变至Vth4，M4的栅源电压Vgs4等于Vth4-VDD，优先设置VDD为0V或更低，即Vgs4>Vth4，此时M4开启；也即，在发光阶段te，M4由关闭至开启，M4的开启时间取决于VdT和时间控制数据电压在发光阶段te的取值，M4的开启时间不受Vth4的影响。
在发光阶段te，M4处于完全开启状态，处于非饱和区。
在图4中，Id为驱动O1发光的驱动电流，Vn1为N1的电压。
在本公开至少一实施例中，显示面板可以包括多行多列上述像素驱动电路，则如图6所示，一帧画面显示时间F1可以包括依次设置的准备阶段和发光阶段te；
所述准备阶段可以包括依次设置的多个准备时间段，每一个准备时间段包括依次设置的复位时间段和补偿时间段；
在图6中，标号为t1-1的为第一复位时间段，标号为t1-2的为第一补偿时间段，标号为t2-1的为第二复位时间段，标号为t2-2的为第二补偿时间段，标号为tn-1的为第n复位时间段，标号为tn-2的为第n补偿时间段，标号为E1的为发光控制线，标号为DTm的为第m列时间控制数据线，标号为R11的为第一行复位控制线，标号为G11的为第一行第一栅线，标号为R12的为第二行复位控制线，标号为G12的为第二行第一栅线，标号为G1n的为第n 行第一栅线，标号为R1n的为第n行复位控制线，标号为Vn11的为第一行第m列像素驱动电路中的第一节点N1的电位，标号为Vn12的为第二行第m列像素驱动电路中的第一节点N1的电位，标号为Id1的为第一行第m列微发光二极管的驱动电流，标号为Id2的为第二行第m列微发光二极管的驱动电流，标号为Idn的为第n行第m列微发光二极管的驱动电流，其中，m为正整数，n为大于2的整数。
在本公开至少一实施例中，第一行第m列像素驱动电路用于驱动第一行第m列微发光二极管，第二行第m列像素驱动电路用于驱动第二行第m列微发光二极管，第n行第m列像素驱动电路用于驱动第n行第m列微发光二极管。
如图6所示，在t1-1，DTm写入第一时间控制数据电压VdT1，在t1-2，DTm写入0V电压；在t1-2，DTm写入第二时间控制数据电压VdT2，在t2-2，DTm写入0V电压；在t1-n，DTm写入第n时间控制数据电压VdTn，在tn-2，DTm写入0V电压；在te，DTm上的数据电压由0V以固定斜率下降，以控制各行微发光二极管的发光时间。
在相关技术中，微发光二极管因其低驱动电压、超高亮度、长寿命、耐高温等特点被认为是次世代显示面板技术，但其转移绑定不成熟、无对应的玻璃基驱动背板，而迟迟不能推向消费者市场。本公开至少一实施例提出玻璃基驱动背板解决方案，提出的像素驱动电路主要解决微发光二极管在不同电流下色坐标偏移以及低电流密度下亮度不稳定的问题。
在相关技术中，微发光二极管的像素驱动电路大部分在PCB(Printed Circuit Board，印刷电路板)基板上的原因是：由于采用低温多晶硅技术以将像素驱动电路制作于玻璃基板上时，会因为由低温多晶硅技术而引起的晶体管的阈值电压偏移而对发光亮度产生影响。而本公开至少一实施例所述的像素驱动电路能够补偿阈值电压的偏移，因此能够提供玻璃基驱动背板解决方案。
本公开至少一实施例所述的像素驱动电路在固定电流下或固定电压下通过控制发光的时间来控制灰阶，且考虑因采用低温多晶硅而引起的晶体管的阈值电压偏移，补偿了阈值电压的偏移，所控制的发光时间控制晶体管M4 的开启不受其阈值电压的影响，可根据时间控制数据电压来精确的控制发光时间使得灰阶更多。
本公开至少一实施例所述的像素驱动电路通过N1的电位控制M4的开启时间，并决定电流导通至微发光二极管的时间，即根据一帧显示时间内微发光二极管发光的时间来决定人眼看到的亮度。
本公开至少一实施例提出玻璃基驱动背板解决方案，提出的像素驱动电路主要解决微发光二极管在不同电流下色坐标偏移以及低电流密度下亮度不稳定的问题。本公开至少一实施例提出一种新的基于玻璃基的微发光二极管显示面板的像素驱动电路，在固定电流下或固定电压下通过控制发光的时间来控制灰阶的驱动方案。
如图7所示，本公开至少一实施例所述的像素驱动电路用于驱动发光元件10发光，所述像素驱动电路包括电流驱动子电路70、发光时间控制子电路11、第一储能子电路1、第一复位子电路12、第一发光控制子电路13、时间控制数据写入子电路14和数据控制子电路15；
所述第一复位子电路12分别与复位控制线R1、第一初始电压端、所述发光时间控制子电路11的第一端、所述发光时间控制子电路11的控制端和所述发光时间控制子电路11的第二端电连接，用于在复位控制线R1输入的复位控制信号的控制下，将第一初始电压端提供的第一初始电压Vi1写入所述发光时间控制子电路11的第一端，并控制所述发光时间控制子电路11的控制端与所述发光时间控制子电路的第二端11之间电连接；
所述第一储能子电路1的第一端与所述发光时间控制子电路11的控制端电连接；
所述时间控制数据写入子电路14分别与第一栅线G1、时间控制数据线DT和所述第一储能子电路1的第二端电连接，用于在第一栅线G1提供的第一栅极驱动信号的控制下，控制时间控制数据线DT与所述第一储能子电路1的第二端之间电连接；
所述数据控制子电路15分别与发光控制线E1、所述时间控制数据线DT和所述第一储能子电路1的第二端电连接，用于在所述发光控制线E1提供的 发光控制信号的控制下，控制所述时间控制数据线DT与所述第一储能子电路1的第二端之间电连接；
所述第一发光控制子电路13分别与所述发光控制线E1、所述发光时间控制子电路11的第一端和第一电压端Vt1电连接，用于在所述发光控制信号的控制下，控制所述发光时间控制子电路11的第一端与第一电压端Vt1之间电连接；
所述发光时间控制子电路11的第二端与所述发光元件10的第一极电连接，所述发光时间控制子电路11用于在其控制端的电位的控制下，控制所述发光时间控制子电路11的第一端与所述发光时间控制子电路11的第二端之间电连接；
所述电流驱动子电路70与电流控制数据线DI电连接，并所述电流驱动子电路70连接于所述发光时间控制子电路11的第二端和所述发光元件10的第一极之间，用于在发光阶段，根据电流控制数据线DI上的电流控制数据电压，产生驱动所述发光元件10发光的驱动电流；
所述发光元件10的第一极与输出端U1电连接，所述发光元件10的第二极接入低电压VSS。
本公开至少一实施例所述的像素驱动电路在工作时，电流驱动子电路70控制驱动所述发光元件10发光的驱动电流的大小，发光时间控制子电路11、第一储能子电路1、第一复位子电路12、第一发光控制子电路13、时间控制数据写入子电路14和数据控制子电路15控制所述发光元件10的发光时间。
本公开至少一实施例所述的像素驱动电路在工作时，显示周期可以包括复位时间段、补偿时间段和发光阶段；
在所述复位时间段，第一复位子电路12在复位控制信号的控制下，将第一初始电压Vi1写入发光时间控制子电路11的第一端，并控制发光时间控制子电路11的控制端与发光时间控制子电路11的第二端之间电连接，时间控制数据写入子电路14在第一栅极驱动信号的控制下，控制时间控制数据线写入预定时间控制数据电压VdT至第一储能子电路1的第二端，发光时间控制子电路11在其控制端的控制下，控制所述发光时间控制子电路11的第一端 与所述发光时间控制子电路11的第二端之间电连接，相应改变所述第一储能子电路1的第一端的电压，直至所述发光时间控制子电路11关断；
在所述补偿时间段，所述时间控制数据写入子电路14在第一栅线G1提供的第一栅极驱动信号的控制下，控制时间控制数据线DT写入预定电压V0至第一储能子电路1的第二端，以相应改变所述第一储能子电路1的第一端的电压；
在发光阶段，电流驱动子电路70根据电流控制数据线DI上的电流控制数据电压，产生驱动所述发光元件10发光的驱动电流；第一发光控制子电路13在发光控制信号的控制下，控制发光时间控制子电路11的第一端与第一电压端Vt1之间电连接，数据控制子电路15在发光控制线E1提供的发光控制信号的控制下，控制时间控制数据线DT与所述第一储能子电路1的第二端之间电连接，以相应改变所述第一储能子电路1的第一端的电压，发光时间控制子电路11在所述第一储能子电路1的第一端的电压的控制下，控制所述发光时间控制子电路11的第一端与所述发光时间控制子电路11的第二端之间电连接或断开。
可选的，所述电流驱动子电路可以包括驱动子电路、电流控制数据写入子电路、第二复位子电路、补偿子电路和第二储能子电路；
所述驱动子电路的第一端与所述发光时间控制子电路的第二端电连接，所述驱动子电路的第二端与所述输出端电连接；所述驱动子电路用于在其控制端的电位的控制下，控制所述驱动子电路的第一端和所述驱动子电路的第二端之间电连接；
所述第二储能子电路的第一端与所述驱动子电路的控制端电连接，所述第二储能子电路的第二端与第二电压端电连接，所述第二储能子电路用于存储电压；
所述电流控制数据写入子电路分别与第二栅线、所述电流控制数据线和所述驱动子电路的第一端电连接，用于在所述第二栅线提供的第二栅极驱动信号的控制下，控制所述电流控制数据线与所述驱动子电路的第一端之间电连接；
所述第二复位子电路分别与所述复位控制线、第二初始电压端和所述驱动子电路的控制端电连接，用于在所述复位控制线输入的复位控制信号的控制下，将所述第二初始电压端提供的第二初始电压提供至所述驱动子电路的控制端；
所述补偿子电路分别与所述第二栅线、所述驱动子电路的控制端和所述驱动子电路的第二端电连接，用于在所述第二栅极驱动信号的控制下，控制所述驱动子电路的控制端与所述驱动子电路的第二端之间电连接。
在本公开至少一实施例中，所述第一储能子电路可以包括时间控制电容，所述第二储能子电路可以包括电流控制电容。
如图8所示，在图7所示的像素驱动电路的至少一实施例的基础上，所述电流驱动子电路可以包括驱动子电路71、电流控制数据写入子电路72、第二复位子电路73、补偿子电路74和第二储能子电路70；
所述驱动子电路71的第一端与所述发光时间控制子电路11的第二端电连接，所述驱动子电路71的第二端与所述发光元件10的第一极电连接；所述驱动子电路71用于在其控制端的电位的控制下，控制所述驱动子电路71的第一端和所述驱动子电路71的第二端之间电连接；
所述第二储能子电路70的第一端与所述驱动子电路71的控制端电连接，所述第二储能子电路70的第二端与第二电压端Vt2电连接；
所述电流控制数据写入子电路72分别与第二栅线G2、电流控制数据线DI和所述驱动子电路71的第一端电连接，用于在第二栅线G2提供的第二栅极驱动信号的控制下，控制电流控制数据线DI与所述驱动子电路71的第一端之间电连接；
所述第二复位子电路73分别与所述复位控制线R1、第二初始电压端和所述驱动子电路71的控制端电连接，用于在复位控制线R1输入的复位控制信号的控制下，将第二初始电压Vi2提供至所述驱动子电路71的控制端；所述第二初始电压端用于提供第二初始电压Vi2；
所述补偿子电路74分别与第二栅线G2、所述驱动子电路71的控制端和所述驱动子电路71的第二端电连接，用于在所述第二栅极驱动信号的控制下，控制所述驱动子电路71的控制端与所述驱动子电路71的第二端之间电连接。
在本公开至少一实施例中，所述第二电压端可以与所述第一电压端相同，但不以此为限。在实际操作时，所述第二电压端也可以与所述第一电压端不同。
本公开如图8所示的像素驱动电路的至少一实施例在工作时，
在所述复位时间段，所述第二复位子电路73在所述复位控制信号的控制下，将第二初始电压Vi2提供至所述驱动子电路71的控制端，以使得所述驱动子电路71在其控制端的电位的控制下，断开所述驱动子电路71的第一端与所述驱动子电路71的第二端之间的连接；
在所述补偿时间段，所述电流控制数据写入子电路72在第二栅线G2提供的第二栅极驱动信号的控制下，控制电流控制数据线DI写入预定电流控制数据电压VdI至所述驱动子电路71的第一端，所述补偿子电路74在所述第二栅极驱动信号的控制下，控制所述驱动子电路71的控制端与所述驱动子电路71的第二端之间电连接，以使得所述驱动子电路71在其控制端的电位的控制下，控制所述驱动子电路71的第一端与所述驱动子电路71的第二端之间电连接，以相应改变所述驱动子电路71的控制端的电位，直至所述驱动子电路71关断；
在所述发光阶段，所述驱动子电路71在其控制端的电位的控制下，产生驱动所述发光元件10发光的驱动电流，以驱动发光元件10发光。
可选的，所述像素驱动电路还可以包括第二发光控制子电路；所述驱动子电路的第一端通过所述第二发光控制子电路与所述发光时间控制子电路的第二端电连接；
所述第二发光控制子电路的控制端与发光控制线电连接，所述第二发光控制子电路的第一端与所述发光时间控制子电路的第二端电连接，所述第二发光控制子电路的第二端与所述驱动子电路电连接；所述第二发光控制子电路用于在所述发光控制线提供的发光控制信号的控制下，控制所述发光时间控制子电路的第二端与所述驱动子电路之间电连接。
可选的，本公开至少一实施例所述的像素驱动电路还可以包括第三发光控制子电路；
所述驱动子电路的第二端通过所述第三发光控制子电路与所述输出端电连接；
所述第三发光控制子电路用于在发光控制线提供的发光控制信号的控制下，控制所述驱动子电路的第二端与所述输出端之间电连接。
如图9所示，在图8所示的像素驱动电路的至少一实施例的基础上，本公开至少一实施例所述的像素驱动电路还可以包括第二发光控制子电路16和第三发光控制子电路75；
所述驱动子电路71的第一端通过所述第二发光控制子电路16与所述发光时间控制子电路11的第二端电连接；
所述第二发光控制子电路16的控制端与发光控制线E1电连接，所述第二发光控制子电路16的第一端与所述发光时间控制子电路11的第二端电连接，所述第二发光控制子电路16的第二端与所述驱动子电路71的第一端电连接；所述第二发光控制子电路16用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述发光时间控制子电路11的第二端与所述驱动子电路71的第一端之间电连接；
所述驱动子电路71的第二端通过所述第三发光控制子电路75与所述发光元件10的第一极电连接；所述发光元件10的第二极接入低电压VSS；所述发光元件10的第一极与输出端U1电连接；
所述第三发光控制子电路75与发光控制线E1电连接，用于在发光控制线E1提供的发光控制信号的控制下，控制所述驱动子电路71的第二端与所述发光元件10的第一极之间电连接。
本公开如图9所示的像素驱动电路的至少一实施例在工作时，在发光阶段，在发光控制信号的控制下，第二发光控制子电路16控制其第一端与其第二端之间电连接，第三发光控制子电路75控制所述驱动子电路71的第二端与所述发光元件10的第一极之间电连接。
可选的，所述第二储能子电路可以包括电流控制电容，所述第二储能子电路的第一端为所述电流控制电容的第一端，所述第二储能子电路的第二端为所述电流控制电容的第二端，但不以此为限。
可选的，所述驱动子电路可以包括驱动晶体管；
所述驱动晶体管的控制极与所述电流控制电容的第一端电连接，所述驱动晶体管的第一极与所述发光时间控制子电路的第二端电连接，所述驱动晶体管的第二极与所述输出端电连接。
可选的，所述电流控制数据写入子电路可以包括电流控制数据写入晶体管；
所述电流控制数据写入晶体管的控制极与所述第二栅线电连接，所述电流控制数据写入晶体管的第一极与所述电流控制数据线电连接，所述电流控制数据写入晶体管的第二极与所述驱动子电路的第一端电连接。
可选的，所述第二复位子电路可以包括第三复位晶体管；
所述第三复位晶体管的控制极与所述复位控制线电连接，所述第三复位晶体管的第一极与第二初始电压端电连接，所述第三复位晶体管的第二极与所述驱动子电路的控制端电连接。
可选的，所述补偿子电路可以包括补偿晶体管；
所述补偿晶体管的控制极与第二栅线电连接，所述补偿晶体管的第一极与所述驱动子电路的控制端电连接，所述补偿晶体管的第二极与所述驱动子电路的第二端电连接。
可选的，所述第三发光控制子电路可以包括第三发光控制晶体管；
所述第三发光控制晶体管的控制极与发光控制线电连接，所述第三发光控制晶体管的第一极与所述驱动子电路的第二端电连接，所述第三发光控制晶体管的第二极与所述输出端电连接。
如图10所示，本公开至少一实施例所述的像素驱动电路用于驱动微发光二极管O1发光；
所述像素驱动电路包括电流驱动子电路、发光时间控制子电路11、第一储能子电路1，第一复位子电路12、第一发光控制子电路13、时间控制数据写入子电路14、数据控制子电路15和第二发光控制子电路15，其中，
所述发光时间控制子电路11包括发光时间控制晶体管M4；所述第一复位子电路12包括第一复位晶体管M3和第二复位晶体管M5；所述时间控制数据写入子电路14包括时间控制数据写入晶体管M1；所述数据控制子电路15包括数据控制晶体管M7；所述第一发光控制子电路13包括第一发光控制 晶体管M2；所述第二发光控制子电路15包括第二发光控制晶体管M6；所述第一储能子电路1包括时间控制电容C1；
M3的栅极与所述复位控制线R1电连接，M3的源极与M4的栅极电连接，M3的漏极与M4的漏极电连接；
M5的栅极与所述复位控制线R1电连接，所述第二复位晶体管M5的源极与M4的源极电连接，M5的漏极与第一初始电压端连接；所述第一初始电压端用于提供所述第一初始电压Vi1；
M1的栅极与所述第一栅线G1电连接，M1的源极与所述时间控制数据线DT电连接，M1的漏极与C1的第二端电连接；C1的第一端与M4的栅极电连接；
M7的栅极与发光控制线E1电连接，M7的源极与所述时间控制数据线DT电连接，M7的漏极与C1的第二端电连接；
M2的栅极与所述发光控制线E1电连接，M2的源极接入第一电压VDD，M2的漏极与M4的源极电连接；
M6的栅极与所述发光控制线E1电连接，M6的源极与M4的漏极电连接；
O1的阴极接入低电压VSS；
所述电流驱动子电路包括驱动子电路71、电流控制数据写入子电路72、第二复位子电路73、补偿子电路74、第三发光控制子电路75和第二储能子电路70；
所述第二储能子电路70包括电流控制电容C2；
所述驱动子电路71包括驱动晶体管M9；
M9的栅极与C2的第一端电连接，M9的源极与M6的漏极端电连接；
所述电流控制数据写入子电路72包括电流控制数据写入晶体管M8；
所述电流控制数据写入晶体管M8的栅极与所述第二栅线G2电连接，所述电流控制数据写入晶体管M8的源极与所述电流控制数据线DI电连接，所述电流控制数据写入晶体管M8的漏极与M9的源极电连接；
所述第二复位子电路73包括第三复位晶体管M11；
M11的栅极与所述复位控制线R1电连接，M11的源极与第二初始电压端电连接，M11的漏极与M9的栅极电连接；所述第二初始电压端用于提供第二初始电压Vi2；
所述补偿子电路74包括补偿晶体管M10；
所述补偿晶体管M10的栅极与第二栅线G2电连接，所述补偿晶体管M10的源极与M9的栅极电连接，M10的漏极与M9的漏极电连接；
所述第三发光控制子电路75包括第三发光控制晶体管M12；
M12的栅极与发光控制线E1电连接，M12的源极与M9的漏极电连接，M12的漏极与所述微发光二极管O1的阳极电连接；
C2的第一端与M9的栅极电连接，C2的第二端接入第一电压VDD。
在图10所示的像素驱动电路的实施例中，所有的晶体管都为p型薄膜晶体管，第一电压端和第二电压端为同一电压端，但不以此为限。
在图10中，标号为N1的为与M4的栅极电连接的第一节点，标号为N2的为与C1的第二端电连接的第二节点，标号为N3的是与M9的栅极电连接的第三节点，N4是与M9的源极电连接的第四节点。在图10所示的像素驱动电路的实施例中，可以省去M6；
在图10所示的像素驱动电路的至少一实施例中，当VdI小于或等于VSS时，可以省去M12；而当VdI大于VSS时，不可以省去M12。
图10所示的像素驱动电路的至少一实施例在工作时，在补偿时间段t2，若不设置M12，当VdI小于或等于VSS时，O1工作于反向偏置状态，则可以省去M12；
而当VdI大于VSS时，则不可省去M12。
如图11所示，图10所示的像素驱动电路的至少一实施例在工作时，显示周期可以包括复位时间段t1、补偿时间段t2和发光阶段te；
在复位时间段t1，如图12A所示，E1输入高电平，M2、M6、M7、M8、M9、M11和M12关闭，R1和G1输入低电平，M1、M3、M4、M5和M11开启；DT输入预定时间控制数据电压VdT，N2的电压为VdT，M4的源极的电压为Vi1，则M4导通以改变M4的栅极的电位，直至N1的电位变为 Vi1+Vth4，Vth4为M4的阈值电压；Vi1被设置为0V，则N1的电位为Vth4，N2的电位为VdT；N3的电压为Vi2；Vi2也可以被设置为0V；
在补偿时间段t2，如图12B所示，EM输入高电平，M2、M6和M7还是关闭，R1输入高电平，M3、M5和M11关闭，DT输入0V电压，根据电荷保持定律，N2的电压从VdT跳变至0V，N1的电位由Vth4跳变至Vth4-VdT；同时G2输入低电平，M8和M10开启，M9开启，以改变N3的电压，直至M9关闭，N3的电压变为VdI+Vth9，且在C2的作用下保持不变；Vth9为M9的阈值电压；
在发光阶段，如图12C所示，此时G1和G2都输入高电平，M1、M8和M10关闭，R1输入高电平，M3、M5和M11保持关闭，E1输入低电平，M2、M6、M7和M12开启；此时DT提供的时间控制数据电压的波形如图11中所示，即所述时间控制数据电压从0V电压按着固定的斜率往下降，直至下一帧显示时间开始，所述时间控制数据电压的电压值为预定电压；
在发光阶段，当所述时间控制数据电压从0V降至VdT时，M4的栅极电压根据电荷保持定律跳变至M4的阈值电压Vth4，M4的栅源电压Vgs4等于Vth4-VDD，VDD为0V或更低，即Vgs4＝VdT-VDD>Vth4；则当时间控制数据电压从0V跳变至VdT时，M4开启，则VdT决定M4开启的时间，不受M4的阈值电压的影响；M9为产生电流的驱动晶体管；根据驱动电流的公式，Id＝K(Vgs9-Vth9) 2＝K(VdI+Vth9-VDD-Vth9) 2＝K(VdI-VDD) 2；其中，Vgs9为M9的栅源电压，K为M9的电流系数，Id为M9产生的驱动电流，由上可知，Id与Vth9无关。
在所述发光阶段，M9处于饱和区。
本公开如图10所示的像素驱动电路的至少一实施例在工作时，M9产生驱动电流，M4控制发光时间，不同的驱动电流配合不同的发光时间能够实现更多的灰阶，并能够补偿阈值电压偏移，使得因低温多晶硅技术引起的M4的阈值电压偏移和M9的阈值电压偏移不会影响显示效果。
在图11中，Vn1为N1的电压，Vn4为N4的电压。在理论上，Vn4等于N3的电位与Vth4的差值。
在具体实施时，所述像素驱动电路用于驱动发光元件；
所述输出端与所述发光元件的第一极电连接；
所述发光元件的第二极与第三电压端电连接。
在本公开至少一实施例中，所述第三电压端可以为低电压端，但不以此为限。
在本公开至少一实施例中，显示面板可以包括多行多列上述像素驱动电路，则如图13所示，一帧画面显示时间可以包括依次设置的准备阶段和发光阶段te；
所述准备阶段可以包括依次设置的多个准备时间段，每一个准备时间段包括依次设置的复位时间段和补偿时间段；
在图13中，标号为F1的为一帧画面显示时间，标号为t1-1的为第一复位时间段，标号为t1-2的为第一补偿时间段，标号为t2-1的为第二复位时间段，标号为t2-2的为第二补偿时间段，标号为tn-1的为第n复位时间段，标号为tn-2的为第n补偿时间段，标号为E1的为发光控制线，标号为DTm的为第m列时间控制数据线，标号为R11的为第一行复位控制线，标号为G11的为第一行第一栅线，标号为R12的为第二行复位控制线，标号为G12的为第二行第一栅线，标号为G1n的为第n行第一栅线，标号为G21的为第一行第二栅线，标号为G22的为第二行第二栅线，标号为G2n的为第n行第二栅线，标号为R1n的为第n行复位控制线，标号为N4(1)的为第一行第m列像素驱动电路中的第四节点的电压，标号为N4(2)的为第二行第m列像素驱动电路中的第四节点的电压，标号为N4(n)的为第n行第m列像素驱动电路中的第四节点的电压，其中，n为大于2的整数。
在图13中，标号为Vn11的为第一行第m列像素驱动电路中的第一节点N1的电位，标号为Vn12的为第二行第m列像素驱动电路中的第一节点N1的电位。
如图13所示，在t1-1，DTm写入第一时间控制数据电压VdT1，在t1-2，DTm写入0V电压；在t1-2，DTm写入第二时间控制数据电压VdT2，在t2-2，DTm写入0V电压；在t1-n，DTm写入第n时间控制数据电压VdTn，在tn-2，DTm写入0V电压；在te，DTm上的数据电压由0V以固定斜率下降，以控制各行微发光二极管的发光时间。
本公开至少一实施例所述的像素驱动方法，应用于上述的像素驱动电路，所述像素驱动方法可以包括：
分别向复位控制线和第一栅线提供打开信号，使得第一初始电压Vi1写入发光时间控制子电路的第一端，使得发光时间控制子电路的控制端与发光时间控制子电路的第二端之间电连接，使得时间控制数据线提供的预定时间控制数据电压VdT写入第一储能子电路的第二端，并使得所述发光时间控制子电路的第一端与所述发光时间控制子电路的第二端之间电连接，相应改变所述第一储能子电路的第一端的电压，直至所述发光时间控制子电路关断；
向所述第一栅线提供打开信号，使得时间控制数据线提供的预定电压V0写入所述第一储能子电路的第二端，以相应改变所述第一储能子电路的第一端的电压；
向发光控制线提供打开信号，使得发光时间控制子电路的第一端与第一电压端之间电连接，并使得所述时间控制数据线与所述第一储能子电路的第二端之间电连接，以相应改变所述第一储能子电路的第一端的电压，以使得所述发光时间控制子电路的第一端与所述发光时间控制子电路的第二端之间电连接或断开。
本公开至少一实施例所述的像素驱动方法能够通过控制发光元件的发光时间来确定发光亮度，可以解决发光元件在不同电流下色坐标偏移以及低电流密度下亮度不稳定的问题，可以在固定的较高电流密度下通过调节发光元件的发光时间来调节发光亮度，并能够补偿采用低温多晶硅技术而引起的晶体管的阈值电压偏移对发光亮度调节的影响。
在本公开至少一实施例中，打开信号可以为能够控制相应的子电路导通的信号；例如，当该子电路包括的晶体管为n型晶体管时，所述打开信号可以为高电压信号；当该子电路包括的晶体管为p型晶体管时，所述打开信号可以为低电压信号；但不以此为限。
可选的，在向发光控制线提供打开信号的同时，所述时间控制数据线提供的数据电压可以等于V0-Kt，t为发光阶段持续的时间；
所述发光时间控制子电路包括的发光时间控制晶体管为p型晶体管，K为正数；或者，
所述发光时间控制子电路包括的发光时间控制晶体管为n型晶体管，K为负数。
可选的，所述像素驱动电路还可以包括电流驱动子电路；
所述像素驱动方法还可以包括：
在向发光控制线提供打开信号的同时，电流驱动子电路根据电流控制数据线提供的电流控制数据电压，产生输出至输出端的驱动电流。
在本公开至少一实施例所述的像素驱动方法中，电流驱动子电路控制驱动所述发光元件发光的驱动电流的大小，所述像素驱动电路包括的其他子电路控制所述发光元件的发光时间，可以通过同时调节驱动电流和发光时间来调节发光亮度。
当本公开至少一实施例所述的像素驱动方法用于驱动微发光二极管时，可以根据微发光二极管在低电流密度下效率低且主波峰偏移，高电流密度下效率高等特点，在高电流密度下采用电流驱动，低电流密度下采用高电流驱动配合发光时间调制的方式来实现各灰阶显示。
可选的，所述电流驱动子电路可以包括驱动子电路、电流控制数据写入子电路、第二复位子电路、补偿子电路和第二储能子电路；所述像素驱动方法还可以包括：
在分别向复位控制线和第一栅线提供打开信号的同时，使得第二初始电压写入所述驱动子电路的控制端，以断开所述驱动子电路的第一端与所述驱动子电路的第二端之间的连接；
在向所述第一栅线提供打开信号的同时，向第二栅线提供打开信号，使得电流控制数据线提供的预定电流控制数据电压VdI写入所述驱动子电路的第一端，并使得所述驱动子电路的控制端与所述驱动子电路的第二端之间电连接，以使得所述驱动子电路的第一端与所述驱动子电路的第二端之间电连接，以相应改变所述驱动子电路的控制端的电位，直至所述驱动子电路关断；
在向发光控制线提供打开信号的同时，驱动子电路产生驱动所述发光元件发光的驱动电流，以驱动发光元件发光。
本公开至少一实施例所述的显示装置包括上述的像素驱动电路。
本公开至少一实施例所提供的显示装置可以为手机、平板电脑、电视机、 显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (22)

  1. 一种像素驱动电路，所述像素驱动电路包括发光时间控制子电路、第一储能子电路，第一复位子电路、第一发光控制子电路、时间控制数据写入子电路和数据控制子电路；
    所述第一复位子电路分别与复位控制线、第一初始电压端、所述发光时间控制子电路的第一端、所述发光时间控制子电路的控制端与所述发光时间控制子电路的第二端电连接，用于在所述复位控制线提供的复位控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述发光时间控制子电路的第一端，并在所述复位控制信号的控制下控制所述发光时间控制子电路的控制端与所述发光时间控制子电路的第二端之间电连接；
    所述第一储能子电路的第一端与所述发光时间控制子电路的控制端电连接；所述第一储能子电路用于存储电压；
    所述时间控制数据写入子电路分别与第一栅线、时间控制数据线和所述第一储能子电路的第二端电连接，用于在所述第一栅线提供的第一栅极驱动信号的控制下，控制所述时间控制数据线与所述第一储能子电路的第二端之间电连接；
    所述数据控制子电路分别与发光控制线、所述时间控制数据线和所述第一储能子电路的第二端电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述时间控制数据线与所述第一储能子电路的第二端之间电连接；
    所述第一发光控制子电路分别与所述发光控制线、所述发光时间控制子电路的第一端和第一电压端电连接，用于在所述发光控制信号的控制下，控制所述发光时间控制子电路的第一端与所述第一电压端之间电连接；
    所述发光时间控制子电路的第二端与输出端电连接，所述发光时间控制子电路用于在其控制端的电位的控制下，控制所述发光时间控制子电路的第一端与所述发光时间控制子电路的第二端之间电连接。
  2. 如权利要求1所述的像素驱动电路，其中，还包括第二发光控制子电路；
    所述第二发光控制子电路分别与所述发光控制线、所述发光时间控制子电路的第二端和所述输出端电连接，用于在所述发光控制信号的控制下，控制所述发光时间控制子电路的第二端与所述输出端之间电连接。
  3. 如权利要求1所述的像素驱动电路，其中，所述发光时间控制子电路包括发光时间控制晶体管；
    所述发光时间控制晶体管的控制极为所述发光时间控制子电路的控制端，所述发光时间控制晶体管的第一极为所述发光时间控制子电路的第一端，所述发光时间控制晶体管的第二极为所述发光时间控制子电路的第二端。
  4. 如权利要求1所述的像素驱动电路，其中，所述第一复位子电路包括第一复位晶体管和第二复位晶体管；
    所述第一复位晶体管的控制极与所述复位控制线电连接，所述第一复位晶体管的第一极与所述发光时间控制子电路的控制端电连接，所述第一复位晶体管的第二极与所述发光时间控制子电路的第二端电连接；
    所述第二复位晶体管的控制极与所述复位控制线电连接，所述第二复位晶体管的第一极与所述发光时间控制子电路的第一端电连接，所述第二复位晶体管的第二极与第一初始电压端连接；所述第一初始电压端用于提供所述第一初始电压。
  5. 如权利要求1所述的像素驱动电路，其中，所述时间控制数据写入子电路包括时间控制数据写入晶体管；
    所述时间控制数据写入晶体管的控制极与所述第一栅线电连接，所述时间控制数据写入晶体管的第一极与所述时间控制数据线电连接，所述时间控制数据写入晶体管的第二极与所述第一储能子电路的第二端电连接。
  6. 如权利要求1所述的像素驱动电路，其中，所述数据控制子电路包括数据控制晶体管；所述第一储能子电路包括时间控制电容；
    所述数据控制晶体管的控制极与所述发光控制线电连接，所述数据控制晶体管的第一极与所述时间控制数据线电连接，所述数据控制晶体管的第二极与所述第一储能子电路的第二端电连接；
    所述第一储能子电路的第一端为所述时间控制电容的第一端，所述第一储能子电路的第二端为所述时间控制电容的第二端。
  7. 如权利要求1所述的像素驱动电路，其中，所述第一发光控制子电路包括第一发光控制晶体管；
    所述第一发光控制晶体管的控制极与所述发光控制线电连接，所述第一发光控制晶体管的第一极与所述第一电压端电连接，所述第一发光控制晶体管的第二极与所述发光时间控制子电路的第一端电连接。
  8. 如权利要求2所述的像素驱动电路，其中，所述第二发光控制子电路包括第二发光控制晶体管；
    所述第二发光控制晶体管的控制极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述发光时间控制子电路的第二端电连接，所述第二发光控制晶体管的第二极与所述输出端电连接。
  9. 如权利要求1所述的像素驱动电路，其中，所述发光时间控制子电路包括发光时间控制晶体管；所述第一复位子电路包括第一复位晶体管和第二复位晶体管；所述时间控制数据写入子电路包括时间控制数据写入晶体管；所述数据控制子电路包括数据控制晶体管；所述第一发光控制子电路包括第一发光控制晶体管；所述第一储能子电路包括时间控制电容；
    所述发光时间控制晶体管的控制极为所述发光时间控制子电路的控制端，所述发光时间控制晶体管的第一极为所述发光时间控制子电路的第一端，所述发光时间控制晶体管的第二极为所述发光时间控制子电路的第二端；
    所述第一复位晶体管的控制极与所述复位控制线电连接，所述第一复位晶体管的第一极与所述发光时间控制子电路的控制端电连接，所述第一复位晶体管的第二极与所述发光时间控制子电路的第二端电连接；
    所述第二复位晶体管的控制极与所述复位控制线电连接，所述第二复位晶体管的第一极与所述发光时间控制子电路的第一端电连接，所述第二复位晶体管的第二极与第一初始电压端连接；所述第一初始电压端用于提供所述第一初始电压；
    所述时间控制数据写入晶体管的控制极与所述第一栅线电连接，所述时间控制数据写入晶体管的第一极与所述时间控制数据线电连接，所述时间控制数据写入晶体管的第二极与所述第一储能子电路的第二端电连接；
    所述数据控制晶体管的控制极与所述发光控制线电连接，所述数据控制 晶体管的第一极与所述时间控制数据线电连接，所述数据控制晶体管的第二极与所述第一储能子电路的第二端电连接；
    所述第一发光控制晶体管的控制极与所述发光控制线电连接，所述第一发光控制晶体管的第一极与所述第一电压端电连接，所述第一发光控制晶体管的第二极与所述发光时间控制子电路的第一端电连接；
    所述第一储能子电路的第一端为所述时间控制电容的第一端，所述第一储能子电路的第二端为所述时间控制电容的第二端。
  10. 如权利要求9所述的像素驱动电路，其中，还包括第二发光控制子电路；
    所述第二发光控制子电路包括第二发光控制晶体管；
    所述第二发光控制晶体管的控制极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述发光时间控制子电路的第二端电连接，所述第二发光控制晶体管的第二极与所述输出端电连接。
  11. 如权利要求1所述的像素驱动电路，其中，还包括电流驱动子电路；
    所述电流驱动子电路连接于所述发光时间控制子电路的第二端和所述输出端之间，所述电流驱动子电路还分别与电流控制数据线和所述输出端电连接，所述电流驱动子电路用于在发光阶段，根据所述电流控制数据线提供的电流控制数据电压，产生输出至所述输出端的驱动电流。
  12. 如权利要求11所述的像素驱动电路，其中，所述电流驱动子电路包括驱动子电路、电流控制数据写入子电路、第二复位子电路、补偿子电路和第二储能子电路；
    所述驱动子电路的第一端与所述发光时间控制子电路的第二端电连接，所述驱动子电路的第二端与所述输出端电连接；所述驱动子电路用于在其控制端的电位的控制下，控制所述驱动子电路的第一端和所述驱动子电路的第二端之间电连接；
    所述第二储能子电路的第一端与所述驱动子电路的控制端电连接，所述第二储能子电路的第二端与第二电压端电连接，所述第二储能子电路用于存储电压；
    所述电流控制数据写入子电路分别与第二栅线、所述电流控制数据线和 所述驱动子电路的第一端电连接，用于在所述第二栅线提供的第二栅极驱动信号的控制下，控制所述电流控制数据线与所述驱动子电路的第一端之间电连接；
    所述第二复位子电路分别与所述复位控制线、第二初始电压端和所述驱动子电路的控制端电连接，用于在所述复位控制线输入的复位控制信号的控制下，将所述第二初始电压端提供的第二初始电压提供至所述驱动子电路的控制端；
    所述补偿子电路分别与所述第二栅线、所述驱动子电路的控制端和所述驱动子电路的第二端电连接，用于在所述第二栅极驱动信号的控制下，控制所述驱动子电路的控制端与所述驱动子电路的第二端之间电连接。
  13. 如权利要求12所述的像素驱动电路，其中，所述像素驱动电路还包括第二发光控制子电路；所述驱动子电路的第一端通过所述第二发光控制子电路与所述发光时间控制子电路的第二端电连接；
    所述第二发光控制子电路的控制端与所述发光控制线电连接，所述第二发光控制子电路的第一端与所述发光时间控制子电路的第二端电连接，所述第二发光控制子电路的第二端与所述驱动子电路电连接；所述第二发光控制子电路用于在所述发光控制线提供的发光控制信号的控制下，控制所述发光时间控制子电路的第二端与所述驱动子电路之间电连接。
  14. 如权利要求12所述的像素驱动电路，其中，还包括第三发光控制子电路；
    所述驱动子电路的第二端通过所述第三发光控制子电路与所述输出端电连接；
    所述第三发光控制子电路的控制端与所述发光控制线电连接，所述第三发光控制子电路用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动子电路的第二端与所述输出端之间电连接。
  15. 如权利要求12所述的像素驱动电路，其中，所述驱动子电路包括驱动晶体管；所述第二储能子电路包括电流控制电容；所述电流控制数据写入子电路包括电流控制数据写入晶体管；所述第二复位子电路包括第三复位晶体管；所述补偿子电路包括补偿晶体管；
    所述驱动晶体管的控制极与所述电流控制电容的第一端电连接，所述驱动晶体管的第一极与所述发光时间控制子电路的第二端电连接，所述驱动晶体管的第二极与所述输出端电连接；
    所述电流控制数据写入晶体管的控制极与所述第二栅线电连接，所述电流控制数据写入晶体管的第一极与所述电流控制数据线电连接，所述电流控制数据写入晶体管的第二极与所述驱动子电路的第一端电连接；
    所述第三复位晶体管的控制极与所述复位控制线电连接，所述第三复位晶体管的第一极与第二初始电压端电连接，所述第三复位晶体管的第二极与所述驱动子电路的控制端电连接；
    所述补偿晶体管的控制极与第二栅线电连接，所述补偿晶体管的第一极与所述驱动子电路的控制端电连接，所述补偿晶体管的第二极与所述驱动子电路的第二端电连接。
  16. 如权利要求14所述的像素驱动电路，其中，所述第三发光控制子电路包括第三发光控制晶体管；
    所述第三发光控制晶体管的控制极与发光控制线电连接，所述第三发光控制晶体管的第一极与所述驱动子电路的第二端电连接，所述第三发光控制晶体管的第二极与所述输出端电连接。
  17. 如权利要求1至16中任一权利要求所述的像素驱动电路，其中，所述像素驱动电路用于驱动发光元件；
    所述输出端与所述发光元件的第一极电连接；
    所述发光元件的第二极与第三电压端电连接。
  18. 如权利要求17所述的像素驱动电路，其中，所述发光元件为微发光二极管。
  19. 一种像素驱动方法，应用于如权利要求1至18中任一权利要求所述的像素驱动电路，所述像素驱动方法包括：
    分别向复位控制线和第一栅线提供打开信号，使得第一初始电压Vi1写入发光时间控制子电路的第一端，使得发光时间控制子电路的控制端与发光时间控制子电路的第二端之间电连接，使得时间控制数据线提供的预定时间控制数据电压VdT写入第一储能子电路的第二端，并使得所述发光时间控制 子电路的第一端与所述发光时间控制子电路的第二端之间电连接，相应改变所述第一储能子电路的第一端的电压，直至所述发光时间控制子电路关断；
    向所述第一栅线提供打开信号，使得时间控制数据线提供的预定电压V0写入所述第一储能子电路的第二端，以相应改变所述第一储能子电路的第一端的电压；
    向发光控制线提供打开信号，使得发光时间控制子电路的第一端与第一电压端之间电连接，并使得所述时间控制数据线与所述第一储能子电路的第二端之间电连接，以相应改变所述第一储能子电路的第一端的电压，以使得所述发光时间控制子电路的第一端与所述发光时间控制子电路的第二端之间电连接或断开。
  20. 如权利要求19所述的像素驱动方法，其中，所述像素驱动电路还包括电流驱动子电路；
    所述像素驱动方法包括：
    在向发光控制线提供打开信号的同时，电流驱动子电路根据电流控制数据线提供的电流控制数据电压，产生输出至输出端的驱动电流。
  21. 如权利要求20所述的像素驱动方法，其中，所述电流驱动子电路包括驱动子电路、电流控制数据写入子电路、第二复位子电路、补偿子电路和第二储能子电路；所述输出端与发光元件电连接；所述像素驱动方法还包括：
    在分别向复位控制线和第一栅线提供打开信号的同时，使得第二初始电压写入所述驱动子电路的控制端，以断开所述驱动子电路的第一端与所述驱动子电路的第二端之间的连接；
    在向所述第一栅线提供打开信号的同时，向第二栅线提供打开信号，使得电流控制数据线提供的预定电流控制数据电压VdI写入所述驱动子电路的第一端，并使得所述驱动子电路的控制端与所述驱动子电路的第二端之间电连接，以使得所述驱动子电路的第一端与所述驱动子电路的第二端之间电连接，以相应改变所述驱动子电路的控制端的电位，直至所述驱动子电路关断；
    在向发光控制线提供打开信号的同时，驱动子电路产生驱动所述发光元件发光的驱动电流，以驱动发光元件发光。
  22. 一种显示装置，包括如权利要求1至18中任一权利要求所述的像素 驱动电路。
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