WO2019227698A1 - 薄膜晶体管阵列基板、显示面板以及显示装置 - Google Patents

薄膜晶体管阵列基板、显示面板以及显示装置 Download PDF

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Publication number
WO2019227698A1
WO2019227698A1 PCT/CN2018/101643 CN2018101643W WO2019227698A1 WO 2019227698 A1 WO2019227698 A1 WO 2019227698A1 CN 2018101643 W CN2018101643 W CN 2018101643W WO 2019227698 A1 WO2019227698 A1 WO 2019227698A1
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WIPO (PCT)
Prior art keywords
electrostatic discharge
substrate
layer
display area
thin film
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Ceased
Application number
PCT/CN2018/101643
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English (en)
French (fr)
Inventor
聂晓辉
张嘉伟
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US16/162,363 priority Critical patent/US11056513B2/en
Publication of WO2019227698A1 publication Critical patent/WO2019227698A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application relates to the field of display technology, and in particular, to a thin film transistor array substrate, a display panel, and a display device.
  • low temperature poly-Si thin film Transistor has outstanding advantages such as high carrier mobility and small device size. It is a key technology for the development of low power consumption and highly integrated display panels.
  • the fabrication of LTPS-TFT array substrates needs to undergo multiple processes such as film formation, photolithography, and cleaning, and involves a variety of process machines. During the production process, the frictional contact between the array substrate and the process machine can easily cause static electricity accumulation and cause electrostatic discharge of the LTPS-TFT film layer. Discharge, ESD) damage, resulting in device failure.
  • a common solution is to make a metal protective circuit (Guard) around the display area of the screen. ring). Both ends of the line use heavily doped Poly-Si as an electrostatic discharge device to guide the discharge of static electricity outside the display area, thereby protecting the semiconductor devices in the display area.
  • the thickness of the film layer of the electrostatic discharge device is large and the thermal expansion coefficient is different from that of other layers, which will cause a stress accumulation between the film layer of the electrostatic discharge device and other layers; meanwhile, the structure of the film layer of the electrostatic discharge device is different from other regions. Larger, so there are steps, when the array substrate and color film (Color When the filter (CF) substrate assembly is cut, the presence of the step leads to a greater stress on the heavily doped Poly-Si electrostatic discharge device, which causes the film to rupture.
  • This application proposes a thin film transistor array substrate, a display panel, and a display device to solve the problem that the LTPS array substrate in the prior art is likely to cause film cracks when it is cut.
  • a technical solution adopted in the present application is to propose a thin film transistor array substrate, including:
  • a substrate including a display area and a non-display area surrounding the display area;
  • the electrostatic discharge circuit layer is disposed in a non-display area on one side of the substrate, and the electrostatic discharge circuit layer includes a conductive line disposed around the display area and an electrostatic discharge device electrically connected to the conductive line;
  • the electrostatic discharge device includes a plurality of electrostatic discharge units arranged at intervals. One end of the electrostatic discharge unit is connected along the edge of the substrate, and the other end is connected to the conductive line.
  • a display panel including a thin film transistor array substrate and a color filter substrate which are arranged in a stack, wherein the thin film transistor array substrate includes:
  • a substrate including a display area and a non-display area surrounding the display area;
  • An electrostatic discharge circuit layer is disposed in the non-display area on one side of the substrate, and the electrostatic discharge circuit layer includes a conductive line disposed around the display area and an electrostatic discharge device electrically connected to the conductive line;
  • the electrostatic discharge device includes a plurality of electrostatic discharge units arranged at intervals. One end of the electrostatic discharge unit is connected along the edge of the substrate, and the other end is connected to the conductive line.
  • the display device includes a display panel, and the display panel includes a thin film transistor array substrate and a color filter substrate disposed in a stack.
  • the thin film transistor array substrate includes :
  • a substrate including a display area and a non-display area surrounding the display area;
  • An electrostatic discharge circuit layer is disposed in the non-display area on one side of the substrate, and the electrostatic discharge circuit layer includes a conductive line disposed around the display area and an electrostatic discharge device electrically connected to the conductive line;
  • the electrostatic discharge device includes a plurality of spaced electrostatic discharge units. One end of the electrostatic discharge unit is connected along the edge of the substrate, and the other end is connected to the conductive line.
  • the beneficial effect of the present application is that by dividing the electrostatic discharge device into a plurality of spaced electrostatic discharge units, the internal stress of the electrostatic discharge device can be reduced, and at the same time, the interval between the electrostatic discharge units can provide sufficient elastic deformation space during cutting. Therefore, the problem of cracking the display panel film layer during cutting can be prevented, thereby improving the cutting yield of the display panel.
  • FIG. 1 is a schematic structural diagram of an embodiment of a thin film transistor array substrate according to the present application.
  • FIG. 2 is a schematic structural diagram of a partially enlarged view of the thin film transistor array substrate shown in FIG. 1 in an I region;
  • FIG. 3 is a schematic structural view of a cross section of the thin film transistor array substrate shown in FIG. 2 at A-A 'section;
  • FIG. 4 is a schematic structural diagram of another embodiment of a partially enlarged view of the thin film transistor array substrate shown in FIG. 1 in the I region;
  • FIG. 4 is a schematic structural diagram of another embodiment of a partially enlarged view of the thin film transistor array substrate shown in FIG. 1 in the I region;
  • Figure 5 is a partial enlarged view of the thin film transistor array substrate shown in FIG. 1 in the region I is a schematic structural view of another embodiment
  • Figure 6 is a partial enlarged view of the thin film transistor array substrate shown in FIG. 1 in the region I is a schematic structural view of another embodiment
  • Figure 7 is a schematic structural diagram of an embodiment of a display panel provided by the present application.
  • FIG. 8 is a schematic structural diagram of an embodiment of a display device provided by the present application.
  • a plurality is at least two, for example, two, three, etc., unless it is specifically and specifically defined otherwise. All directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship between components in a specific posture (as shown in the drawing) , Movement, etc., if the specific posture changes, the directional indication will change accordingly. Furthermore, the terms “including” and “having”, as well as any of them, are intended to cover non-exclusive inclusion.
  • a process, method, system, product, or device containing a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes Other steps or units inherent to these processes, methods, products or equipment.
  • an embodiment herein means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they independent or alternative embodiments that are mutually exclusive with other embodiments. It is clearly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
  • FIG. 1 is a schematic structural diagram of an embodiment of a thin film transistor array substrate according to the present application
  • FIG. 2 is a schematic structural diagram of a partially enlarged view of an area I of the thin film transistor array substrate shown in FIG. 1
  • FIG. 3 is a schematic structural view of a cross section of the thin film transistor array substrate shown in FIG. 2 along the AA ′ cross section.
  • the thin film transistor array substrate 100 includes a substrate 110 and an electrostatic discharge circuit layer 120 disposed on one side of the substrate 110.
  • the substrate 110 includes a display area 111 and a non-display area 112.
  • the display area 111 is located in a middle area of the substrate 110 and the non-display area 112.
  • the electrostatic discharge circuit layer 120 is disposed in an edge region of the substrate 110 to surround the display region 111.
  • the electrostatic discharge circuit layer 120 includes a conductive circuit 121 and an electrostatic discharge device 122.
  • the conductive circuit 121 will display the region 111. Surrounded, two ends of the conductive line 121 are respectively connected to an electrostatic discharge device 122.
  • the electrostatic discharge device 122 includes a plurality of electrostatic discharge units 1221 disposed at intervals. One end of each electrostatic discharge unit 1221 is connected to the edge of the substrate 110 and the other end thereof.
  • dividing the electrostatic discharge device 122 into a plurality of spaced electrostatic discharge units 1221 can reduce the internal stress of the electrostatic discharge devices, and at the same time, the interval between the electrostatic discharge units 1221 can provide sufficient Elastically deformable space to prevent display during cutting
  • the problem of panel film cracking further improves the cutting yield of the display panel.
  • the plurality of electrostatic discharge units 1221 may be arranged in a comb-tooth shape, so that the structure of the electrostatic discharge device 122 is compact, thereby reducing the installation space of the electrostatic discharge device 122. Therefore, the compactness of the structure of the thin film transistor array substrate 100 is further improved.
  • the plurality of electrostatic discharge units 1221 may not be arranged in a comb-tooth shape.
  • FIG. 4 is a schematic structural diagram of another embodiment of a partial enlarged view of the thin film transistor array substrate shown in FIG. 1 in the I region.
  • at least one electrostatic discharge unit 1221 may be arranged to gradually decrease in width from the edge of the substrate 100 to the inside of the substrate 100.
  • FIG. 5 is a schematic structural diagram of another embodiment of a partial enlarged view of the thin film transistor array substrate shown in FIG. 1 in the I region.
  • at least one electrostatic discharge unit 1221 may be set to gradually increase in width.
  • FIG. 6 is a schematic structural diagram of another embodiment of a partial enlarged view of the thin film transistor array substrate shown in FIG. 1 in the I region.
  • the electrostatic discharge unit 1221 may extend in a curved shape.
  • the electrostatic discharge unit 1221 may extend in an arc-shaped line or may extend in an S-line shape, and the shape of the curve is not limited herein. By setting the electrostatic discharge unit 1221 in a curved shape, it is possible to bypass other components during the electrostatic discharge unit 1221 and prevent line interference.
  • one end of the electrostatic discharge unit 1221 is connected to the edge of the substrate 110, and the other end extends into the substrate 110 to be electrically connected to the conductive line 121.
  • the substrate 110 is a glass substrate, and a buffer layer 130 is further provided between the substrate 110 and the electrostatic discharge circuit layer 120.
  • the layer buffer layer 130 is disposed on a surface of the substrate 110 side, and the electrostatic discharge circuit layer 120 is disposed on The layer buffer layer 130 faces away from the surface on the substrate 110 side.
  • the material composition of the buffer layer 130 is any one or more of silicon nitride (SiNx) or silicon oxide (SiOx), and its role is to prevent the metal ions in the substrate 110 from penetrating into the electrostatic discharge circuit layer 120.
  • Direction of diffusion It is ensured that the thin film transistor array substrate 100 can work normally.
  • the electrostatic discharge device 122 is heavily doped polysilicon.
  • the electrostatic discharge circuit layer 120 composed of the electrostatic discharge device 122 and the conductive line 121 can discharge the static electricity generated in the thin film transistor array substrate 100, thereby improving the thin film transistor array.
  • the substrate 100 has an antistatic capability.
  • a side of the electrostatic discharge circuit layer 120 facing away from the buffer layer 130 further includes a gate insulating layer 140, an interlayer insulating layer 150, a spacer layer 160, and a passivation protection layer 170 that are stacked in this order.
  • the gate insulating layer 140 is used to form an accommodating space with the buffer layer 130 to surround the electrostatic discharge circuit layer 120.
  • the gate insulating layer 140 can isolate and protect the electrostatic discharge circuit layer 120.
  • the interlayer insulating layer 150 is provided on the surface of the gate insulating layer 140 facing away from the electrostatic discharge circuit layer 120, the spacer layer 160 is provided on the surface of the interlayer insulating layer 150 facing away from the gate insulating layer 140, and the passivation protective layer 170 It is provided on the surface of the spacer layer 160 facing away from the interlayer insulating layer 150.
  • each of the electrostatic discharge units 1221 includes a gate insulation layer 140, an interlayer insulation layer 150, a spacer layer 160, and a passivation protection layer 170, which are sequentially stacked, and each of the electrostatic discharge units 1221.
  • the widths of the gate insulating layer 140, the interlayer insulating layer 150, the spacer layer 160, and the passivation protective layer 170 are equal to the width of the electrostatic discharge unit 1221, that is, the gate insulating layer 140, the interlayers on the multiple electrostatic discharge units 1221.
  • the insulating layer 150, the spacer layer 160, and the passivation protective layer 170 are also arranged in a comb-tooth shape.
  • the gate insulating layer 140 is composed of silicon oxide (SiOx), and the interlayer insulating layer 150 is composed of silicon oxide and / or silicon nitride (SiNx / SiOx).
  • the spacer layer 160 is composed of silicon nitride (SiNx), and the passivation protection layer 170 is composed of silicon nitride (SiNx).
  • the spacer layer 160 and the passivation protection layer 170 can be made of the same material, it can also be understood that, in the non-display region 112, the spacer layer 160 and the passivation protection layer 170 are the same film layer formed of the same material.
  • the interlayer insulation layer 150 separates the conductive circuit 121 into a first circuit layer and a second circuit layer, wherein the first circuit layer is composed of metal molybdenum and the second circuit is a metal titanium aluminum alloy.
  • the interlayer insulating layer 150 is sequentially stacked with the first circuit layer and the second circuit layer.
  • the first circuit layer is disposed on the side of the insulating layer 150 near the substrate 110, and the second circuit layer is disposed on the side of the insulating layer 150 facing away from the substrate 110.
  • the main function of the passivation protection layer 170 is to isolate and protect the thin film transistors in the display area 111.
  • the buffer layer 130, the electrostatic discharge circuit layer 120, the gate insulation layer 140, the interlayer insulation layer 150, the spacer layer 160, and the passivation protection layer can be sequentially formed on the substrate 110 by photolithography.
  • FIG. 7 is a schematic structural diagram of an embodiment of a display panel provided in the present application.
  • the display panel 200 includes a color film substrate 220 and a thin film transistor.
  • the array substrate 210, wherein the thin film transistor array substrate 210 may include the thin film transistor array substrate described in any one of the foregoing, and details are not described herein.
  • FIG. 8 is a schematic structural diagram of an embodiment of a display device provided by the present application.
  • the display device 300 includes a thin film transistor array substrate. 310.
  • the thin film transistor array substrate 310 may include the thin film transistor array substrate described in any one of the foregoing, and details are not described herein.
  • the display device 300 may be a device with a display screen such as a mobile phone, a tablet, a computer, and a television.
  • the present application proposes an electric thin film transistor array substrate, a display panel, and a display device.
  • the electrostatic discharge device of the thin film transistor array substrate By setting the electrostatic discharge device of the thin film transistor array substrate to a comb-tooth type, the internal stress of the electrostatic discharge device can be reduced and prevented. The problem of cracking the display panel film layer occurs during cutting, thereby improving the cutting yield of the display panel.

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Abstract

本申请公开了一种薄膜晶体管阵列基板、显示面板以及显示装置。阵列基板包括基板以及静电释放线路层，静电释放线路层设置在基板一侧的非显示区内，静电释放线路层包括围绕显示区设置的导电线路及与导电线路电连接的静电释放器件；其中，静电释放器件包括多个间隔设置的静电释放单元，静电释放单元一端连接基板边缘，另一端连接导电线路。通过将静电释放器件的截面设置为梳齿状可以解决现有的显示面板在切割的过程中容易出现膜层损坏的问题，从而提高显示面板的切割良率。

Description

薄膜晶体管阵列基板、显示面板以及显示装置
【技术领域】
本申请涉及显示技术领域，特别是涉及一种薄膜晶体管阵列基板、显示面板以及显示装置。
【背景技术】
低温多晶硅薄膜晶体管（Low Temperature Poly-Si Thin Film Transistor，LTPS-TFT）具有载流子迁移率高，器件尺寸小等突出优点，是发展低功耗、高集成度显示面板的关键技术。LTPS-TFT阵列基板的制作需经历成膜、光刻、清洗等多道工艺，涉及多种制程机台。在生产过程中，阵列基板与制程机台的摩擦接触极易导致静电积累，引起LTPS-TFT膜层静电放电（Electrostatic Discharge, ESD）损伤，导致器件失效。为防止LTPS-TFT阵列基板制造过程中器件ESD损伤，常用的方案是在屏幕的显示区域外围制作金属防护线路（Guard ring）,线路的两端使用重掺杂的Poly-Si作为静电释放器件，引导静电在显示区域外释放，从而实现对显示区域半导体器件的保护。
然而现有技术中静电释放器件膜层的厚度较大且与其他层的热膨胀系数不同因此会导致静电释放器件膜层与其他层之间形成应力积累；同时静电释放器件膜层结构与其他区域差别较大，从而存在台阶，当阵列基板和彩膜(Color Filter, CF)基板组立完成切割时，台阶的存在导致重掺杂Poly-Si静电释放器件所受应力较大，造成膜层破裂。
【发明内容】
本申请提出一种薄膜晶体管阵列基板、显示面板以及显示装置，以解决现有技术中的LTPS阵列基板切割时容易造成膜层破裂的问题。
为解决上述技术问题，本申请采用的一个技术方案是：提出一种薄膜晶体管阵列基板，包括：
基板，包括显示区及包围显示区的非显示区；
静电释放线路层，设置在基板一侧的非显示区内，静电释放线路层包括围绕显示区设置的导电线路及与导电线路电连接的静电释放器件；
其中，静电释放器件包括多个间隔设置的静电释放单元，静电释放单元一端连接沿述基板边缘，另一端与导电线路连接。
为解决上述技术问题，本申请采用的另一个技术方案是：提出一种一种显示面板，包括层叠设置的薄膜晶体管阵列基板和彩膜基板，其中，薄膜晶体管阵列基板包括：
基板，包括显示区及包围所述显示区的非显示区；
静电释放线路层，设置在所述基板一侧的所述非显示区内，所述静电释放线路层包括围绕所述显示区设置的导电线路及与所述导电线路电连接的静电释放器件；
其中，静电释放器件包括多个间隔设置的静电释放单元，静电释放单元一端连接沿述基板边缘，另一端与导电线路连接。
为解决上述技术问题，本申请采用的又一个技术方案是：提出一种显示装置，显示装置包括显示面板，显示面板包括层叠设置的薄膜晶体管阵列基板和彩膜基板，其中，薄膜晶体管阵列基板包括：
基板，包括显示区及包围所述显示区的非显示区；
静电释放线路层，设置在所述基板一侧的所述非显示区内，所述静电释放线路层包括围绕所述显示区设置的导电线路及与所述导电线路电连接的静电释放器件；
其中，所述静电释放器件包括多个间隔设置的静电释放单元，所述静电释放单元一端连接沿述基板边缘，另一端与所述导电线路连接。
本申请的有益效果是：通过将静电释放器件分割为多个间隔设置的静电释放单元可以减小静电释放器件的内应力，同时在切割时静电释放单元之间的间隔可以提供充足的弹性形变空间，从而可以防止在切割时出现显示面板膜层破裂的问题，进而提高了显示面板的切割良率。
【附图说明】
图1是本申请一种薄膜晶体管阵列基板一实施例的结构示意图；
图2是图1所示薄膜晶体管阵列基板在I区域的局部放大图的结构示意图；
图3是图2所示薄膜晶体管阵列基板在A-A’截面的剖面的结构示意图；
图4是图1所示薄膜晶体管阵列基板在I区域的局部放大图另一实施例的结构示意图；
图5是图1所示薄膜晶体管阵列基板在I区域的局部放大图另一实施例的结构示意图;
图6是图1所示薄膜晶体管阵列基板在I区域的局部放大图另一实施例的结构示意图;
图7是本申请提供的一种显示面板一实施例的结构示意图;
图8是本申请提供的一种显示装置一实施例的结构示意图。
【具体实施方式】
为使本申请解决的技术问题、采用的技术方案和达到的技术效果更加清楚，下面将结合附图对本申请实施例的技术方案作进一步的详细描述。
本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。本申请实施例中所有方向性指示（诸如上、下、左、右、前、后……）仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
请参阅图1至图3，其中图1是本申请一种薄膜晶体管阵列基板一实施例的结构示意图，图2是图1所示薄膜晶体管阵列基板I区域的局部放大图的结构示意图，图3是图2所示薄膜晶体管阵列基板在A-A’截面的剖面的结构示意图。其中薄膜晶体管阵列基板100包括基板110以及设置在基板110一侧的静电释放线路层120；其中基板110包括显示区域111和非显示区域112，显示区域111位于基板110的中间区域，非显示区域112设置在基板110的边缘区域以将显示区域111包围，静电释放线路层120设置在非显示区域112内，静电释放线路层120包括导电线路121和静电释放器件122，其中导电线路121将显示区域111包围，导电线路121的两端分别连接一个静电释放器件122，其中静电释放器件122包括多个间隔设置的静电释放单元1221，每一个静电释放单元1221的一端均连接基板110的边缘，其另一端向基板110的内侧延伸，因此将静电释放器件122分割为多个间隔设置的静电释放单元1221可以减小静电释放器件的内应力，同时在切割时静电释放单元1221之间的间隔可以提供充足的弹性形变空间，从而可以防止在切割时出现显示面板膜层破裂的问题，进而提高了显示面板的切割良率。
请进一步参阅图2及图3，在本实施例中，多个静电释放单元1221可以呈梳齿状排布，以使得静电释放器件122的结构紧凑，从而可以减小静电释放器件122的设置空间，进而提高薄膜晶体管阵列基板100结构的紧凑性。
在其他的实施例中，多个静电释放单元1221也可以不呈梳齿状排布。
请参阅图4，图4是图1所示薄膜晶体管阵列基板在I区域的局部放大图另一实施例的结构示意图。其中，在由基板100的边缘到基板100内侧的反向上，至少一个静电释放单元1221可以设置为宽度逐渐减小。
请参阅图5，图5是图1所示薄膜晶体管阵列基板在I区域的局部放大图另一实施例的结构示意图。其中，在由基板100的边缘到基板100内侧的方向上，至少一个静电释放单元1221可以设置为宽度逐渐增大。
请参阅图6，图6是图1所示薄膜晶体管阵列基板在I区域的局部放大图另一实施例的结构示意图。其中，静电释放单元1221可以呈曲线状延伸。其中，静电释放单元1221可以呈弧形线状延伸或者也可以呈S线状延伸，对于曲线状的形状在此不做限定。通过将静电释放单元1221设置为曲线形，从而可以使得在静电释放单元1221时能够绕开其他的元件，防止出现线路干扰。
本实施例中，静电释放单元1221一端连接基板110的边缘，另一端向基板110内延伸而与导电线路121电连接。
本实施例中，基板110为玻璃基板，在基板110与静电释放线路层120之间还具有一层缓冲层130，层缓冲层130设置在基板110一侧的表面，静电释放线路层120设置在层缓冲层130背对基板110一侧的表面。其中，缓冲层130的材料组成为硅的氮化物（SiNx）或者硅的氧化物（SiOx）中的任意一种或者多种，其作用是防止基板110中的金属离子向深入静电释放线路层120的方向扩散。确保薄膜晶体管阵列基板100能够正常工作。
在本实施例中，静电释放器件122为重掺杂多晶硅，静电释放器件122与导电线路121组成的静电释放线路层120可以将薄膜晶体管阵列基板100中产生的静电导出，从而可以提高薄膜晶体管阵列基板100抗静电能力。
本实施例中，静电释放线路层120背对缓冲层130的一侧还具有依次层叠设置的栅绝缘层140、层间绝缘层150、间隔层160以及钝化保护层170。其中栅绝缘层140用于与缓冲层130形成容置空间以将静电释放线路层120包围起来。栅绝缘层140可以对静电释放线路层120起到隔离以及保护作用。层间绝缘层150设置在栅绝缘层140背对静电释放线路层120的一侧的表面，间隔层160设置在层间绝缘层150背对栅绝缘层140一侧的表面，钝化保护层170设置在间隔层160背对层间绝缘层150的一侧的表面。
其中在A-A’截面上，每个静电释放单元1221上均包括依次层叠设置的栅绝缘层140、层间绝缘层150、间隔层160以及钝化保护层170，且在各个静电释放单元1221上的栅绝缘层140、层间绝缘层150、间隔层160以及钝化保护层170的宽度都与静电释放单元1221的宽度相等，即多个静电释放单元1221上的栅绝缘层140、层间绝缘层150、间隔层160以及钝化保护层170也呈梳齿型排布。
其中，栅绝缘层140由硅的氧化物（SiOx）组成，层间绝缘层150由硅的氧化物和/或硅的氮化物（SiNx/SiOx）组成。间隔层160由硅的氮化物（SiNx）组成，钝化保护层170由硅的氮化物（SiNx）组成。
由于间隔层160与钝化保护层170可以采用相同的材料制成，因此也可以理解为，在非显示区112内，间隔层160与钝化保护层170为由相同材料形成的同一膜层。
其中，层间绝缘层150将导电线路121分隔为第一线路层和第二线路层，其中第一线路层由金属钼组成，第二线路为金属钛铝合金。其中层间绝缘层150与第一线路层和第二线路层依次层叠设置，第一线路层设置在绝缘层150靠近基板110的一侧，第二线路层设置在绝缘层150背对基板110的一侧。钝化保护层170主要作用是对显示区域111内的薄膜晶体管起到隔离和保护作用。
本实施例中，缓冲层130、静电释放线路层120栅绝缘层140、层间绝缘层150、间隔层160以及钝化保护层，可以通过光刻技术依次在基板110上依次成型。
区别于现有技术本申请还提供了一种显示面板，请参阅图7，图7是本申请提供的一种显示面板一实施例的结构示意图，其中显示面板200包括彩膜基板220和薄膜晶体管阵列基板210，其中薄膜晶体管阵列基板210可以包括前文任一项所述的薄膜晶体管阵列基板，在此不做赘述。
进一步地，区别于现有技术本申请还提供了一种显示装置，请参阅图8，图8是本申请提供的一种显示装置一实施例的结构示意图，其中显示装置300包括薄膜晶体管阵列基板310，薄膜晶体管阵列基板310可以包括前文任一项所述的薄膜晶体管阵列基板，在此不做赘述，其中显示装置300可以是手机、平板、电脑以及电视等具有显示屏的装置。
综上所述，本申请提出一种电薄膜晶体管阵列基板、显示面板以及显示装置，通过将薄膜晶体管阵列基板的静电释放器件设置为梳齿型，从而可以减小静电释放器件的内应力，防止在切割时出现显示面板膜层破裂的问题，进而提高了显示面板的切割良率。
以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (14)

  1. 一种薄膜晶体管阵列基板，其中，包括：
    基板，包括显示区及包围所述显示区的非显示区；
    静电释放线路层，设置在所述基板一侧的所述非显示区内，所述静电释放线路层包括围绕所述显示区设置的导电线路及与所述导电线路电连接的静电释放器件；
    其中，所述静电释放器件包括多个间隔设置的静电释放单元，所述静电释放单元一端连接沿述基板边缘，另一端与所述导电线路连接。
  2. 根据权利要求1所述的薄膜晶体管阵列基板，其中，多个所述静电释放单元的截面呈梳齿型。
  3. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述基板与所述静电释放线路层之间还具有缓冲层。
  4. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述静电释放单元的材质包括多晶硅。
  5. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述静电释放单元背对所述基板的一侧还包括依次层叠设置的栅绝缘层、层间绝缘层、间隔层以及钝化保护层。
  6. 一种显示面板，其中，包括层叠设置的薄膜晶体管阵列基板和彩膜基板，其中，所述薄膜晶体管阵列基板包括：
    基板，包括显示区及包围所述显示区的非显示区；
    静电释放线路层，设置在所述基板一侧的所述非显示区内，所述静电释放线路层包括围绕所述显示区设置的导电线路及与所述导电线路电连接的静电释放器件；
    其中，所述静电释放器件包括多个间隔设置的静电释放单元，所述静电释放单元一端连接沿述基板边缘，另一端与所述导电线路连接。
  7. 根据权利要求6所述的显示面板，其中，多个所述静电释放单元的截面呈梳齿型。
  8. 根据权利要求6所述的显示面板，其中，所述基板与所述静电释放线路层之间还具有缓冲层。
  9. 根据权利要求5所述的显示面板，其中，所述静电释放单元的材质包括多晶硅；
    所述静电释放单元背对所述基板的一侧还包括依次层叠设置的栅绝缘层、层间绝缘层、间隔层以及钝化保护层。
  10. 一种显示装置，其中，所述显示装置包括显示面板，所述显示面板包括层叠设置的薄膜晶体管阵列基板和彩膜基板，其中，所述薄膜晶体管阵列基板包括：
    基板，包括显示区及包围所述显示区的非显示区；
    静电释放线路层，设置在所述基板一侧的所述非显示区内，所述静电释放线路层包括围绕所述显示区设置的导电线路及与所述导电线路电连接的静电释放器件；
    其中，所述静电释放器件包括多个间隔设置的静电释放单元，所述静电释放单元一端连接沿述基板边缘，另一端与所述导电线路连接。
  11. 根据权利要求10所述的显示装置，其中，多个所述静电释放单元的截面呈梳齿型。
  12. 根据权利要求10所述的显示装置，其中，所述基板与所述静电释放线路层之间还具有缓冲层。
  13. 根据权利要求10所述的显示装置，其中，所述静电释放单元的材质包括多晶硅。
  14. 根据权利要求10所述的显示装置，其中，所述静电释放单元背对所述基板的一侧还包括依次层叠设置的栅绝缘层、层间绝缘层、间隔层以及钝化保护层。
PCT/CN2018/101643 2018-05-30 2018-08-22 薄膜晶体管阵列基板、显示面板以及显示装置 Ceased WO2019227698A1 (zh)

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