WO2016127372A1 - 顶栅薄膜晶体管、阵列基板及其制造方法以及tft器件 - Google Patents

顶栅薄膜晶体管、阵列基板及其制造方法以及tft器件 Download PDF

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Publication number
WO2016127372A1
WO2016127372A1 PCT/CN2015/072949 CN2015072949W WO2016127372A1 WO 2016127372 A1 WO2016127372 A1 WO 2016127372A1 CN 2015072949 W CN2015072949 W CN 2015072949W WO 2016127372 A1 WO2016127372 A1 WO 2016127372A1
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WIPO (PCT)
Prior art keywords
layer
signal line
conductive layer
array substrate
film transistor
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PCT/CN2015/072949
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English (en)
French (fr)
Inventor
袁泽
余晓军
魏鹏
罗浩俊
赵继刚
刘自鸿
Original Assignee
深圳市柔宇科技有限公司
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Priority to CN201580000112.XA priority Critical patent/CN106030821B/zh
Priority to PCT/CN2015/072949 priority patent/WO2016127372A1/zh
Publication of WO2016127372A1 publication Critical patent/WO2016127372A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a top gate thin film transistor, an array substrate including the top gate thin film transistor, a method of manufacturing the array substrate, and a TFT device including the array substrate.
  • Thin film transistor Transistor has been widely used in the field of flat panel display technologies such as liquid crystal and organic light (OLED).
  • the active layer mostly uses semiconductor materials such as amorphous silicon (a-Si) and poly-silicon (poly-Si), and generally uses amorphous silicon TFT, which can cover flat panel display products of almost all sizes, and polysilicon.
  • a-Si amorphous silicon
  • poly-Si poly-silicon
  • TFT can only be used for small and medium size products.
  • higher and higher requirements are put forward for the performance of TFTs.
  • the characteristics of amorphous silicon TFTs and polysilicon TFTs cannot meet the requirements of complex structure, large leakage current and uniform mass production.
  • Metal oxide TFTs have emerged as a replacement for the above two semiconductor materials.
  • Metal oxide is used as the active layer material of the TFT, and the structure of the TFT can be divided into two types: a bottom gate type and a top gate type.
  • the bottom gate type can also be called an inverted staggered electrode structure, and the top gate type is also called interlaced.
  • Type electrode structure The bottom gate type TFT structure is further divided into an etch protection type and a back channel etch type, and the etch protection type requires a passivation layer to block damage to the semiconductor caused by source/drain metal etching, and the method increases the process. The complexity increases the cost.
  • OLEDs have two illumination modes: top-emitting and bottom-emitting modes.
  • the pixel electrode of the backplane needs to be a metal layer with high reflectivity, and the latter requires a transparent conductive material, a common transparent conductive material. Conductivity is usually much higher than metal and is not suitable for global signal and data line transmission.
  • a top gate thin film transistor including a first conductive layer, an active layer, an insulating layer and a second conductive layer formed in sequence;
  • the first conductive layer includes spaced apart source and drain electrodes a channel is interposed between the source and the drain;
  • the active layer includes a semiconductor layer disposed in the channel and having two ends overlapping the source and the top of the drain, respectively And a protective layer attached to the semiconductor layer;
  • the insulating layer includes a gate insulating portion on the protective layer and the source and drain;
  • the second conductive layer includes a gate a gate portion provided on the insulating portion with respect to the channel.
  • the present invention also provides an array substrate comprising a substrate and a thin film transistor, wherein the thin film transistor is the top gate thin film transistor, the insulating layer further includes a pixel portion on the substrate, the second conductive layer Also included is a pixel electrode formed on the pixel portion, the pixel electrode being connected to the drain through a via hole on the insulating layer.
  • the present invention also provides a TFT device including an array substrate and a data signal line and a control signal line formed by the first conductive layer, the data signal line and the control signal line intersecting and at the intersection of the data signal line Disconnecting from one of the control signal lines to form a break, the insulating layer further comprising a signal line insulating portion covering the portion of the data signal line or the control signal line passing through the break portion,
  • the second conductive layer further includes a connection portion of the data signal line or the control signal line that covers the signal line insulation portion and is electrically disconnected; the source is electrically connected to the data signal line.
  • the gate portion is electrically connected to the data signal line.
  • the invention also provides a method for manufacturing an array substrate, comprising the following steps:
  • a first photolithographic mask exposing, developing, and etching the first conductive layer such that the first conductive layer forms spaced apart source and drain electrodes on the substrate, the source Forming a channel between the drain and the substrate;
  • a second photolithography mask exposing, developing, and etching the semiconductor layer and the protective layer, etching away the contact with the channel, the source, and the drain a semiconductor layer and the protective layer;
  • a third photolithography mask exposing, developing, and etching the insulating layer, so that the insulating layer forms a gate insulating portion on the protective layer and the source and drain electrodes and communicates with the a through hole of the drain;
  • a fourth photolithography mask exposing, developing, and etching the second conductive layer, so that the second conductive layer forms spaced gate portions and pixel electrodes, the gate portion and the semiconductor Corresponding to the layer, the pixel electrode is connected to the drain through the through hole.
  • the technical effect of the present invention is that the top gate thin film transistor protects the semiconductor layer by using the protective layer, avoids the influence of the gate insulating layer on the semiconductor layer, and is the gate insulating layer.
  • a more and better alternative is provided, that is, a dense gate insulating layer can be used, so that the gate insulating layer acts as a passivation without adding an additional passivation layer, which simplifies the process steps.
  • FIG. 1 is a schematic plan view of a top gate thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of an array substrate according to an embodiment of the present invention, which is a cross-sectional view taken along line A-A of FIG. 1;
  • FIG. 3 is a schematic structural view of a source/drain base layer deposited on a sinking bottom according to an embodiment of the present invention
  • FIG. 4 is a schematic structural view of a first photolithography mask according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a second photolithography mask according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural view of depositing a gate insulating layer on a source/drain base layer according to an embodiment of the present invention
  • FIG. 7 is a schematic structural view of a third photolithography mask according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural view of a fourth photolithography mask according to an embodiment of the present invention, which is a cross-sectional view taken along line B-B of FIG. 1;
  • FIG. 9 is another schematic structural diagram of a fourth photolithography mask according to an embodiment of the present invention, the first conductive layer includes an ohmic contact layer;
  • Figure 10 is a plan view corresponding to Figure 4.
  • Figure 11 is a plan view corresponding to Figure 5;
  • Figure 12 is a plan view corresponding to Figure 7.
  • a top gate thin film transistor 10 includes a first conductive layer 11 , an active layer 12 , an insulating layer 13 , and a second conductive layer 14 , which are sequentially formed, the first conductive layer.
  • the 11 includes a source 112 and a drain 114 disposed at intervals, a channel 116 is interposed between the source 112 and the drain 114, and the active layer 12 is disposed in the channel 116 and two a semiconductor layer 122 overlapping the top of the source 112 and the drain 114 and a protective layer 124 attached to the semiconductor layer 122;
  • the insulating layer 13 includes the protective layer 124 and the The gate insulating portion 132 on the source 112 and the drain 114;
  • the second conductive layer 14 includes a gate portion 142 disposed on the gate insulating portion 132 and disposed opposite to the channel 116.
  • the first conductive layer 11 is made of a metal material, which may be molybdenum, aluminum, titanium, copper, nickel, tungsten, gold, palladium, chromium, lanthanum, zinc, cobalt, manganese or Silver and so on.
  • the first conductive layer 11 is formed on the substrate 20 to form a source 112 and a drain.
  • the bottom of the 114 contacts the TFT structure, and the second conductive layer 14 is disposed on a side away from the substrate 20 to form a top gate TFT structure, effectively preventing the first conductive layer 11 from being protected by the passivation layer.
  • the top gate thin film transistor 10 provided by the embodiment of the present invention protects the semiconductor layer by using the protective layer 124 122.
  • the influence of the insulating layer 13 on the semiconductor layer 122 is avoided, and the insulating layer 13 is provided with more and better choices, that is, the dense insulating layer 13 can be used, so that the insulating layer 13 acts as a passivation layer. Process steps are simplified without the need for additional passivation layers.
  • the second conductive layer 14 is made of a transparent conductive material.
  • the second conductive layer 14 is made of a transparent conductive metal oxide.
  • the second conductive layer 14 is made of indium oxide, zinc oxide, indium tin oxide, indium zinc oxide, zinc aluminum oxide, gallium zinc oxide or any combination thereof.
  • the second conductive layer 14 is made of a metal material.
  • the second conductive layer 14 is made of molybdenum, aluminum, titanium, copper, nickel, tungsten, gold, palladium, chromium, ruthenium, zinc, cobalt, manganese, silver or a compound having any of the above elements.
  • the semiconductor layer 122 is made of an amorphous silicon semiconductor material or a metal oxide semiconductor material.
  • the semiconductor layer 122 is made of at least one of zinc, indium, tin, gallium, and antimony.
  • the protective layer 124 is made of an insulating semiconductor material.
  • the protective layer 124 is made of silicon oxide, silicon nitride or aluminum oxide or the like.
  • the first conductive layer 11 further includes an ohmic contact layer 118 disposed between the source 112 and the drain 114 and the semiconductor layer 122 .
  • the ohmic contact layer 118 has good conductivity for reducing leakage current of the top gate thin film transistor 10.
  • the ohmic contact layer 118 is made of n+ doped a-Si.
  • an array substrate provided by an embodiment of the present invention includes a substrate 20 and a thin film transistor.
  • the thin film transistor is the top gate thin film transistor 10
  • the insulating layer 13 further includes the substrate.
  • a pixel portion 134 on the second conductive layer 14 further includes a pixel electrode 144 formed on the pixel portion 134, the pixel electrode 144 passing through the through hole 130 on the insulating layer 13 and the drain 114 connections.
  • the top gate thin film transistor 10 has the same structure as the top gate thin film transistor 10 of the above embodiments, and has the same function and function, and will not be described herein. It can be understood that the second conductive layer 14 and the pixel electrode 144 are formed side by side on the insulating layer 13 , and the pixel electrode 144 and the drain 114 are electrically connected through the through hole 130 .
  • the substrate 20 is made of glass, plastic or stainless steel or the like.
  • the second conductive layer 14 further includes a buffer layer 146 formed between the substrate 20 and the top gate thin film transistor 10, the source 112 and the A drain electrode 114 is formed on a surface of the buffer layer 146.
  • the buffer layer 146 is made of silicon oxide, silicon nitride or a metal oxide, for example, the metal oxide is alumina or the like.
  • the buffer layer 146 is composed of a single buffer layer material, is formed by laminating a plurality of buffer layers, or is formed by interlacing a plurality of buffer layers.
  • a TFT device includes an array substrate and a data signal line 30 and a control signal line 40 formed by the first conductive layer 11 , the data signal line 30 and a control signal line.
  • the insulating layer 13 further comprising covering the data signal line 30 or the control signal line 40 and passing through the signal line insulating portion 136 of the disconnecting portion 50
  • the second conductive layer 14 further including the data signal line 30 covering the signal line insulating portion 136 and electrically disconnected or the The connection portion 148 of the control signal line 40; the source 112 is electrically connected to the data signal line 30, and the gate portion 142 is electrically connected to the data signal line 30.
  • the array substrate includes a substrate 20 and a thin film transistor, wherein the thin film transistor is the top gate thin film transistor 10, and the array substrate further includes a pixel electrode 144 formed on the insulating layer 13, and the pixel electrode 144 passes through the A via 130 on the insulating layer 13 is connected to the drain 114; the TFT device further includes a data signal line 30 and a control signal line 40.
  • the top gate thin film transistor 10 has the same structure as the top gate thin film transistor 10 of the above embodiments, and has the same function and function, and will not be described herein.
  • the substrate 20 is made of glass, plastic or stainless steel or the like.
  • the TFT device is an organic light emitting diode (OLED), and for the bottom emitting OLED, the second conductive layer 14 and the pixel electrode 144 may be a transparent conductive material, such as a transparent conductive metal oxide.
  • the transparent metal oxide may be indium oxide, zinc oxide, indium tin oxide, indium zinc oxide, zinc aluminum oxide or gallium zinc oxide; for the top emitting OLED, the second conductive layer 14 and the pixel
  • the electrode 144 can be made of a metal having high reflection efficiency, for example, molybdenum, aluminum, titanium, copper, nickel, tungsten, gold, palladium, chromium, ruthenium, zinc, cobalt, manganese or silver, etc., using a metal having high reflection efficiency as a metal.
  • the second conductive layer 14 and the pixel electrode 144 may block the influence of light emitted by the OLED on the semiconductor layer 122, thereby improving the stability of the performance of the TFT device.
  • the array substrate further includes a buffer layer 146 formed between the substrate 20 and the top gate thin film transistor 10 , the source 112 and the drain 114 .
  • a buffer layer 146 formed between the substrate 20 and the top gate thin film transistor 10 , the source 112 and the drain 114 .
  • the buffer layer 146 is made of silicon oxide, silicon nitride or a metal oxide, for example, the metal oxide is alumina or the like.
  • the buffer layer 146 is composed of a single buffer layer material, is formed by laminating a plurality of buffer layers, or is formed by interlacing a plurality of buffer layers.
  • the data signal line 30 is turned on by the first conductive layer 11
  • the control signal line 40 is turned on by the second conductive layer 14 .
  • the first conductive layer Turning on the data signal line 30 and turning on the control signal line 40 by the second conductive layer 14 improves stability of TFT device performance.
  • the data signal line 30 and the control signal line 40 are both turned on by the first conductive layer 11.
  • the data signal line 30 and the control signal line 40 are turned on by the first conductive layer 11 in consideration of the transparent conductive material having a lower conductivity.
  • the intersection of the signal line 30 and the control signal line 40 is connected by a transparent conductive material to avoid a short circuit.
  • the first conductive layer 11 may be covered by the semiconductor layer 122 and the protective layer 124 to further reduce leakage current.
  • a method for manufacturing an array substrate according to an embodiment of the present invention includes the following steps:
  • first conductive layer 11 Depositing a first conductive layer 11 as shown in FIG. 3; it is understood that a first conductive layer 11 is deposited on the surface of the substrate 20; preferably, the substrate 20 is made of glass, plastic or stainless steel or the like;
  • the first conductive layer 11 is made of a metal material, which may be molybdenum, aluminum, titanium, copper, nickel, tungsten, gold, palladium, chromium, ruthenium, zinc, cobalt, manganese or silver.
  • the first photolithographic mask is used for exposing, developing, and etching the first conductive layer 11 such that the first conductive layer 11 forms spaced apart source 112 and drain 114 on the substrate 20.
  • a channel 116 is formed between the source 112, the drain 114 and the substrate 20, as shown in FIG. 4; it can be understood that the bottom of the channel 116 is the top surface of the substrate 20.
  • the source 112 and the drain 114 are formed to contact the TFT structure, and the second conductive layer 14 is disposed on a side away from the substrate 20 to form a top gate TFT structure, thereby effectively avoiding the use of the barrier layer pair.
  • the first conductive layer 11 is protected.
  • the semiconductor layer 122 and the protective layer 124 are sequentially deposited as shown in FIG. 5; it can be understood that the semiconductor layer 122 and the protective layer 124 are sequentially deposited on the first conductive layer 11; in the overlapping portion of the two conductive materials, the first The conductive layer 11 may be covered by the semiconductor layer 122 and the protective layer 124 to further reduce leakage current.
  • a second photolithography mask exposing, developing, and etching the semiconductor layer 122 and the protective layer 124, etching away the channel 116, the source 112, and the drain 114
  • the semiconductor layer 122 and the protective layer 124 other than the contact, as shown in FIG. 5;
  • the insulating layer 13 covers the surface of the source 112, the drain 114, the protective layer 124 and extends to the surface of the substrate 20, as shown in FIG. 6; preferably, the The insulating layer 13 may be silicon oxide, silicon nitride, aluminum oxide or tantalum oxide or the like.
  • the third photolithography mask exposes, develops, and etches the insulating layer 13 to form a gate on the insulating layer 13 on the protective layer 124 and the source 112 and the drain 114.
  • the insulating portion 132 and the through hole 130 connected to the drain 114 are as shown in FIG. 7;
  • the fourth photolithography mask exposes, develops, and etches the second conductive layer 14 to form the second conductive layer 14 with the gate portion 142 and the pixel electrode 144 which are spaced apart, and the gate portion 142 corresponds to the semiconductor layer 122, and the pixel electrode 144 is connected to the drain 114 through the via 130, as shown in FIG.
  • the manufacturing method of the array substrate provided by the embodiment of the present invention protects the semiconductor layer 122 by using the protective layer 124, so that the semiconductor layer 122 is not affected by the deposition process of the insulating layer 13, so that the dense insulating layer can be used. 13, and simultaneously using the insulating layer 13 as a passivation layer without additionally providing a passivation layer, simplifying the process arrangement, forming the first conductive layer 11 bottom contact on the substrate 20 only by four photolithographic masks And the second conductive layer 14 is topped by the TFT structure.
  • the method further includes the steps of: coating a photoresist on an upper surface of the first conductive layer 11; and transferring the pattern on the mask to the light by an exposure process using ultraviolet light. On the engraving; developing the exposed photoresist and the first conductive layer 11 to obtain the source 112 and the drain 114, and between the source 112 and the drain 114 Forming the channel 116; and stripping the photoresist attached to the source 112 and the drain 114 after development processing.
  • the method further includes the steps of: coating a photoresist on the surface of the protective layer 124; and transferring the pattern on the mask onto the photoresist by exposure processing using ultraviolet light. Developing the exposed photoresist, the protective layer 124, and the semiconductor layer 122 to obtain the semiconductor layer 122 and the protective layer connected between the source 112 and the drain 114 124; and peeling off the photoresist attached to the protective layer 124 after the development process.
  • the method further includes the steps of: coating a photoresist on the surface of the insulating layer 13; and transferring the pattern on the mask to the photoresist by exposure processing using ultraviolet light. Developing the exposed photoresist and the insulating layer 13 to obtain the insulating layer 13 having the via hole 130; and peeling off the photoresist attached to the insulating layer 13 after development processing .
  • the method further includes the steps of: coating a photoresist on the surface of the second conductive layer 14; and transferring the pattern on the mask to the photolithography by exposure processing using ultraviolet light. On the glue; developing the exposed photoresist and the second conductive layer 14 to obtain a gate portion 142 and a pixel electrode 144; and peeling the developed portion and attaching to the gate portion 142 and the pixel Photoresist on electrode 144.
  • the buffer layer 146 is made of silicon oxide, silicon nitride or a metal oxide, for example, the metal oxide is alumina or the like.
  • the buffer layer 146 is composed of a single buffer layer material, is formed by laminating a plurality of buffer layers, or is formed by interlacing a plurality of buffer layers.
  • the step of the first photolithography mask further comprising depositing an ohmic contact layer 118 on the first conductive layer 11; in the step of the first photolithography mask, The first conductive layer 11 and the ohmic contact layer 118 are simultaneously exposed, developed, and etched.
  • the ohmic contact layer 118 has good conductivity for reducing leakage current of the top gate thin film transistor 10.
  • the ohmic contact layer 118 is made of n+ doped a-Si.
  • the semiconductor layer 122 is made of an amorphous silicon semiconductor material or a metal oxide semiconductor material.
  • the semiconductor layer 122 is made of at least one of zinc, indium, tin, gallium, and antimony.
  • the protective layer 124 is made of an insulating semiconductor material.
  • the protective layer 124 is made of silicon oxide, silicon nitride or aluminum oxide.
  • the second conductive layer 14 is a transparent conductive material or a metal material.
  • the TFT device is an organic light emitting diode (OLED).
  • OLED organic light emitting diode
  • the second conductive layer 14 may be a transparent conductive material.
  • the second conductive layer 14 is a transparent conductive metal oxide, for example, The transparent conductive metal oxide is indium oxide, zinc oxide, indium tin oxide, indium zinc oxide, zinc aluminum oxide or gallium zinc oxide; for the top emitting OLED, the second conductive layer 14 can adopt a metal with high reflection efficiency.
  • the conductive layer 14 and the pixel electrode 144 can block the influence of light emitted from the OLED on the semiconductor layer 122, thereby improving the stability of the performance of the TFT device.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • ALD Atomic Layer Deposition
  • the step of the first photolithography mask further comprising forming the first conductive layer 11 to form a data signal line 30 and a control signal line 40, the data signal line 30 and the Control signal line 40 intersects and at the intersection, one of the data signal line 30 and the control signal line 40 is turned off to form a break 50; the source 112 is electrically connected to the data signal line 30.
  • the step of the second photolithography mask further comprising covering the semiconductor layer 122 and the protective layer 124 over the data signal line 30 or the control signal line 40. Break point Part of 50.
  • step of the third photolithography mask further comprising: causing the insulating layer 13 to cover the data signal line 30 or the control signal line 40 to pass through the portion of the disconnect portion 50.
  • Signal line insulating portion 136 further comprising: causing the insulating layer 13 to cover the data signal line 30 or the control signal line 40 to pass through the portion of the disconnect portion 50.
  • the step of the fourth photolithography mask further comprising: causing the second conductive layer 14 to include the data signal line 30 covering the signal line insulating portion 136 and electrically disconnected or The connection portion 148 of the signal line 40 is controlled.
  • step of the fourth photolithography mask further comprising electrically connecting the gate portion 142 to the data signal line 30 .
  • the embodiment of the invention further provides an array substrate, which is fabricated by using the above method for manufacturing the array substrate.
  • the manufacturing method of the array substrate is the same as the steps of the manufacturing method of the array substrate in the above embodiments, and has the same functions and functions, and details are not described herein.
  • the embodiment of the present invention further provides a TFT device including an array substrate, wherein the array substrate is fabricated by using the above method for fabricating the array substrate, and the TFT device further includes a data signal line 30 and a control signal line 40.
  • the manufacturing method of the array substrate is the same as the steps of the manufacturing method of the array substrate in the above embodiments, and has the same functions and functions, and details are not described herein.
  • the data signal line 30 is turned on by the first conductive layer 11
  • the control signal line 40 is turned on by the second conductive layer 14 .
  • the first conductive layer Turning on the data signal line 30 and turning on the control signal line 40 by the second conductive layer 14 improves stability of TFT device performance.
  • the data signal line 30 and the control signal line 40 are both turned on by the first conductive layer 11.
  • the transparent conductive layer 14 has a lower conductivity, and the first conductive layer 11 turns on the data signal line 30 and the control signal line 40.
  • the intersection of the data signal line 30 and the control signal line 40 is connected by a transparent second conductive layer 14 to avoid a short circuit.

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Abstract

提供了一种顶栅薄膜晶体管（10），旨在解决现有技术中采用钝化层来阻挡源漏金属刻蚀时对半导体造成的伤害的问题。该顶栅薄膜晶体管（10）包括依次形成的第一导电层（11）、有源层（12）、绝缘层（13）和第二导电层（14）；第一导电层（11）包括间隔设置的源极（112）与漏极（114），源极（112）和漏极（114）之间夹设有沟道（116）；有源层（12）包括设置于沟道（116）内且两端分别搭接于源极（112）和漏极（114）顶部的半导体层（122）以及贴附于半导体层（122）上的保护层（124）；绝缘层（13）包括位于保护层（124）及源极（112）与漏极（114）上的栅极绝缘部（132）；第二导电层（14）包括位于栅极绝缘部（132）上并相对于沟道（116）而设置的栅极部（142）。采用保护层（124）保护半导体层（122），避免栅极绝缘层（132）对半导体层（122）的影响，这样，采用致密栅极绝缘层以起到钝化作用，而无需增设额外的钝化层，简化了工艺步骤。

Description

顶栅薄膜晶体管、阵列基板及其制造方法以及TFT器件 技术领域
本发明属于半导体技术领域，尤其涉及一种顶栅薄膜晶体管、包含该顶栅薄膜晶体管的阵列基板、该阵列基板的制造方法以及包含该阵列基板的TFT器件。
 背景技术
薄膜晶体管（Thin Film Transistor，TFT）在液晶和有机发光（OLED）等平板显示技术领域得到了非常广泛的应用。目前，在TFT技术中，有源层多采用非晶硅（a-Si）和多晶硅（poly-Si）等半导体材料，一般多用非晶硅TFT，可以覆盖几乎所有尺寸的平板显示产品，而多晶硅TFT只能适用于中小尺寸产品。随着平板显示技术的快速发展，对TFT的性能提出了越来越高的要求，非晶硅TFT和多晶硅TFT的特性已无法满足构造复杂、漏电流大和量产均一等方面的要求，在此要求下，金属氧化物TFT应运而生，成为上述两种半导体材料的替代者。
采用金属氧化物作为TFT的有源层材料，可以将TFT的结构可以分为底栅型和顶栅型两类，底栅型也可以称为反交错型电极结构，顶栅型也称为交错型电极结构。底栅型TFT结构又分为刻蚀保护型和背沟道刻蚀型，而刻蚀保护型需要钝化层来阻挡源漏金属刻蚀时对半导体造成的伤害，这样的方法，增加了工艺的复杂程度进而增加成本。
有机发光二极管（OLED）有两种发光模式：顶发光与底发光模式，对于前者，背板的像素电极需要为反射率高的金属层，对于后者则需要透明导电材料，常见的透明导电材料导电率通常远高于金属，不适宜用于全局信号线和数据线的传输。
 技术问题
本发明的目的在于提供一种顶栅薄膜晶体管，旨在解决现有技术中采用钝化层来阻挡源漏金属刻蚀时对半导体造成的伤害的问题。
 技术解决方案
本发明是这样实现的，一种顶栅薄膜晶体管，包括依次形成的第一导电层、有源层、绝缘层和第二导电层；所述第一导电层包括间隔设置的源极与漏极，所述源极和所述漏极之间夹设有沟道；所述有源层包括设置于所述沟道内且两端分别搭接于所述源极和所述漏极顶部的半导体层以及贴附于所述半导体层上的保护层；所述绝缘层包括位于所述保护层及所述源极与漏极上的栅极绝缘部；所述第二导电层包括位于所述栅极绝缘部上并相对于所述沟道而设置的栅极部。
本发明还提供了一种阵列基板，包括衬底以及薄膜晶体管，所述薄膜晶体管为上述顶栅薄膜晶体管，所述绝缘层还包括位于所述衬底上的像素部，所述第二导电层还包括形成于所述像素部上的像素电极，所述像素电极通过所述绝缘层上的通孔与所述漏极连接。
本发明还提供了一种TFT器件，包括阵列基板以及由所述第一导电层形成的数据信号线和控制信号线，所述数据信号线和控制信号线相交并且在相交处所述数据信号线和所述控制信号线之一断开以形成断开处，所述绝缘层还包括覆盖所述数据信号线或所述控制信号线穿过所述断开处的部分的信号线绝缘部，所述第二导电层还包括覆盖所述信号线绝缘部并电性连接断开的所述数据信号线或所述控制信号线的连接部；所述源极电性连接所述数据信号线，所述栅极部电性连接所述数据信号线。
本发明还提供了一种阵列基板的制造方法，包括以下步骤：
提供衬底；
沉积第一导电层；
第一次光刻掩模，对所述第一导电层进行曝光、显影和刻蚀，使所述第一导电层在所述衬底上形成间隔设置的源极和漏极，所述源极、所述漏极和所述衬底之间形成沟道；
依次沉积半导体层和保护层；
第二次光刻掩模，对所述半导体层和所述保护层进行曝光、显影和刻蚀，刻蚀掉除与所述沟道、所述源极和所述漏极接触以外的所述半导体层和所述保护层；
沉积绝缘层；
第三次光刻掩模，对所述绝缘层进行曝光、显影和刻蚀，使所述绝缘层形成位于所述保护层及所述源极与漏极上的栅极绝缘部以及连通至所述漏极的通孔；
沉积第二导电层；
第四次光刻掩模，对所述第二导电层进行曝光、显影和刻蚀，使所述第二导电层形成间隔设置的栅极部和像素电极，所述栅极部与所述半导体层相对应，所述像素电极通过所述通孔与所述漏极相连接。
 有益效果
本发明相对于现有技术的技术效果是：顶栅薄膜晶体管采用所述保护层保护所述半导体层，避免所述栅极绝缘层对所述半导体层的影响，并为所述栅极绝缘层提供了更多更好的选择，即可以采用致密栅极绝缘层，这样栅极绝缘层起到钝化作用，而无需增设额外的钝化层，简化了工艺步骤。
 附图说明
图1是本发明实施例提供的顶栅薄膜晶体管的平面示意图；
图2是本发明实施例提供的阵列基板的结构示意图，其是沿图1中A-A方向的剖视图；
图3是本发明实施例提供的源漏基层沉积于沉底上的结构示意图；
图4是本发明实施例提供的第一次光刻掩模后的结构示意图；
图5是本发明实施例提供的第二次光刻掩模后的结构示意图；
图6是本发明实施例提供的将栅极绝缘层沉积于源漏基层上的结构示意图；
图7是本发明实施例提供的第三次光刻掩模后的结构示意图；
图8是本发明实施例提供的第四次光刻掩模后的结构示意图，其是沿图1中B-B方向的剖视图；
图9是本发明实施例提供的第四次光刻掩模后的另一结构示意图，该第一导电层包括欧姆接触层；
图10是对应于图4的平面示意图；
图11是对应于图5的平面示意图；
图12是对应于图7的平面示意图。
 本发明的实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
请参照图1至图8，本发明实施例提供的顶栅薄膜晶体管10包括依次形成的第一导电层11、有源层12、绝缘层13和第二导电层14，所述第一导电层11包括间隔设置的源极112与漏极114，所述源极112和所述漏极114之间夹设有沟道116，所述有源层12包括设置于所述沟道116内且两端分别搭接于所述源极112和所述漏极114顶部的半导体层122以及贴附于所述半导体层122上的保护层124；所述绝缘层13包括位于所述保护层124及所述源极112与漏极114上的栅极绝缘部132；所述第二导电层14包括位于所述栅极绝缘部132上并相对于所述沟道116而设置的栅极部142。
在该实施例中，所述第一导电层11由金属材料制成，该金属材料可以是钼、铝、钛、铜、镍、钨、金、钯、铬、铌、锌、钴、锰或者银等。
在该实施例中，所述第一导电层11形成于衬底20上，从而形成源极112、漏极 114底接触TFT结构，并且将所述第二导电层14设置于远离所述衬底20的一侧，以形成顶栅TFT结构，有效地避免采用钝化层对第一导电层11进行保护。
本发明实施例提供的顶栅薄膜晶体管10采用所述保护层124保护所述半导体层 122，避免所述绝缘层13对所述半导体层122的影响，并为所述绝缘层13提供了更多更好的选择，即可以采用致密绝缘层13，这样绝缘层13起到钝化作用，而无需增设额外的钝化层，简化了工艺步骤。
进一步地，所述第二导电层14由透明导电材料制成。优选地，所述第二导电层14由透明导电金属氧化物制成。进一步优选地，所述第二导电层14由氧化铟、氧化锌、氧化铟锡、氧化铟锌、氧化锌铝、氧化镓锌或者上述任意组合制成。
进一步地，所述第二导电层14由金属材料制成。优选地，所述第二导电层14由钼、铝、钛、铜、镍、钨、金、钯、铬、铌、锌、钴、锰、银或者具有上述任一元素的化合物制成。
进一步地，所述半导体层122由非晶硅半导体材料或者金属氧化物半导体材料制成。优选地，所述半导体层122由锌、铟、锡、镓、铪中的至少一种而制成。
在该实施例中，所述保护层124由具有绝缘性的半导体材料制成，优选地，所述保护层124采用氧化硅、氮化硅或者氧化铝等制成。
请参照图9，进一步地，所述第一导电层11还包括设置于所述源极112和所述漏极114与所述半导体层122之间的欧姆接触层118。所述欧姆接触层118具有较好的导电性，用于减小顶栅薄膜晶体管10的漏电流。优选地，所述欧姆接触层118由n+掺杂的a-Si制成。
请参照图1至图8，本发明实施例提供的阵列基板包括衬底20以及薄膜晶体管，所述薄膜晶体管为上述顶栅薄膜晶体管10，所述绝缘层13还包括位于所述衬底 20上的像素部134，所述第二导电层14还包括形成于所述像素部134上的像素电极144，所述像素电极144通过所述绝缘层13上的通孔130与所述漏极114连接。在该实施例中，所述顶栅薄膜晶体管10与上述各实施例中顶栅薄膜晶体管10的结构相同，且具有相同的功能和作用，此处不赘述。可以理解，所述第二导电层14与所述像素电极144并排形成于所述绝缘层13上，且所述像素电极144与所述漏极114通过所述通孔130电连接。
在该实施例中，所述衬底20由玻璃、塑料或者不锈钢等制成。
请参照图3和图4，进一步地，所述第二导电层14还包括形成于所述衬底20与所述顶栅薄膜晶体管10之间的缓冲层146，所述源极112和所述漏极114形成于所述缓冲层146表面。优选地，所述缓冲层146由氧化硅、氮化硅或者金属氧化物制成，例如，所述金属氧化物为氧化铝等。
进一步地，所述缓冲层146由单层缓冲层材料构成、由多层缓冲层材料层叠设置而构成或者由多层缓冲层材料交错设置而构成。
请参照图1至图8，本发明实施例提供的TFT器件包括阵列基板以及由所述第一导电层11形成的数据信号线30和控制信号线40，所述数据信号线30和控制信号线40相交并且在相交处所述数据信号线30和所述控制信号线40之一断开以形成断开处50，所述绝缘层13还包括覆盖所述数据信号线30或所述控制信号线40并穿过所述断开处50的信号线绝缘部136，所述第二导电层14还包括覆盖所述信号线绝缘部136并电性连接断开的所述数据信号线30或所述控制信号线40的连接部148；所述源极112电性连接所述数据信号线30，所述栅极部142电性连接所述数据信号线30。
所述阵列基板包括衬底20以及薄膜晶体管，所述薄膜晶体管为上述顶栅薄膜晶体管10，所述阵列基板还包括形成于所述绝缘层13上的像素电极144，所述像素电极144通过所述绝缘层13上的通孔130与所述漏极114连接；所述TFT器件还包括数据信号线30和控制信号线40。
在该实施例中，所述顶栅薄膜晶体管10与上述各实施例中顶栅薄膜晶体管10的结构相同，且具有相同的功能和作用，此处不赘述。
在该实施例中，所述衬底20由玻璃、塑料或者不锈钢等制成。
在该实施例中，所述TFT器件为有机发光二极管（OLED），对于底发光的OLED，所述第二导电层14和所述像素电极144可以采用透明导电材料，例如透明导电金属氧化物，具体地，该透明金属氧化物可以是氧化铟、氧化锌、氧化铟锡、氧化铟锌、氧化锌铝或者氧化镓锌等；对于顶发光的OLED，所述第二导电层14和所述像素电极144可以采用反射效率高的金属制成，例如，钼、铝、钛、铜、镍、钨、金、钯、铬、铌、锌、钴、锰或者银等，利用反射效率高的金属作为第二导电层14和像素电极144可以阻挡OLED发出的光对所述半导体层122的影响，从而提升了TFT器件性能的稳定性。
请参照图3至图8，进一步地，所述阵列基板还包括形成于所述衬底20与所述顶栅薄膜晶体管10之间的缓冲层146，所述源极112和所述漏极114形成于所述缓冲层146表面。优选地，所述缓冲层146由氧化硅、氮化硅或者金属氧化物制成，例如，所述金属氧化物为氧化铝等。
进一步地，所述缓冲层146由单层缓冲层材料构成、由多层缓冲层材料层叠设置而构成或者由多层缓冲层材料交错设置而构成。
进一步地，所述数据信号线30由所述第一导电层11导通，所述控制信号线40由所述第二导电层14导通。对于TFT器件为顶发光的OLED时，由所述第一导电层 11导通所述数据信号线30以及由所述第二导电层14导通所述控制信号线40，提高了TFT器件性能的稳定性。
进一步地，所述数据信号线30和所述控制信号线40均由所述第一导电层11导通。对于TFT器件为底发光的OLED时，考虑到透明导电材料具有较低的导电率，由所述第一导电层11导通所述数据信号线30和所述控制信号线40，在所述数据信号线30和所述控制信号线40相交处，采用透明导电材料相连接以避免短路。
在该实施例中，在两层导电材料重叠部分，所述第一导电层11上可由半导体层122及所述保护层124覆盖，以进而减小漏电流。
请参照图1至图8，本发明实施例提供的阵列基板的制造方法包括以下步骤：
提供衬底20；
沉积第一导电层11，如图3所示；可以理解，在所述衬底20表面沉积一层第一导电层11；优选地，所述衬底20由玻璃、塑料或者不锈钢等制成；所述第一导电层11由金属材料制成，该金属材料可以是钼、铝、钛、铜、镍、钨、金、钯、铬、铌、锌、钴、锰或者银等。
第一次光刻掩模，对所述第一导电层11进行曝光、显影和刻蚀，使所述第一导电层11在所述衬底20上形成间隔设置的源极112和漏极114，所述源极112、所述漏极114和所述衬底20之间形成沟道116，如图4所示；可以理解，所述沟道116的底部为所述衬底20的顶面，这样形成源极112、漏极114底接触TFT结构，并且将所述第二导电层14设置于远离所述衬底20的一侧，以形成顶栅TFT结构，有效地避免采用阻挡层对第一导电层11进行保护。
依次沉积半导体层122和保护层124，如图5所示；可以理解，在所述第一导电层11上依次沉积半导体层122和保护层124；在两层导电材料重叠部分，所述第一导电层11上可由半导体层122及所述保护层124覆盖，以进而减小漏电流。
第二次光刻掩模，对所述半导体层122和所述保护层124进行曝光、显影和刻蚀，刻蚀掉除与所述沟道116、所述源极112和所述漏极114接触以外的所述半导体层122和所述保护层124，如图5所示；
沉积绝缘层13；可以理解，所述绝缘层13覆盖于所述源极112、漏极114、保护层124表面并延伸至所述衬底20表面，如图6所示；优选地，所述绝缘层13可以是氧化硅、氮化硅、氧化铝或者氧化铪等。
第三次光刻掩模，对所述绝缘层13进行曝光、显影和刻蚀，使所述绝缘层13上形成位于所述保护层124及所述源极112与漏极114上的栅极绝缘部132以及连通至所述漏极114的通孔130，如图7所示；
在所述绝缘层13上沉积第二导电层14；
第四次光刻掩模，对所述第二导电层14进行曝光、显影和刻蚀，使所述第二导电层14形成间隔设置的栅极部142和像素电极144，所述栅极部142与所述半导体层122相对应，所述像素电极144通过所述通孔130与所述漏极114相连接，如图8所示。
本发明实施例提供的阵列基板的制造方法利用保护层124保护所述半导体层122，使得所述半导体层122不受所述绝缘层13淀积工艺的影响，从而可以使用致密的所述绝缘层13，并同时利用该绝缘层13作为钝化层，而无需额外设置钝化层，简化了工艺布置，仅通过四次光刻掩模在所述衬底20上形成第一导电层11底接触且第二导电层14置顶的TFT结构。
在第一次光刻掩模步骤中，具体包括以下步骤：在所述第一导电层11的上表面涂覆光刻胶；利用紫外光将掩模板上的图形通过曝光处理转印至该光刻胶上；对曝光处理后的光刻胶和所述第一导电层11进行显影得到所述源极112和所述漏极114，并在所述源极112和所述漏极114之间形成所述沟道116；以及剥离经显影处理后贴附于所述源极112和所述漏极114上的光刻胶。
在第二次光刻掩膜步骤中，具体包括以下步骤：在所述保护层124的表面涂覆光刻胶；利用紫外光将掩模板上的图形通过曝光处理转印至该光刻胶上；对曝光处理后的光刻胶、所述保护层124和所述半导体层122进行显影得到连接于所述源极112和所述漏极114之间的所述半导体层122和所述保护层124；以及剥离经显影处理后贴附于所述保护层124上的光刻胶。
在第三次光刻掩模步骤中，具体包括以下步骤：在所述绝缘层13的表面涂覆光刻胶；利用紫外光将掩模板上的图形通过曝光处理转印至该光刻胶上；对曝光处理后的光刻胶和所述绝缘层13进行显影得到具有所述通孔130的所述绝缘层13；以及剥离经显影处理后贴附于所述绝缘层13上的光刻胶。
在第四次光刻掩膜步骤中，具体包括以下步骤：在所述第二导电层14的表面涂覆光刻胶；利用紫外光将掩模板上的图形通过曝光处理转印至该光刻胶上;对曝光处理后的光刻胶和所述第二导电层14进行显影得到栅极部142和像素电极144；以及剥离经显影处理后贴附于所述栅极部142和所述像素电极144上的光刻胶。
请参照图3，进一步地，在沉积第一导电层11的步骤之前，还包括：在所述衬底20表面沉积一缓冲层146的步骤；在沉积第一导电层11的步骤中，所述第一导电层11沉积在所述缓冲层146上。优选地，所述缓冲层146由氧化硅、氮化硅或者金属氧化物制成，例如，所述金属氧化物为氧化铝等。
进一步地，所述缓冲层146由单层缓冲层材料构成、由多层缓冲层材料层叠设置而构成或者由多层缓冲层材料交错设置而构成。
请参照图9，进一步地，在第一次光刻掩模的步骤之前，，还包括在第一导电层11上沉积欧姆接触层118；在第一次光刻掩模的步骤中，对所述第一导电层11和欧姆接触层118同时进行曝光、显影和刻蚀。所述欧姆接触层118具有较好的导电性，用于减小顶栅薄膜晶体管10的漏电流。优选地，所述欧姆接触层118由n+掺杂的a-Si制成。
进一步地，所述半导体层122由非晶硅半导体材料或者金属氧化物半导体材料制成。优选地，所述半导体层122由锌、铟、锡、镓、铪中的至少一种而制成。所述保护层124由具有绝缘性的半导体材料制成，优选地，所述保护层124采用氧化硅、氮化硅或者氧化铝等制成。
进一步地，在第四次光刻掩模步骤中，所述第二导电层14为透明导电材料或者金属材料。所述TFT器件为有机发光二极管（OLED），对于底发光的OLED，所述第二导电层14可以采用透明导电材料，优选地，所述第二导电层14为透明导电金属氧化物，例如，所述透明导电金属氧化物为氧化铟、氧化锌、氧化铟锡、氧化铟锌、氧化锌铝或者氧化镓锌；对于顶发光的OLED，所述第二导电层14可以采用反射效率高的金属制成，例如，钼、铝、钛、铜、镍、钨、金、钯、铬、铌、锌、钴、锰、银或者具有上述任一元素的化合物，利用反射效率高的金属作为第二导电层14和像素电极144可以阻挡OLED发出的光对所述半导体层122的影响，从而提升了TFT器件性能的稳定性。
进一步地，在沉积绝缘层13的步骤中，采用化学气相沉积（Chemical Vapor Deposition，简称CVD）、等离子体增强化学气相沉积法（Plasma Enhanced Chemical Vapor Deposition，简称PECVD）、原子层沉积（Atomic Layer Deposition，简称ALD）或者溅射方式实现。
请参照图10，进一步地，在第一次光刻掩模的步骤中，还包括使所述第一导电层11形成数据信号线30和控制信号线40，所述数据信号线30和所述控制信号线 40相交并且在相交处所述数据信号线30和控制信号线40之一断开以形成断开处 50；所述源极112电性连接所述数据信号线30。
请参照图11，进一步地，在第二次光刻掩模的步骤中，还包括使所述半导体层122和所述保护层124覆盖在所述数据信号线30或控制信号线40穿过所述断开处 50的部分。
请参照图12，进一步地，在第三次光刻掩模的步骤中，还包括使所述绝缘层13包括覆盖所述数据信号线30或控制信号线40穿过上述断开处50部分的信号线绝缘部136。
请参照图1，进一步地，在第四次光刻掩模的步骤中，还包括使所述第二导电层14包括覆盖上述信号线绝缘部136并电性连接断开的数据信号线30或控制信号线40的连接部148。
请参照图1，进一步地，在第四次光刻掩模的步骤中，还包括使所述栅极部142电性连接所述数据信号线30。
本发明实施例还提供了阵列基板，所述阵列基板采用上述阵列基板的制造方法而制成。在该实施例中，所述阵列基板的制造方法与上述各实施例中阵列基板的制造方法的步骤相同，且具有相同的功能和作用，此处不赘述。
本发明实施例还提供了一种TFT器件包括阵列基板，所述阵列基板采用上述阵列基板的制造方法而制成，所述TFT器件还包括数据信号线30和控制信号线40。在该实施例中，所述阵列基板的制造方法与上述各实施例中阵列基板的制造方法的步骤相同，且具有相同的功能和作用，此处不赘述。
进一步地，所述数据信号线30由所述第一导电层11导通，所述控制信号线40由所述第二导电层14导通。对于TFT器件为顶发光的OLED时，由所述第一导电层 11导通所述数据信号线30以及由所述第二导电层14导通所述控制信号线40，提高了TFT器件性能的稳定性。
进一步地，所述数据信号线30和所述控制信号线40均由所述第一导电层11导通。对于TFT器件为底发光的OLED时，考虑到透明第二导电层14具有较低的导电率，由所述第一导电层11导通所述数据信号线30和所述控制信号线40，在所述数据信号线30和所述控制信号线40相交处，采用透明第二导电层14相连接以避免短路。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (27)

  1. 一种顶栅薄膜晶体管，其特征在于，包括依次形成的第一导电层、有源层、绝缘层和第二导电层；所述第一导电层包括间隔设置的源极与漏极，所述源极和所述漏极之间夹设有沟道；所述有源层包括设置于所述沟道内且两端分别搭接于所述源极和所述漏极顶部的半导体层以及贴附于所述半导体层上的保护层；所述绝缘层包括位于所述保护层及所述源极与漏极上的栅极绝缘部；所述第二导电层包括位于所述栅极绝缘部上并相对于所述沟道而设置的栅极部。
  2. 如权利要求1所述的顶栅薄膜晶体管，其特征在于，所述第二导电层由透明导电材料制成。
  3. 如权利要求2所述的顶栅薄膜晶体管，其特征在于，所述第二导电层由透明导电金属氧化物制成。
  4. 如权利要求3所述的顶栅薄膜晶体管，其特征在于，所述第二导电层由氧化铟、氧化锌、氧化铟锡、氧化铟锌、氧化锌铝、氧化镓锌或者上述任意组合制成。
  5. 如权利要求1所述的顶栅薄膜晶体管，其特征在于，所述第二导电层由金属材料制成。
  6. 如权利要求5所述的顶栅薄膜晶体管，其特征在于，所述第二导电层由钼、铝、钛、铜、镍、钨、金、钯、铬、铌、锌、钴、锰、银或者具有上述任一元素的化合物制成。
  7. 如权利要求1所述的顶栅薄膜晶体管，其特征在于，所述半导体层由非晶硅半导体材料或者金属氧化物半导体材料制成。
  8. 如权利要求1所述的顶栅薄膜晶体管，其特征在于，所述第一导电层还包括设置于所述源极和所述漏极与所述半导体层之间的欧姆接触层。
  9. 一种阵列基板，包括衬底以及薄膜晶体管，其特征在于，所述薄膜晶体管为如权利要求1至8任意一项所述的顶栅薄膜晶体管，所述绝缘层还包括位于所述衬底上的像素部，所述第二导电层还包括形成于所述像素部上的像素电极，所述像素电极通过所述绝缘层上的通孔与所述漏极连接。
  10. 如权利要求9所述的阵列基板，其特征在于，所述第二导电层还包括形成于所述衬底与所述顶栅薄膜晶体管之间的缓冲层，所述源极和所述漏极形成于所述缓冲层表面。
  11. 如权利要求10所述的阵列基板，其特征在于，所述缓冲层由单层缓冲层材料构成、由多层缓冲层材料层叠设置而构成或者由多层缓冲层材料交错设置而构成。
  12. 一种TFT器件，其特征在于，包括如权利要求9至11任意一项所述阵列基板以及由所述第一导电层形成的数据信号线和控制信号线，所述数据信号线和控制信号线相交并且在相交处所述数据信号线和所述控制信号线之一断开以形成断开处，所述绝缘层还包括覆盖所述数据信号线或所述控制信号线穿过所述断开处的部分的信号线绝缘部，所述第二导电层还包括覆盖所述信号线绝缘部并电性连接断开的所述数据信号线或所述控制信号线的连接部；所述源极电性连接所述数据信号线，所述栅极部电性连接所述数据信号线。
  13. 一种阵列基板的制造方法，其特征在于，包括以下步骤：
    提供衬底；
    沉积第一导电层；
    第一次光刻掩模，对所述第一导电层进行曝光、显影和刻蚀，使所述第一导电层在所述衬底上形成间隔设置的源极和漏极，所述源极、所述漏极和所述衬底之间形成沟道；
    依次沉积半导体层和保护层；
    第二次光刻掩模，对所述半导体层和所述保护层进行曝光、显影和刻蚀，刻蚀掉除与所述沟道、所述源极和所述漏极接触以外的所述半导体层和所述保护层；
    沉积绝缘层；
    第三次光刻掩模，对所述绝缘层进行曝光、显影和刻蚀，使所述绝缘层形成位于所述保护层及所述源极与漏极上的栅极绝缘部以及连通至所述漏极的通孔；
    沉积第二导电层；
    第四次光刻掩模，对所述第二导电层进行曝光、显影和刻蚀，使所述第二导电层形成间隔设置的栅极部和像素电极，所述栅极部与所述半导体层相对应，所述像素电极通过所述通孔与所述漏极相连接。
  14. 如权利要求13所述的阵列基板的制造方法，其特征在于，在沉积第一导电层的步骤之前，还包括：在所述衬底表面沉积一缓冲层的步骤；在沉积第一导电层的步骤中，所述第一导电层沉积在所述缓冲层上。
  15. 如权利要求14所述的阵列基板的制造方法，其特征在于，所述缓冲层由单层缓冲层材料构成、由多层缓冲层材料层叠设置而构成或者由多层缓冲层材料交错设置而构成。
  16. 如权利要求13所述的阵列基板的制造方法，其特征在于，在第一次光刻掩模的步骤之前，还包括在第一导电层上沉积欧姆接触层；在第一次光刻掩模的步骤中，对所述第一导电层和欧姆接触层同时进行曝光、显影和刻蚀。
  17. 如权利要求13所述的阵列基板的制造方法，其特征在于，所述半导体层由非晶硅半导体材料或者金属氧化物半导体材料制成。
  18. 如权利要求13所述的阵列基板的制造方法，其特征在于，所述第二导电层为透明导电材料或者金属材料。
  19. 如权利要求13所述的阵列基板的制造方法，其特征在于，所述第二导电层为透明导电金属氧化物。
  20. 如权利要求13所述的阵列基板的制造方法，其特征在于，所述第二导电层为氧化铟、氧化锌、氧化铟锡、氧化铟锌、氧化锌铝或者氧化镓锌。
  21. 如权利要求13所述的阵列基板的制造方法，其特征在于，所述第二导电层为钼、铝、钛、铜、镍、钨、金、钯、铬、铌、锌、钴、锰、银或者具有上述任一元素的化合物。
  22. 如权利要求13所述的阵列基板的制造方法，其特征在于，在沉积绝缘层的步骤中，采用化学气相沉积、等离子体增强化学气相沉积法、原子层沉积或者溅射方式实现。
  23. 如权利要求13所述的阵列基板的制造方法，其特征在于，在第一次光刻掩模的步骤中，还包括使所述第一导电层形成数据信号线和控制信号线，所述数据信号线和所述控制信号线相交并且在相交处所述数据信号线和控制信号线之一断开以形成断开处；所述源极电性连接所述数据信号线。
  24. 如权利要求23所述的阵列基板的制造方法，其特征在于，在第二次光刻掩模的步骤中，还包括使所述半导体层和所述保护层覆盖在所述数据信号线或控制信号线穿过所述断开处的部分。
  25. 如权利要求23所述的阵列基板的制造方法，其特征在于，在第三次光刻掩模的步骤中，还包括使所述绝缘层包括覆盖所述数据信号线或控制信号线穿过上述断开处部分的信号线绝缘部。
  26. 如权利要求25所述的阵列基板的制造方法，其特征在于，在第四次光刻掩模的步骤中，还包括使所述第二导电层包括覆盖上述信号线绝缘部并电性连接断开的数据信号线或控制信号线的连接部。
  27. 如权利要求26所述的阵列基板的制造方法，其特征在于，在第四次光刻掩模的步骤中，还包括使所述栅极部电性连接所述数据信号线。
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