WO2021097733A1 - 一种薄膜晶体管及其制造方法与薄膜晶体管阵列 - Google Patents

一种薄膜晶体管及其制造方法与薄膜晶体管阵列 Download PDF

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WO2021097733A1
WO2021097733A1 PCT/CN2019/119807 CN2019119807W WO2021097733A1 WO 2021097733 A1 WO2021097733 A1 WO 2021097733A1 CN 2019119807 W CN2019119807 W CN 2019119807W WO 2021097733 A1 WO2021097733 A1 WO 2021097733A1
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layer
electrode layer
metal
thin film
film transistor
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PCT/CN2019/119807
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English (en)
French (fr)
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李刘中
伍凯义
林子平
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重庆康佳光电技术研究院有限公司
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Priority to CN201980002786.1A priority Critical patent/CN110998811B/zh
Priority to PCT/CN2019/119807 priority patent/WO2021097733A1/zh
Priority to US17/057,919 priority patent/US20210305286A1/en
Publication of WO2021097733A1 publication Critical patent/WO2021097733A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

Definitions

  • the invention belongs to the technical field of semiconductor optoelectronics, and particularly relates to a thin film transistor, a manufacturing method thereof, and a thin film transistor array.
  • LCD liquid crystal display
  • OLED organic electroluminescence display
  • Mini-LED inorganic electroluminescence display
  • TFT thin film transistor
  • the TFT includes a semiconductor layer, which has source/drain regions doped with high-concentration dopants and a channel region formed between the source/drain regions, and is arranged on a gate corresponding to the channel region and insulated from the semiconductor layer, And the source/drain in contact with each source/drain region.
  • Metal oxide semiconductor materials are often used as gate channel materials in existing TFTs. Metal oxide semiconductor materials include In-Ga oxide, In-Zn oxide, or In-M-Zn oxide (M can be Al, Ga, Y, La, Ce, Sn, etc.), an amorphous metal oxide semiconductor (In-Ga-Zn-O, abbreviated as IGZO) composed of indium, gallium, zinc, and oxygen is generally used.
  • a source-drain electrode is further formed on the metal oxide semiconductor of IGZO. When the source-drain electrode is etched, the etchant will damage the oxide semiconductor of IGZO, thereby affecting the performance of the entire TFT.
  • the purpose of the present invention is to provide a thin film transistor, a manufacturing method thereof, and a thin film transistor array, which overcomes the problem of etching agents when multiple source-drain electrodes are etched in the prior art. Defects that will destroy the metal oxide semiconductor of IGZO, thereby affecting the performance of the entire TFT.
  • the first embodiment disclosed in the present invention is a manufacturing method of a thin film transistor, wherein the manufacturing method includes:
  • the etching protection layer is etched to expose the metal oxide semiconductor layer.
  • the step of etching the metal electrode layer to form a source electrode layer and a drain electrode layer specifically includes:
  • the metal electrode layer is etched, and the pattern of the photoresist layer is transferred to the metal electrode layer to form a source electrode layer and a drain electrode layer.
  • the step of forming a photoresist material layer on the metal electrode layer and patterning the photoresist material layer to form a photoresist layer specifically includes:
  • Exposing and developing the photoresist material layer removing the photoresist material layer on the metal electrode layer in contact with the etching protection layer to form a photoresist layer.
  • the method further includes:
  • An ITO layer is formed on the source electrode layer, the drain electrode layer and the gate electrode channel.
  • the method further includes:
  • the ITO layer is etched, and the pattern of the photoresist layer is transferred to the ITO layer.
  • the method further includes:
  • a protective layer is formed on the source electrode layer, the drain electrode layer, and the gate electrode channel.
  • the etching protection layer is a titanium metal layer; and the etching protection layer has a thickness of
  • the metal electrode layer is a double-layer metal layer of an aluminum metal layer and a molybdenum metal layer; the thickness of the aluminum metal layer is The thickness of the molybdenum metal layer is
  • the second embodiment disclosed in the present invention is a thin film transistor, which includes:
  • An etching protection layer located on the metal oxide semiconductor layer
  • a source electrode layer and a drain electrode layer located on the gate insulating layer and separated from each other and arranged at both ends of the etching protection layer.
  • the etching protection layer is located on the surface of the metal oxide semiconductor layer away from the gate electrode layer, and the etching protection layer completely covers the metal oxide before being etched.
  • Semiconductor layer In the thin film transistor, the etching protection layer is located on the surface of the metal oxide semiconductor layer away from the gate electrode layer, and the etching protection layer completely covers the metal oxide before being etched. Semiconductor layer.
  • the thin film transistor further includes an ITO layer on the drain electrode layer and the gate insulating layer.
  • the thin film transistor further includes a protective layer on the source electrode layer, the drain electrode layer, the metal oxide semiconductor layer, and the ITO layer.
  • the thickness of the protective layer is 2 to 4 ⁇ m.
  • the third embodiment disclosed in the present invention is a thin film transistor array, which at least includes the above-mentioned thin film transistors.
  • the thin film transistor array which further includes a storage capacitor, a metal overlap region, and a substrate contact hole.
  • the present invention provides a thin film transistor, a manufacturing method thereof, and a thin film transistor array.
  • an etching protection layer on the metal oxide semiconductor layer, the metal electrode layer and the ITO layer are etched and protected by etching.
  • the layer protects the metal oxide semiconductor layer, so as to prevent the metal oxide semiconductor layer from being etched by the etching solution and affect the performance of the thin film transistor.
  • FIG. 1 is a flowchart of a preferred embodiment of a method for manufacturing a thin film transistor provided by the present invention
  • FIG. 2 is a schematic diagram of the manufacturing process of a method for manufacturing a thin film transistor provided by the present invention
  • FIG. 3 is a schematic diagram of the structure of a thin film transistor provided by the present invention.
  • FIG. 4 is a schematic diagram of the structure of the thin film transistor array provided by the present invention.
  • FIG. 5 is a schematic diagram of the manufacturing process of the thin film transistor array provided by the present invention.
  • the metal oxide semiconductor layer will be damaged by the etchant, thereby affecting the performance of the entire TFT.
  • a method for manufacturing a thin film transistor is provided in the first embodiment of the present invention.
  • FIG. 1 is a flowchart of a preferred embodiment of a method for manufacturing a thin film transistor provided by the present invention
  • FIG. 2 is a schematic diagram of a manufacturing process of a method for manufacturing a thin film transistor provided by the present invention.
  • the manufacturing method of the thin film transistor includes the following steps:
  • a gate insulating layer 12 is formed on the gate electrode layer 11.
  • the gate electrode layer 11 of the TFT when manufacturing a TFT, it is first necessary to select a material as the gate electrode layer 11 of the TFT.
  • the material for the gate electrode layer 11 can be a metal material, such as copper, aluminum, tungsten, gold, silver, etc., and a conductive semiconductor material such as Doped polysilicon, etc.
  • a gate insulating layer 12 is formed on the gate electrode layer 11.
  • the material of the gate insulating layer 12 is mainly an inorganic material, for example, an oxide material such as silicon dioxide, or a nitride material such as nitride. Silicon etc.
  • the method for forming the gate insulating layer 12 on the gate electrode layer 11 can be formed by deposition or coating, such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or coater coating.
  • a gate insulating layer 12 is formed on the gate electrode layer 11 by using a plasma chemical vapor phase.
  • the manufacturing method of the thin film transistor further includes the following steps:
  • a metal oxide semiconductor layer 13 and an etching protection layer 14 are continuously deposited on the gate insulating layer 12.
  • the metal oxide semiconductor layer 13 and the etching protection layer 14 are continuously deposited on the gate insulating layer 12, wherein The etching protection layer 14 completely covers the metal oxide semiconductor layer 13 to protect the metal oxide semiconductor layer 13 from being etched away by an etchant when forming source and drain electrodes.
  • the metal oxide semiconductor layer 13 may be a metal oxide, such as In-Ga oxide, In-Zn oxide, In-M-Zn oxide, etc., where M is one of Al, Ga, Y, La, etc. Species, or compound semiconductors such as SiGe, GaAs, etc.
  • the metal oxide semiconductor layer 13 is an amorphous metal oxide semiconductor (In-Ga-Zn-O, referred to as IGZO) composed of indium, gallium, zinc, aluminum, tin, and oxygen.
  • IGZO amorphous metal oxide semiconductor
  • the wet etching method uses an etching solution such as nitric acid, a mixed acid of phosphoric acid and acetic acid, and oxalic acid.
  • the dry etching method For example, Cl 2 plasma etching will etch the metal oxide semiconductor layer 13.
  • an etching protection layer 14 is deposited on the metal oxide semiconductor layer 13 in this embodiment, and the etching protection layer 14 may not be etched. Any metal layer etched away by liquid, such as titanium, tungsten, molybdenum-tungsten alloy, etc.
  • the etching protection layer 14 is a titanium metal layer.
  • the main consideration is that when the titanium metal layer is used as a protection layer for etching the gate electrode channel, the metal oxide semiconductor layer 13 can be better protected and formed The gate electrode channel is easy to control.
  • the thinner the etching protection layer 14 for protecting the metal oxide semiconductor layer 13, the better, but too thin is not conducive to the protection of the metal oxide semiconductor layer 13 during the etching process, so the control in this embodiment
  • the thickness of the etching protection layer 14 is In a specific embodiment,
  • the manufacturing method of the thin film transistor further includes the following steps:
  • the gate insulating layer 12 and the etching protection layer 14 are further deposited on the gate insulating layer 12 and the etching protection layer 14.
  • a metal electrode layer 15 is formed thereon, wherein the metal electrode layer 15 completely covers the etching protection layer 14 and the gate insulating layer 12.
  • the metal electrode layer 15 is a two-layer metal layer, including a first metal layer 151 and a second metal layer 152.
  • the first metal layer 151 is an aluminum metal layer
  • the second metal layer 152 is The molybdenum metal layer, where the aluminum metal layer is used as the main circuit wire of the thin film transistor, it directly contacts the etching protection layer 14, and the resistance of aluminum is low, which is beneficial to the preparation of the thin film transistor and is pollution-free.
  • the thickness of the first metal layer 151 as the main circuit conductor is greater than the thickness of the second metal layer 152
  • the thickness of the first metal layer 151 is The thickness of the second metal layer 152 is
  • the methods for forming the metal electrode layer 15 on the etching protection layer 14 and the gate insulating layer 12 include deposition, coating, and sputtering. In a specific embodiment, the sputtering method is used for the etching protection A metal electrode layer 15 is formed on the layer 14 and the gate insulating layer 12.
  • the manufacturing method of the thin film transistor further includes the following steps:
  • the metal electrode layer 15 is formed on the gate insulating layer 12 and the etching protection layer 14, since the etching protection layer 14 protects the metal oxide semiconductor layer 13, it can be directly etched The metal electrode layer 15 is etched by liquid, and only the metal electrode layer 15 in contact with the metal oxide semiconductor layer 13 or the etching protection layer 14 needs to be etched away, and the metal electrode layers 15 at both ends are retained to form the source electrode layer 18 and drain electrode layer 19.
  • the etching methods include wet etching and dry etching.
  • the metal electrode layer 15 is etched by an etching solution, that is, the wet etching is used for etching.
  • the etching solution is a mixed acid solution of nitric acid, phosphoric acid, and acetic acid. Since titanium metal will not be etched away by the etching solution, the metal under the etching protection layer 14 can be well protected.
  • the metal electrode layer 15 is etched by the mixed solution to obtain the source electrode layer 18 and the drain electrode layer 19 with relatively good vertical width.
  • step S4 specifically includes:
  • the metal electrode layer is etched, and the pattern of the photoresist layer is transferred to the metal electrode layer to form a source electrode layer and a drain electrode layer.
  • a photoresist material layer is further formed on the metal electrode layer 15 and patterned
  • the photoresist material layer forms the photoresist layer 20, wherein the photoresist material layer is formed of a material that is not etched by the etchant.
  • the metal electrode layer 15 is etched. Since the etchant only etches the area without the photoresist layer 20, there is a photoresist layer. The area 20 is protected by the photoresist layer 20 and will not be etched away, so that the pattern of the photoresist layer 20 is transferred to the metal electrode layer 15 to form the source electrode layer 18 and the drain electrode layer 19.
  • step S41 further includes the steps:
  • S412 Expose and develop the photoresist material layer, and remove the photoresist material layer on the metal electrode layer in contact with the etching protection layer to form a photoresist layer.
  • a photoresist material layer is first formed on the metal electrode layer 15 by a coating method, and then a photoresist material layer is formed on the metal electrode layer 15 by a coating method, and then exposed through a mask using an exposure machine and then developed to remove the etch protection layer 14 in contact with the photoresist material layer.
  • the photoresist material layer on the metal electrode layer 15 forms the photoresist layer 20. That is, after the metal electrode layer 15 is patterned, there is no photoresist layer 20 on the metal electrode layer 15 in contact with the etching protection layer 14, but there is light at both ends of the etching protection layer 14.
  • the metal electrode layer 15 directly in contact with the etching protection layer 14 is directly etched because there is no protection of the photoresist layer 20
  • the metal electrode layer 15 at both ends of the etch protection layer 14 is not etched because it is protected by the photoresist layer 20, so that a source electrode layer 18 and a leakage current are formed at both ends of the etch protection layer 14. ⁇ 19.
  • the thickness of the photoresist layer 20 is 1.5-2 ⁇ m.
  • the method further includes the following steps:
  • the thin film transistor needs to be connected with other components to drive the liquid crystal pixels in cooperation, such as storage capacitors, pixel capacitors, and so on. Therefore, after the source electrode layer 18 and the drain electrode layer 19 are formed at both ends of the metal oxide semiconductor layer 13, an ITO layer 17 is further formed on the source electrode layer 18, the drain electrode layer 19 and the gate electrode channel. The thin film transistor and the storage capacitor are connected through the ITO layer 17.
  • the metal electrode layer 15 is etched to form the source electrode layer 18 and the drain electrode layer 19 before the photoresist layer 20 is coated on the metal electrode layer 15.
  • a photoresist stripping device is required to remove The photoresist layer 20 on the surface of the metal electrode layer 15. Then, an ITO layer 17 is formed on the source electrode layer 18, the drain electrode layer 19, and the gate electrode channel.
  • the method further includes the following steps:
  • an ITO layer 17 is formed on the source electrode layer 18, the drain electrode layer 19 and the gate electrode channel 20.
  • the unnecessary ITO layer 17 needs to be further etched away with an etchant.
  • the inventors etched the metal electrode layer 1 similarly to the previous steps. First, a photoresist material layer is formed on the ITO layer 17, and the photoresist material layer is exposed and then developed to pattern the photoresist material layer to form a photoresist layer. Then the ITO layer 17 is etched, the ITO layer 17 with the photoresist layer remains, but the ITO layer 17 without the protection of the photoresist layer is removed, so that the ITO layer 17 at the required position is retained.
  • the ITO layer 17 is etched by a wet etching method.
  • the etchant is oxalic acid, although oxalic acid can also etch the metal oxide semiconductor layer 13.
  • the etching protection layer 14 can be used in addition to etching the metal electrode layer 15. In terms of protection, the etching protection layer 14 at the time of etching the ITO layer 17 can also protect the metal semiconductor oxide layer 13.
  • the manufacturing method of the thin film transistor further includes the following steps:
  • the etching protection layer 14 is used to protect the metal oxide semiconductor layer 13 from being etched away. After the metal electrode layer 15 and the ITO layer 17 are etched, in order to prevent the source electrode layer 18 and the leakage current from being etched away. A gate electrode channel is formed between the electrode layers 19, and the etching protection layer 14 needs to be further removed to expose the metal oxide semiconductor layer 13.
  • the etching methods mentioned in the foregoing steps include wet etching and dry etching.
  • the etching protection layer 14 is removed by the dry etching method to expose the metal oxide semiconductor layer 13.
  • the etching protection layer 14 in the example not only needs to not be etched away by the etching solution, but also needs to be able to be etched away by the dry etching method.
  • the etching protection layer 14 is plasma-etched by BCl 3 /Cl 2 to expose the metal oxide semiconductor layer 13. The main reason is that BCl 3 /Cl 2 has good etching properties on the titanium metal layer, and does not etch the molybdenum metal layer and the aluminum metal layer on the source electrode layer 18 and the drain electrode layer 19.
  • BCl 3 /Cl 2 plasma can also etch the metal oxide semiconductor layer 13, since the etching protection layer 14 is completely covered by the metal oxide semiconductor layer 13, it is necessary to etch the etching protection layer.
  • the metal oxide semiconductor layer 13 can be etched only after 14, and the etching protection layer 14 can be controlled by controlling the etching time. After the etching is completed, the metal oxide semiconductor layer 13 is only etched Within, the thickness of the metal oxide semiconductor layer 13 mentioned earlier is Even if it is etched away The thickness of the metal oxide semiconductor layer still has
  • the manufacturing method of the thin film transistor further includes the following steps:
  • the source electrode layer 18, the drain electrode layer 19 and the gate electrode layer A protective layer 16 is formed on the channel.
  • the protective layer 16 can protect the source electrode layer 18, the drain electrode layer 19 and the gate electrode channel, and on the other hand can position the thin film transistor.
  • the material of the protective layer 16 is an organic material with a thickness of 2 to 4 ⁇ m.
  • the protective layer 16 can be formed by a photoresist coating, exposure, and development method.
  • the present invention also provides a thin film transistor, which is manufactured by the above-mentioned manufacturing method.
  • FIG. 3 it is a schematic diagram of the structure of the thin film transistor provided by the present invention.
  • the thin film transistor 1 includes a gate electrode layer 11, a gate insulating layer 12, a metal oxide semiconductor layer 13, an etching protection layer 14, and a source electrode layer 18. ,
  • the gate electrode layer 11 is completely covered by the gate insulating layer 12, the metal oxide semiconductor layer 13 is located on the surface of the gate insulating layer 12 away from the gate electrode layer 11, and the gate insulating layer 12 is on the gate electrode layer 11.
  • the orthographic projection falls on the gate electrode layer 11; the etching protection layer 14 is located on the surface of the metal oxide semiconductor layer 13 away from the gate electrode layer 11, and the etching protection layer 14 completely covers the metal oxide semiconductor layer 13 before being etched.
  • the metal oxide semiconductor layer 13, and its orthographic projection on the gate electrode layer 11 coincides with the orthographic projection of the metal oxide semiconductor layer 13 on the gate electrode layer 11; the source electrode layer 18 and the drain electrode layer 19 are located on the gate electrode.
  • the insulating layer 12 is far away from the surface of the gate electrode layer 11, and is located at both ends of the metal oxide semiconductor layer 13 and the etching protection layer 14 respectively; between the source electrode layer 18 and the drain electrode layer 19, the metal electrode is etched
  • the layer 15 forms a gate electrode channel; an ITO layer 17 is also formed on the thin film transistor 1, and the ITO layer 17 is used to connect to the storage capacitor 2.
  • the gate voltage when a voltage is applied to the gate electrode layer 11, the gate voltage generates an electric field in the gate insulating layer 12.
  • the line of force is directed from the gate electrode layer 11 to the surface of the metal oxide semiconductor layer 13, and charges are generated on the surface.
  • the metal oxide semiconductor layer 13 changes from a depletion layer to an electron accumulation layer, forming an inversion layer.
  • the source electrode layer 18 and the drain electrode layer 19 Carriers pass through the gate channel, and the source-drain voltage is further increased to turn on the power supply, thereby driving the pixels in the liquid crystal display device.
  • the present invention also provides a thin film transistor array.
  • the structure diagram of the thin film transistor array is shown in FIG. 4, and the present invention also provides a manufacturing process diagram of the thin film transistor array as shown in FIG. 5. Show.
  • the thin film transistor array shown also includes a storage capacitor 2, a metal overlap region 3, and a substrate contact hole 4.
  • the structure of the thin film transistor 1 is the same as the structure of the thin film transistor described above, and the specific structure is as described above.
  • the storage capacitor 2 is composed of a second gate insulating layer 21, a gate insulating layer 12, a metal electrode layer 15, an ITO layer 17 and a protective layer 16.
  • the gate insulating layer 12 completely covers the second gate insulating layer 21; the surface of the gate insulating layer 12 away from the second gate insulating layer 21 is provided with a metal electrode layer 15;
  • An ITO layer 17 is provided on the surface of the metal electrode layer 15 away from the gate insulating layer 12, and the ITO layer 17 is used to connect with the thin film transistor 1; on the ITO layer 17 away from the metal electrode layer 15
  • a protective layer 16 is also provided on the surface of, and the protective layer 16 is used to protect and position the storage capacitor 2.
  • the manufacturing method of the storage capacitor 2 shown corresponds to the manufacturing method of the aforementioned thin film transistor 1.
  • the gate insulating layer 12 is formed on the gate electrode layer 11 while the gate insulating layer 12 is formed on the second gate insulating layer 21, and then the A metal electrode layer 15 is formed on the gate insulating layer 12, and the metal electrode layer 15 is patterned so that the metal electrode layer 15 in contact with the gate insulating layer 12 on the second gate insulating layer 21 is photo-resisted.
  • the layer 20 is protected and retained; then an ITO layer 17 is formed on the metal electrode layer 15, and the ITO layer 17 is patterned so that the ITO layer 17 connected to the thin film transistor 1 on the storage capacitor 2 is retained, and is placed on the ITO layer 17.
  • the protective layer 16 is deposited on the metal electrode layer 15 and the storage capacitor 2 is formed.
  • the substrate contact hole 4 is composed of a fourth gate insulating layer 41, a gate insulating layer 12 and an ITO layer 17.
  • the gate insulating layer 12 is disposed on the fourth gate insulating layer 41, and the gate insulating layer 12 in contact with the fourth gate insulating layer 41 is etched to expose the fourth gate insulating layer 41.
  • the ITO layer 17 is disposed on the fourth gate insulating layer 41 and the gate insulating layer 12.
  • the manufacturing process of the substrate contact hole 4 corresponds to the manufacturing method of the aforementioned thin film transistor 1.
  • the gate insulating layer 12 on the fourth gate insulating layer 41 is further etched to expose the first Four-gate insulating layer 41; then an ITO layer 17 is deposited on the fourth gate insulating layer 41 and the gate insulating layer 12 for connection with the storage capacitor 2, thereby forming a substrate contact hole 4.
  • the present invention provides a thin film transistor, a manufacturing method thereof, and a thin film transistor array.
  • the manufacturing method includes: forming a gate insulating layer on a gate electrode layer; and continuously depositing metal on the gate insulating layer.
  • An oxide semiconductor layer and an etching protection layer forming a metal electrode layer on the gate insulating layer and the etching protection layer; etching the metal electrode layer to form a source electrode layer and a drain electrode layer;
  • the etching protection layer is etched to expose the metal oxide semiconductor layer.
  • an etching protection layer is formed on the metal oxide semiconductor layer.
  • the metal oxide semiconductor layer is protected by the etching protection layer, thereby preventing the metal oxide semiconductor layer from being etched.
  • Liquid etching affects the performance of the thin film transistor, and there is no need to add a protective layer when protecting the metal oxide semiconductor layer, and the manufacturing method is simple and low in cost.

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Abstract

一种薄膜晶体管及其制造方法与薄膜晶体管阵列，所述制造方法包括：在栅电极层（11）上形成栅极绝缘层（12）；在所述栅极绝缘层（12）上连续沉积金属氧化物半导体层（13）和刻蚀保护层（14）；在所述栅极绝缘层（12）和所述刻蚀保护层（14）上形成金属电极层（15）；对所述金属电极层（15）进行刻蚀形成源电极层（18）和漏电极层（19）；对所述刻蚀保护层（14）进行刻蚀露出所述金属氧化物半导体层（13）。通过在金属氧化物半导体层（13）上形成一层刻蚀保护层（14），刻蚀金属电极层（15）和ITO层（17）时，通过刻蚀保护层（14）保护金属氧化物半导体层（13），从而避免金属氧化物半导体层（13）被刻蚀液刻蚀影响薄膜晶体管的性能，在保护金属氧化物半导体层（13）时无需另外增加保护层，制造方法简单、成本低。

Description

一种薄膜晶体管及其制造方法与薄膜晶体管阵列 技术领域
本发明属于半导体光电子技术领域，尤其涉及一种薄膜晶体管及其制造方法与薄膜晶体管阵列。
背景技术
随着显示科技的发展，各种显示设备如液晶显示(LCD)设备、有机电致发光显示(OLED)设备、或无机电致发光显示(Mini-LED,Micro-LED)设备已经得到广泛应用。而液晶显示(LCD)设备中的每个液晶像素点都由集成在像素点后面的薄膜晶体管(TFT)来驱动，从而可以做到高速度、高亮度、高对比度显示屏信息，是目前最好的彩色显示设备之一。
TFT包括半导体层，它具有掺有高浓度掺杂物的源/漏区及在源/漏区之间形成的沟道区，布置在对应于沟道区上并与半导体层绝缘的栅极，以及与每个源/漏区接触的源/漏极。现有TFT中常常使用金属氧化物半导体材料作为栅极沟道材料，金属氧化物半导体材料包括In-Ga氧化物、In-Zn氧化物、或者In-M-Zn氧化物(M可以是Al、Ga、Y、La、Ce、Sn等)，通常使用由铟、镓、锌和氧构成的非晶金属氧化物半导体(In-Ga-Zn-O，简称IGZO)。IGZO的金属氧化物半导体上会进一步形成源-漏电极，在对源-漏电极进行刻蚀时，由于刻蚀剂会破坏IGZO的氧化物半导体，从而影响整个TFT性能。
因此，现有技术有待于进一步的改进。
发明内容
鉴于上述现有技术中的不足之处，本发明的目的在于提供一种薄膜晶体管及其制造方法与薄膜晶体管阵列，克服现有技术中在多源-漏电极进行刻蚀时，由于刻蚀剂会破坏IGZO的金属氧化物半导体，从而影响整个TFT性能的缺陷。
本发明所公开的第一实施例为一种薄膜晶体管的制造方法，其中，所述制造方法包括：
在栅电极层上形成栅极绝缘层；
在所述栅极绝缘层上连续沉积金属氧化物半导体层和刻蚀保护层；
在所述栅极绝缘层和所述刻蚀保护层上形成金属电极层；
对所述金属电极层进行刻蚀形成源电极层和漏电极层；
对所述刻蚀保护层进行刻蚀露出所述金属氧化物半导体层。
所述的薄膜晶体管的制造方法，其中，所述对所述金属电极层进行刻蚀形成源电极层和漏电极层的步骤具体包括：
在所述金属电极层上形成光阻材料层，并图案化所述光阻材料层形成光阻层；
刻蚀所述金属电极层，将所述光阻层的图案转移至所述金属电极层上形成源电极层和漏电极层。
所述的薄膜晶体管的制造方法，其中，所述在所述金属电极层上形成光阻材料层，并图案化所述光阻材料层形成光阻层的步骤具体包括：
在所述金属电极层上形成光阻材料层；
对所述光阻材料层进行曝光再显影，去除与所述刻蚀保护层接触的所述金属电极层上的光阻材料层形成光阻层。
所述的薄膜晶体管的制造方法，其中，所述对所述金属电极层进行刻蚀形成源电极层和漏电极层的步骤之后还包括：
去除所述金属电极层表面的光阻层；
在所述源电极层、所述漏电极层以及所述栅电极沟道上形成ITO层。
所述的薄膜晶体管的制造方法，其中，所述在所述源电极层、所述漏电极层以及所述栅电极沟道上形成ITO层的步骤之后还包括：
在所述ITO层上形成光阻材料层，并图案化所述光阻材料层形成光阻层；
刻蚀所述ITO层，将所述光阻层的图案转移至所述ITO层。
所述的薄膜晶体管的制造方法，其中，所述对所述刻蚀保护层进行刻蚀露出所述金属氧化物半导体层的步骤之后还包括：
在所述源电极层、所述漏电极层以及所述栅电极沟道上形成保护层。
所述的薄膜晶体管的制造方法，其中，所述刻蚀保护层为钛金属层；所述刻蚀保护层厚度为
Figure PCTCN2019119807-appb-000001
所述的薄膜晶体管的制造方法，其中，所述金属电极层为铝金属层和钼金属层的双层金属层；所述铝金属层厚度为
Figure PCTCN2019119807-appb-000002
所述钼金属层厚度为
Figure PCTCN2019119807-appb-000003
本发明所公开的第二实施例为一种薄膜晶体管，其中，包括：
栅电极层；
位于所述删电极层上的栅极绝缘层；
位于所述栅极绝缘层上的金属氧化物半导体层；
位于所述金属氧化物半导体层上的刻蚀保护层；
位于所述栅极绝缘层上并彼此分隔设置在所述刻蚀保护层两端的源电极层和漏电极层。
所述的薄膜晶体管，其中，所述刻蚀保护层位于所述金属氧化物半导体层远离所述栅电极层的表面上，所述刻蚀保护层未被刻蚀前完全覆盖所述金属氧化物半导体层。
所述的薄膜晶体管，其中，还包括位于所述漏电极层和所述栅极绝缘层上的ITO层。
所述的薄膜晶体管，其中，还包括位于所述源电极层、漏电极层、金属氧化物半导体层以及所述ITO层上的保护层。
所述的薄膜晶体管，其中，所述保护层为有机材料；所述保护层的厚度为2～4μm。
本发明所公开的第三实施例为一种薄膜晶体管阵列，其中，至少包括上述所述的薄膜晶体管。
所述的薄膜晶体管阵列，其中，还包括存储电容、金属交迭区以及衬底接触孔。
有益效果，本发明提供了一种薄膜晶体管及其制造方法与薄膜晶体管阵列，通过在金属氧化物半导体层上形成一层刻蚀保护层，刻蚀金属电极层和ITO层时，通过刻蚀保护层保护金属氧化物半导体层，从而避免金属氧化物半导体层被刻蚀液刻蚀影响薄膜晶体管的性能，在保护金属氧化物半导体层时无需另外增加保护层，制造方法简单、成本低。
附图说明
图1是本发明提供的一种薄膜晶体管的制造方法的较佳实施例的流程图；
图2是本发明提供的一种薄膜晶体管的制造方法的制程示意图；
图3是本发明所提供的薄膜晶体管的结构示意图；
图4是本发明所提供的薄膜晶体管阵列的结构示意图；
图5是本发明所提供的薄膜晶体管阵列的制程示意图。
具体实施方式
为使本发明的目的、技术方案及优点更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并 不用于限定本发明。
由于现有技术中刻蚀源电极层和漏电极层时，由于刻蚀剂会破坏金属氧化物半导体层，从而影响整个TFT的性能。为了解决上述问题，本发明实施例一中提供了一种薄膜晶体管的制造方法。
请参照图1和图2，图1是本发明提供的一种薄膜晶体管的制造方法的较佳实施例的流程图；图2是本发明提供的一种薄膜晶体管的制造方法的制程示意图。结合图1和图2，在一具体实施例中，所述薄膜晶体管的制造方法包括以下步骤：
S1、在栅电极层11上形成栅极绝缘层12。
在一具体实施方式中，制造TFT时首先需要选择材料作为TFT的栅电极层11，作为栅电极层11的材料可以为金属材料,例如铜、铝、钨、金、银等，导电半导体材料如掺杂的多晶硅等。然后在所述栅电极层11上形成一层栅极绝缘层12，作为所述栅极绝缘层12的材料主要为无机材料，例如氧化物材料如二氧化硅等，或氮化物材料如氮化硅等。在所述栅电极层11上形成栅极绝缘层12的方法可以采用沉积或涂布的方式形成，如采用物理气相沉积(PVD)、化学气相沉积(CVD)或涂布机涂布。在一具体实施例中，采用等离子体化学气相在栅电极层11上形成一层栅极绝缘层12。
请继续参阅图1和图2，在一具体实施方式中，所述薄膜晶体管的制造方法还包括以下步骤：
S2、在所述栅极绝缘层12上连续沉积金属氧化物半导体层13和刻蚀保护层14。
在一具体实施方式中，在所述栅电极层11上形成栅极绝缘层12后，继续在所述栅极绝缘层12上连续沉积形成金属氧化物半导体层13和刻蚀保护层14，其中，所述刻蚀保护层14完全覆盖所述金属氧化物半导体层13，以保护所述金属氧化物半导体层13在形成源漏电极时不被刻蚀剂刻蚀掉。所述金属氧化物半导体层13可以为金属氧化物，如In-Ga氧化物、In-Zn氧化物、In-M-Zn氧化物等，其中M为Al、Ga、Y、La等中的一种，或者化合物半导体如SiGe、GaAs等。在一具体实施例中，所述金属氧化物半导体层13为由铟、镓、锌、铝、锡和氧构成的非晶金属氧化物半导体(In-Ga-Zn-O，简称IGZO)，所述IGZO膜厚度为
Figure PCTCN2019119807-appb-000004
在一具体实施方式中，由于金属氧化物半导体层13上需要通过刻蚀形成栅电极沟道，湿刻蚀法使用的刻蚀液如硝酸、磷酸和醋酸的混合酸、草酸，干刻蚀法如Cl 2等离子刻蚀等均会刻蚀金属氧化物半导体层13。为了使金属氧化物半导体层13在刻蚀时不被影响，本实施例中在金属氧化物半导体层13上沉积一层刻蚀保护层14，所述刻蚀保 护层14可以为不被刻蚀液刻蚀掉的任意金属层，如钛、钨、钼钨合金等。在一具体实施例中，所述刻蚀保护层14为钛金属层，主要是考虑钛金属层作为刻蚀栅电极沟道的保护层时可以较好的保护金属氧化物半导体层13，并且形成的栅电极沟道易于控制。此外，一般来说用于保护金属氧化物半导体层13的刻蚀保护层14越薄越好，但是太薄在刻蚀过程中不利于金属氧化物半导体层13的保护，因此本实施例中控制刻蚀保护层14的厚度为
Figure PCTCN2019119807-appb-000005
在一具体实施例中为
Figure PCTCN2019119807-appb-000006
请继续参阅图1和图2，在一具体实施方式中，所述薄膜晶体管的制造方法还包括以下步骤：
S3、在所述栅极绝缘层12和所述刻蚀保护层14上形成金属电极层15。
在一具体实施方式中，本实施例在栅极绝缘层12上依次沉积金属氧化物半导体层13和刻蚀保护层14后，进一步在所述栅极绝缘层12和所述刻蚀保护层14上形成金属电极层15，其中所述金属电极层15完全覆盖所述刻蚀保护层14和所述栅极绝缘层12。所述金属电极层15为两层金属层，包括第一金属层151和第二金属层152，在一具体实施例中，所述第一金属层151为铝金属层，第二金属层152为钼金属层，其中，铝金属层作为薄膜晶体管的主要线路导线，其直接与刻蚀保护层14接触，且铝的阻值低，有利于薄膜晶体管的制备并且无污染。进一步地，作为主要线路导线的第一金属层151厚度大于第二金属层152的厚度，所述第一金属层151厚度为
Figure PCTCN2019119807-appb-000007
第二金属层152厚度为
Figure PCTCN2019119807-appb-000008
在所述刻蚀保护层14和栅极绝缘层12上形成金属电极层15的方法包括沉积法、涂布法和溅射法等，在一具体实施例中，采用溅射法在刻蚀保护层14和栅极绝缘层12上形成金属电极层15。
请继续参阅图1和图2，在一具体实施方式中，所述薄膜晶体管的制造方法还包括以下步骤：
S4、对所述金属电极层15进行刻蚀形成源电极层18和漏电极层19。
在一具体实施方式中，在栅极绝缘层12和刻蚀保护层14上形成金属电极层15后，由于有刻蚀保护层14对金属氧化物半导体层13进行保护，因此可以直接通过刻蚀液刻蚀所述金属电极层15，刻蚀时只需要刻蚀掉与金属氧化物半导体层13即刻蚀保护层14接触的金属电极层15，而保留两端的金属电极层15以形成源电极层18和漏电极层19。
具体实施时，刻蚀方法包括湿刻蚀法和干刻蚀法，而本实施例中对金属电极层15通过刻蚀液进行刻蚀，即采用湿刻蚀法进行刻蚀。在一具体实施例中，所述刻蚀液为硝酸、磷酸及醋酸的混合酸溶液，由于钛金属不会被刻蚀液刻蚀掉，因此可以很好的保护 刻蚀保护层14下面的金属氧化物半导体层13，通过该混合溶液对金属电极层15进行刻蚀可以得到纵宽比较好的源电极层18和漏电极层19。
在一具体实施方式中，所述步骤S4具体包括：
S41、在所述金属电极层上形成光阻材料层，并图案化所述光阻材料层形成光阻层；
S42、刻蚀所述金属电极层，将所述光阻层的图案转移至所述金属电极层上形成源电极层和漏电极层。
在一具体实施方式中，本实施例在栅极绝缘层12和所述刻蚀保护层14上形成金属电极层15后，进一步在所述金属电极层15上形成光阻材料层，并图案化所述光阻材料层形成光阻层20，其中，所述光阻材料层由不被所述刻蚀剂刻蚀的材料形成。对所述光阻材料层进行图案化处理形成光阻层20后，刻蚀所述金属电极层15，由于刻蚀剂只会对没有光阻层20的区域进行刻蚀，而有光阻层20的区域由于受到光阻层20保护而不会被刻蚀掉，从而将光阻层20的图案转移至所述金属电极层15上，进而形成源电极层18和漏电极层19。
在一具体实施方式中，所述步骤S41进一步包括步骤：
S411、在所述金属电极层上形成光阻材料层；
S412、对所述光阻材料层进行曝光再显影，去除与所述刻蚀保护层接触的所述金属电极层上的光阻材料层形成光阻层。
在一具体实施方式中，首先利用涂布法在所述金属电极层15上形成光阻材料层，然后利用曝光机通过掩膜曝光再显影，去除与所述刻蚀保护层14接触的所述金属电极层15上的光阻材料层形成光阻层20。即对所述金属电极层15进行图案化处理后，与所述刻蚀保护层14接触的所述金属电极层15上没有光阻层20，而在所述刻蚀保护层14两端有光阻层20的保护，在后续步骤中对所述金属电极层15进行刻蚀时，与所述刻蚀保护层14直接接触的金属电极层15上由于没有光阻层20的保护而直接被刻蚀掉，而在所述刻蚀保护层14两端的金属电极层15由于被所述光阻层20保护没有被刻蚀，从而在所述刻蚀保护层14两端形成源电极层18和漏电极层19。在一具体实施例中，所述光阻层20厚度为1.5～2μm。
在一具体实施方式中，所述步骤S412之后还包括步骤：
S413、去除所述金属电极层15表面的光阻层；
S414、在所述源电极层18、所述漏电极层19以及所述栅电极沟道上形成ITO层17。
具体实施时，由于薄膜晶体管需要与其它部件连接以协同驱动液晶像素，如存储电 容、像素电容等。因此在金属氧化物半导体层13两端形成源电极层18和漏电极层19后，还进一步在所述源电极层18、所述漏电极层19以及所述栅电极沟道上形成ITO层17，通过ITO层17连接薄膜晶体管与存储电容。前述步骤中提到刻蚀金属电极层15形成源电极层18和漏电极层19前在金属电极层15上涂覆光阻层20，因此在形成ITO层17之前，需要利用光阻剥离设备去除金属电极层15表面的光阻层20。然后在源电极层18、漏电极层19以及栅电极沟道上形ITO层17。
在一具体实施方式中，所述步骤S414之后还包括步骤：
S415、在所述ITO层17上形成光阻材料层，并图案化所述光阻材料层形成光阻层20；
S416、刻蚀所述ITO层17，将所述光阻层20的图案转移至所述ITO层17。
在一具体实施方式中，为了避免源电极层18、漏电极层19与栅电极沟道之间发生短路现象，在源电极层18、漏电极层19和栅电极沟道20上形成ITO层17后，需要进一步通过刻蚀剂将不必要的ITO层17刻蚀掉。为了去除不必要的ITO层17，发明人通过与前述步骤对金属电极层1进行刻蚀的步骤类似。首先在ITO层17上形成光阻材料层，并对所述光阻材料层进行曝光再显影以图案化所述光阻材料层形成光阻层。然后刻蚀所述ITO层17，有光阻层的ITO层17仍然保留，而没有光阻层保护的ITO层17则被去除，从而将需要位置的ITO层17保留下来。
在一具体实施方式中，采用湿刻蚀法对所述ITO层17进行刻蚀，在一具体实施例中，所述刻蚀剂为草酸，虽然草酸也可以刻蚀金属氧化物半导体层13，但由于此时金属氧化物半导体层13仍然被刻蚀保护层14完全覆盖，而草酸不能对刻蚀保护层14进行刻蚀，因此刻蚀保护层14除了能够在刻蚀金属电极层15时起到保护作用，在刻蚀ITO层17时刻蚀保护层14也同样可以对所述金属半导体氧化层13起到保护作用。
请继续参阅图1和图2，在一具体实施方式中，所述薄膜晶体管的制造方法还包括以下步骤：
S5、对所述刻蚀保护层14进行刻蚀露出所述金属氧化物半导体层13。
在一具体实施方式中，刻蚀保护层14是用于保护金属氧化物半导体层13不被刻蚀掉，在对金属电极层15和ITO层17刻蚀结束后为了在源电极层18和漏电极层19之间形成栅电极沟道，需要进一步将所述刻蚀保护层14去掉以露出金属氧化物半导体层13。
具体实施时，前述步骤中提到刻蚀方法包括湿刻蚀法和干刻蚀法，本实施例中通 过干刻蚀法去除刻蚀保护层14以露出金属氧化物半导体层13，因此本实施例中的刻蚀保护层14除了需要满足不被刻蚀液刻蚀掉外，还需要满足能够被干刻蚀法刻蚀掉。在一具体实施例中，通过BCl 3/Cl 2对所述刻蚀保护层14进行等离子刻蚀露出所述金属氧化物半导体层13。主要是因为BCl 3/Cl 2对钛金属层有很好的刻蚀性，而不会刻蚀源电极层18和漏电极层19上的钼金属层和铝金属层。在这个过程中，虽然BCl 3/Cl 2等离子也可以对金属氧化物半导体层13进行刻蚀，但由于刻蚀保护层14完全被金属氧化物半导体层13覆盖，需要刻蚀完刻蚀保护层14后才能刻蚀金属氧化物半导体层13，通过控制刻蚀时间可以控制刻蚀保护层14被刻蚀完成后，金属氧化物半导体层13仅被刻蚀
Figure PCTCN2019119807-appb-000009
以内，前面提到金属氧化物半导体层13的厚度为
Figure PCTCN2019119807-appb-000010
即使被刻蚀掉
Figure PCTCN2019119807-appb-000011
金属氧化物半导体层的厚度仍然有
Figure PCTCN2019119807-appb-000012
请继续参阅图1和图2，在一具体实施方式中，所述薄膜晶体管的制造方法还包括以下步骤：
S6、在所述源电极层18、所述漏电极层19以及所述栅电极沟道上形成保护层。
在一具体实施方式中，对所述刻蚀保护层14进行刻蚀露出所述金属氧化物半导体层13后，还需要在所述源电极层18、所述漏电极层19以及所述栅极沟道上形成保护层16，所述保护层16一方面可以保护源电极层18、漏电极层19以及栅电极沟道，另一方面可以对薄膜晶体管进行定位。所述保护层16的材料为有机材料，厚度为2～4μm，所述保护层16可以通过光刻胶涂布曝光显影方法形成。
在一具体实施方式中，本发明还提供一种薄膜晶体管，所述薄膜晶体管采用上述制造方法制造而成。如图3所示，为本发明提供的薄膜晶体管的结构示意图，其中薄膜晶体管1包括栅电极层11，栅极绝缘层12、金属氧化物半导体层13、刻蚀保护层14、源电极层18、漏电极层19、ITO层17以及保护层16。
其中，栅电极层11被栅极绝缘层12完全覆盖，金属氧化物半导体层13位于所述栅极绝缘层12远离栅电极层11的表面，且栅极绝缘层12在栅电极层11上的正投影落在栅电极层11上；刻蚀保护层14位于所述金属氧化物半导体层13远离栅电极层11的表面上，所述刻蚀保护层14在未被刻蚀前完全覆盖所述金属氧化物半导体层13，且其在栅电极层11上的正投影与金属氧化物半导体层13在栅电极层11上的正投影重合；源电极层18和漏电极层19位于所述栅极绝缘层12远离栅电极层11的表面，且其分别位于金属氧化物半导体层13和刻蚀保护层14两端；所述源电极层18与所述漏电极层19之间通过刻蚀金属电极层15形成栅电极沟道；所述薄膜晶体管1上还形成ITO层17， 所述ITO层17用于和存储电容2连接。实际应用过程中，当给栅电极层11施加电压时，栅压在栅极绝缘层12中产生电场，电力线由栅电极层11指向金属氧化物半导体层13表面，并在表面处产生电荷，随着栅电压增加，金属氧化物半导体层13由耗净层转变为电子积累层，形成反型层，当达到强反型时，源电极层18和漏电极层19间在电压的作用下会有载流子通过栅极沟道，源漏电压进一步增大达到开启电源，从而驱动液晶显示设备中的像素。
在一具体实施方式中，本发明还提供了一种薄膜晶体管阵列，所述薄膜晶体管阵列的结构示意图如图4所示，并且本发明还提供了所示薄膜晶体管阵列的制程示意图如图5所示。所示薄膜晶体管阵列除包括上述所述的薄膜晶体管1外，还包括存储电容2、金属交迭区3、衬底接触孔4。
其中，所述薄膜晶体管1的结构与上述所述薄膜晶体管结构相同，具体结构如上所述。所述存储电容2由第二栅极绝缘层21、栅极绝缘层12、金属电极层15、ITO层17以及保护层16组成。其中，所述栅极绝缘层12完全覆盖所述第二栅极绝缘层21；所述栅极绝缘层12上远离所述第二栅极绝缘层21的表面设置有金属电极层15；所述金属电极层15上远离所述栅极绝缘层12的表面上设置有ITO层17，所述ITO层17用于与所述薄膜晶体管1连接；所述ITO层17上远离所述金属电极层15的表面还设置有保护层16，所述保护层16用于保护和定位所述存储电容2。所示存储电容2的制造方法与前述薄膜晶体管1的制造方法对应，在栅电极层11上形成栅极绝缘层12的同时在第二栅极绝缘层21上形成栅极绝缘层12，然后在栅极绝缘层12上形成金属电极层15，对所述金属电极层15进行图案化处理使得与所述第二栅极绝缘层21上的栅极绝缘层12接触的金属电极层15被光阻层20保护而保留下来；然后在金属电极层15上形成ITO层17，对ITO层17进行图案化处理使得存储电容2上与薄膜晶体管1连接的ITO层17被保留下来，并在ITO层17和金属电极层15上沉积保护层16，从而形成存储电容2。
在一具体实施方式中，所述衬底接触孔4由第四栅极绝缘层41、栅极绝缘层12和ITO层17组成。其中，所述栅极绝缘层12设置在所述第四栅极绝缘层41上，并且与所述第四栅极绝缘层41接触的栅极绝缘层12被刻蚀露出第四栅极绝缘层41，所述ITO层17设置在所述第四栅极绝缘层41和栅极绝缘层12上。所述衬底接触孔4的制造过程与前述薄膜晶体管1的制造方法对应，在前述步骤S4之后，进一步对所述第四栅极绝缘层41上的栅极绝缘层12进行刻蚀以露出第四栅极绝缘层41；然后在第四栅极绝缘层41和栅极绝缘层12上沉积ITO层17，以用于与存储电容2连接，从而形成衬底接 触孔4。
综上所述，本发明提供了一种薄膜晶体管及其制造方法与薄膜晶体管阵列，所述制造方法包括：在栅电极层上形成栅极绝缘层；在所述栅极绝缘层上连续沉积金属氧化物半导体层和刻蚀保护层；在所述栅极绝缘层和所述刻蚀保护层上形成金属电极层；对所述金属电极层进行刻蚀形成源电极层和漏电极层；对所述刻蚀保护层进行刻蚀露出所述金属氧化物半导体层。本申请通过在金属氧化物半导体层上形成一层刻蚀保护层，刻蚀金属电极层和ITO层时，通过刻蚀保护层保护金属氧化物半导体层，从而避免金属氧化物半导体层被刻蚀液刻蚀影响薄膜晶体管的性能，在保护金属氧化物半导体层时无需另外增加保护层，制造方法简单、成本低。
应当理解的是，本发明的系统应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本发明所附权利要求的保护范围。

Claims (15)

  1. 一种薄膜晶体管的制造方法，其特征在于，所述制造方法包括步骤：
    在栅电极层上形成栅极绝缘层；
    在所述栅极绝缘层上连续沉积金属氧化物半导体层和刻蚀保护层；
    在所述栅极绝缘层和所述刻蚀保护层上形成金属电极层；
    对所述金属电极层进行刻蚀形成源电极层和漏电极层；
    对所述刻蚀保护层进行刻蚀露出所述金属氧化物半导体层。
  2. 根据权利要求1所述的薄膜晶体管的制造方法，其特征在于，所述对所述金属电极层进行刻蚀形成源电极层和漏电极层的步骤具体包括：
    在所述金属电极层上形成光阻材料层，并图案化所述光阻材料层形成光阻层；
    刻蚀所述金属电极层，将所述光阻层的图案转移至所述金属电极层上形成源电极层和漏电极层。
  3. 根据权利要求2所述的薄膜晶体管的制造方法，其特征在于，所述在所述金属电极层上形成光阻材料层，并图案化所述光阻材料层形成光阻层的步骤具体包括：
    在所述金属电极层上形成光阻材料层；
    对所述光阻材料层进行曝光再显影，去除与所述刻蚀保护层接触的所述金属电极层上的光阻材料层形成光阻层。
  4. 根据权利要求3所述的薄膜晶体管的制造方法，其特征在于，所述对所述金属电极层进行刻蚀形成源电极层和漏电极层的步骤之后还包括：
    去除所述金属电极层表面的光阻层；
    在所述源电极层、所述漏电极层以及所述栅电极沟道上形成ITO层。
  5. 根据权利要求4所述的薄膜晶体管的制造方法，其特征在于，所述在所述源电极层、所述漏电极层以及所述栅电极沟道上形成ITO层的步骤之后还包括：
    在所述ITO层上形成光阻材料层，并图案化所述光阻材料层形成光阻层；
    刻蚀所述ITO层，将所述光阻层的图案转移至所述ITO层。
  6. 根据权利要求1所述的薄膜晶体管的制造方法，其特征在于，所述对所述刻蚀保护层进行刻蚀露出所述金属氧化物半导体层的步骤之后还包括：
    在所述源电极层、所述漏电极层以及所述栅电极沟道上形成保护层。
  7. 根据权利要求6所述的薄膜晶体管的制造方法，其特征在于，所述刻蚀保护层为钛金属层；所述刻蚀保护层厚度为
    Figure PCTCN2019119807-appb-100001
  8. 根据权利要求6所述的薄膜晶体管的制造方法，其特征在于，所述金属电极层 为铝金属层和钼金属层的双层金属层；所述铝金属层厚度为
    Figure PCTCN2019119807-appb-100002
    所述钼金属层厚度为
    Figure PCTCN2019119807-appb-100003
  9. 一种薄膜晶体管，其特征在于，包括：
    栅电极层；
    位于所述删电极层上的栅极绝缘层；
    位于所述栅极绝缘层上的金属氧化物半导体层；
    位于所述金属氧化物半导体层上的刻蚀保护层；
    位于所述栅极绝缘层上并彼此分隔设置在所述刻蚀保护层两端的源电极层和漏电极层。
  10. 根据权利要求9所述的薄膜晶体管，其特征在于，所述刻蚀保护层位于所述金属氧化物半导体层远离所述栅电极层的表面上，所述刻蚀保护层未被刻蚀前完全覆盖所述金属氧化物半导体层。
  11. 根据权利要求9所述的薄膜晶体管，其特征在于，还包括位于所述漏电极层和所述栅极绝缘层上的ITO层。
  12. 根据权利要求11所述的薄膜晶体管，其特征在于，还包括位于所述源电极层、漏电极层、金属氧化物半导体层以及所述ITO层上的保护层。
  13. 根据权利要求12所述的薄膜晶体管，其特征在于，所述保护层为有机材料；所述保护层的厚度为2～4μm。
  14. 一种薄膜晶体管阵列，其特征在于，至少包括如权利要求9所述的薄膜晶体管。
  15. 根据权利要求14所述的薄膜晶体管阵列，其特征在于，还包括存储电容、金属交迭区以及衬底接触孔。
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