WO2019179151A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2019179151A1
WO2019179151A1 PCT/CN2018/116642 CN2018116642W WO2019179151A1 WO 2019179151 A1 WO2019179151 A1 WO 2019179151A1 CN 2018116642 W CN2018116642 W CN 2018116642W WO 2019179151 A1 WO2019179151 A1 WO 2019179151A1
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WIPO (PCT)
Prior art keywords
trace
layer
array substrate
sub
hole
Prior art date
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Ceased
Application number
PCT/CN2018/116642
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English (en)
French (fr)
Inventor
余朋飞
张嘉伟
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US16/252,731 priority Critical patent/US10901280B2/en
Publication of WO2019179151A1 publication Critical patent/WO2019179151A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/921—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application relates to the field of display, and in particular to array substrates and display panels.
  • anti-static traces are set on the display panel (also known as dummy traces or dummy M2 routing).
  • the antistatic wiring easily accumulates static electricity, the electrostatic breakdown of the array substrate film layer occurs, which in turn causes the display panel to display an abnormality.
  • the technical problem to be solved by the present application is to provide an array substrate and a display panel, which can prevent the display panel from displaying abnormality due to electrostatic breakdown of the antistatic traces.
  • a technical solution adopted in the present application is to provide an array substrate, wherein the display area of the array substrate includes at least one anti-static trace and a plurality of scan lines, and the anti-static trace is used to guide static electricity;
  • the electrostatic traces are staggered and insulated from the scan lines; wherein the antistatic traces include the connected first trace portion and the second trace portion, and the first trace portion and the second trace portion are in different layers;
  • the line portion is interlaced with the scan line, the second trace portion is located on both sides of the scan line, and/or the antistatic trace is located in the display area near the non-display area;
  • the display area includes the first function sequentially disposed on the substrate a layer, a second functional layer, a signal line layer and a second metal layer, wherein the second functional layer is used to form a thin film transistor; and includes a second trace portion, the second functional layer is provided with a first through hole, and the second trace portion is worn The first through hole is connected to the first wire portion.
  • another technical solution adopted by the present application is to provide an array substrate, the display area of the array substrate includes at least one anti-static trace and a plurality of scan lines, and the anti-static trace is used to guide static electricity.
  • the antistatic trace is staggered and insulated from the scan line; wherein the antistatic trace includes the connected first trace portion and the second trace portion, and the first trace portion and the second trace portion are at different layers.
  • another technical solution adopted by the present application is to provide a display panel including the above array substrate.
  • the utility model has the beneficial effects that the display area of the array substrate of the present application includes at least one anti-static trace and a plurality of scan lines, and the anti-static trace is used for guiding static electricity; the anti-static trace and the method are different from the prior art.
  • the scan lines are staggered and insulated; wherein the anti-static traces comprise connected first trace portions and second trace portions, the first trace portions and the second trace portions being in different layers.
  • the antistatic trace includes the connected first trace portion and the second trace portion, and the first trace portion and the second trace portion are in different layers, the charge accumulation of the antistatic trace can be reduced to avoid
  • the static electricity of the anti-static trace breaks through the film between the anti-static trace and the scan line, which prevents the anti-static trace from short-circuiting with the scan line, resulting in abnormal display.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present application.
  • Figure 2 is a schematic view showing the structure of the embodiment of Figure 1 taken along the A-A section or the B-B section;
  • Figure 3 is a schematic view showing the structure of another embodiment of Figure 1 taken along the A-A section or the B-B section;
  • FIG. 4 is a schematic structural view of an array substrate according to another embodiment of the present application.
  • Figure 5 is a schematic view showing the structure of the embodiment of Figure 4 taken along the line B-B;
  • FIG. 6 is a schematic structural view of a display panel according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • references to "an embodiment” herein mean that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the present application.
  • the appearances of the phrases in various places in the specification are not necessarily referring to the same embodiments, and are not exclusive or alternative embodiments that are mutually exclusive. Those skilled in the art will understand and implicitly understand that the embodiments described herein can be combined with other embodiments.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present application
  • FIG. 2 is a schematic structural view of the embodiment of FIG. 1 along an AA cross section or a BB cross section
  • FIG. 3 is another embodiment of FIG. Schematic diagram of the AA section or the BB section.
  • the array substrate 10 includes a display area 11 and a non-display area 12 surrounding the display area 11.
  • the display area 11 may include a plurality of scan lines 112, a plurality of data lines 113, and at least one antistatic trace 111.
  • the plurality of scan lines 112 and the plurality of data lines 113 are interdigitated to divide the display area 11 into a plurality of pixels.
  • the non-display area 12 may be provided with a scan line driving circuit 121 and a data line driving circuit 122.
  • the scanning line driving circuit 121 is respectively connected to the plurality of scanning lines 112 for supplying scanning signals to the plurality of scanning lines 112.
  • the data line driving circuit 122 Connected to a plurality of data lines 113 for providing data signals to the plurality of data lines 113.
  • the anti-static traces 111 are used to conduct static electricity, for example, to conduct static electricity generated by the non-display area 12, such as static electricity generated by circuits in the non-display area 12.
  • the anti-static traces 111 are interleaved and insulated from the scan lines 112.
  • the anti-static traces 111 and the scan lines are disposed in different layers to achieve the above-described staggered and insulated arrangement.
  • the antistatic trace 111 includes a connected first trace portion 1111 and a second trace portion 1112, wherein the first trace portion 1111 and the second trace portion 1112 are in different layers.
  • the anti-static trace 1111 is divided into two trace portions of different layers, that is, the anti-static trace 111 is disconnected by using a jumper, the charge accumulation of the anti-static trace can be reduced to avoid the anti-static trace.
  • the electrostatic breakdown of the film between the antistatic trace and the scan line eliminates the influence of the antenna effect, thereby preventing the antistatic trace from being short-circuited with the scan line and causing display abnormality.
  • first trace portion 1111 is interlaced with the scan line 112, and the second trace portion 1112 is located at two sides of the scan line 112, that is, the first trace portion 1111 is a portion of the antistatic trace 111 interlaced with the scan line.
  • the second trace portion 1112 is a portion of the antistatic trace 111 located on both sides of the scan line 112, and the second trace portion 1112 located at each side of the scan line 112 is connected by the first trace portion 1111. It can be understood that the first trace portion 1111 can be a portion where the anti-static trace 111 is interlaced with all the scan lines, as shown in FIG.
  • the first trace portion can also be an anti-static trace 111 and
  • the portion where the partial scanning lines are staggered, that is, the portion where the antistatic wiring 111 is interlaced with the remaining scanning lines is disposed in the same layer as the second wiring portion. Since the trace portion interleaved with the scan line is disposed on a layer different from the rest of the anti-static trace, it can ensure that even if the anti-static trace is electrostatically broken, the trace portion and the scan which are interlaced with the scan line are not caused. The line is shorted.
  • the first trace portion 1111 in this embodiment may be made of a light-transmitting conductive material or a light-tight conductive material.
  • the first trace portion 1111 may be indium tin oxide (ITO) or indium zinc oxide (IZO), one of aluminum-doped zinc oxide (AZO), fluorine-doped tin dioxide (FTO), phosphorus-doped tin dioxide (PTO), and a metal material.
  • the second trace portion 1112 may be an opaque conductive material, and may specifically be consistent with the material of the data line 113, the gate or the source.
  • first trace portion 1111 and the second trace portion 1112 are at different layers means that the positions of the first trace portion 1111 and the second trace portion 1112 with respect to the scan line 112 are different.
  • first trace portion 1111 may be located on the upper side of the scan line 112
  • second trace portion 1112 may be the lower side of the scan line 112
  • first trace portion 1111 may be located on the lower side of the scan line 112
  • the second trace portion 1112 may be located on the upper side of the scan line 112.
  • the first trace portion 1111 and the second trace portion 1112 may both be located on the upper side or the lower side of the scan line 112, except that the first trace portion The distance between the 1111 and the second trace and the scan line 112 is different.
  • the antistatic trace 111 is located at, but not limited to, a position in the display area 11 near the non-display area 12, that is, a position at the edge of the display area 11.
  • the antistatic traces 111 may be parallel to the data lines 113 and disposed on both sides of the data lines 113.
  • the antistatic traces 111 are two, and the two antistatic traces 111 are disposed outside the plurality of data lines 113 and disposed parallel to the data lines 113.
  • the anti-static traces 111 may also be one, three, or three, and the specific number may be determined according to actual conditions.
  • the anti-static traces 111 may be four, and each of the two anti-static traces 111 is disposed outside the plurality of data lines 113 and disposed parallel to the data line 113.
  • the antistatic trace 111 is too long, a large amount of static electricity is easily accumulated on the antistatic trace 111, and if the static electricity is large, the scan line 112 is broken.
  • the film layer between the anti-static traces 111 and the anti-static traces 111 is short-circuited between the scan lines 112 and the anti-static traces 111. , causing the display panel to display abnormally.
  • the antistatic trace 111 By setting the antistatic trace 111 to the connected first trace portion 1111 and the second trace portion 1112, the first trace portion 1111 and the second trace portion 1112 are connected, and the first trace portion 1111 and the second portion are connected.
  • the trace portion 1112 is located at different layers.
  • the antistatic trace 111 can be disconnected, so that the accumulation of electrostatic charges on the antistatic trace 111 is reduced, thereby preventing electrostatic breakdown of the antistatic trace.
  • the film between the trace and the scan line enhances the antistatic discharge of the antistatic trace 111 (Electro-Static) Discharge, ESD) capabilities.
  • the display area 11 includes a first functional layer, a second functional layer 14, a signal line layer, and a second metal layer sequentially disposed on the substrate, and the second functional layer 14 is used.
  • TFT Thin Film Transistor
  • the first functional layer includes the first trace portion 1111
  • the second metal layer includes the second trace portion 1112
  • the second functional layer 14 is provided with the first via hole 15 and the second trace portion 1112 is connected to the first wire portion 1111 through the first through hole 15.
  • the second functional layer 14 includes a buffer layer 141, a semiconductor layer 142, and a first insulating layer 143 which are disposed in a stacked manner; the signal line layer includes a first metal layer 144 and a second insulating layer 145 which are stacked, and the first metal layer 144 includes a scan line. 112 and the gate of the thin film transistor, the second metal layer further includes a data line 112, a source 161 of the thin film transistor, and a drain 162. It can be understood that in other embodiments, the first trace portion 1111 can also be disposed in the second functional layer, for example, disposed in the buffer layer, or disposed on the buffer layer and on the first trace portion 1111. An insulating layer is further disposed, and the semiconductor layer is disposed on the additional insulating layer.
  • the materials of the first insulating layer 143 and the second insulating layer 145 may each include a single layer of silicon nitride (SiNx), a single layer of silicon oxide (SiOx), and a stack of silicon oxide (SiOx) and silicon nitride (SiNx).
  • SiNx silicon nitride
  • SiOx silicon oxide
  • SiNx silicon nitride
  • the first functional layer is disposed on the substrate
  • the buffer layer 141 is disposed on the first functional layer
  • the semiconductor layer 142 is disposed on the buffer layer 141
  • the first insulating layer 143 is disposed on the semiconductor layer 142.
  • the first metal layer 144 is disposed on the first insulating layer 143
  • the second insulating layer 145 is disposed on the first metal layer 144 and the first insulating layer 143
  • the second metal layer is disposed on the second insulating layer 145.
  • the first insulating layer 143 may be disposed on the semiconductor layer 142 and on the buffer layer 141.
  • the second insulating layer 145 includes a first region 1451 disposed on the first insulating layer 143, the first region 1451 is provided with a second via 155, and the second trace portion 1112 passes through the second insulating layer.
  • the second through hole 155 of the 145 and the first through hole 15 of the second functional layer 14 are connected to the first wire portion 1111.
  • the first through hole 15 is disposed under the second through hole 155, that is, the first through hole 15 is disposed on a side of the second through hole 155 near the substrate, and the first through hole 15 and the second through hole 155 are coaxial and first.
  • the inner walls of the through hole 15 and the second through hole 155 are flush so that the second wire passes through the second through hole 155 and the first through hole 15 is connected to the first wire portion 1111, so that the second wire is in the There is no break point between the two through holes 155 and the first through hole 15, thereby reinforcing the strength of the second wire portion 1112.
  • the areas of the first through hole 15 and the second through hole 155 may gradually decrease along the buffer layer 141 to the substrate direction.
  • the first through hole 15 and the second through hole 155 The area may gradually increase or decrease along the buffer layer 141 to the substrate direction.
  • the area of the first through hole 15 and the second through hole 155 may be a polygon such as a triangle, a quadrangle or a pentagon or the like. This application does not limit this.
  • the first region 1451 and the first insulating layer 143 of the second insulating layer 145 are each provided with a third via hole 163, and the source electrode 161 and the drain electrode 162 are both connected to the semiconductor layer 142 through the third via hole 163.
  • the first insulating layer 143 includes a second sub-via 153 disposed on the buffer layer 141, the second sub-region 1431 is provided with a first sub-via 153, and the buffer layer 141 is provided with a second sub-via 152 corresponding to the first sub-via 153.
  • the first sub-via 153 and the second sub-via 152 form a first via 15 , wherein the aperture of the second via 155 is greater than or equal to the aperture of the first sub-via 153 , and the aperture of the first sub-via 153 is greater than Or equal to the aperture of the second sub-via 152.
  • the first insulating layer 143 is disposed on the semiconductor layer 142 and the buffer layer 141, that is, the second trace portion 1112 passes through the second via hole 155, the first sub-via 153, and the second sub-pass.
  • the hole 152 is in contact with the semiconductor layer 142, the semiconductor layer 142 and the second trace portion 1112 are prevented from interfering with each other, thereby reducing the static electricity guiding capability of the antistatic trace 111.
  • the inner walls of the second through hole 155, the first sub-through hole 153, and the second sub-through hole 152 are flush.
  • the first insulating layer 143 includes a second region 1431 disposed on the buffer layer 141, the second region 1431 is provided with a first sub-via 153, and the semiconductor layer 142 corresponds to the first sub-portion
  • the through hole 153 is provided with a second sub-via 152, and the buffer layer 141 is provided with a third sub-via 151 corresponding to the second sub-via 152.
  • the first sub-via 153, the second sub-via 152 and the third sub-via The first through hole 15 is formed, wherein the aperture of the second through hole 155 is greater than or equal to the aperture of the first sub-via 153, and the aperture of the first sub-via 153 is greater than or equal to the aperture of the second sub-via 152, and The aperture of the second sub-via 152 is greater than or equal to the aperture of the third sub-via 151.
  • the first insulating layer 143 is disposed on the semiconductor layer 142, that is, when the second trace portion 1112 sequentially passes through the second via 155, the first sub via 153, the second sub via 152, and the third sub via 151. Contact with the semiconductor layer 142.
  • the second wiring portion 1112 is in contact with the semiconductor layer 142. Therefore, in order to prevent mutual influence between the semiconductor layer 142 and the second wiring portion 1112, it is possible to avoid influence on other semiconductor layers 142, such as a semiconductor of a thin film transistor.
  • the layer 142 is insulated from the semiconductor layer 142 between the semiconductor layer 142 and the thin film transistor of the antistatic trace 111, thereby preventing the second trace portion 1112 from affecting the semiconductor layer 142 of the thin film transistor when conducting static electricity.
  • the inner walls of the second through hole 155, the first sub-through hole 153, the second sub-through hole 152, and the third sub-through hole 151 are flush.
  • the first functional layer may further include a light shielding portion 1113 corresponding to the thin film transistor, that is, corresponding to the position of the thin film transistor in the pixel region.
  • the light shielding portion 1113 and the first wiring portion 1111 can be formed by the same mask etching, that is, the light shielding portion 1113 and the first wiring portion 1111 can be formed by the same process, so that the manufacturing process of the array substrate 10 is simple. , thereby reducing production costs.
  • the light shielding portion 1113 and the first wiring portion 1111 may be formed by different processes, which is not limited herein.
  • the antistatic trace 111 can be grounded to conduct static electricity.
  • one end of the anti-static trace 111 is grounded through the transfer interface to conduct the internally generated charges.
  • the anti-static trace 111 can be connected to the common electrode of the display panel through the interface to achieve grounding together with the ground of the common electrode.
  • FIG. 4 is a schematic structural view of an array substrate according to another embodiment of the present application; and FIG. 5 is a schematic structural view of the embodiment of FIG. 4 along a B-B cross section.
  • the first trace portion 1111 is only interleaved with the two scan lines 112 of the edge
  • the second trace portion 1112 is interleaved with the plurality of scan lines 112 on the inner side, and is interleaved with the plurality of scan lines 112 on the inner side.
  • the second trace portion 1112 is disposed on the second insulating layer 145.
  • the first trace portion 1111 may also be interleaved with the plurality of scan lines 112, and the second trace portion 1112 may be interleaved with the additional plurality of scan lines 112.
  • the first trace portion 1111 may be interleaved with a plurality of scan lines 112, and the second trace portion 1112 may be interleaved with the plurality of scan lines 112; for example, the first trace portion 1111 may be overlapped with the first n scan lines 112.
  • the second trace portion 1112 can be interleaved with the last m scan lines 112, where m+n is the total number of scan lines 112, which is not limited in this application.
  • FIG. 6 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • the display panel 60 includes an array substrate 61, a color filter substrate 62 disposed opposite the array substrate 61, and a liquid crystal layer 63 between the color filter substrate 62 and the array substrate 61.
  • the liquid crystal layer includes liquid crystal molecules. By controlling the voltage across the liquid crystal molecules, thereby changing the alignment of the liquid crystal molecules, to achieve the purpose of shading and light transmission, the images of different shades and patches are displayed.
  • the array substrate 61 may be the array substrate 10 in any of the above embodiments.
  • FIG. 7 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • the display device 70 includes a display panel 71 and a backlight module 72 on the light incident side of the display panel.
  • the backlight module 72 is used to provide backlighting for the display panel 71.
  • the display panel 71 may be the display panel 60 in the above embodiment.
  • Step 1 Provide a substrate.
  • the material of the substrate can be glass or plastic.
  • Step 2 Form a light shielding portion and a first wiring portion on the substrate.
  • the light shielding portion and the first wiring portion can be formed by the same process.
  • the opaque portion and the first trace portion may be disposed in an interlaced area of the antistatic trace and the scan line.
  • the first trace portion may be disposed in an interlaced area of the antistatic trace and the most edge two scan lines, and the shading The part can be placed in an interlaced area of the antistatic trace and the inner scan line. It should be understood that the length of the first trace portion may be greater than, less than, or equal to the length of the staggered area of the antistatic trace and the most edge two scan lines.
  • the light shielding portion and the first wiring portion may be formed by the same process, for example, the light shielding portion and the first wiring portion are formed by etching using the same mask.
  • Step 3 Form a buffer layer on the substrate, the light shielding portion, and the first trace portion.
  • the buffer layer can be formed by a plating process such as plasma enhanced chemical vapor deposition (PECVD), which can shield the influence of substrate defects and avoid defective devices or coatings.
  • PECVD plasma enhanced chemical vapor deposition
  • the buffer layer may be subjected to a perforation process, that is, the buffer layer may be perforated on both sides of the first trace portion to obtain a third sub-via.
  • Step 4 Form a semiconductor layer on the buffer layer.
  • the amorphous silicon layer may be formed on the buffer layer first, and the amorphous silicon layer is subjected to laser laser annealing treatment to form a polysilicon layer, and the polysilicon layer is perforated at a position corresponding to the third sub-via. a sub via; and after the via, the polysilicon layer may be ion doped to form a semiconductor layer. Alternatively, after the semiconductor layer is formed, the semiconductor layer may be perforated to obtain a second sub-via.
  • the semiconductor layer may not be perforated.
  • Step 5 Form a first insulating layer on the semiconductor layer.
  • the first insulating layer may be perforated at a position corresponding to the second sub-via to obtain a first sub-via.
  • the semiconductor layer may be hydrogenated by hydrogen in the first insulating layer as a hydrogen source before or after the first insulating layer is perforated.
  • first insulating layer on the light shielding portion may be perforated so that the second metal layer can be connected to the semiconductor layer through the via of the first insulating layer.
  • Step 6 Form a first metal layer on the first insulating layer, and pattern the first metal layer to obtain a gate.
  • Step 7 Form a second insulating layer on the first metal layer and the first insulating layer.
  • the second insulating layer may be perforated corresponding to the position of the first sub-via to obtain a second via.
  • the second insulating layer on the light shielding portion may be perforated so that the second metal layer can be sequentially connected to the semiconductor layer through the via hole of the second insulating layer and the via hole of the first insulating layer.
  • Step 8 Form a second metal layer on the second insulating layer, and pattern the second metal layer to form a source, a drain, and a first trace portion.
  • the display area of the array substrate of the present application includes at least one anti-static trace and a plurality of scan lines, and the anti-static traces are used to guide static electricity; the anti-static traces are staggered and insulated from the scan lines;
  • the antistatic trace includes a connected first trace portion and a second trace portion, and the first trace portion and the second trace portion are at different layers.
  • the antistatic trace includes the connected first trace portion and the second trace portion, and the first trace portion and the second trace portion are in different layers, the charge accumulation of the antistatic trace can be reduced to avoid
  • the static electricity of the anti-static trace breaks through the film between the anti-static trace and the scan line, which prevents the anti-static trace from short-circuiting with the scan line, resulting in abnormal display.

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Abstract

一种阵列基板（10）及显示面板（60，71），该阵列基板（10）的显示区（11）包括至少一条防静电走线（111）和多条扫描线（112），防静电走线（111）用于导走静电；防静电走线（111）与扫描线（112）交错且绝缘设置；其中，防静电走线（111）包括相连的第一走线部分（1111）和第二走线部分（1112），第一走线部分（1111）和第二走线部分（1112）处于不同层。还公开了一种显示面板。通过上述方式，能够避免由于防静电走线（111）的静电击穿导致显示异常。

Description

阵列基板及显示面板
【技术领域】
本申请涉及显示领域，特别是涉及阵列基板及显示面板。
【背景技术】
目前，显示面板特别是利用低温多晶硅技术（Low Temperature Poly-silicon，LTPS）的液晶显示面板，由于具有高开口率和高解析度的优点，已被广泛应用各种领域中以进行显示。
为了保护显示面板上的器件，显示面板上设置防静电走线（也可以称为dummy走线或dummy M2走线）。然而，由于防静电走线容易积累静电，从而出现静电击穿阵列基板膜层的情况，进而导致显示面板显示异常。
【发明内容】
本申请主要解决的技术问题是提供一种阵列基板及显示面板，能够避免由于防静电走线的静电击穿阵列基板的膜层而导致显示面板显示异常。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种阵列基板，阵列基板的显示区包括至少一条防静电走线和多条扫描线，防静电走线用于导走静电；防静电走线与扫描线交错且绝缘设置；其中，防静电走线包括相连的第一走线部分和第二走线部分，第一走线部分和第二走线部分处于不同层；第一走线部分与扫描线交错，第二走线部分位于扫描线的两侧，和/或防静电走线位于显示区中靠近非显示区的位置；显示区包括依序设置在基板上的第一功能层、第二功能层、信号线层以及第二金属层，第二功能层用于形成薄膜晶体管；包括第二走线部分，第二功能层设有第一通孔，第二走线部分穿过第一通孔与第一走线部分连接。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种阵列基板，该阵列基板的显示区包括至少一条防静电走线和多条扫描线，防静电走线用于导走静电；防静电走线与扫描线交错且绝缘设置；其中，防静电走线包括相连的第一走线部分和第二走线部分，第一走线部分和第二走线部分处于不同层。
为解决上述技术问题，本申请采用的又一个技术方案是：提供一种显示面板，该显示面板包括上述的阵列基板。
本申请的有益效果是：区别于现有技术的情况，本申请阵列基板的显示区包括至少一条防静电走线和多条扫描线，防静电走线用于导走静电；防静电走线与扫描线交错且绝缘设置；其中，防静电走线包括相连的第一走线部分和第二走线部分，第一走线部分和第二走线部分处于不同层。由于防静电走线包括相连的第一走线部分和第二走线部分，且第一走线部分和第二走线部分处于不同层，因此，能够减少防静电走线的电荷积累，以避免防静电走线的静电击穿防静电走线与扫描线之间的膜层，进而防止防静电走线与扫描线出现短路，导致显示异常。
【附图说明】
图1是本申请实施例阵列基板的结构示意图；
图2是图1中实施例沿A-A截面或B-B截面的结构示意图；
图3是图1中另一实施例沿A-A截面或B-B截面的结构示意图；
图4是本申请另一实施例阵列基板的结构示意图；
图5是图4中实施例沿B-B截面的结构示意图；
图6是本申请实施例显示面板的结构示意图；
图7是本申请实施例显示装置的结构示意图。
【具体实施方式】
为使本申请的上述目的、特征和优点能够更为明显易懂，下面结合附图，对本申请的具体实施方式做详细的说明。可以理解的是，此处所描述的具体实施例仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
请参阅图1~图3，图1是本申请实施例阵列基板的结构示意图；图2是图1中实施例沿A-A截面或B-B截面的结构示意图；图3是图1中另一实施例沿A-A截面或B-B截面的结构示意图。
阵列基板10包括显示区11和围绕该显示区11的非显示区12。显示区11可以包括多条扫描线112，多条数据线113，以及至少一条防静电走线111，多条扫描线112和多条数据线113互相交错，以将显示区11划分为多个像素区域114。非显示区12可以设置扫描线驱动电路121和数据线驱动电路122，扫描线驱动电路121分别与多条扫描线112连接，用于提供扫描信号至该多条扫描线112，数据线驱动电路122与多条数据线113连接，用于提供数据信号至该多条数据线113。
在本实施例中，防静电走线111用于导走静电，例如用于导走非显示区12产生的静电，具体如非显示区12中的电路产生的静电。防静电走线111与扫描线112交错且绝缘设置，通常防静电走线111与扫描线设置在不同层，以实现上述交错且绝缘设置。具体地，防静电走线111包括相连的第一走线部分1111和第二走线部分1112，其中，第一走线部分1111和第二走线部分1112处于不同层。由于防静电走线1111分为不同层的两个走线部分，即采用跳线方式断开了该防静电走线111，故能够减少防静电走线的电荷积累，以避免防静电走线的静电击穿防静电走线与扫描线之间的膜层，即消除天线效应影响，进而防止防静电走线与扫描线出现短路而导致显示异常。
进一步地，第一走线部分1111与扫描线112交错，第二走线部分1112位于扫描线112的两侧，即第一走线部分1111为防静电走线111中与扫描线交错的部分，第二走线部分1112为防静电走线111中位于扫描线112的两侧的部分，分别位于扫描线112的两侧的第二走线部分1112通过第一走线部分1111进行连接。可以理解的是，该第一走线部分1111可以为防静电走线111与所有扫描线交错的部分，如图1所示；或者，该第一走线部分也可为防静电走线111与部分扫描线交错的部分，也即防静电走线111与其余扫描线交错的部分设置为与第二走线部分同层。由于将与扫描线交错的走线部分设置在与防静电走线其余部分不同的层，可以保证即使防静电走线即使发生静电击穿，也不会导致与扫描线交错的走线部分与扫描线短路。
本实施例中的第一走线部分1111可以是由透光的导电材料或者不透光的导电材料制成，例如，第一走线部分1111可以为氧化铟锡(ITO)、氧化铟锌(IZO)、掺铝氧化锌(AZO)、掺氟二氧化锡(FTO)、掺磷二氧化锡(PTO)以及金属材料中的一种。第二走线部分1112可以为不透光的导电材料，具体可以与数据线113、栅极或者源极的材料一致。第一走线部分1111和第二走线部分1112处于不同层是指第一走线部分1111和第二走线部分1112相对扫描线112的位置不同。例如，第一走线部分1111可以位于扫描线112的上侧，第二走线部分1112可以为扫描线112的下侧，或者，第一走线部分1111可以位于扫描线112的下侧，第二走线部分1112可以位于扫描线112的上侧，再例如，第一走线部分1111和第二走线部分1112可以均位于扫描线112的上侧或者下侧，只不过第一走线部分1111和第二走线与扫描线112之间的距离不同。
具体地，防静电走线111位于但不限于位于显示区11中靠近非显示区12的位置，也即位于显示区11边缘的位置。例如，防静电走线111可以平行于数据线113且设置在数据线113的两侧。本实施例中，防静电走线111为两条，两条防静电走线111均设置在多条数据线113的外侧且平行于数据线113设置。在其它实施例中，防静电走线111还可以为一条、三条或者三条以上，具体的数量可根据实际情况确定。例如，在其它实施例中，防静电走线111可以为四条，每两条防静电走线111均设置多条数据线113的外侧且平行于数据线113设置。
以下说明防静电走线111的工作原理：在阵列基板10中，由于防静电走线111过长，因此容易在防静电走线111上累积大量静电，如果静电较多时，会击穿扫描线112与防静电走线111之间的膜层，例如为下述的位于扫描线112与防静电走线111之间的第二绝缘层145，此时，扫描线112与防静电走线111会短路，进而造成显示面板的显示异常。而通过将防静电走线111设置为相连的第一走线部分1111和第二走线部分1112，第一走线部分1111和第二走线部分1112连接，第一走线部分1111和第二走线部分1112位于不同层，因此，能够断开了该防静电走线111，故减少断开了该防静电走线111上的静电电荷积累，从而避免防静电走线的静电击穿防静电走线与扫描线之间的膜层，从而提升防静电走线111的抗静电释放（Electro-Static discharge，ESD）能力。
请继续参阅图2，在一具体实施例中，显示区11包括依序设置在基板上的第一功能层、第二功能层14、信号线层以及第二金属层，第二功能层14用于形成薄膜晶体管（Thin Film Transistor，TFT）；其中，第一功能层包括第一走线部分1111中，第二金属层包括第二走线部分1112，第二功能层14设有第一通孔15，第二走线部分1112穿过第一通孔15与第一走线部分1111连接。
第二功能层14包括层叠设置的缓冲层141、半导体层142、第一绝缘层143；信号线层包括层叠设置的第一金属层144和第二绝缘层145，第一金属层144包括扫描线112和薄膜晶体管的栅极，第二金属层还包括数据线112、薄膜晶体管的源极161和漏极162。可以理解的是，在其他实施例中，第一走线部分1111也可设置在第二功能层中，例如，设置在缓冲层中，或者设置在缓冲层上且在第一走线部分1111上另设一层绝缘层，该半导体层设置在该另设的绝缘层上。
第一绝缘层143、第二绝缘层145的材料均可以包括单层的氮化硅(SiNx)、单层的氧化硅(SiOx)以及氧化硅(SiOx)和氮化硅(SiNx)形成的叠层中的一种。例如在本实施例中，第一绝缘层143、第二绝缘层145的材料均包括氮化硅。
以下说明各层之间的关系：第一功能层设置在基板上，缓冲层141设置在第一功能层上，半导体层142设置在缓冲层141上，第一绝缘层143设置在半导体层142上，第一金属层144设置在第一绝缘层143上，第二绝缘层145设置在第一金属层144和第一绝缘层143上，第二金属层设置在第二绝缘层145上。在其它实施例中，第一绝缘层143可以设置在半导体层142上和缓冲层141上。
在本实施例中，第二绝缘层145包括设置在第一绝缘层143上的第一区域1451，第一区域1451设有第二通孔155，第二走线部分1112穿过第二绝缘层145的第二通孔155和第二功能层14的第一通孔15连接第一走线部分1111。
其中第一通孔15设置在第二通孔155下面，即第一通孔15设置在第二通孔155靠近基板的一侧，第一通孔15和第二通孔155同轴且第一通孔15和第二通孔155的内壁平齐，以使第二走线穿过第二通孔155和第一通孔15与第一走线部分1111连接时，使第二走线在第二通孔155和第一通孔15之间没有折断点，从而加强了第二走线部分1112的强度。
在本实施例中，第一通孔15和第二通孔155的面积可以沿缓冲层141至基板方向上逐渐减小，在其它实施例中，第一通孔15和第二通孔155的面积可以沿缓冲层141至基板方向上逐渐增大或者不变。另外，第一通孔15和第二通孔155的面积可以为多边形，例如三角形、四边形或者五边形等等。本申请对此不作限定。
第二绝缘层145的第一区域1451、第一绝缘层143均设置第三通孔163，源极161和漏极162均通过第三通孔163连接半导体层142。
第一绝缘层143包括设置在缓冲层141上的第二区域1431，第二区域1431设有第一子通孔153，缓冲层141对应第一子通孔153设有第二子通孔152，第一子通孔153和第二子通孔152形成第一通孔15，其中，第二通孔155的孔径大于或等于第一子通孔153的孔径，第一子通孔153的孔径大于或等于第二子通孔152的孔径。
即在本实施例中，第一绝缘层143设置在半导体层142和缓冲层141上，即第二走线部分1112在穿过第二通孔155、第一子通孔153、第二子通孔152时，不与半导体层142接触，以避免半导体层142和第二走线部分1112之间互相干扰，从而降低防静电走线111的导静电能力。同样地，第二通孔155、第一子通孔153以及第二子通孔152内壁平齐。
请继续参阅图3，在该实施例中，第一绝缘层143包括设置在缓冲层141上的第二区域1431，第二区域1431设置有第一子通孔153，半导体层142对应第一子通孔153设有第二子通孔152，缓冲层141对应第二子通孔152设有第三子通孔151，第一子通孔153、第二子通孔152和第三子通孔151形成第一通孔15，其中，第二通孔155的孔径大于或等于第一子通孔153的孔径，第一子通孔153的孔径大于或等于第二子通孔152的孔径，以及第二子通孔152的孔径大于或等于第三子通孔151的孔径。第一绝缘层143设置在半导体层142上，即第二走线部分1112依次穿过第二通孔155、第一子通孔153、第二子通孔152、第三子通孔151时，与半导体层142接触。应注意有第二走线部分1112和半导体层142接触，因此，为了防止半导体层142与第二走线部分1112之间的相互影响，避免对其它半导体层142产生影响，例如是薄膜晶体管的半导体层142，应使与防静电走线111的半导体层142与薄膜晶体管之间的半导体层142绝缘，从而避免第二走线部分1112在导走静电时对薄膜晶体管的半导体层142产生影响。同样地，第二通孔155、第一子通孔153、第二子通孔152以及第三子通孔151内壁平齐。
第一功能层还可以包括遮光部1113，遮光部1113对应薄膜晶体管设置，即对应上述像素区域中的薄膜晶体管的位置设置。其中，遮光部1113和第一走线部分1111可以采用同一光罩刻蚀形成的，即遮光部1113和第一走线部分1111可以采用相同的工艺制成，以使阵列基板10的制造工艺简单，进而降低制作成本。在其它实施例中，遮光部1113和第一走线部分1111可以采用不同工艺制成，本申请不作限定。
在本实施例中，防静电走线111可以通过接地的方式以导走静电。例如，防静电走线111一端通过转接口接地，从而将内部产生的电荷导走。在另一实施例中，防静电走线111可以通过转接口连接显示面板的公共电极，以实现与公共电极的接地端一并接地。
请参阅图4和图5，图4是本申请另一实施例阵列基板的结构示意图；图5是图4中实施例沿B-B截面的结构示意图。在该实施例中，第一走线部分1111仅与边缘的两条扫描线112交错，第二走线部分1112与内侧的多条扫描线112交错，与内侧的多条扫描线112交错的第二走线部分1112设置在第二绝缘层145上。
在其它实施例中，第一走线部分1111也可以与多条扫描线112交错，第二走线部分1112与另外的多条扫描线112交错。例如，第一走线部分1111可以与单数条扫描线112交错，第二走线部分1112可以与双数条扫描线112交错；再例如，第一走线部分1111可以与前n条扫描线112交错，第二走线部分1112可以与后m条扫描线112交错，其中m+n为扫描线112的总条数，本申请对此不做限定。
请参阅图6，图6是本申请实施例显示面板的结构示意图。
显示面板60包括：阵列基板61、与阵列基板61相对设置的彩膜基板62以及位于彩膜基板62和阵列基板61之间的液晶层63，液晶层包括液晶分子。通过控制液晶分子两端的电压，进而改变液晶分子的排列状况，以达到遮光和透光的目的来显示深浅不一，错落有致的图象。其中，阵列基板61可以为上述任一实施例中的阵列基板10。
请参阅图7，图7是本申请实施例显示装置的结构示意图。
显示装置70包括显示面板71和位于显示面板入光侧的背光模组72，背光模组72用于为显示面板71提供背光。显示面板71可以为上述实施例中的显示面板60。
下面对上述阵列基板的制作过程进行举例说明：
步骤1、提供基板。
基板的材质可以为玻璃或塑料。
步骤2、在基板上形成遮光部和第一走线部分。
遮光部和第一走线部分可以采用相同的工艺制成。遮光部和第一走线部分可以设置在防静电走线和扫描线的交错区域，具体而言，第一走线部分可以设置在防静电走线和最边缘两条扫描线的交错区域，遮光部可以设置在防静电走线和内侧扫描线的交错区域。应理解，第一走线部分的长度可以大于、小于或者等于防静电走线和最边缘两条扫描线的交错区域的长度。
可选地，遮光部和第一走线部分可以采用同一工艺制成，例如，遮光部和第一走线部分采用同一光罩刻蚀形成。
步骤3、在基板、遮光部以及第一走线部分上形成缓冲层。
可以通过镀膜工艺如等离子体增强化学的气相沉积法(PECVD)形成缓冲层，缓冲层可以屏蔽基板缺陷的影响，避免引起的器件或涂层不良。形成缓冲层之后，可以对缓冲层进行穿孔处理，即可以在第一走线部分的两侧对缓冲层进行穿孔，得到第三子通孔。
步骤4、在缓冲层上形成半导体层。
具体而言，可以先再缓冲层上先形成非晶硅层，对非晶硅层进行镭射激光退火处理以形成多晶硅层，并在对应第三子通孔的位置对多晶硅层进行穿孔得到第二子通孔；以及在穿孔之后，可以对多晶硅层进行离子掺杂，以形成半导体层。或者可以在形成半导体层后，对半导体层穿孔，以得到第二子通孔。
在其它实施例中，可以不对半导体层极性穿孔。
步骤5、在半导体层上形成第一绝缘层。
在形成第一绝缘层之后，可以在对应第二子通孔的位置对第一绝缘层进行穿孔，以得到第一子通孔。另外，对第一绝缘层穿孔之前或者穿孔之后，可以通过第一绝缘层中的氢作为氢源对所述半导体层进行氢化。
另外，可以对遮光部上的第一绝缘层进行穿孔，以使第二金属层能够通过第一绝缘层的过孔与半导体层连接。
步骤6、在第一绝缘层上形成第一金属层，对第一金属层进行图形化处理，得到栅极。
步骤7、在第一金属层和第一绝缘层上形成第二绝缘层。
在形成第二绝缘层之后，可以对应第一子通孔的位置对第二绝缘层进行穿孔，以得到第二通孔。
另外，可以对遮光部上的第二绝缘层进行穿孔，以使第二金属层能够依次通过第二绝缘层的过孔和第一绝缘层的过孔与半导体层连接。
步骤8、在第二绝缘层上形成第二金属层，对第二金属层进行图形化处理形成源极、漏极以及第一走线部分。
区别于现有技术的情况，本申请阵列基板的显示区包括至少一条防静电走线和多条扫描线，防静电走线用于导走静电；防静电走线与扫描线交错且绝缘设置；其中，防静电走线包括相连的第一走线部分和第二走线部分，第一走线部分和第二走线部分处于不同层。由于防静电走线包括相连的第一走线部分和第二走线部分，且第一走线部分和第二走线部分处于不同层，因此，能够减少防静电走线的电荷积累，以避免防静电走线的静电击穿防静电走线与扫描线之间的膜层，进而防止防静电走线与扫描线出现短路，导致显示异常。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其它相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (19)

  1. 一种阵列基板，其中，所述阵列基板的显示区包括至少一条防静电走线和多条扫描线，所述防静电走线用于导走静电；所述防静电走线与所述扫描线交错且绝缘设置；
    其中，所述防静电走线包括相连的第一走线部分和第二走线部分，所述第一走线部分和第二走线部分处于不同层；
    所述第一走线部分与所述扫描线交错，所述第二走线部分位于所述扫描线的两侧，和/或所述防静电走线位于所述显示区中靠近非显示区的位置；
    所述显示区包括依序设置在基板上的第一功能层、第二功能层、信号线层以及第二金属层，所述第二功能层用于形成薄膜晶体管；
    其中，所述第一功能层包括所述第一走线部分，所述第二金属层包括所述第二走线部分，所述第二功能层设有第一通孔，所述第二走线部分穿过所述第一通孔与所述第一走线部分连接。
  2. 一种阵列基板，其中，所述阵列基板的显示区包括至少一条防静电走线和多条扫描线，所述防静电走线用于导走静电；所述防静电走线与所述扫描线交错且绝缘设置；
    其中，所述防静电走线包括相连的第一走线部分和第二走线部分，所述第一走线部分和第二走线部分处于不同层。
  3. 根据权利要求2所述的阵列基板，其中，
    所述第一走线部分与所述扫描线交错，所述第二走线部分位于所述扫描线的两侧，和/或；
    所述防静电走线位于所述显示区中靠近非显示区的位置。
  4. 根据权利要求1所述的阵列基板，其中，
    所述显示区包括依序设置在基板上的第一功能层、第二功能层、信号线层以及第二金属层，所述第二功能层用于形成薄膜晶体管；
    其中，所述第一功能层包括所述第一走线部分，所述第二金属层包括所述第二走线部分，所述第二功能层设有第一通孔，所述第二走线部分穿过所述第一通孔与所述第一走线部分连接。
  5. 根据权利要求4所述的阵列基板，其中，
    所述第二功能层包括层叠设置的缓冲层、半导体层、第一绝缘层；
    所述信号线层包括层叠设置的第一金属层和第二绝缘层，所述第一金属层包括所述扫描线和所述薄膜晶体管的栅极，所述第二金属层还包括薄膜晶体管的源极和漏极。
  6. 根据权利要求5所述的阵列基板，其中，所述第二绝缘层包括设置在所述第二绝缘层上的第一区域，所述第一区域设有第二通孔，所述第二走线部分穿过所述第二绝缘层的第二通孔和所述第二功能层的第一通孔连接至所述第一走线部分。
  7. 根据权利要求6所述的阵列基板，其中，所述第二金属层还包括所述数据线；所述第二绝缘层的第一区域、第一绝缘层均设置第三通孔，所述源极和漏极均通过所述第三通孔连接所述半导体层。
  8. 根据权利要求6所述的阵列基板，其中，所述第一绝缘层包括设置在所述缓冲层上的第二区域，所述第二区域设有第一子通孔，所述缓冲层对应所述第一子通孔设有第二子通孔，所述第一子通孔和所述第二子通孔形成所述第一通孔，其中，所述第二通孔的孔径大于或等于所述第一子通孔的孔径，所述第一子通孔的孔径大于或等于所述第二子通孔的孔径。
  9. 根据权利要求4所述的阵列基板，其中，所述第一功能层还包括遮光部，所述遮光部对应所述薄膜晶体管设置。
  10. 根据权利要求9所述的阵列基板，其中，所述遮光部和所述第一走线部分采用同一光罩刻蚀形成的。
  11. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板的显示区包括至少一条防静电走线和多条扫描线，所述防静电走线用于导走静电；所述防静电走线与所述扫描线交错且绝缘设置；
    其中，所述防静电走线包括相连的第一走线部分和第二走线部分，所述第一走线部分和第二走线部分处于不同层。
  12. 根据权利要求11所述的显示面板，其中，
    所述第一走线部分与所述扫描线交错，所述第二走线部分位于所述扫描线的两侧，和/或；
    所述防静电走线位于所述显示区中靠近非显示区的位置。
  13. 根据权利要求11所述的显示面板，其中，
    所述显示区包括依序设置在基板上的第一功能层、第二功能层、信号线层以及第二金属层，所述第二功能层用于形成薄膜晶体管；
    其中，所述第一功能层包括所述第一走线部分，所述第二金属层包括所述第二走线部分，所述第二功能层设有第一通孔，所述第二走线部分穿过所述第一通孔与所述第一走线部分连接。
  14. 根据权利要求13所述的阵列基板，其中，
    所述第二功能层包括层叠设置的缓冲层、半导体层、第一绝缘层；
    所述信号线层包括层叠设置的第一金属层和第二绝缘层，所述第一金属层包括所述扫描线和所述薄膜晶体管的栅极，所述第二金属层还包括薄膜晶体管的源极和漏极。
  15. 根据权利要求14所述的阵列基板，其中，所述第二绝缘层包括设置在所述第二绝缘层上的第一区域，所述第一区域设有第二通孔，所述第二走线部分穿过所述第二绝缘层的第二通孔和所述第二功能层的第一通孔连接至所述第一走线部分。
  16. 根据权利要求15所述的阵列基板，其中，所述第二金属层还包括所述数据线；所述第二绝缘层的第一区域、第一绝缘层均设置第三通孔，所述源极和漏极均通过所述第三通孔连接所述半导体层。
  17. 根据权利要求15所述的阵列基板，其中，所述第一绝缘层包括设置在所述缓冲层上的第二区域，所述第二区域设有第一子通孔，所述缓冲层对应所述第一子通孔设有第二子通孔，所述第一子通孔和所述第二子通孔形成所述第一通孔，其中，所述第二通孔的孔径大于或等于所述第一子通孔的孔径，所述第一子通孔的孔径大于或等于所述第二子通孔的孔径。
  18. 根据权利要求13所述的阵列基板，其中，所述第一功能层还包括遮光部，所述遮光部对应所述薄膜晶体管设置。
  19. 根据权利要求18所述的阵列基板，其中，所述遮光部和所述第一走线部分采用同一光罩刻蚀形成的。
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