WO2022036748A1 - 阵列基板、阵列基板制作方法及液晶显示面板 - Google Patents

阵列基板、阵列基板制作方法及液晶显示面板 Download PDF

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Publication number
WO2022036748A1
WO2022036748A1 PCT/CN2020/112081 CN2020112081W WO2022036748A1 WO 2022036748 A1 WO2022036748 A1 WO 2022036748A1 CN 2020112081 W CN2020112081 W CN 2020112081W WO 2022036748 A1 WO2022036748 A1 WO 2022036748A1
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Prior art keywords
common
wiring
layer
array substrate
common wiring
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PCT/CN2020/112081
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English (en)
French (fr)
Inventor
张占东
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武汉华星光电技术有限公司
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Priority to US17/051,707 priority Critical patent/US20230101097A1/en
Publication of WO2022036748A1 publication Critical patent/WO2022036748A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a method for fabricating the array substrate, and a liquid crystal display panel.
  • LCD Liquid Crystal Display
  • the common electrode in the liquid crystal display is a full-surface-covering electrode, which receives a voltage signal at the edge area or non-display area of the liquid crystal display, and then transmits it to the entire display surface.
  • the loss is caused by the impedance of the common electrode, resulting in uneven voltage distribution, which affects the uniformity of the display. This problem is particularly prominent in the display of large-sized liquid crystal displays.
  • the method to solve this problem in the prior art is to set a common line parallel to the gate line on the gate line layer of the liquid crystal display, and electrically connect the common line to the common electrode, and connect the common electrode through the common line.
  • the area close to the middle is supplemented with voltage to ensure that the voltage distribution on the common electrode is balanced.
  • gate traces and common traces arranged side by side on the same layer have many problems in the manufacturing process. Referring to FIG. 1 , the gate wiring 03 and the common wiring 02 arranged on the substrate 01 are both elongated wirings running through the display area.
  • the fabrication process is to deposit a metal layer on the substrate 01, and then apply the After exposure, development and etching processes, gate wiring 03 and common wiring 02 are formed.
  • the gate traces 03 and the common traces 02 are both elongated traces, after the development process, two strips of photoresist 04 will be formed side by side on the metal layer; after the etching process, the etching solution 05 It will be accumulated between the two adjacent photoresists 04 and cannot be removed in time, resulting in excessive etching of the metal layers on both sides by the etching solution 05, thereby making the gate wiring 03 and the common wiring 02 too thin. Or there is a disconnection problem, which seriously affects the product yield.
  • the gate wiring and the common wiring are arranged on the same layer and side by side, and both the gate wiring and the common wiring are long strip wirings; the gate wiring and the common wiring are fabricated by an etching method.
  • the etching solution is easy to accumulate between the two traces and cannot be removed in time, resulting in excessive etching of the gate traces and the common traces, causing the gate traces and the common traces to be too thin or broken. .
  • an array substrate including:
  • the array layer includes gate wirings and source-drain wirings arranged on the gate wirings, the array layer further includes a first common wiring arranged in the same layer as the gate wirings, and a a second common line provided on the same layer of the source-drain line, the second common line is electrically connected to the first common line, and the first common line is a discontinuous line segment; and
  • a common electrode is disposed on the array layer and is electrically connected to the second common wiring.
  • a break is provided on the second common wire, and the second common wire on both sides of the break is electrically connected to the same first common wire respectively.
  • the source-drain wiring and the second common wiring intersect at the fracture, and the source-drain wiring and the second common wiring are insulated from each other.
  • a plurality of discontinuous first common lines are provided along the extending direction of the second common lines, and the second common lines correspond to each of the first common lines
  • the fractures are provided at the positions of the wires, and the second common wires located on both sides of the fracture are electrically connected to the same first common wire respectively.
  • common wiring terminals are provided on both sides of the array substrate, and both ends of the second common wiring are connected to the common wiring terminals.
  • the first common wiring is parallel to the gate wiring.
  • the array substrate further includes a pixel electrode disposed on the common electrode, and the pixel electrode is electrically connected to the source-drain wiring.
  • the array layer is disposed on a base substrate, and the array layer includes an active layer disposed on the base substrate, a gate insulating layer covering the active layer, and an active layer disposed on the base substrate.
  • the second common wiring is electrically connected to the first common wiring through a via hole on the interlayer insulating layer, and the source-drain wiring passes through the gate
  • the insulating layer and the via hole on the interlayer insulating layer are electrically connected to the active layer.
  • a flat layer is disposed between the array layer and the common electrode, and the common electrode is electrically connected to the second common wiring through a via hole on the flat layer.
  • a passivation layer is disposed between the common electrode and the pixel electrode, and the pixel electrode is connected to the source and drain lines through the passivation layer and via holes on the flat layer. Electrical connection.
  • a light shielding layer is provided on the base substrate at a position corresponding to the active layer, for shielding the light emitted to the active layer.
  • the present application also provides a method for fabricating an array substrate, comprising the following steps:
  • a second common wiring and a source-drain wiring arranged in the same layer are fabricated on the first common wiring and the gate wiring, so that the second common wiring and the first common wiring are formed electrical connection;
  • a common electrode is formed on the second common wiring and the gate wiring to form an electrical connection between the common electrode and the second common wiring.
  • the steps of fabricating the first common wiring and the gate wiring include: fabricating a first metal layer, and patterning the first metal layer to form the first metal layer. the first common wiring and the gate wiring.
  • the steps of fabricating the second common wiring and the source-drain wiring include: fabricating a second metal layer, and patterning the second metal layer to form the second common wiring and the source-drain wiring.
  • a fracture is provided on the formed second common wiring, and the second common wiring located on both sides of the fracture and the same first common wiring are respectively electrically connected; the source-drain wiring and the second common wiring intersect at the fracture, and the source-drain wiring and the second common wiring are insulated from each other.
  • the manufacturing method of the array substrate further comprises the following steps:
  • a pixel electrode is formed on the upper layer of the common electrode, and the pixel electrode is electrically connected with the source and drain lines.
  • the present application also provides a liquid crystal display panel, comprising:
  • an array substrate including an array layer and a common electrode
  • the array layer includes a gate wiring, a first common wiring arranged on the same layer as the gate wiring, and a source and drain electrodes arranged on the gate wiring a wiring, and a second common wiring arranged on the same layer as the source-drain wiring, the second common wiring is electrically connected with the first common wiring, and the first common wiring is not a continuous line segment, the common electrode is electrically connected to the second common wiring;
  • a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • a fracture is provided on the second common wiring, and the second common wiring on both sides of the fracture is electrically connected to the same first common wiring, respectively.
  • the source-drain wiring and the second common wiring intersect at the fracture, and the source-drain wiring and the second common wiring are insulated from each other;
  • Common wiring terminals are disposed on both sides of the array substrate, and both ends of the second common wiring are connected to the common wiring terminals.
  • the first common wiring on the same layer as the gate wiring is arranged in a discontinuous segment shape, and is electrically connected with the second common wiring, Then, the voltage of the common electrode is supplemented to ensure that the voltage distribution of the common electrode is balanced; at the same time, there are many openings for the etchant to flow between the discontinuous line-shaped first common line and the gate line, so the etching After the operation is completed, the etching solution is more easily removed, preventing the first common wiring and the gate wiring from being too thin or disconnected due to the accumulation of the etching solution.
  • 1 is a schematic diagram of the accumulation of etchant between the common wiring and the gate wiring when the array substrate is fabricated in the prior art
  • FIG. 2 is a schematic perspective view of a plane structure of an array substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of a method for fabricating an array substrate provided by an embodiment of the present application
  • FIG. 5 is a schematic structural diagram after the first metal layer is fabricated in the method for fabricating an array substrate provided by an embodiment of the present application;
  • FIG. 6 is a schematic structural diagram of the patterned first metal layer in the method for fabricating an array substrate provided by an embodiment of the present application;
  • FIG. 7 is a schematic structural diagram after the second metal layer is fabricated in the method for fabricating an array substrate provided by an embodiment of the present application;
  • FIG. 8 is a schematic structural diagram of the second metal layer after patterning in the method for fabricating an array substrate provided by an embodiment of the present application;
  • FIG. 9 is a schematic structural diagram of an array substrate obtained by the method for fabricating an array substrate provided in an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a liquid crystal display panel provided by an embodiment of the present application.
  • the present application provides an array substrate, the array substrate includes a discontinuous line segment-shaped first common line provided on the same layer as the gate line, and a second common line provided on the same layer as the source and drain lines,
  • the first common line and the second common line are used to supplement the voltage of the common electrode; there is more for etching between the first common line and the gate line in the shape of discontinuous line segments
  • the first common trace and the gate trace are too thin or broken.
  • FIG. 2 is a schematic perspective view of the structure of the array substrate provided by the embodiment of the present application
  • FIG. 3 is a schematic view of the cross-sectional structure of the array substrate provided by the embodiment of the present application.
  • the array substrate 10 includes an array layer 13 and a common electrode 15 disposed on the array layer 13 .
  • the array substrate 10 may further include a base substrate 11 , a buffer layer 12 disposed on the base substrate 11 , and a flat layer 14 disposed between the array layer 13 and the common electrode 15 , a passivation layer 16 disposed on the common electrode 15 , and a pixel electrode 17 disposed on the passivation layer 16 .
  • the base substrate 11 can be a rigid substrate or a flexible substrate; when the base substrate 11 is a rigid substrate, it can be made of hard materials such as glass; the base substrate 11 is a flexible substrate It can be made of flexible materials such as polyimide.
  • the buffer layer 12 is disposed on the base substrate 11 to balance the performance difference between the base substrate 11 and the array layer 13 .
  • a light shielding layer 121 is provided on the side of the buffer layer 12 close to the base substrate 11 or the side close to the array layer 13 for shielding the light emitted to the active layer 132 in the array layer 13 .
  • the array layer 13 includes gate traces 133 and source and drain traces 136 disposed on the gate traces 133 .
  • the array layer 13 further includes an active layer 132 , a gate insulating layer 131 , and an interlayer insulating layer 135 .
  • the active layer 132 is disposed on the buffer layer 12.
  • the active layer 132 is made of a semiconductor material, such as a metal oxide semiconductor or a low temperature polysilicon semiconductor.
  • Two ends of the active layer 132 are respectively A source electrode and a drain electrode are formed by an ion doping process, and a channel region connecting the source electrode and the drain electrode is formed in the middle region of the active layer 132 ; the gate insulating layer 131 is disposed on the buffer layer 12 and covers The active layer 132 and the gate insulating layer 131 can be made of ceramic materials such as silicon nitride and silicon oxide; the gate wiring 133 and the first common wiring 134 are arranged on the gate insulating layer.
  • the interlayer insulating layer 135 is disposed on the gate insulating layer 131 and covers the gate wiring 133 and the first common wiring 134, the interlayer insulating layer 135 may be made of nitrogen Silicone, silicon oxide and other ceramic materials; the source and drain traces 136 and the second common traces 137 are disposed on the interlayer insulating layer 135, and the source and drain traces 136 pass through the layer
  • the interlayer insulating layer 135 and the vias on the gate insulating layer 131 are electrically connected to the source and drain electrodes of the active layer 132 , and the second common wiring 137 passes through the interlayer insulating layer 135
  • the via hole is electrically connected to the first common trace 134 .
  • the first common line 134 is a discontinuous line segment, and in a direction consistent with the extending direction of the gate line 133 , a plurality of the first common line segments in the shape of discontinuous line segments are arranged side by side. Common trace 134 .
  • a plurality of the first common wirings 134 arranged side by side are parallel to the gate wirings 133 . It should be noted that, in this embodiment, the first common lines 134 arranged side by side with the gate lines 133 are all discontinuous line segments, and two adjacent line segments of the first common lines 134 There is an opening area between them.
  • the etching solution can be easily removed through the opening area, so as to avoid the etching solution in the first common wiring 134 and the gate wiring 133.
  • the second common trace 137 is stacked on the upper layer of the first common trace 134 , and there are a plurality of discontinuous all traces along the extending direction of the second common trace 137 .
  • the first common wiring 134 line segment, the second common wiring 137 is provided with a fracture 137a at the position corresponding to each of the first common wiring 134, and the second common wiring 137a is located on both sides of the fracture 137a.
  • the traces 137 are electrically connected to the same first common trace 134, so that the second common traces 137 located on both sides of the break 137a are electrically connected to form the first common trace 134 and the second common wiring 137 across the layer bridge structure.
  • the source-drain traces 136 and the second common traces 137 intersect at the fracture 137a, and there is no electricity between them and the second common traces 137 on both sides of the fracture 137a
  • a wiring structure in which the second common wiring 137 and the source-drain wiring 136 are electrically insulated from each other is formed.
  • the source-drain traces 136 and the second common traces 137 are arranged vertically, and the intersection point of the vertical intersection is located at the fracture 137a.
  • the gate traces 133 and the source-drain traces 136 form a plurality of lattice areas on the array substrate 10 , and each lattice area corresponds to a sub-pixel on the array substrate 10 Area.
  • the common wiring terminal 101 is used to transmit a common voltage signal to the second common wiring 137 ; under the action of the electrical connection of the first common wiring 134 , the common voltage signal is at The entire second common wiring 137 is transmitted and further transmitted to the common electrode 15 (refer to FIG. 2 and FIG. 3 ) to ensure that the voltage distribution on the common electrode 15 is balanced.
  • One side of the array substrate 10 is further provided with a data signal control terminal 102, the data signal control terminal 102 is electrically connected to the source-drain trace 136 through the fan-out trace 103, and is used for connecting the source-drain trace to the source-drain trace.
  • the wiring 136 transmits a data signal, and the data signal is further transmitted to the pixel electrode 17 (refer to FIG. 2 and FIG. 3 ) to regulate the voltage state of the pixel electrode 17 .
  • the common electrode 15 is electrically connected to the second common wiring 137 through the via hole on the flat layer 14 , so as to ensure that the voltage signal on the second common wiring 137 can be transmitted to the common electrode 15 .
  • the pixel electrode 17 is electrically connected to the source and drain traces 136 through the via hole on the passivation layer 16 and the via hole on the flat layer 14 , and the pixel electrode 17 and the common electrode are electrically connected Electrical insulation is maintained between 15 , and the pixel electrode 17 receives the data signal transmitted by the source-drain wiring 136 to generate an electric field effect. It should be noted that when the array substrate 10 is applied to a liquid crystal display panel, the common electrodes 15 and the pixel electrodes 17 respectively generate electric fields, and the liquid crystal in the liquid crystal display panel is deflected under the action of the two electric fields to adjust the display gray scale, so that the liquid crystal display panel can generate different pictures.
  • the array substrate provided by the embodiment of the present application includes a discontinuous line segment-shaped first common line provided on the same layer as the gate line, and a second common line provided on the same layer as the source and drain lines. , use the first common line and the second common line to supplement the voltage of the common electrode to ensure a balanced voltage distribution of the common electrode; the first common line and the gate line in the shape of discontinuous line segments There are many openings for the circulation of the etching solution, so that after the etching operation is completed, the etching solution existing between the first common wiring and the gate wiring is easily removed to prevent the occurrence of The problem that the first common wiring and the gate wiring are too thin or disconnected due to the accumulation of etching solution.
  • An embodiment of the present application further provides a method for manufacturing an array substrate. As shown in FIG. 4 , the method for manufacturing an array substrate includes the following steps:
  • Step S1 as shown in FIG. 6 , a first common wiring 134 and a gate wiring 133 arranged on the same layer are fabricated, so that the first common wiring 134 is formed into a discontinuous line segment. Specifically include the following steps:
  • a base is provided; optionally, the base includes a base substrate 11, a light shielding layer 121 disposed on the base substrate 11, and a buffer layer disposed on the base substrate 11 and covering the light shielding layer 121 12.
  • a first metal layer M1 is fabricated on the substrate; optionally, a method for fabricating the first metal layer M1 may be a vapor deposition method or a spraying method.
  • the first metal layer M1 is patterned to form the first common wiring 134 and the gate wiring 133 , and the first common wiring 134 is in the shape of a discontinuous line segment.
  • performing a patterning process operation on the first metal layer M1 includes: coating photoresist, exposing and developing the photoresist, and performing pattern etching on the first metal layer M1.
  • the first common traces 134 formed in this embodiment are in the shape of discontinuous line segments, so an opening area is formed between two adjacent segments of the first common traces 134.
  • the etching solution is easily removed through the opening area, which avoids the difficulty of the etching solution between the first common wiring 134 and the gate wiring 133 for a long time.
  • the line width is too thin or broken due to removal.
  • Step S2 fabricate a second common wiring 137 and a source-drain wiring 136 in the same layer on the first common wiring 134 and the gate wiring 133 , so that the first common wiring 137 and the source-drain wiring 136
  • the two common traces 137 are electrically connected to the first common trace 134 . Specifically include the following steps:
  • an interlayer insulating layer 135 covering the first common wiring 134 and the gate wiring 133 is first fabricated.
  • the insulating layer 135 may be fabricated from ceramic materials such as silicon nitride and silicon oxide through a chemical vapor deposition process.
  • a second metal layer M2 is formed on the interlayer insulating layer 135 , so that the second metal layer M2 is connected to the first common wiring through the via hole on the interlayer insulating layer 135 134 is electrically connected, and is electrically connected to the active layer 132 through the interlayer insulating layer 135 and the via hole on the gate insulating layer 131;
  • the method may be vapor deposition or spray coating.
  • the second metal layer M2 is patterned to form the second common wiring 137 and the source-drain wiring 136 .
  • performing a patterning process operation on the second metal layer M2 includes: coating a photoresist, exposing and developing the photoresist, and performing pattern etching on the second metal layer M2.
  • the first common wires 134 are respectively electrically connected, so that the second common wires 137 located on both sides of the break 137a are electrically connected to form the first common wires 134 and the second common wires 137
  • the cross-layer bridge structure of the common wiring 137 The formed source-drain traces 136 and the second common traces 137 intersect at the break 137a, and the second common traces 137 and the source-drain traces 136 maintain electrical properties insulation.
  • Step S3 as shown in FIG. 9 , a common electrode 15 is formed on the second common wiring 137 and the gate wiring 136 , so that the common electrode 15 and the second common wiring 137 are electrically connected connect.
  • the method further includes fabricating a flat layer 14 covering the second common wiring 137 and the source-drain wiring 136 , and the common electrode 15 passes through the flat layer 14 .
  • the via holes are electrically connected to the second common traces 137 . It should be understood that using the common voltage transmission line formed by the second common wiring 137 and the first common wiring 134 to transmit the common voltage to the common electrode 15 is beneficial to the voltage distribution on the common electrode 15 balanced.
  • the method for fabricating the array substrate further includes: fabricating a passivation layer 16 on the common electrode 15, fabricating a pixel electrode 17 on the passivation layer 16, and making the pixel electrode 17 and the The source-drain traces 136 are electrically connected.
  • the first common wiring is formed in a discontinuous segment shape, so that there is more etching solution between the first common wiring and the gate wiring. Therefore, after the etching operation is completed, the etching solution existing between the first common wiring and the gate wiring can be easily removed, preventing the occurrence of the first etching solution caused by the accumulation of the etching solution. A problem that the common wiring and the gate wiring are too thin or disconnected can improve the production yield of the array substrate.
  • the liquid crystal display panel includes an array substrate 10 , a color filter substrate 20 disposed opposite to the array substrate 10 , and a color filter substrate 20 disposed on the array substrate 10 .
  • the liquid crystal display panel provided by the embodiment of the present application overcomes the problem that the first common wiring and the gate wiring are too thin or disconnected due to the accumulation of etching solution that is easy to occur during the production process, which is beneficial to improve Production yield.

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Abstract

本申请提供一种阵列基板、阵列基板制作方法及液晶显示面板，所述阵列基板包括与栅极走线同层设置的不连续线段状的第一公共走线和与源漏极走线同层设置的第二公共走线，所述第一公共走线与所述第二公共走线电性连接；不连续线段状的第一公共走线与栅极走线之间形成较多供刻蚀液流通的开口，防止因刻蚀液存积而导致第一公共走线和栅极走线过细或断线。

Description

阵列基板、阵列基板制作方法及液晶显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、阵列基板的制作方法及液晶显示面板。
 背景技术
液晶显示器（Liquid Crystal Display，LCD）是目前应用最为广泛的显示装置之一，其工作原理是通过像素电极和公共电极共同形成的电场的变化来实现对液晶分子偏转的控制，进而达到显示效果。
液晶显示器中的公共电极是整面覆盖型的电极，其通过在液晶显示器的边缘区域或非显示区域接收电压信号，然后传递至整个显示面。电压信号在公共电极上传递过程中由于受到公共电极自身阻抗的作用而产生损耗，造成电压分布不均匀，进而影响显示的均一性，这种问题在大尺寸液晶显示器的显示中尤为突出。
现有技术解决这一问题的方法是在液晶显示器的栅极走线层设置与栅极走线并排的公共走线，并将公共走线电性连接至公共电极，通过公共走线对公共电极的靠近中间的区域进行电压补充，以保证公共电极上的电压分布均衡。但是，同层且并排设置的栅极走线和公共走线在制造过程中会存在较多问题。参考图1所示，设置于基底01上的栅极走线03和公共走线02均为贯穿显示区的长条形走线，其制作过程是在基底01上沉积金属层，然后对金属层进行曝光、显影和刻蚀制程后形成栅极走线03和公共走线02。由于栅极走线03和公共走线02均为长条形走线，经显影制程后会在金属层上形成并排的两条长条状光刻胶04；刻蚀制程后，刻蚀液05会存积于相邻两条光刻胶04之间，而无法及时去除，造成刻蚀液05对两侧金属层的过度刻蚀，进而使形成的栅极走线03和公共走线02过细或出现断线问题，严重影响产品良率。
 技术问题
现有技术的阵列基板中，栅极走线与公共走线同层且并排设置，且栅极走线和公共走线均为长条形走线；通过刻蚀方法制作栅极走线和公共走线时，刻蚀液容易在两条走线之间积存而无法及时去除，造成栅极走线和公共走线被过度刻蚀，引发栅极走线和公共走线过细或断线的问题。
 技术解决方案
为了解决上述技术问题，本申请提供的技术方案如下：
本申请提供一种阵列基板，包括：
阵列层，包括栅极走线和设置于所述栅极走线上的源漏极走线，所述阵列层还包括与所述栅极走线同层设置的第一公共走线、以及与所述源漏极走线同层设置的第二公共走线，所述第二公共走线与所述第一公共走线电性连接，所述第一公共走线为不连续线段；以及
公共电极，设置于所述阵列层上，与所述第二公共走线电性连接。
在本申请的阵列基板中，所述第二公共走线上设置有断口，位于所述断口两侧的所述第二公共走线与同一条所述第一公共走线分别电性连接。
在本申请的阵列基板中，所述源漏极走线与所述第二公共走线在所述断口处相交，且所述源漏极走线与所述第二公共走线彼此绝缘。
在本申请的阵列基板中，沿所述第二公共走线的延伸方向设置有多个不连续的所述第一公共走线，所述第二公共走线对应每个所述第一公共走线的位置均设置有所述断口，且位于所述断口两侧的所述第二公共走线与同一条所述第一公共走线分别电性连接。
在本申请的阵列基板中，所述阵列基板的两侧设置有公共走线端，所述第二公共走线的两端连接至所述公共走线端。
在本申请的阵列基板中，所述第一公共走线与所述栅极走线平行。
在本申请的阵列基板中，所述阵列基板还包括设置于所述公共电极上的像素电极，所述像素电极与所述源漏极走线电性连接。
在本申请的阵列基板中，所述阵列层设置于衬底基板上，所述阵列层包括设置于所述衬底基板上的有源层、覆盖所述有源层的栅极绝缘层、设置于所述栅极绝缘层上的所述栅极走线和所述第一公共走线、覆盖所述栅极走线和所述第一公共走线的层间绝缘层、以及设置于所述层间绝缘层上的源漏极走线和所述第二公共走线。
在本申请的阵列基板中，所述第二公共走线通过所述层间绝缘层上的过孔与所述第一公共走线电性连接，所述源漏极走线通过所述栅极绝缘层和所述层间绝缘层上的过孔与所述有源层电性连接。
在本申请的阵列基板中，所述阵列层与所述公共电极之间设置有平坦层，所述公共电极通过所述平坦层上的过孔与所述第二公共走线电性连接。
在本申请的阵列基板中，所述公共电极与所述像素电极之间设置有钝化层，所述像素电极通过钝化层及所述平坦层上的过孔与所述源漏极走线电性连接。
在本申请的阵列基板中，所述衬底基板上与所述有源层相对应的位置设置有遮光层，用于遮挡射向所述有源层的光线。
本申请还提供一种阵列基板的制作方法，包括以下步骤：
制作同层设置的第一公共走线和栅极走线，使所述第一公共走线形成不连续的线段状；
在所述第一公共走线和所述栅极走线上层制作同层设置的第二公共走线和源漏极走线，使所述第二公共走线与所述第一公共走线形成电性连接；
在所述第二公共走线和所述栅极走线上层制作公共电极，使所述公共电极与所述第二公共走线形成电性连接。
在本申请的阵列基板制作方法中，制作所述第一公共走线和所述栅极走线的步骤包括：制作第一金属层，并对所述第一金属层进行图案化处理，形成所述第一公共走线和所述栅极走线。
在本申请的阵列基板制作方法中，制作所述第二公共走线和所述源漏极走线的步骤包括：制作第二金属层，并对所述第二金属层进行图案化处理，形成所述第二公共走线和所述源漏极走线。
在本申请的阵列基板制作方法中，制作形成的所述第二公共走线上设置有断口，位于所述断口两侧的所述第二公共走线与同一条所述第一公共走线分别电性连接；所述源漏极走线与所述第二公共走线在所述断口处相交，且所述源漏极走线与所述第二公共走线彼此绝缘。
在本申请的阵列基板制作方法中，所述阵列基板的制作方法还包括以下步骤：
在所述公共电极的上层制作像素电极，并使所述像素电极与所述源漏极走线电性连接。
本申请还提供一种液晶显示面板，包括：
阵列基板，包括阵列层和公共电极，所述阵列层包括栅极走线、与所述栅极走线同层设置的第一公共走线、设置于所述栅极走线上的源漏极走线、及与所述源漏极走线同层设置的第二公共走线，所述第二公共走线与所述第一公共走线电性连接，所述第一公共走线为不连续线段，所述公共电极与所述第二公共走线电性连接；
与所述阵列基板相对设置的彩膜基板；以及
设置于所述阵列基板与所述彩膜基板之间的液晶层。
在本申请的液晶显示面板中，所述第二公共走线上设置有断口，位于所述断口两侧的所述第二公共走线与同一条所述第一公共走线分别电性连接。
在本申请的液晶显示面板中，所述源漏极走线与所述第二公共走线在所述断口处相交，且所述源漏极走线与所述第二公共走线彼此绝缘；
所述阵列基板的两侧设置有公共走线端，所述第二公共走线的两端连接至所述公共走线端。
 有益效果
本申请实施例提供的阵列基板、阵列基板制作方法及液晶显示面板，将与栅极走线同层的第一公共走线设置为不连续线段状，并与第二公共走线电性连接，进而对公共电极进行电压补充，保证了公共电极的电压分布均衡；同时不连续线段状的第一公共走线与栅极走线之间存在较多供刻蚀液流通的开口，因而在刻蚀操作完成后，刻蚀液更加容易被去除，防止因刻蚀液存积而导致第一公共走线和栅极走线过细或断线。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中制作阵列基板时刻蚀液在公共走线和栅极走线之间积存的示意图；
图2是本申请实施例提供的阵列基板的平面透视结构示意图；
图3是本申请实施例提供的阵列基板的截面结构示意图；
图4是本申请实施例提供的阵列基板制作方法流程图；
图5是本申请实施例提供的阵列基板制作方法中制作完成第一金属层后的结构示意图；
图6是本申请实施例提供的阵列基板制作方法中对第一金属层图案化后的结构示意图；
图7是本申请实施例提供的阵列基板制作方法中制作完成第二金属层后的结构示意图；
图8是本申请实施例提供的阵列基板制作方法中对第二金属层图案化后的结构示意图；
图9是本申请实施例提供的阵列基板制作方法制得的阵列基板结构示意图；
图10是本申请实施例提供的液晶显示面板结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请提供一种阵列基板，所述阵列基板包括与栅极走线同层设置的不连续线段状的第一公共走线，以及与源漏极走线同层设置的第二公共走线，利用所述第一公共走线和所述第二公共走线对公共电极进行电压补充；不连续线段状的所述第一公共走线与所述栅极走线之间存在较多供刻蚀液流通的开口，从而在刻蚀操作完成后，存在于所述第一公共走线和所述栅极走线之间的刻蚀液容易被去除，防止出现因刻蚀液存积而导致的第一公共走线和栅极走线过细或断线的问题。
如图2和图3所示，其中图2是本申请实施例提供的阵列基板的平面透视结构示意图，图3是本申请实施例提供的阵列基板的截面结构示意图。所述阵列基板10包括阵列层13以及设置于所述阵列层13上的公共电极15。可选地，所述阵列基板10还可以包括衬底基板11、设置于所述衬底基板11上的缓冲层12、设置于所述阵列层13与所述公共电极15之间的平坦层14、设置于所述公共电极15上的钝化层16、以及设置于所述钝化层16上的像素电极17。
需要说明的是，本申请中，关于“一个元素设置在另一个元素上”的描述，仅用于说明两个元素之间的相对位置关系，这两个元素之间可以设置有其它元素，也可以不设置其它元素。
所述衬底基板11可以是硬质基板，也可以是柔性基板；当所述衬底基板11是硬质基板时，其可以选用玻璃等硬质材料制作；所述衬底基板11为柔性基板时，其可以选用聚酰亚胺等柔性材料制作。
所述缓冲层12设置于所述衬底基板11上，用于平衡所述衬底基板11与所述阵列层13之间的性能差异。所述缓冲层12靠近所述衬底基板11的一侧，或靠近所述阵列层13的一侧设置有遮光层121，用于遮挡射向所述阵列层13中的有源层132的光线。
所述阵列层13包括栅极走线133和设置于所述栅极走线133上的源漏极走线136，所述阵列层13还包括与所述栅极走线133同层设置的第一公共走线134、以及与所述源漏极走线136同层设置的第二公共走线137。可选地，所述阵列层13还包括有源层132、栅极绝缘层131、以及层间绝缘层135。所述有源层132设置于所述缓冲层12上，所述有源层132由半导体材料制作而成，例如可以是金属氧化物半导体或低温多晶硅半导体，所述有源层132的两端分别通过离子掺杂工艺形成源极和漏极，所述有源层132的中间区域形成连接源极和漏极的沟道区；所述栅极绝缘层131设置于所述缓冲层12上且覆盖所述有源层132，所述栅极绝缘层131可以由氮化硅、氧化硅等陶瓷材料制作；所述栅极走线133和所述第一公共走线134设置于所述栅极绝缘层131上；所述层间绝缘层135设置于所述栅极绝缘层131上且覆盖所述栅极走线133和所述第一公共走线134，所述层间绝缘层135可以由氮化硅、氧化硅等陶瓷材料制作；所述源漏极走线136和所述第二公共走线137设置于所述层间绝缘层135上，所述源漏极走线136通过所述层间绝缘层135和所述栅极绝缘层131上的过孔与所述有源层132的源极和漏极电性连接，所述第二公共走线137通过所述层间绝缘层135上的过孔与所述第一公共走线134电性连接。
如图2所示，所述第一公共走线134为不连续线段，在与所述栅极走线133的延伸方向一致的方向上，并排设置有多个不连续线段状的所述第一公共走线134。可选地，并排设置的多个所述第一公共走线134与所述栅极走线133平行。需要说明的是，在本实施例中，与所述栅极走线133并排设置的所述第一公共走线134均为不连续线段状，相邻两个所述第一公共走线134线段之间存在开口区域，在通过刻蚀工艺制作所述第一公共走线134和所述栅极走线133时，刻蚀液容易通过该开口区域去除，避免了刻蚀液在所述第一公共走线134和所述栅极走线133之间长时间难以去除而导致的线宽过细或断线的问题。
如图2和图3所示，所述第二公共走线137叠层于所述第一公共走线134的上层，沿所述第二公共走线137的延伸方向存在多个不连续的所述第一公共走线134线段，所述第二公共走线137对应每个所述第一公共走线134的位置均设置有断口137a，且位于所述断口137a两侧的所述第二公共走线137与同一条所述第一公共走线134分别电性连接，从而使位于所述断口137a两侧的所述第二公共走线137产生电性连接，形成所述第一公共走线134与所述第二公共走线137的跨层桥连结构。
进一步地，所述源漏极走线136与所述第二公共走线137在所述断口137a处相交，且与所述断口137a两侧的所述第二公共走线137之间不存电性连接，形成所述第二公共走线137与所述源漏极走线136彼此电性绝缘的布线结构。可选地，所述源漏极走线136与所述第二公共走线137垂直设置，且垂直相交的交点位于所述断口137a处。需要说明的是，所述栅极走线133与所述源漏极走线136在所述阵列基板10上围成多个格子区，每一个格子区对应所述阵列基板10上的一个子像素区。
如图2所示，所述阵列基板10的两侧分别设置有公共走线端101，所述第二公共走线137的两端分别电性连接至所述阵列基板10两侧的所述公共走线端101上。需要说明的是，所述公共走线端101用于向所述第二公共走线137传输公共电压信号；在所述第一公共走线134的电性连接作用下，所述公共电压信号在整条所述第二公共走线137上传输，并进一步传输至所述公共电极15（参考图2和图3），以保证所述公共电极15上的电压分布均衡。
所述阵列基板10的一侧还设置有数据信号控制端102，所述数据信号控制端102通过扇出走线103与所述源漏极走线136电性连接，用于向所述源漏极走线136传输数据信号，该数据信号进一步传输至所述像素电极17上（参考图2和图3所示），以调控所述像素电极17的电压状态。
如图3所示，所述公共电极15通过所述平坦层14上的过孔与所述第二公共走线137电性连接，从而保证所述第二公共走线137上的电压信号可以传输至所述公共电极15。可选地，每条所述第二公共走线137与所述公共电极15之间均存在多个电性连接点，使所述第二公共走线137传输的公共电压信号均匀地分布于所述公共电极15上，保证所述公共电极15上的电压分布均衡。
所述像素电极17通过所述钝化层16上的过孔和所述平坦层14上的过孔与所述源漏极走线136电性连接，且所述像素电极17与所述公共电极15之间保持电性绝缘，所述像素电极17接收所述源漏极走线136传输的数据信号而产生电场作用。需要说明的是，所述阵列基板10应用于液晶显示面板中时，所述公共电极15和所述像素电极17分别产生电场作用，液晶显示面板中的液晶在两电场作用下产生偏转以调整显示灰阶，进而使所述液晶显示面板产生不同画面。
综上所述，本申请实施例提供的阵列基板包括与栅极走线同层设置的不连续线段状的第一公共走线，以及与源漏极走线同层设置的第二公共走线，利用所述第一公共走线和所述第二公共走线对公共电极进行电压补充，保证公共电极电压分布均衡；不连续线段状的所述第一公共走线与所述栅极走线之间存在较多供刻蚀液流通的开口，从而在刻蚀操作完成后，存在于所述第一公共走线和所述栅极走线之间的刻蚀液容易被去除，防止出现因刻蚀液存积而导致的第一公共走线和栅极走线过细或断线的问题。
本申请实施例还提供一种阵列基板的制作方法，如图4所示，所述阵列基板的制作方法包括以下步骤：
步骤S1、如图6所示，制作同层设置的第一公共走线134和栅极走线133，使所述第一公共走线134形成不连续的线段状。具体包括以下步骤：
提供一基底；可选地，所述基底包括衬底基板11、设置于所述衬底基板11上的遮光层121、设置于所述衬底基板11上并覆盖所述遮光层121的缓冲层12、设置于所述缓冲层12上的有源层132、以及设置于所述有源层132上的栅极绝缘层131，其中，所述遮光层121用于遮挡射向所述有源层132的光线。
如图5所示，在所述基底上制作第一金属层M1；可选地，制作所述第一金属层M1的方法可以是气相沉积法或喷涂法。
如图6所示，对所述第一金属层M1进行图案化处理，形成所述第一公共走线134和所述栅极走线133，所述第一公共走线134为不连续线段状；可选地，对所述第一金属层M1进行图案化制程操作包括：涂布光刻胶、对光刻胶进行曝光和显影、以及对所述第一金属层M1进行图案化刻蚀。需要说明的是，本实施例制作形成的所述第一公共走线134为不连续线段状，因此相邻两个所述第一公共走线134线段之间形成开口区域，在使用刻蚀液对所述第一金属层M1刻蚀完成后，刻蚀液容易通过该开口区域去除，避免了刻蚀液在所述第一公共走线134和所述栅极走线133之间长时间难以去除而导致的线宽过细或断线的问题。
步骤S2、如图8所示，在所述第一公共走线134和所述栅极走线133上层制作同层设置的第二公共走线137和源漏极走线136，使所述第二公共走线137与所述第一公共走线134形成电性连接。具体包括以下步骤：
制作所述第二公共走线137和所述源漏极走线136之前，首先制作覆盖所述第一公共走线134和所述栅极走线133的层间绝缘层135，所述层间绝缘层135可以由氮化硅、氧化硅等陶瓷材料通过化学气相沉积工艺制作而成。
如图7所示，在所述层间绝缘层135上制作第二金属层M2，使所述第二金属层M2通过所述层间绝缘层135上的过孔与所述第一公共走线134电性连接，并通过所述层间绝缘层135和所述栅极绝缘层131上的过孔与所述有源层132电性连接；可选地，制作所述第二金属层M2的方法可以是气相沉积法或喷涂法。
如图8所示，对所述第二金属层M2进行图案化处理，形成所述第二公共走线137和所述源漏极走线136。可选地，对所述第二金属层M2进行图案化制程操作包括：涂布光刻胶、对光刻胶进行曝光和显影、以及对所述第二金属层M2进行图案化刻蚀。制作形成的所述第二公共走线137的对应每个所述第一公共走线134的位置均存在断口137a，且位于所述断口137a两侧的所述第二公共走线137与同一条所述第一公共走线134分别电性连接，从而使位于所述断口137a两侧的所述第二公共走线137产生电性连接，形成所述第一公共走线134与所述第二公共走线137的跨层桥连结构。形成的所述源漏极走线136与所述第二公共走线137在所述断口137a处相交，且所述第二公共走线137与所述源漏极走线136之间保持电性绝缘。
步骤S3、如图9所示，在所述第二公共走线137和所述栅极走线136上层制作公共电极15，使所述公共电极15与所述第二公共走线137形成电性连接。具体地，在制作所述公共电极15之前，还包括制作覆盖所述第二公共走线137和所述源漏极走线136的平坦层14，所述公共电极15通过所述平坦层14上的过孔与所述第二公共走线137电性连接。应当理解的是，利用所述第二公共走线137和所述第一公共走线134组成的公共电压传输线路向所述公共电极15传输公共电压，有利于所述公共电极15上的电压分布均衡。
可选地，所述阵列基板制作方法还包括：在所述公共电极15上制作钝化层16、以及在所述钝化层16上制作像素电极17，并使所述像素电极17与所述源漏极走线136电性连接。
综上所述，本申请实施例提供的阵列基板制作方法，制作形成的第一公共走线为不连续线段状，使第一公共走线与栅极走线之间存在较多供刻蚀液流通的开口，从而在刻蚀操作完成后，存在于所述第一公共走线和所述栅极走线之间的刻蚀液容易被去除，防止出现因刻蚀液存积而导致的第一公共走线和栅极走线过细或断线的问题，提高阵列基板的生产良率。
本申请实施例还提供一种液晶显示面板，如图10所示，所述液晶显示面板包括阵列基板10、与所述阵列基板10相对设置的彩膜基板20、以及设置于所述阵列基板10与所述彩膜基板20之间的液晶层30；其中，所述阵列基板10为本申请实施例所提供的阵列基板，或是通过本申请实施例提供的阵列基板制作方法制作而成的阵列基板。需要说明的是，本申请实施例提供的液晶显示面板，克服了制作过程中容易出现的刻蚀液积存而导致的第一公共走线和栅极走线过细或断线的问题，有利于提高生产良率。
需要说明的是，虽然本申请以具体实施例揭露如上，但上述实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括：
    阵列层，包括栅极走线和设置于所述栅极走线上的源漏极走线，所述阵列层还包括与所述栅极走线同层设置的第一公共走线、以及与所述源漏极走线同层设置的第二公共走线，所述第二公共走线与所述第一公共走线电性连接，所述第一公共走线为不连续线段；以及
    公共电极，设置于所述阵列层上，与所述第二公共走线电性连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第二公共走线上设置有断口，位于所述断口两侧的所述第二公共走线与同一条所述第一公共走线分别电性连接。
  3. 根据权利要求2所述的阵列基板，其中，所述源漏极走线与所述第二公共走线在所述断口处相交，且所述源漏极走线与所述第二公共走线彼此绝缘。
  4. 根据权利要求2所述的阵列基板，其中，沿所述第二公共走线的延伸方向设置有多个不连续的所述第一公共走线，所述第二公共走线对应每个所述第一公共走线的位置均设置有所述断口，且位于所述断口两侧的所述第二公共走线与同一条所述第一公共走线分别电性连接。
  5. 根据权利要求1所述的阵列基板，其中，所述阵列基板的两侧设置有公共走线端，所述第二公共走线的两端连接至所述公共走线端。
  6. 根据权利要求1所述的阵列基板，其中，所述第一公共走线与所述栅极走线平行。
  7. 根据权利要求1所述的阵列基板，其中，还包括设置于所述公共电极上的像素电极，所述像素电极与所述源漏极走线电性连接。
  8. 根据权利要求7所述的阵列基板，其中，所述阵列层设置于衬底基板上，所述阵列层包括设置于所述衬底基板上的有源层、覆盖所述有源层的栅极绝缘层、设置于所述栅极绝缘层上的所述栅极走线和所述第一公共走线、覆盖所述栅极走线和所述第一公共走线的层间绝缘层、以及设置于所述层间绝缘层上的源漏极走线和所述第二公共走线。
  9. 根据权利要求8所述的阵列基板，其中，所述第二公共走线通过所述层间绝缘层上的过孔与所述第一公共走线电性连接，所述源漏极走线通过所述栅极绝缘层和所述层间绝缘层上的过孔与所述有源层电性连接。
  10. 根据权利要求8所述的阵列基板，其中，所述阵列层与所述公共电极之间设置有平坦层，所述公共电极通过所述平坦层上的过孔与所述第二公共走线电性连接。
  11. 根据权利要求10所述的阵列基板，其中，所述公共电极与所述像素电极之间设置有钝化层，所述像素电极通过钝化层及所述平坦层上的过孔与所述源漏极走线电性连接。
  12. 根据权利要求8所述的阵列基板，其中，所述衬底基板上与所述有源层相对应的位置设置有遮光层，用于遮挡射向所述有源层的光线。
  13. 一种阵列基板的制作方法，其包括以下步骤：
    制作同层设置的第一公共走线和栅极走线，使所述第一公共走线形成不连续的线段状；
    在所述第一公共走线和所述栅极走线上层制作同层设置的第二公共走线和源漏极走线，使所述第二公共走线与所述第一公共走线形成电性连接；
    在所述第二公共走线和所述栅极走线上层制作公共电极，使所述公共电极与所述第二公共走线形成电性连接。
  14. 根据权利要求13所述的阵列基板制作方法，其中，制作所述第一公共走线和所述栅极走线的步骤包括：制作第一金属层，并对所述第一金属层进行图案化处理，形成所述第一公共走线和所述栅极走线。
  15. 根据权利要求13所述的阵列基板制作方法，其中，制作所述第二公共走线和所述源漏极走线的步骤包括：制作第二金属层，并对所述第二金属层进行图案化处理，形成所述第二公共走线和所述源漏极走线。
  16. 根据权利要求13所述的阵列基板制作方法，其中，制作形成的所述第二公共走线上设置有断口，位于所述断口两侧的所述第二公共走线与同一条所述第一公共走线分别电性连接；所述源漏极走线与所述第二公共走线在所述断口处相交，且所述源漏极走线与所述第二公共走线彼此绝缘。
  17. 根据权利要求13所述的阵列基板制作方法，其中，还包括以下步骤：
    在所述公共电极的上层制作像素电极，并使所述像素电极与所述源漏极走线电性连接。
  18. 一种液晶显示面板，其包括：
    阵列基板，包括阵列层和公共电极，所述阵列层包括栅极走线、与所述栅极走线同层设置的第一公共走线、设置于所述栅极走线上的源漏极走线、及与所述源漏极走线同层设置的第二公共走线，所述第二公共走线与所述第一公共走线电性连接，所述第一公共走线为不连续线段，所述公共电极与所述第二公共走线电性连接；；
    与所述阵列基板相对设置的彩膜基板；以及
    设置于所述阵列基板与所述彩膜基板之间的液晶层。
  19. 根据权利要求18所述的液晶显示面板，其中，所述第二公共走线上设置有断口，位于所述断口两侧的所述第二公共走线与同一条所述第一公共走线分别电性连接。
  20. 根据权利要求19所述的液晶显示面板，其中，所述源漏极走线与所述第二公共走线在所述断口处相交，且所述源漏极走线与所述第二公共走线彼此绝缘；
    所述阵列基板的两侧设置有公共走线端，所述第二公共走线的两端连接至所述公共走线端。
PCT/CN2020/112081 2020-08-19 2020-08-28 阵列基板、阵列基板制作方法及液晶显示面板 WO2022036748A1 (zh)

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