WO2019167456A1 - Condensateur à couches minces et son procédé de fabrication - Google Patents

Condensateur à couches minces et son procédé de fabrication Download PDF

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Publication number
WO2019167456A1
WO2019167456A1 PCT/JP2019/001075 JP2019001075W WO2019167456A1 WO 2019167456 A1 WO2019167456 A1 WO 2019167456A1 JP 2019001075 W JP2019001075 W JP 2019001075W WO 2019167456 A1 WO2019167456 A1 WO 2019167456A1
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dielectric film
lower electrode
layer
insulating layer
thin film
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PCT/JP2019/001075
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English (en)
Japanese (ja)
Inventor
信之 奥澤
大亮 廣瀬
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Tdk株式会社
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Priority to JP2020502849A priority Critical patent/JPWO2019167456A1/ja
Publication of WO2019167456A1 publication Critical patent/WO2019167456A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 

Definitions

  • the present disclosure relates to a thin film capacitor and a manufacturing method thereof.
  • thin film capacitors having various capacitor structures have been used as thin film capacitors.
  • a dielectric film is provided along the outer surface of the lower electrode layer on the substrate, and the upper electrode layer is provided on the lower electrode layer via the dielectric film.
  • a provided capacitor structure is disclosed.
  • the inventors have conducted research on capacitor structures applied to thin film capacitors, and by making the thickness of the dielectric film uniform, cracks and chips can be suppressed, and the reliability of the device can be improved. Obtained knowledge. As a result of intensive research, they discovered a new technology that can make the thickness of the dielectric film uniform in a thin film capacitor.
  • the present disclosure is intended to provide a thin film capacitor with improved reliability and a method for manufacturing the same.
  • a thin film capacitor according to an embodiment of the present disclosure includes a lower electrode layer, a dielectric film provided in contact with the upper surface of the lower electrode layer, and a plurality of upper electrode layers provided on the dielectric film.
  • the upper surface of the lower electrode layer and the upper surface of the lower insulating layer constitute the same surface, and the lower surface of the dielectric film is a flat surface over the entire dielectric film. Therefore, stress concentration is less likely to occur in the dielectric film, and the reliability of the thin film capacitor is improved by suppressing cracks, chips and the like due to the stress concentration.
  • a thin film capacitor according to another embodiment further includes an upper insulating layer that covers the upper electrode layer, and a plurality of terminals that are provided on the upper insulating layer and are electrically connected to the plurality of upper electrode layers, respectively.
  • the side surface of the layer and the side surface of the lower insulating layer constitute an element side surface.
  • the end of the dielectric film extends beyond the outer edge of the lower electrode layer when viewed from the stacking direction of the capacitor portion, and the end face of the dielectric film is exposed from the element side surface. Yes. In this case, since the contact area between the end portion of the dielectric film and the upper insulating layer and the lower insulating layer is increased, peeling of the dielectric film is suppressed.
  • the end of the dielectric film extends beyond the outer edge of the lower electrode layer when viewed from the stacking direction of the capacitor, and the end face of the dielectric film retreats from the side surface of the element. And not exposed from the side of the element. In this case, since the contact area between the end portion of the dielectric film and the upper insulating layer and the lower insulating layer is increased, peeling of the dielectric film is suppressed.
  • the upper insulating layer and the lower insulating layer may be made of the same material, and the upper insulating layer and the lower insulating layer may be made of different materials.
  • the upper electrode layer is located inside the outer edge of the lower electrode layer when viewed from the stacking direction of the capacitor portion. In this case, a thin film capacitor having a desired capacitance can be obtained even when the positional accuracy regarding the formation position of the upper electrode layer is not sufficiently high.
  • the lower electrode layer includes a lower electrode buffer layer formed over the entire upper surface, the lower electrode buffer layer is in contact with the dielectric film, and the lower electrode buffer layer is uniform Has a thickness. In this case, the breakdown voltage in the thin film capacitor can be improved.
  • the upper electrode buffer layer includes an upper electrode buffer layer formed over the entire lower surface, and the upper electrode buffer layer is in contact with the dielectric film, and the upper electrode buffer layer is uniform. Has a thickness. In this case, the breakdown voltage in the thin film capacitor can be improved.
  • a manufacturing method of a thin film capacitor includes a lower electrode layer, a dielectric film provided in contact with an upper surface of the lower electrode layer, and a plurality of upper electrodes provided on the dielectric film
  • a lower electrode layer forming step for forming a lower electrode layer on the lower surface of the dielectric film exposed in the transfer step, and a lower insulating layer covering the lower electrode layer on the lower surface of the dielectric film on which the lower electrode layer is formed Forming a lower insulating layer.
  • a thin film capacitor is obtained in which the upper surface of the lower electrode layer and the upper surface of the lower insulating layer constitute the same surface, and the lower surface of the dielectric film is flat over the entire dielectric film. It becomes a surface. For this reason, stress concentration is unlikely to occur in the dielectric film of the thin film capacitor, and cracks and chips caused by the stress concentration are suppressed, thereby improving the reliability of the thin film capacitor.
  • the lower electrode layer forming step includes a step of forming a lower electrode buffer layer having a uniform thickness over the entire lower surface of the dielectric film. In this case, the breakdown voltage of the thin film capacitor manufactured by this manufacturing method can be improved.
  • the upper electrode layer forming step includes a step of forming an upper electrode buffer layer having a uniform thickness on the upper surface of the dielectric film. In this case, the breakdown voltage of the thin film capacitor manufactured by this manufacturing method can be improved.
  • a manufacturing method of a thin film capacitor includes a lower electrode layer, a dielectric film provided in contact with an upper surface of the lower electrode layer, and a plurality of upper electrodes provided on the dielectric film
  • a method of manufacturing a thin film capacitor including a capacitor portion having a layer, a lower insulating layer preparation step of preparing a lower insulating layer having a cavity, and filling the cavity of the lower insulating layer and exposing from the cavity of the lower insulating layer
  • a lower electrode layer forming step for forming a lower electrode layer having an upper surface that is coplanar with the upper surface of the lower insulating layer, and a dielectric film covering the entire upper surface of the lower electrode layer exposed from the cavity of the lower insulating layer is formed.
  • a thin film capacitor is obtained in which the upper surface of the lower electrode layer and the upper surface of the lower insulating layer constitute the same surface, and the lower surface of the dielectric film is flat over the entire dielectric film. It becomes a surface. For this reason, stress concentration is unlikely to occur in the dielectric film of the thin film capacitor, and cracks and chips caused by the stress concentration are suppressed, thereby improving the reliability of the thin film capacitor.
  • a thin film capacitor with improved reliability and a method for manufacturing the same are provided.
  • FIG. 1 is a schematic cross-sectional view of a thin film capacitor according to an embodiment of the present disclosure. It is the figure which showed each process of the manufacturing method of the thin film capacitor shown in FIG. It is the figure which showed each process of the manufacturing method of the thin film capacitor shown in FIG. It is the schematic sectional drawing which showed the thin film capacitor of a different aspect. It is the schematic sectional drawing which showed the thin film capacitor of a different aspect. It is the schematic sectional drawing which showed the thin film capacitor of a different aspect. It is the figure which showed each process of the manufacturing method of a different aspect. It is the schematic sectional drawing which showed the thin film capacitor of a different aspect. It is the figure which showed each process of the manufacturing method of the thin film capacitor shown in FIG.
  • a thin film capacitor 10 includes a capacitance unit 20, a lower insulating layer 30, and an upper insulating layer 40.
  • the thin film capacitor 10 has a thickness of 0.125 mm and a planar size of 0.25 mm ⁇ 0.125 mm.
  • the capacitor unit 20 includes a dielectric film 21, a lower electrode 22 (lower electrode layer), and an electrode layer 24 (upper electrode layer) of the upper electrode 23.
  • the capacitor unit 20 has a configuration in which the lower electrode 22 and the electrode layer 24 of the upper electrode 23 face each other with the dielectric film 21 interposed therebetween.
  • the dielectric film 21 is made of a dielectric material such as SiN, has a substantially uniform thickness, and has a flat layer shape.
  • the thickness of the dielectric film 21 is, for example, 0.1 to 3.0 ⁇ m.
  • the lower electrode 22 is made of a metal material, and is made of Cu as an example.
  • the lower electrode 22 has a layer shape, and its thickness is, for example, 0.1 to 20 ⁇ m.
  • the lower electrode 22 is formed so as to fill the cavity 32 of the lower insulating layer 30 described later.
  • the upper electrode 23 includes a first upper electrode 23A and a second upper electrode 23B.
  • Each of the first upper electrode 23A and the second upper electrode 23B includes an electrode layer 24, a via conductor 25, and a terminal 26.
  • the electrode layer 24, the via conductor 25, and the terminal 26 are made of a metal material, and are made of Cu as an example.
  • the electrode layer 24A of the first upper electrode 23A and the electrode layer 24B of the second upper electrode 23B are both provided so as to be in contact with the upper surface 21a of the dielectric film 21 and have a layered shape.
  • the via conductor 25A of the first upper electrode 23A and the via conductor 25B of the second upper electrode 23B are both provided in the upper insulating layer 40 described later and provided on the upper surface of the upper insulating layer 40 from the electrode layer 24. Extending to the terminal 26. Both the terminal 26A of the first upper electrode 23A and the terminal 26B of the second upper electrode 23B are provided on the upper surface of the upper insulating layer 40, and are electrically connected to the electrode layer 24 through the via conductor 25. ing.
  • a plating layer 28 is formed on the surface of each terminal 26, and the plating layer 28 is composed of two layers, a Ni underlayer and an Au surface layer.
  • the lower insulating layer 30 is made of an insulating material, and a known inorganic material, organic material, ceramic material, or glass material can be used as the insulating material of the lower insulating layer 30.
  • the lower insulating layer 30 has a cavity 32 that houses the lower electrode 22 described above.
  • the cavity 32 is entirely filled with the lower electrode 22, and only the upper surface 22 a of the lower electrode 22 is exposed from the cavity 32. Therefore, the inner dimension of the cavity 32 and the outer dimension of the lower electrode 22 are substantially the same.
  • the upper surface 30a of the lower insulating layer 30 is flush with the upper surface 22a of the lower electrode 22 (that is, is flush with the upper surface 30a of the lower insulating layer 30 and the upper surface 22a of the lower electrode 22).
  • a flat surface is constructed.
  • the upper insulating layer 40 is made of an insulating material, and a known inorganic material, organic material, ceramic material, or glass material can be used as the insulating material of the upper insulating layer 40.
  • the upper insulating layer 40 covers the electrode layer 24 of the upper electrode 23.
  • a terminal 26 is provided on the upper surface 40 a of the upper insulating layer 40, and a via conductor 25 extending from the electrode layer 24 to the terminal 26 is provided through the upper insulating layer 40.
  • the side surface 40 b of the upper insulating layer 40 is in the same plane as the side surface 30 b of the lower insulating layer 30.
  • the lower insulating layer 30 and the upper insulating layer 40 may be made of the same material or different materials.
  • the thin film capacitor 10 functions as a circuit in which two capacitors are connected in series because a pair of upper electrodes 23A and 23B are opposed to a single lower electrode 22 via a dielectric film 21. That is, the upper electrode 23A, the dielectric film 21 and the lower electrode 22 constitute one capacitor, and the upper electrode 23B, the dielectric film 21 and the lower electrode 22 constitute the other capacitor.
  • the penetration wiring 27 which penetrates the dielectric film 21 between the electrode layer 24B and the lower electrode 22 of the upper electrode 23B, one capacitor was provided.
  • a thin film capacitor 10 may also be used.
  • the dielectric film 21 is provided on a flat surface constituted by the upper surface 30 a of the lower insulating layer 30 and the upper surface 22 a of the lower electrode 22. More specifically, the dielectric film 21 covers the entire upper surface 30 a of the lower insulating layer 30 and is provided across the upper surface 30 a of the lower insulating layer 30 and the upper surface 22 a of the lower electrode 22. In other words, the dielectric film 21 is provided so as to close the cavity 32 of the lower insulating layer 30.
  • the end portion of the dielectric film 21 extends beyond the outer edge (the edge of the cavity 32) of the lower electrode 22 when viewed from the stacking direction of the capacitor portion 20, and the end face 21 c of the dielectric film 21 is the side surface of the lower electrode 22. It has reached 30b.
  • the end face 21 c of the dielectric film 21 is exposed from the element side face constituted by the side face 30 b of the lower insulating layer 30 and the side face 40 b of the upper insulating layer 40. At this time, the end portion of the dielectric film 21 is sandwiched between the lower insulating layer 30 and the upper insulating layer 40 from the stacking direction of the capacitor portion 20.
  • the first substrate 50 is prepared as shown in FIG.
  • the first substrate 50 has a configuration in which a 200 nm thick SiO 2 film 51 is formed on a 725 ⁇ m thick Si substrate.
  • the dielectric film 21 is formed on the entire upper surface 50a so as to be in contact with the upper surface 50a of the first substrate 50 (dielectric film forming step).
  • the upper electrode 23 is formed on the upper surface 21a of the dielectric film 21 (upper electrode layer forming step).
  • a via conductor 25 is formed as shown in FIG.
  • An upper insulating layer 40 provided with an opening 42 is formed, and a via conductor 25, a terminal 26, and a plating layer 28 are formed as shown in FIG.
  • the second substrate 54 is attached to the first substrate 50 from the upper electrode 23 side using the adhesive 52, and the first substrate 50 is removed by etching.
  • the dielectric film 21 and the upper electrode 23 are transferred to the second substrate 54 (transfer process).
  • the second substrate 54 has high rigidity, and a constituent material and a thickness dimension that can realize high rigidity can be adopted.
  • the lower surface 21b of the dielectric film 21 is exposed by the transfer process.
  • the lower electrode 22 is formed on the lower surface 21b of the dielectric film 21 exposed in the transfer process (lower electrode layer forming process). At this time, the lower electrode 22 is formed to have a size smaller than the outer dimension of the dielectric film 21, and the outer edge of the lower surface 21 b of the dielectric film 21 is exposed from the lower electrode 22.
  • a lower insulating layer 30 covering the lower electrode 22 is formed on the lower surface 21b of the dielectric film 21 on which the lower electrode 22 is formed (lower insulating layer forming step).
  • the side surface and the lower surface of the lower electrode 22 are covered with the lower insulating layer 30, and the cavity 32 of the lower insulating layer 30 is formed.
  • the lower insulating layer 30 is in contact with the lower surface 21 b of the dielectric film 21 at the outer edge of the dielectric film 21.
  • the upper surface 22a of the lower electrode 22 and the upper surface 30a of the lower insulating layer 30 constitute the same surface.
  • the above-described thin film capacitor 10 is obtained by removing the adhesive 52 and the second substrate 54 used in the transfer process.
  • the upper surface 22a of the lower electrode 22 and the upper surface 30a of the lower insulating layer 30 constitute the same surface. Therefore, the lower surface 21 b of the dielectric film 21 is a flat surface over the entire dielectric film 21. In other words, the lower surface 21b of the dielectric film 21 is not formed with a step that may cause stress concentration. Therefore, in the thin film capacitor 10, the stress concentration in the dielectric film 21 is suppressed. Therefore, in the thin film capacitor 10, cracks, chips and the like due to the stress concentration are suppressed, and reliability is improved.
  • the dielectric film 21 covers the upper surface 22 a of the lower electrode 22, but does not cover the side surface of the lower electrode 22.
  • the dielectric film according to the prior art the dielectric film is provided along the upper surface and the side surface of the lower electrode provided on the flat substrate. Therefore, as the thickness of the lower electrode is increased, the dielectric with respect to the side surface of the lower electrode is increased. As a result, the contact of the film gradually decreases, and as a result, the dielectric film is easily cracked or chipped.
  • the thickness of the lower electrode 22 can be set to a desired element.
  • the thickness can be increased to a thickness where the characteristics can be obtained.
  • the thin film capacitor 10 can be used as a capacitor having a high Q value (so-called Hi-Q capacitor).
  • the thickness of the lower electrode 22 can be about 10 times the thickness of the electrode layer 24 of the upper electrode 23.
  • the end face 21 c of the dielectric film 21 is exposed from the element side face constituted by the side face 30 b of the lower insulating layer 30 and the side face 40 b of the upper insulating layer 40. Therefore, the position of the end face 21 c of the dielectric film 21 is the same as the position of the outer edge of the lower electrode 22, compared with the case where only the end face 21 c of the dielectric film 21 is in contact with the lower insulating layer 30 or the upper insulating layer 40.
  • the contact area between the end portion of the dielectric film 21 and the lower insulating layer 30 and the upper insulating layer 40 is increased. Therefore, in the thin film capacitor 10, peeling of the dielectric film 21 from the lower insulating layer 30 and the upper insulating layer 40 is suppressed.
  • the end face 21c of the dielectric film 21 retreats from the element side face constituted by the side face 30b of the lower insulating layer 30 and the side face 40b of the upper insulating layer 40 (that is, the element side face).
  • the configuration of the thin film capacitor 10 is different from the configuration of the thin film capacitor 10 in that it is not exposed from the side surface of the device.
  • the lower surface 21b of the dielectric film 21A is flat across the entire dielectric film 21. It is a surface. Therefore, also in the thin film capacitor 10 ⁇ / b> A, the reliability improvement is realized like the thin film capacitor 10 described above. Further, in the thin film capacitor 10A, like the thin film capacitor 10, the position of the end face 21c of the dielectric film 21 is the same as the position of the outer edge of the lower electrode 22, and only the end face 21c of the dielectric film 21 has the lower insulating layer 30 or the upper insulating layer.
  • the contact area between the end portion of the dielectric film 21A and the lower insulating layer 30 and the upper insulating layer 40 is increased as compared with the case where it is in contact with the layer 40, the lower insulating layer 30 and the upper portion of the dielectric film 21A are increased. Peeling from the insulating layer 40 is suppressed.
  • each electrode layer 24 of the upper electrodes 23A and 23B is located inside a predetermined distance d from the outer edge of the lower electrode 22 when viewed from the stacking direction of the capacitor portion 20.
  • the distance d can be designed to satisfy 0 ⁇ d ⁇ F / 2, where F is the length of the lower electrode 22 in the direction in which the upper electrodes 23A and 23B are arranged.
  • the lower surface 21b of the dielectric film 21A is flat over the entire dielectric film 21. It is a surface. Therefore, also in the thin film capacitor 10B, the reliability improvement is implement
  • the thin film capacitor 10 can be used as long as the shift amount is equal to or less than the distance d.
  • the capacity of is not changed. Therefore, in the thin film capacitor 10B, even when the positional accuracy regarding the formation position of the electrode layer 24 of the upper electrode 23 is not sufficiently high, the positional deviation at the time of forming the electrode layer 24 of the upper electrode 23 can be allowed to some extent. Thus, a thin film capacitor having a desired capacity can be obtained.
  • the thin film capacitor 10C shown in FIG. 6 is different from the structure of the thin film capacitor 10 in that the plate member 56 is provided on the entire lower surface 30c of the lower insulating layer 30, but the other structure is the same as the structure of the thin film capacitor 10. It is the same.
  • the plate member 56 can be made of Si, for example.
  • the lower surface 21b of the dielectric film 21A is flat across the entire dielectric film 21. It is a surface. Therefore, also in the thin film capacitor 10 ⁇ / b> C, as in the thin film capacitor 10 described above, an improvement in reliability is realized.
  • the handleability is improved compared to the extremely thin elements such as the thin film capacitors 10, 10A, and 10B described above.
  • the thin film capacitor 10 can be manufactured by other manufacturing methods instead of the manufacturing method described above.
  • the structure of the thin film capacitor 10 can also be realized by the manufacturing method shown in FIG.
  • a procedure for manufacturing the thin film capacitor 10 by the manufacturing method shown in FIG. 7 will be described.
  • the lower insulating layer 30 having the cavity 32 is prepared (lower insulating layer preparing step) as shown in FIG.
  • Si is used as the material of the lower insulating layer 30, and the lower insulating layer 30 has an upper surface 30 a and an SiN film 34 that constitutes the inner surface of the cavity 32.
  • the cavity 32 can be formed by, for example, reactive ion etching (RIE).
  • RIE reactive ion etching
  • the lower electrode 22 is formed (lower electrode layer forming step).
  • the lower electrode 22 is configured by Cu plating, for example. After plating, polishing treatment such as CMP can be performed so that the upper surface 22a of the lower electrode 22 and the upper surface 30a of the lower insulating layer 30 are flush with each other.
  • a dielectric film 21 covering the entire upper surface 22a of the lower electrode 22 exposed from the cavity 32 of the lower insulating layer 30 is formed (dielectric film forming step).
  • the dielectric film forming step when viewed from the stacking direction of the capacitor portion 20 (that is, in a plan view of FIG. 7C), the end portion of the dielectric film 21 forms the outer edge of the lower electrode 22 (the edge of the cavity 32).
  • the dielectric film 21 is formed so as to extend beyond the end face 21c of the dielectric film 21 to the side face 30b of the lower electrode 22.
  • the dielectric film 21 is formed by a vacuum film forming method.
  • the dielectric film 21 can also be formed by applying and firing a liquid material such as MOD. In that case, ashing may be performed before the dielectric film 21 is formed in the dielectric film forming step. Good.
  • the upper electrode 23 is formed on the upper surface 21a of the dielectric film 21 (upper electrode layer forming step), and the above-described thin film capacitor 10 is obtained.
  • the upper electrode layer forming step after forming each electrode layer 24 on the dielectric film 21 as shown in FIG. 7D, a via conductor 25 is formed as shown in FIG. 7E.
  • the upper insulating layer 40 provided with the opening 42 is formed, and the via conductor 25, the terminal 26, and the plating layer 28 are formed as shown in FIG.
  • the upper insulating layer 40 can be formed by applying polyimide, exposing and developing.
  • the terminal 26 can be formed by patterning by applying a predetermined resist, exposing, developing, and plating after forming a sputtered film.
  • the lower electrode 22 may be provided with a buffer layer on the upper surface 22a side. That is, as in the thin film capacitor 10D shown in FIG. 8, the upper surface 22a of the lower electrode 22 is constituted by the lower electrode buffer layer 61, and the lower electrode 22 is in contact with the dielectric film 21 in the lower electrode buffer layer 61. There may be.
  • the lower electrode buffer layer 61 is made of a material different from Cu of the lower electrode 22 and can be made of, for example, a sputtered layer of Ti or Cr.
  • the lower electrode buffer layer 61 is formed using the lower surface 21b of the dielectric film 21 as a film formation surface as described later, and is provided with a uniform thickness over the entire upper surface 22a of the lower electrode 22.
  • the thickness of the lower electrode buffer layer 61 is about 5 to 20 nm, for example, 10 nm. Since the lower electrode 22 includes the lower electrode buffer layer 61, the adhesion between the lower electrode 22 and the dielectric film 21 is improved, and the breakdown voltage is improved. Further, the lower electrode buffer layer 61 is provided with a uniform thickness of about 5 to 20 nm over the entire upper surface 22a of the lower electrode 22, so that an increase in electric resistance of the lower electrode buffer layer 61 is suppressed and high breakdown is achieved. Voltage can be realized.
  • the upper electrode 23 may be provided with a buffer layer on the lower surface 23a side. That is, as shown in FIG. 8, the lower surface 23 a of each upper electrode 23 may be configured by the upper electrode buffer layer 62, and the upper electrode 23 may be in contact with the dielectric film 21 in the upper electrode buffer layer 62. .
  • the upper electrode buffer layer 62 is made of a material different from Cu of the upper electrode 23 and can be made of, for example, a sputtered layer of Ti or Cr.
  • the upper electrode buffer layer 62 is formed with the upper surface 21a of the dielectric film 21 as a film formation surface as described later, and is provided with a uniform thickness over the entire lower surface 23a of the upper electrode 23.
  • the thickness of the upper electrode buffer layer 62 is about 5 to 20 nm, for example, 10 nm. Since each upper electrode 23 includes the upper electrode buffer layer 62, the adhesion between the upper electrode 23 and the dielectric film 21 is improved, and the breakdown voltage is improved. Further, since the upper electrode buffer layer 62 is provided with a uniform thickness of about 5 to 20 nm over the entire lower surface 23a of the upper electrode 23, high breakdown is suppressed while suppressing an increase in electric resistance of the upper electrode buffer layer 62. Voltage can be realized.
  • the dielectric film 21 is formed on the upper surface 50a of the first substrate 50 in the same manner as the process shown in FIG. Film formation step).
  • the lower electrode 22 including the lower electrode buffer layer 61 is formed on the lower surface 21b of the dielectric film 21 (lower electrode layer forming step).
  • a Cu layer is formed after forming a Ti layer to be the lower electrode buffer layer 61 by sputtering.
  • the upper surface 50 a of the first substrate 50 is covered with a polyimide film 35 that becomes a part of the lower insulating layer 30 together with the dielectric film 21 and the lower electrode 22 formed on the upper surface 50 a. Further, as shown in FIG.
  • the substrate 60 is attached to the first substrate 50 from the lower electrode 22 side by using an adhesive 36 which becomes a part of the lower insulating layer 30, and FIG. As shown in FIG. 2, the first substrate 50 is removed by etching, and the dielectric film 21 and the lower electrode 22 are transferred to the substrate 60 (transfer process).
  • the upper electrode 23 including the upper electrode buffer layer 62 is formed on the upper surface 21a of the dielectric film 21 (upper electrode layer forming step).
  • a Ti layer that becomes the upper electrode buffer layer 62 is formed on the upper surface 21a of the dielectric film 21 by sputtering, and each electrode layer 24 is formed.
  • an upper insulating layer 40 having an opening 42 for forming the via conductor 25 is formed, and the via conductor 25 and the terminal are formed as shown in FIG. 10 (c). 26, and a plating layer 28 is formed on the surface of the terminal 26 as shown in FIG. Thereby, the above-described thin film capacitor 10D is obtained.
  • the thin film capacitor 10 ⁇ / b> D may include any one of the lower electrode buffer layer 61 and the upper electrode buffer layer 62.
  • the inventors conducted the following experiment in order to confirm the effect of the breakdown voltage of the thin film capacitor including the lower electrode buffer layer and the upper electrode buffer layer described above.
  • each sample was made of the same material except for the constituent material of the lower electrode buffer layer (that is, the constituent material of the upper electrode buffer layer was Ti, the constituent material of the lower electrode and the upper electrode was Cu, and the constituent material of the dielectric film was SiN). .
  • the results were as shown in the table of FIG.
  • the inventors measured the breakdown voltage of the conventional thin film capacitor 110 having the configuration shown in FIG. 12 for comparison.
  • the thin film capacitor 110 has a configuration in which a lower electrode 122, a dielectric film 121, and an upper electrode 123 are sequentially formed on a substrate 60.
  • the lower electrode 122 has a lower electrode buffer layer 161 similar to the lower electrode buffer layer 61 described above, and the upper electrode 123 includes an upper electrode buffer layer 162 similar to the upper electrode buffer layer 62 described above.
  • the lower electrode buffer layer 161 and the upper electrode buffer layer 162 can be formed of, for example, a sputtered layer of Ti or Cr.
  • a dielectric film 121 is provided along the outer surface of the lower electrode 122, and the dielectric film 121 includes a concave portion and a convex portion. Therefore, stress concentration is likely to occur in the dielectric film 121, and cracks, chips, etc. due to the stress concentration may occur.
  • the thin film capacitor 110 has a configuration in which the dielectric film 121 is formed after the lower electrode 122 is formed. Therefore, the dielectric film 121 is also formed by applying and firing a liquid material such as MOD. The lower electrode 122 is exposed to a high temperature during firing. In this case, problems such as oxidation of the lower electrode 122 and diffusion of the constituent material (for example, Ti) of the lower electrode buffer layer 161 into the lower electrode 122 may occur.
  • the inventors prepared a plurality of samples each having a configuration similar to that of the thin film capacitor 110 and having different constituent materials for the lower electrode buffer layer, and measured the breakdown voltage for each sample.
  • Each sample was made of the same material except for the constituent material of the lower electrode buffer layer (that is, the constituent material of the upper electrode buffer layer was Ti, the constituent material of the lower electrode and the upper electrode was Cu, and the constituent material of the dielectric film was SiN). .
  • the results were as shown in the table of FIG.
  • sample No. in FIG. 14 has a configuration in which the lower electrode buffer layer is removed from the configuration of the thin film capacitor 110.
  • the lower electrode buffer layer 61 and the upper electrode buffer layer 62 extend in a predetermined plane and are provided with a uniform thickness.
  • a high breakdown voltage can be realized.
  • a thin film capacitor having high reliability can be obtained.
  • the configuration of the above-described thin film capacitors 10, 10A to 10D unlike the configuration of the thin film capacitor 110 according to the prior art, it is manufactured by the procedure of forming the dielectric film 21 before the lower electrode 22 is formed. Therefore, the situation where the lower electrode 22 is exposed to a high temperature can be avoided. Therefore, a wide variety of materials (for example, materials having a relatively low electrical resistance) can be employed as the constituent material of the lower electrode 22 and the lower electrode buffer layer 61.
  • the present disclosure has been described above. However, the present disclosure is not limited to the above-described embodiments, and various changes can be made.
  • the number of upper electrodes 23 is not limited to two, and can be appropriately increased to, for example, four.
  • the lower electrode 22 can be divided into a plurality of parts.

Abstract

L'invention concerne un condensateur à couches minces 10 dans lequel une surface supérieure 22a d'une électrode inférieure 22 et une surface supérieure 30a d'une couche isolante inférieure 30 constituent le même plan. Par conséquent, une surface inférieure 21b d'un film diélectrique 21 comprend une surface plate sur tout le film diélectrique 21. En d'autres termes, sur la surface inférieure 21b du film diélectrique 21, aucun échelon qui pourrait provoquer une concentration de contraintes n'est formé. Par conséquent, dans le condensateur à couches minces 10, une concentration de contraintes dans le film diélectrique 21 est supprimée. Par conséquent, dans le condensateur à couches minces 10, une fissuration, un écaillage et analogues dus à la concentration de contraintes sont supprimés et la fiabilité est améliorée.
PCT/JP2019/001075 2018-02-28 2019-01-16 Condensateur à couches minces et son procédé de fabrication WO2019167456A1 (fr)

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JP2020502849A JPWO2019167456A1 (ja) 2018-02-28 2019-01-16 薄膜キャパシタおよびその製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0722725A (ja) * 1993-06-22 1995-01-24 Shinko Electric Ind Co Ltd 薄膜コンデンサ付回路基板及びその製造方法
JP2007116177A (ja) * 2005-10-21 2007-05-10 E I Du Pont De Nemours & Co 電力コアデバイスおよびその製造方法
JP2014222656A (ja) * 2010-04-28 2014-11-27 株式会社村田製作所 誘電体材料、およびそれを用いた薄膜コンデンサ
WO2017026233A1 (fr) * 2015-08-10 2017-02-16 株式会社村田製作所 Condensateur

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0722725A (ja) * 1993-06-22 1995-01-24 Shinko Electric Ind Co Ltd 薄膜コンデンサ付回路基板及びその製造方法
JP2007116177A (ja) * 2005-10-21 2007-05-10 E I Du Pont De Nemours & Co 電力コアデバイスおよびその製造方法
JP2014222656A (ja) * 2010-04-28 2014-11-27 株式会社村田製作所 誘電体材料、およびそれを用いた薄膜コンデンサ
WO2017026233A1 (fr) * 2015-08-10 2017-02-16 株式会社村田製作所 Condensateur

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