WO2019165975A1 - GaN基器件欧姆接触电极的制备方法 - Google Patents

GaN基器件欧姆接触电极的制备方法 Download PDF

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WO2019165975A1
WO2019165975A1 PCT/CN2019/076323 CN2019076323W WO2019165975A1 WO 2019165975 A1 WO2019165975 A1 WO 2019165975A1 CN 2019076323 W CN2019076323 W CN 2019076323W WO 2019165975 A1 WO2019165975 A1 WO 2019165975A1
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ohmic contact
contact electrode
dielectric layer
layer
region
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PCT/CN2019/076323
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English (en)
French (fr)
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谭永亮
付兴中
胡泽先
刘相伍
张力江
崔玉兴
付兴昌
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中国电子科技集团公司第十三研究所
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Priority to JP2020542489A priority Critical patent/JP6976451B2/ja
Priority to US16/968,977 priority patent/US11239081B2/en
Publication of WO2019165975A1 publication Critical patent/WO2019165975A1/zh

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    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2258—Diffusion into or out of AIIIBV compounds
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
    • H01L21/0425—Making electrodes
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/3105—After-treatment
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present application belongs to the field of semiconductor technology, and in particular, to a method for preparing an ohmic contact electrode of a GaN-based device.
  • the wide bandgap semiconductor GaN has the advantages of large forbidden band width, high two-dimensional electron gas density combined with AlGaN, high breakdown field strength, high electron saturation drift speed, etc., and has great advantages in high-temperature microwave power devices and high-speed power electronic device manufacturing. potential.
  • a good ohmic contact electrode not only improves the performance of the device, but also helps to increase the lifetime of the device.
  • the conventional method of forming an ohmic contact electrode is to form a ohmic contact electrode by rapid thermal annealing of a metal layer at a temperature higher than 800 ° C.
  • the ohmic contact electrode formed by this method is inferior in quality, and a metal surface morphology exists after annealing. Roughness, irregular metal edges and other shortcomings can cause problems such as electrical breakdown, device reliability and reduced lifetime.
  • the embodiments of the present application provide a method for preparing an ohmic contact electrode of a GaN-based device to solve the problem of poor quality of an ohmic contact electrode formed in the prior art.
  • the embodiment of the present application provides a method for preparing an ohmic contact electrode of a GaN-based device, comprising the following steps:
  • Step S1 growing a first dielectric layer on an upper surface of the device
  • Step S2 implanting silicon ions and/or indium ions in a region corresponding to the first dielectric layer and the ohmic contact electrode region and the ohmic contact electrode region of the device;
  • Step S3 growing a second dielectric layer on an upper surface of the first dielectric layer
  • Step S4 activating the silicon ions and/or the indium ions by a high temperature annealing process to form an N-type heavily doped;
  • Step S5 removing portions of the first dielectric layer and the second dielectric layer corresponding to the ohmic contact electrode regions, respectively;
  • Step S6 growing a metal layer on the upper surface of the ohmic contact electrode region of the device to form an ohmic contact electrode.
  • step S2 specifically includes the following steps:
  • Step S21 coating a first photoresist layer on an upper surface of a portion of the first dielectric layer corresponding to the first region, wherein the first region is an area of the device other than the ohmic contact electrode region ;
  • Step S22 implanting the silicon ions and/or the indium ions by ion implantation
  • Step S23 removing the first photoresist layer.
  • step S3 and the step S4 specifically include the following steps:
  • Step S31 coating a second photoresist layer on an upper surface of a portion of the second dielectric layer corresponding to the first region;
  • Step S32 removing portions corresponding to the first dielectric layer and the second dielectric layer and the ohmic contact electrode region by a dry etching process
  • Step S33 evaporating the metal layer on the upper surface of the device by an electron beam evaporation process
  • Step S34 removing the second photoresist layer.
  • the first dielectric layer is a SiN layer or a SiO 2 layer; and the first dielectric layer has a thickness of 10 nm to 50 nm.
  • the second dielectric layer is a SiN layer or an AlN layer; and the second dielectric layer has a thickness of 10 nm to 200 nm.
  • the silicon ion has an implantation energy of 30 keV to 200 keV, an implantation dose of 10 14 cm -2 to 10 16 cm -2 ;
  • the indium ion has an implantation energy of 30 keV to 200 keV, and the implantation dose is 10 13 cm - 2 to 10 16 cm -2 ;
  • the metal layer comprises a Ti/Au layer, a Ti/Pt/Au layer, a Ti/Al layer or a Ti/Al/Ni/Au layer.
  • the silicon ions and/or indium ions are implanted to a depth of 80 nm to 120 nm.
  • the high temperature annealing process has the following conditions: an annealing temperature of 850 ° C to 1400 ° C, and a time of 10 minutes to 60 minutes.
  • silicon ions and/or indium ions are implanted in an ohmic contact electrode region of the device and a portion corresponding to the first dielectric layer and the ohmic contact electrode region, Forming a second dielectric layer as a protective layer on the upper surface of the first dielectric layer, and activating the silicon ions and/or indium ions by a high temperature annealing process to form an N-type heavily doped, and finally, removing the first dielectric layer and the second dielectric layer
  • the portion corresponding to the ohmic contact electrode region exposes the ohmic contact electrode region of the device, and a metal layer is grown on the upper surface of the ohmic contact electrode region of the device to form an ohmic contact electrode, since the metal layer does not need to undergo a high temperature annealing process, thereby preparing A good quality ohmic contact electrode ensures that the surface of
  • FIG. 1 is a schematic flow chart showing an implementation process of a method for preparing an ohmic contact electrode of a GaN-based device according to an embodiment of the present application
  • FIG. 2 is a schematic structural flow diagram of a method for preparing an ohmic contact electrode of a GaN-based device according to an embodiment of the present application.
  • a method for preparing an ohmic contact electrode of a GaN-based device includes the following steps:
  • step S1 a first dielectric layer is grown on the upper surface of the device.
  • the first dielectric layer is a SiN layer or a SiO 2 layer, and has a thickness of 10 nm to 50 nm as a scattering layer for ion implantation in a subsequent process.
  • the GaN-based device in the embodiment of the present application includes a GaN substrate 201 and an AlGaN layer 202.
  • the GaN-based device is divided into an ohmic contact electrode region and a first region, wherein the first region is the device.
  • An ohmic contact electrode is prepared in an ohmic contact electrode region of the GaN-based device in a region other than the ohmic contact electrode region.
  • a first dielectric layer 203 is deposited on the upper surface of the AlGaN layer 202 by chemical vapor deposition (CVD) as a scattering layer for ion implantation.
  • CVD chemical vapor deposition
  • step S2 silicon ions and/or indium ions are implanted in a region of the first dielectric layer corresponding to the ohmic contact electrode region and the ohmic contact electrode region of the device.
  • the implantation energy of the silicon ions is 30 keV to 200 keV, and the implantation dose is 10 14 cm -2 to 10 16 cm -2 .
  • the implantation energy of indium ions is 30 keV to 200 keV, and the implantation dose is 10 13 cm -2 to 10 16 cm -2 .
  • step S2 is: applying a first photoresist layer on an upper surface of a portion of the first dielectric layer corresponding to the first region, wherein the first region is the device The ohmic contact region outside the electrode region; implanting the silicon ions and/or the indium ions by ion implantation; removing the first photoresist layer.
  • the first photoresist layer 204 is covered on the upper surface of the portion corresponding to the first region of the first dielectric layer 203 by a glue coating, exposure, development, and hard film process.
  • the portion of the first dielectric layer 203 corresponding to the ohmic contact electrode region is exposed, wherein the first photoresist layer 204 has a thickness of 2 micrometers to 5 micrometers.
  • silicon ions and/or indium ions are implanted into the device by ion implantation, wherein only the portion of the exposed first dielectric layer 204 corresponding to the ohmic contact electrode region and the ohmic contact electrode region of the device are implanted with ions, as shown in FIG. 2 (FIG. 2) 5)
  • the dotted line region shown in 205 the remaining portion is protected from ions by the first photoresist layer 204, and finally, the first photoresist layer 204 is removed.
  • Step S3 growing a second dielectric layer on the upper surface of the first dielectric layer.
  • the second dielectric layer 206 includes a SiN layer or an AlN layer, and the second dielectric layer 206 has a thickness of 10 nm to 200 nm.
  • the second dielectric layer 206 acts as a protective layer for the subsequent high temperature annealing process.
  • the second dielectric layer 206 is grown on the upper surface of the first dielectric layer 203 by CVD.
  • step S4 the silicon ions and/or the indium ions are activated by a high temperature annealing process to form an N-type heavily doped.
  • the annealing temperature is 850 ° C to 1400 ° C, and the time is 10 minutes to 60 minutes.
  • the implanted silicon ions and/or indium ions are activated by a high temperature annealing process to form an N-type heavily doped.
  • Step S5 removing portions of the first dielectric layer and the second dielectric layer corresponding to the ohmic contact electrode regions, respectively.
  • step S6 a metal layer is grown on the upper surface of the ohmic contact electrode region of the device to form an ohmic contact electrode.
  • the metal layer is a Ti/Au layer, a Ti/Pt/Au layer, a Ti/Al layer, or a Ti/Al/Ni/Au layer.
  • step S5 and step S6 is: coating the upper surface region of the portion of the second dielectric layer 206 corresponding to the first region a second photoresist layer 207; respectively removing portions of the first dielectric layer 203 and the second dielectric layer 206 corresponding to the ohmic contact electrode region by a dry etching process; evaporating the metal by an electron beam evaporation process Layer 208; removing the second photoresist layer 207.
  • the second photoresist layer 207 is covered on the upper surface of the portion corresponding to the first region of the second dielectric layer 206 by a glue coating, exposure, development, and hard film process to expose the second dielectric layer 206.
  • the portions of the first dielectric layer 203 and the second dielectric layer 206 corresponding to the ohmic contact regions are respectively removed by a dry etching process to expose the ohmic contact regions of the device.
  • the metal layer 208 is evaporated by an electron beam evaporation process, and finally the second photoresist layer 207 is removed.
  • Metal layer 208 is in contact with N-type heavily doped AlGaN layer 202 to form an ohmic contact.
  • silicon ions and/or indium are implanted in the ohmic contact electrode region of the device and the first dielectric layer 203 corresponding to the ohmic contact electrode region by growing the first dielectric layer 203 as an ion implantation scattering layer on the upper surface of the device.
  • the second dielectric layer 206 is grown as a protective layer on the upper surface of the first dielectric layer 203, and the silicon ions and/or indium ions are activated by a high temperature annealing process to form an N-type heavily doped.
  • the first dielectric layer 203 is removed.
  • a portion corresponding to the second dielectric layer 206 and the ohmic contact electrode region exposing the ohmic contact electrode region of the device, and growing the metal layer 208 on the upper surface of the ohmic contact electrode region of the device, thereby forming an ohmic contact electrode, since the metal layer is not required
  • a good quality ohmic contact electrode is prepared, which can ensure that the surface of the metal layer is smooth, the edges are smooth and tidy, the breakdown voltage of the device is stable, the reliability and the service life are long.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

一种GaN基器件欧姆接触电极的制备方法，该方法包括以下步骤：在器件的上表面生长第一介质层（203）（S1）；在所述第一介质层（203）与欧姆接触电极区对应的区域和所述器件的所述欧姆接触电极区注入硅离子和/或铟离子（S2）；在所述第一介质层（203）的上表面生长第二介质层（206）（S3）；通过高温退火工艺激活所述硅离子和/或所述铟离子，形成N型重掺杂（S4）；分别去除所述第一介质层（203）和所述第二介质层（206）与所述欧姆接触电极区对应的部分（S5）；在所述器件的所述欧姆接触电极区的上表面生长金属层（208），形成欧姆接触电极（S6）。由所述方法制备的欧姆接触电极能够保证金属层（208）表面平整、边缘光滑整齐，器件击穿电压稳定、可靠性和寿命长。

Description

GaN基器件欧姆接触电极的制备方法
本申请申明享有2018年2月28日递交的申请号为2018101668418、名称为“GaN基器件欧姆接触电极的制备方法”中国专利申请的优先权，该中国专利申请的整体内容以参考的方式结合在本申请中。
技术领域
本申请属于半导体技术领域，尤其涉及一种GaN基器件欧姆接触电极的制备方法。
 背景技术
宽禁带半导体GaN具有禁带宽度大、与AlGaN结合二维电子气密度高、击穿场强高、电子饱和漂移速度高等优点，在高温微波功率器件以及高速电力电子器件制造领域具有很大的潜力。在GaN基器件中，良好的欧姆接触电极不仅可以改善器件的性能，而且还利于提高器件的使用寿命。传统的形成欧姆接触电极的方法是将金属层在高于800℃的温度下经快速热退火形成欧姆接触电极，但是，这种方法形成的欧姆接触电极质量差，在退火后存在金属表面形貌粗糙、金属边缘不齐整等缺点，会造成器件容易发生电击穿现象、器件可靠性和寿命降低等问题。
 技术问题
有鉴于此，本申请实施例提供了一种GaN基器件欧姆接触电极的制备方法，以解决现有技术中形成的欧姆接触电极质量差的问题。
 技术解决方案
本申请实施例的提供了一种GaN基器件欧姆接触电极的制备方法，包括以下步骤：
步骤S1：在器件的上表面生长第一介质层；
步骤S2：在所述第一介质层与欧姆接触电极区对应的区域和所述器件的所述欧姆接触电极区注入硅离子和/或铟离子；
步骤S3：在所述第一介质层的上表面生长第二介质层；
步骤S4：通过高温退火工艺激活所述硅离子和/或所述铟离子，形成N型重掺杂；
步骤S5：分别去除所述第一介质层和所述第二介质层与所述欧姆接触电极区对应的部分；
步骤S6：在所述器件的所述欧姆接触电极区的上表面生长金属层，形成欧姆接触电极。
可选的，所述步骤S2具体包括以下步骤：
步骤S21：在所述第一介质层与第一区域对应的部分的上表面涂覆第一光刻胶层，其中，所述第一区域为所述器件除所述欧姆接触电极区以外的区域；
步骤S22：通过离子注入法注入所述硅离子和/或所述铟离子；
步骤S23：去除所述第一光刻胶层。
可选的，所述步骤S3和步骤S4具体包括以下步骤：
步骤S31：在所述第二介质层与所述第一区域对应的部分的上表面涂覆第二光刻胶层；
步骤S32：通过干法刻蚀工艺分别去除所述第一介质层和所述第二介质层与所述欧姆接触电极区对应的部分；
步骤S33：通过电子束蒸发工艺在所述器件的上表面蒸发所述金属层；
步骤S34：去除所述第二光刻胶层。
可选的，所述第一介质层为SiN层或SiO 2层；所述第一介质层的厚度为10纳米至50纳米。
可选的，所述第二介质层为SiN层或AlN层；所述第二介质层的厚度为10纳米至200纳米。
可选的，所述硅离子的注入能量为30keV至200keV，注入剂量为10 14cm -2至10 16cm -2；所述铟离子的注入能量为30keV至200keV，注入剂量为10 13cm -2至10 16cm -2；
可选的，所述金属层包括Ti/Au层、Ti/Pt/Au层、Ti/Al层或Ti/Al/Ni/Au层。
可选的，所述硅离子和/或铟离子的注入深度为80纳米至120纳米。
可选的，所述高温退火工艺的工艺条件为：退火温度为850℃至1400℃，时间为10分钟至60分钟。
 有益效果
本申请实施例通过在器件的上表面生长第一介质层作为离子注入散射层，在器件的欧姆接触电极区和第一介质层与欧姆接触电极区对应的部分注入硅离子和/或铟离子，在第一介质层的上表面生长第二介质层作为保护层，并通过高温退火工艺激活硅离子和/或铟离子，形成N型重掺杂，最后，去除第一介质层和第二介质层与欧姆接触电极区对应的部分，露出器件的欧姆接触电极区，在器件的欧姆接触电极区的上表面生长金属层，即可形成欧姆接触电极，由于金属层不需要经过高温退火工艺，从而制备出质量良好的欧姆接触电极，能够保证金属层表面平整、边缘光滑整齐，器件击穿电压稳定、可靠性和寿命长。
 附图说明
图1是本申请实施例提供的GaN基器件欧姆接触电极的制备方法的实现流程示意图；
图2是本申请实施例提供的GaN基器件欧姆接触电极的制备方法的结构实现流程示意图。
本申请的实施方式
为了说明本申请所述的技术方案，下面通过具体实施例来进行说明。
请参考图1，GaN基器件欧姆接触电极的制备方法包括以下步骤：
步骤S1，在器件的上表面生长第一介质层。
在本申请实施例中，第一介质层为SiN层或SiO 2层，厚度为10纳米至50纳米，作为后续工艺中离子注入的散射层。
请参考图2（1），本申请实施例中的GaN基器件包括GaN衬底201和AlGaN层202，GaN基器件分为欧姆接触电极区和第一区域，其中第一区域为所述器件除欧姆接触电极区以外的区域，在GaN基器件的欧姆接触电极区制备欧姆接触电极。请参考图2（2），通过化学气相沉积法（chemical vapor deposition, CVD）在AlGaN层202的上表面淀积第一介质层203，作为离子注入的散射层。
步骤S2，在所述第一介质层与欧姆接触电极区对应的区域和所述器件的所述欧姆接触电极区注入硅离子和/或铟离子。
在本申请实施例中，硅离子的注入能量为30keV至200keV，注入剂量为10 14cm -2至10 16cm -2。铟离子的注入能量为30keV至200keV，注入剂量为10 13cm -2至10 16cm -2。
可选的，步骤S2的具体实现方式为：在所述第一介质层与第一区域对应的部分的上表面涂覆第一光刻胶层，其中，所述第一区域为所述器件除所述欧姆接触电极区以外的区域；通过离子注入法注入所述硅离子和/或所述铟离子；去除所述第一光刻胶层。
请参考图2（3）至图2（5），通过涂胶、曝光、显影、坚膜工艺，在第一介质层203与第一区域对应的部分的上表面覆盖第一光刻胶层204，露出第一介质层203与欧姆接触电极区对应的部分，其中，第一光刻胶层204的厚度为2微米至5微米。再通过离子注入法在器件中注入硅离子和/或铟离子，其中，只有露出的第一介质层204与欧姆接触电极区对应的部分和器件的欧姆接触电极区被注入离子，如图2（5）中205所示的虚线区域，其余部分由于有第一光刻胶层204保护不会被注入离子，最后，去除第一光刻胶层204。
步骤S3，在所述第一介质层的上表面生长第二介质层。
在本申请实施例中，请参考图2（6），第二介质层206包括SiN层或AlN层，第二介质层206的厚度为10纳米至200纳米。第二介质层206作为后续高温退火工艺的保护层。通过CVD在第一介质层203的上表面生长第二介质层206。
步骤S4，通过高温退火工艺激活所述硅离子和/或所述铟离子，形成N型重掺杂。
在本申请实施例中，退火温度为850℃至1400℃，时间为10分钟至60分钟。通过高温退火工艺激活注入的硅离子和/或铟离子，形成N型重掺杂。
步骤S5，分别去除所述第一介质层和所述第二介质层与所述欧姆接触电极区对应的部分。
步骤S6，在所述器件的所述欧姆接触电极区的上表面生长金属层，形成欧姆接触电极。
在本申请实施例中，金属层为Ti/Au层、Ti/Pt/Au层、Ti/Al层或Ti/Al/Ni/Au层。
请参考图2（7）至图2（10），步骤S5和步骤S6的具体实现方式为：在所述第二介质层206的与所述第一区域对应的部分的上表面域涂覆第二光刻胶层207；通过干法刻蚀工艺分别去除所述第一介质层203和所述第二介质层206与所述欧姆接触电极区对应的部分；通过电子束蒸发工艺蒸发所述金属层208；去除所述第二光刻胶层207。
在本申请实施例中，通过涂胶、曝光、显影、坚膜工艺，在第二介质层206与第一区域对应的部分的上表面覆盖第二光刻胶层207，露出第二介质层206与欧姆接触电极区对应的部分，其中，第二光刻胶层207的厚度为1微米至2微米。通过干法刻蚀工艺分别去除第一介质层203和第二介质层206与欧姆接触区域对应的部分，露出器件的欧姆接触区域。通过电子束蒸发工艺蒸发金属层208，最后去除第二光刻胶层207。金属层208与N型重掺杂的AlGaN层202接触形成欧姆接触。
本申请实施例通过在器件的上表面生长第一介质层203作为离子注入散射层，在器件的欧姆接触电极区和与欧姆接触电极区对应的第一介质层203中注入硅离子和/或铟离子，在第一介质层203的上表面生长第二介质层206作为保护层，并通过高温退火工艺激活硅离子和/或铟离子，形成N型重掺杂，最后，去除第一介质层203和第二介质层206与欧姆接触电极区对应的部分，露出器件的欧姆接触电极区，在器件的欧姆接触电极区的上表面生长金属层208，即可形成欧姆接触电极，由于金属层不需要经过高温退火工艺，从而制备出质量良好的欧姆接触电极，能够保证金属层表面平整、边缘光滑整齐，器件击穿电压稳定、可靠性和寿命长。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (9)

  1. 一种GaN基器件欧姆接触电极的制备方法，其特征在于，包括以下步骤：
    步骤S1：在器件的上表面生长第一介质层；
    步骤S2：在所述第一介质层与欧姆接触电极区对应的区域和所述器件的所述欧姆接触电极区注入硅离子和/或铟离子；
    步骤S3：在所述第一介质层的上表面生长第二介质层；
    步骤S4：通过高温退火工艺激活所述硅离子和/或所述铟离子，形成N型重掺杂；
    步骤S5：分别去除所述第一介质层和所述第二介质层与所述欧姆接触电极区对应的部分；
    步骤S6：在所述器件的所述欧姆接触电极区的上表面生长金属层，形成欧姆接触电极。
  2. 如权利要求1所述的GaN基器件欧姆接触电极的制备方法，其特征在于，所述步骤S2具体包括以下步骤：
    步骤S21：在所述第一介质层与第一区域对应的部分的上表面涂覆第一光刻胶层，其中，所述第一区域为所述器件除所述欧姆接触电极区以外的区域；
    步骤S22：通过离子注入法注入所述硅离子和/或所述铟离子；
    步骤S23：去除所述第一光刻胶层。
  3. 如权利要求1所述的GaN基器件欧姆接触电极的制备方法，其特征在于，所述步骤S3和步骤S4具体包括以下步骤：
    步骤S31：在所述第二介质层与所述第一区域对应的部分的上表面涂覆第二光刻胶层；
    步骤S32：通过干法刻蚀工艺分别去除所述第一介质层和所述第二介质层与所述欧姆接触电极区对应的部分；
    步骤S33：通过电子束蒸发工艺在所述器件的上表面蒸发所述金属层；
    步骤S34：去除所述第二光刻胶层。
  4. 如权利要求1所述的GaN基器件欧姆接触电极的制备方法，其特征在于，所述第一介质层为SiN层或SiO 2层；所述第一介质层的厚度为10纳米至50纳米。
  5. 如权利要求1所述的GaN基器件欧姆接触电极的制备方法，其特征在于，所述第二介质层为SiN层或AlN层；所述第二介质层的厚度为10纳米至200纳米。
  6. 如权利要求1所述的GaN基器件欧姆接触电极的制备方法，其特征在于，所述硅离子的注入能量为30keV至200keV，注入剂量为10 14cm -2至10 16cm -2；所述铟离子的注入能量为30keV至200keV，注入剂量为10 13cm -2至10 16cm -2；
  7. 如权利要求1所述的GaN基器件欧姆接触电极的制备方法，其特征在于，所述金属层包括Ti/Au层、Ti/Pt/Au层、Ti/Al层或Ti/Al/Ni/Au层。
  8. 如权利要求1所述的GaN基器件欧姆接触电极的制备方法，其特征在于，所述硅离子和/或铟离子的注入深度为80纳米至120纳米。
  9. 如权利要求1至8任一项所述的GaN基器件欧姆接触电极的制备方法，其特征在于，所述高温退火工艺的工艺条件为：退火温度为850℃至1400℃，时间为10分钟至60分钟。
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