WO2020052204A1 - 一种基于电荷分部调制的高线性毫米波器件 - Google Patents

一种基于电荷分部调制的高线性毫米波器件 Download PDF

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WO2020052204A1
WO2020052204A1 PCT/CN2019/076274 CN2019076274W WO2020052204A1 WO 2020052204 A1 WO2020052204 A1 WO 2020052204A1 CN 2019076274 W CN2019076274 W CN 2019076274W WO 2020052204 A1 WO2020052204 A1 WO 2020052204A1
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gate
layer
region
millimeter wave
wave device
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PCT/CN2019/076274
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French (fr)
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马晓华
郝跃
武盛
宓珉瀚
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西安电子科技大学
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788Vertical transistors

Definitions

  • the invention belongs to the technical field of semiconductor devices, and particularly relates to a highly linear millimeter wave device based on charge partial modulation.
  • the third-generation semiconductors GaN, AlN, InN, and their alloys have a direct band gap, a continuously adjustable forbidden band width, High penetration field strength, fast saturated electron drift speed, high thermal conductivity, good radiation resistance and other advantages.
  • Electronic devices based on third-generation semiconductor materials have higher frequencies and higher power, greatly improving device performance, and quickly filling the first and second-generation semiconductor materials that cannot meet the needs of the semiconductor device field.
  • the structure of the GaN-based High Electron Mobility Transistor can maximize the advantages of nitride materials, which is different from that of Si-based MOS and GaAs-based high electron mobility transistors (HEMTs).
  • the two-dimensional electron gas of the mass-junction channel has the advantages of high density, large saturation current and output power, fast switching speed, high breakdown voltage, etc., and can adapt to harsh working environments such as high voltage, high temperature, and irradiation. It has a very broad application prospect in military and civilian dual-use fields such as active phased array radar, electronic warfare system, 5G communication, smart grid, and 4C industry.
  • the transconductance is able to maintain a high peak value over a large range of gate voltages.
  • the transconductance is mainly affected by the increase in capacitance at low field voltages, and the capacitance tends to be saturated at high field voltages. At this time, the transconductance is mainly affected by the decrease in mobility.
  • the current mainstream approach is to increase the thickness of the barrier layer to reduce the partial pressure on the channel, so that the channel electron mobility is at a high level under high gate voltage; a field plate structure is introduced into the device to modulate the gate edge
  • the peak value of the electric field flattens the electric field segment of the channel; the dual-channel structure is used to make the device open in steps as the gate voltage increases during operation, and the second channel is turned on to compensate for the crossover at high gate voltage.
  • the tendency of the derivative value to decrease; or the gate-source capacitance is modulated by the Fin-HEMT structure, so that it has a tendency of increasing capacitance under high field voltage to compensate for the tendency of decreasing mobility.
  • these methods introduce extra parasitic parameters, reduce the transconductance peaks, and affect the frequency characteristics of the device.
  • the field plate structure is mainly used to modulate the electric field segment of the device
  • the Fin structure is used to improve the device's Core Graphics System (CGS)
  • the dual-channel structure is used for multi-threshold regulation.
  • the two channels are turned on to compensate for the decrease in transconductance.
  • A.Chini et al. Proposed to adopt a method such as Yamashita but notches and a metal field plate structure to prepare a high linear device that can be applied to the C-band on a 4H-SiC substrate.
  • the field plate is located above the gate from the gate. 0.7 ⁇ m from the center to the drain end to modulate the peak of the electric field under the gate.
  • the transconductance of the device is 260mS / mm
  • the peak PAE is 74% (power output is 6W / mm)
  • the IMD is as high as 45dBc.
  • the present invention provides a highly linear millimeter wave device based on charge distribution regulation and a manufacturing method thereof.
  • the technical problem to be solved by the present invention is achieved through the following technical solutions:
  • An embodiment of the present invention provides a method for manufacturing a highly linear millimeter-wave device based on charge distribution regulation, including steps:
  • a source electrode 7 and a drain electrode 8 are fabricated on two sides of an epitaxial substrate, wherein the epitaxial substrate includes a substrate layer 1, an AIN nucleation layer 2, a GaN buffer layer 3, an AlN insertion layer 4 and AlGaN barrier layer 5;
  • a passivation layer 6 is grown on the AlGaN barrier layer 5.
  • a metal interconnection layer 10 is fabricated on the source electrode 7 and the drain electrode 8 to obtain a highly linear millimeter wave device based on charge distribution regulation.
  • step S1 further includes:
  • step S3 the method further includes:
  • the active region electrical isolation structure is formed on both sides of the GaN epitaxial layer 3.
  • the step S3 includes:
  • a plurality of first exposure intervals are provided along a gate width direction from a first side of the gate area on the adhesive layer to a center of the gate area on the adhesive layer.
  • the first exposure interval is performed at a gradually increasing preset dose from the first side of the gate region to the center of the gate region, and from the second side of the gate region on the glue layer to the glue.
  • the center of the gate region on the layer is provided with a plurality of second exposure intervals along the gate width direction, and the plurality of second exposure intervals along the gate width direction are from the second side of the gate region to the gate.
  • the center of the area is exposed according to a gradually increasing preset dose, and a gradual grooved gel structure is formed in the glue layer;
  • the preset dose is 4.7 to 7.0 C / m 2 .
  • the step S6 includes:
  • Photolithographic metal interconnection regions are formed on the source electrode 7 and the drain electrode 8 of the metal interconnection opening region.
  • S63 Strip the epitaxial substrate that has completed the interconnection metal evaporation, and manufacture a highly linear millimeter wave device based on the regulation of the charge distribution.
  • a highly linear millimeter wave device based on charge distribution regulation is produced by the method for manufacturing a highly linear millimeter wave device based on charge distribution regulation in the above embodiment.
  • the present invention utilizes the exposure properties of the electron beam photoresist and the etching ratio of the etching technology to realize a groove with a gradient depth in the region of the gate groove.
  • the thickness of the two-dimensional electron gas under the gate is controlled by different thicknesses of the AlGaN barrier layer. 2DEG)
  • the density is gradually modulated by partial modulation to achieve high linearity. The entire process does not introduce parasitic parameters, which is safe and reliable.
  • the present invention performs groove etching on the AlGaN barrier layer under the gate, while maintaining the original thickness of the AlGaN barrier layer in other regions, which can ensure the gate control ability without reducing the output current of the device.
  • the present invention realizes the regulation of the current density when the device is turned on through the partial modulation of the gate download carrier density.
  • the current is mainly controlled on both sides of the device, which effectively solves the problem that the device is difficult to dissipate heat during continuous wave operation The problem.
  • FIG. 1 is a schematic diagram of a manufacturing process of a highly linear millimeter wave device according to the present invention
  • 2a-2g are schematic diagrams of a method for manufacturing a highly linear millimeter wave device according to the present invention.
  • FIG. 3 is a schematic diagram of a three-dimensional structure of a highly linear millimeter wave device according to the present invention.
  • 4a-4f are schematic side views of photolithography of a progressive groove structure with a highly linear millimeter wave device according to the present invention.
  • the starting material of the GaN-based high-electron-mobility transistor for a graded gate groove in this embodiment is an epitaxial substrate, and the epitaxial substrate includes a substrate 1, an AlN nucleation layer 2, a GaN buffer layer 3, and an AlN in order from bottom to top The insertion layer 4 and the AlGaN barrier layer 5.
  • FIG. 3 is a schematic diagram of a three-dimensional three-dimensional structure of a highly linear millimeter wave device according to the present invention.
  • the material of the substrate 1 in this embodiment is insulating sapphire or Si or SiC with a thickness of 400 ⁇ m to 500 ⁇ m, the thickness of the AlN nucleation layer 2 is 180 nm, the thickness of the GaN buffer layer 3 is 1.5 ⁇ m to 2 ⁇ m, and the thickness of the AlN insertion layer 4
  • the thickness is 1 nm; the thickness of the AlGaN barrier layer 5 is 20 nm to 25 nm, wherein the aluminum composition is 20% to 30%, and the length of the progressive groove region 901 of the gate electrode 9 on the surface in the gate length direction is 0.1 ⁇ m ⁇ 0.12 ⁇ m, the height of the gate foot region 902 is 120nm ⁇ 200nm, the width of the gate cap region 903 is 360nm ⁇ 540nm; the depth of the gradation groove structure in the gradation groove region 901 varies from 0nm to 16nm along the gate width direction; gradation The thickness of the passivation layer 6 on both sides of the groove
  • a highly linear GaN device structure with a groove depth of 0 to 16 nm and a passivation layer thickness of 120 nm is selected on the SiC substrate.
  • FIG. 1 is a schematic diagram of a manufacturing process of a highly linear millimeter wave device according to the present invention. The specific steps for manufacturing are as follows:
  • Step 1 Fabricate a source electrode 7 and a drain electrode 8 on both sides of the GaN buffer layer 3 of the epitaxial substrate, wherein the epitaxial substrate includes a substrate 1, an AIN nucleation layer 2, and a GaN buffer layer 3 which are sequentially grown and formed. , AlN insertion layer 4 and AlGaN barrier layer 5.
  • Step 11 Photolithographically source and drain electrode pattern areas on both sides of the AlGaN barrier layer 5.
  • the epitaxial substrate is baked on a hot plate at 200 ° C. for 5 minutes to bake out the moisture of the epitaxial substrate.
  • the peeling adhesive PMGI-SF6 is coated on both sides of the AlGaN barrier layer 5. Glue and flip-flop, at a speed of 2000 rpm, the flip-flop thickness is 350 nm, and the formed epitaxial substrate with a flip-flop thickness of 350 nm is baked on a hot plate at 200 ° C.
  • the photoresist EPI621 was coated and spun off at a speed of 770 nm at a speed of 5000 rpm, and the epitaxial substrate with a thickness of 770 nm was baked on a hot plate at 90 ° C for 1 minute; after that, Put the epitaxial substrate after the photoresist EPI621 has been coated and spun off into a stepping lithography machine to expose the photoresist EPI621 in the source electrode region and the drain electrode region to an exposure intensity of 240ms; finally, Put the exposed epitaxial substrate into the developing solution for about 85s. After removing the double-layer adhesive in the source electrode area and the drain electrode area, rinse it with ultrapure water and blow dry it with nitrogen to form a source. The electrode 7 and the drain electrode 8 are lithographically patterned.
  • Step 12 The source electrode pattern region and the drain electrode pattern region are respectively subjected to an evaporation metal process, so that an ohmic metal is formed on the AlGaN barrier layer 5.
  • the epitaxial substrates with the lithographic patterns of the active electrode 7 and the drain electrode 8 are placed in a plasma degumming machine for the bottom film processing, and the processing time is 5 minutes.
  • the epitaxial substrates after the bottom film processing are placed
  • the entire surface of the epitaxial substrate after the previous step is evaporated under the condition that the reaction chamber vacuum is 2 ⁇ 10 -6 Torr, wherein the metal is sequentially turned from Ti to Ti Metal stack structure consisting of four layers of metal, Al, Ni and Au, where The metal in the source electrode pattern region and the drain electrode pattern region is an ohmic metal; after that, the epitaxial substrate after the evaporation of the ohmic metal is subjected to a stripping process, and sequentially put into an acetone solution, a stripping solution, an acetone solution, and an ethanol solution.
  • the epitaxial substrate was etched and peeled, and dried with nitrogen.
  • Step 13 Thermally anneal the epitaxial substrate after the evaporation metal treatment is performed, so that the ohmic metal on the AlGaN barrier layer 5 in the source electrode pattern region and the drain electrode pattern region sinks to the GaN buffer.
  • Layer 3 completes the fabrication of the source electrode 8 and the drain electrode 9.
  • step S12 The epitaxial substrate after the completion of step S12 is placed in a rapid thermal annealing furnace, and subjected to a rapid thermal annealing treatment at 850 ° C. and 30 s under an N 2 environment, so that the AlGaN barrier layer 5 in the source electrode pattern region and the drain electrode pattern region 5
  • the upper ohmic metal electrode sinks to the GaN buffer layer 3, so that an ohmic contact is formed between the ohmic metal and the buffer layer 3, and the production of the source electrode 7 and the drain electrode 8 is completed, as shown in FIG. 2a.
  • Step 2 Fabricate an active region electrical isolation structure on the AlGaN barrier layer 5.
  • Step 21 photolithographically isolate a region on the AlGaN barrier layer 5.
  • the epitaxial substrate prepared with the source electrode 7 and the drain electrode 8 is baked on a hot plate at 200 ° C. for 5 minutes; then, the surface of the epitaxial substrate is resisted to the photoresist EPI621 at a speed of 3500 rpm Shake the glue to form a 400 nm thick glue layer, and bake the glued epitaxial substrate on a hot plate at 90 ° C for 1 minute. Then, place the baked epitaxial substrate into a stepping lithography machine. The photoresist in the electrically isolated area is exposed with an exposure intensity of 260ms. Finally, the exposed device is placed in the developing solution EPD1000 for 60s to remove the photoresist in the electrically isolated area and superimpose it. Rinse with pure water and dry with nitrogen.
  • Step 22 Etching sequentially from both sides of the AlGaN barrier layer (5) to both sides of the GaN epitaxial layer (3), and forming the active regions on both sides of the GaN epitaxial layer (3). Electrically isolated structure.
  • the AlGaN barrier layer 5, the AlN insertion layer 4 and the GaN epitaxial layer 3 of the electrically isolated region are sequentially etched, and the two-dimensional electron gas (2DEG) of the device is etched.
  • the L shape is formed on both sides of the device, and the electrically isolated structure of the active area is shown in FIG. 2b.
  • the electrically isolated area is etched into the GaN epitaxial layer 3 to achieve the mesa isolation of the active area of the device.
  • the total etch depth is 120nm
  • the etch power is 80W
  • the etch time is 120s.
  • the epitaxial substrate after the two-dimensional electron gas is etched is sequentially placed in the order of acetone solution, stripping solution, acetone solution, and ethanol solution. Cleaning is performed to remove the photoresist outside the electrically isolated area; finally, the cleaned device is rinsed with ultrapure water and blown dry with nitrogen. As shown in Figure 2b.
  • multiple devices will be formed on a substrate. In order to prevent the devices from interfering with each other, the two-dimensional electron gas (2DEG) of the devices is cut, that is, the multiple devices are isolated.
  • 2DEG two-dimensional electron gas
  • Step 3 A passivation layer 6 is grown on the AlGaN barrier layer 5.
  • the device blown with nitrogen is put into a chemical plasma enhanced chemical weathering deposition (PECVD) device.
  • the power is 200 W
  • the flow rate of SiH 4 is 100 sccm
  • the flow rate of NH 4 is 100 sccm
  • the pressure is 600 mTorr
  • the temperature is 300 ° C.
  • a passivation treatment is performed on the surface of the AlGaN barrier layer 5 for a time of 1 h to form a 120 nm-thick SiN passivation layer 6, as shown in FIG. 2c.
  • Step 4 Photolithography is performed on the gate region on the passivation layer 6 to form a progressive groove structure, wherein the gate region includes a progressive groove region 901, a gate foot region 902, and a gate cap region 903.
  • FIG. 4a to FIG. 4f are schematic side views of a photolithography step of a progressive groove structure with a highly linear millimeter wave device in this embodiment
  • FIG. 4a is a A schematic side view of photoresist coating of a linear millimeter wave device
  • FIG. 4b is a schematic side view of a photoresist exposure with a high linear millimeter wave device in this embodiment
  • FIG. 4c is a high linearity photoresist of this embodiment
  • FIG. 4d is a schematic side view of the passivation layer with a high linearity millimeter wave device to remove the gate pin region in this embodiment
  • FIG. 4a is a A schematic side view of photoresist coating of a linear millimeter wave device
  • FIG. 4b is a schematic side view of a photoresist exposure with a high linear millimeter wave device in this embodiment
  • FIG. 4c is a high linearity photore
  • FIG. 4e is the present embodiment An example of a side view of an AlGaN barrier layer with a highly linear millimeter wave device in a region with a progressive groove removed;
  • FIG. 4f is a side view of a graded groove structure with a high linear millimeter wave device in this embodiment ⁇ Schematic.
  • 11 is an adhesive layer.
  • Step 41 Apply an anti-etching photoresist on the passivation layer 6 to form an adhesive layer, as shown in FIG. 4a.
  • the epitaxial substrate obtained in step 3 is baked on a hot plate at 200 ° C. for 5 minutes; then, the surface of the epitaxial substrate after baking is resisted against the etching electron beam photoresist PMMA by a spin-off at a speed of 4000 rpm. An adhesive layer with a thickness of approximately 360 nm was formed, and the epitaxial substrate after the spin-off was placed on a hot plate at 180 ° C. and baked for 2 minutes.
  • Step 42 A plurality of first exposure intervals are provided along the gate width direction from the first side of the gate region on the glue layer to the center of the gate area on the glue layer, and a plurality of The first exposure interval is exposed at a gradually increasing preset dose from the first side of the gate region to the center of the gate region, and from the second side of the gate region on the glue layer to the gate region.
  • the center of the gate region on the adhesive layer is provided with a plurality of second exposure intervals along the gate width direction, and the plurality of second exposure intervals along the gate width direction are from the second side of the gate region to the gate.
  • the center of the polar region is exposed according to a gradually increasing preset dose, and a gel structure with gradual grooves is formed in the glue layer, as shown in FIG. 4b.
  • EBL electron beam lithography machine
  • TRG Transitional Recessed Gate
  • the exposure dose 4.7 is an initial stage of exposing a plurality of the first exposure intervals along the gate width direction from the first side of the gate region to the center of the gate region according to a gradually increasing preset dose.
  • Exposure dose; and the exposure dose 4.7 is also a plurality of second exposure intervals along the grid width direction from the second side of the gate area to the center of the gate area to perform exposure at a gradually increasing preset dose.
  • Initial exposure dose, exposure dose 7.0 is the exposure dose at the center of the gate region.
  • the exposure dose gradually increased from 4.7 to 7.0 in 32 exposure intervals of 16 groups.
  • step 43 the passivation layer 6 in the gate foot region 902 and the AlGaN barrier layer 5 in the gate groove region 901 are removed by etching.
  • the inductively coupled plasma (ICP) etching process was used to remove the SiN passivation layer 6 in the gate foot region 902 using CF 4 as an etching gas.
  • the etching depth was 120 nm
  • the upper electrode power was 60 W
  • the lower electrode power was 10 W.
  • CF 4 The flow rate is 25 sccm
  • the O 2 flow rate is 10 sccm
  • the pressure is 5 mT
  • the etching time is about 240 s, as shown in FIG. 4d.
  • the ICP etching process was used to remove the AlGaN barrier layer 5 in the progressive groove region 901 with BCl 3 as an etching gas.
  • the etching depth was 16 nm
  • the power of the upper electrode was 120 W
  • the power of the lower electrode was 10 W
  • the flow rate of BCl 3 was 20 sccm. 2
  • the flow rate is 8 sccm
  • the pressure is 5 mT
  • the etching power is 40 W
  • the etching time is about 8 minutes, forming a progressive groove structure.
  • the schematic view of the gradient exposure front view is shown in Figures 4e and 4f.
  • Step 5 On the passivation layer 6, a gate cap region 903 of the gate electrode 9 is etched by using an electronic photolithography process.
  • step 51 the surface of the epitaxial substrate after the completion of step 4 is subjected to a flip-flop of a T-gate double-layer photoresist.
  • the epitaxial substrate after the 5 steps of removing the passivation layer 6 in the gate foot region 902 and the AlGaN barrier layer in the gate groove 901 region is baked on a hot plate at 200 ° C. for 5 min.
  • the baked device surface resists the etching electron beam photoresist PMMA-MAA and spins at 2000 rpm to form a bottom adhesive layer with a thickness of about 350 nm.
  • the device prepared after the spin is exposed to heat at 180 ° C. Bake on the board for 2 minutes; finally, the surface of the stripping adhesive PMMA-MAA resists the etching of the electron beam photoresist PMMA and spins at a speed of 4000 rpm to form a top rubber layer with a thickness of about 630 nm.
  • the device with a top glue layer of about 630 nm was baked on a hot plate at 150 ° C for 1 minute.
  • Step 52 Put the photoresist in the target area of the grid cap 903 in the electron beam lithography machine EBL to perform the indiscriminate exposure by placing the device after the flipping and baking, wherein the length of the grid cap area is 500nm and the width is 50um. . As shown in Figure 2e.
  • Step 6 Form a gate electrode pattern by photolithography on the gate cap region.
  • Step 7 The gate electrode 9 is formed by evaporating the gate metal on the gate electrode pattern.
  • the device with the gate electrode pattern formed by photolithography was put into a plasma degumming machine to perform a bottom film treatment.
  • the power was 200 W
  • the O 2 flow was 50 sccm
  • the operation time was 30 s.
  • the device treated by the base film was placed in an electron beam evaporation table, and the gate metal was evaporated on the entire surface of the epitaxial substrate under the condition that the vacuum degree of the reaction chamber was 2 ⁇ 10 -6 Torr.
  • Metal stack structure consisting of three layers of Ni, Au and Ni, where The gate metal of the gate groove region 901, the gate foot region 902, and the gate cap region 903 is the gate electrode 9 of the device. As shown in Figure 2f.
  • Step 8 A metal interconnection layer 10 is fabricated on the source electrode 7 and the drain electrode 8 to obtain a highly linear millimeter wave device based on charge distribution regulation.
  • step 81 a metal interconnection region is etched on the source electrode 7 and the drain electrode 8 of the metal interconnection opening region.
  • the metal interconnect etched device was baked on a hot plate at 200 ° C for 5 minutes.
  • the release electrode PMGI-SF6 was coated on the source electrode 8 and the drain electrode 9 in the metal interconnect open area. And peeling, the peeling thickness is 350 nm at a speed of 4500 rpm, and the device is baked on a hot plate at 200 ° C for 5 minutes; after that, the photoresist EPI621 is coated and peeled on the peeling adhesive, which is The thickness of the photoresist is 770nm at a speed of 5000 rpm, and the device is baked on a hot plate at 90 ° C for 1 minute.
  • the device that finishes the photoresist EPI621 coating and spin-off is put into the stepping lithography machine. Exposure of the photoresist in the metal interconnection area; finally, the exposed device is placed in a developing solution to remove the photoresist and stripper in the metal interconnection area, and it is washed with ultrapure water and nitrogen. To form a metal interconnect lithographic pattern.
  • Step 82 Evaporate the interconnection metal on the source electrode 7 and the drain electrode 8.
  • the device with the metal interconnection lithographic pattern was put into a plasma debonding machine to perform a base film treatment in a vacuum environment.
  • the power was 200 W
  • the O 2 flow rate was 50 sccm
  • the processing time was 5 min.
  • the device is placed in an electron beam evaporation stage, and the entire surface of the epitaxial substrate after the previous step is evaporated is subjected to evaporation of the interconnection metal under the condition that the reaction chamber has a vacuum of 2 ⁇ 10 -6 Torr, wherein the interconnection metal Is the thickness from bottom to top Ti and thickness are A metal stack structure composed of Au, and the metal located in the metal interconnection area is the metal interconnection layer 10.
  • Step 83 Strip the device that has completed the evaporation of the interconnected metal to produce a highly linear millimeter wave device based on the regulation of the charge distribution.
  • the device that has completed the interconnection metal evaporation is stripped to remove the interconnection metal, photoresist, and stripper outside the metal interconnection layer area. Finally, the device is rinsed with ultrapure water and blown with nitrogen to complete the device preparation. As shown in Figure 2g.
  • the exposure properties of the electron beam photoresist and the etching ratio of the etching technology are used to realize a groove with a gradient depth in the region of the gate groove.
  • the thickness of the 2DEG under the gate is gradually divided by the thickness of the AlGaN barrier layer. It can achieve high linearity without external parasitics, which is safe and reliable.
  • groove etching is performed on the AlGaN barrier layer under the gate, while the AlGaN barrier layer in other regions maintains the original thickness, which can ensure the gate control ability without reducing the output current of the device.
  • the partial modulation of the gated carrier density is used to realize the current density control when the device is turned on, and the current is mainly controlled on both sides of the device, which more effectively solves the problem that the center of the device is difficult to dissipate heat during continuous wave operation. problem.

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Abstract

提供一种基于电荷分布调控的高线性毫米波器件及其制作方法,包括:在外延基片上两侧制作源电极(7)和漏电极(8),外延基片包括依次生长形成的衬底层(1)、AIN成核层(2)、GaN缓冲层(3)、AlN插入层(4)和AlGaN势垒层(5);在AlGaN势垒层上生长钝化层(6);在钝化层上的栅极区光刻形成渐变凹槽结构,栅极区包括渐变凹槽区域(901)、栅脚区域(902)和栅帽区域(903);在栅帽区域上光刻形成栅电极图形;对栅电极图形蒸发栅金属制作栅电极(9);在源电极和所述漏电极上制作金属互联层(10),制作得到基于电荷分布调控的高线性毫米波器,有效地解决了器件在连续波工作时中心难散热的问题。

Description

一种基于电荷分部调制的高线性毫米波器件
本申请要求于2018年09月10日提交中国专利局、申请号为201811052290.9发明名称为“一种基于电荷分部调制的高线性毫米波器件”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本发明属于半导体器件技术领域,具体涉及一种基于电荷分部调制的高线性毫米波器件。
背景技术
继第一代元素半导体材料Si、Ge和第二代化合物半导体材料GaAs、InP等之后,第三代半导体GaN、AlN、InN及其合金具有直接带隙、禁带宽度连续可调制范围大、击穿场强高、饱和电子漂移速度快、热导率高、抗辐照性能好等优点。以第三代半导体材料为基体的电子器件具有更高的频率、更高的功率,大大的提高了器件性能,迅速填补了第一、二代半导体材料无法满足半导体器件领域的需求。同时GaN基高电子迁移率晶体管(High Electron Mobility Transistor,简称HEMT)的结构能够最大限度发挥氮化物材料的优势,其与Si基MOS和GaAs基高电子迁移率晶体管(HEMTs)相比,具有异质结沟道二维电子气密度高、饱和电流和输出功率大、开关速度快、击穿电压高等优点,并能够适应高压、高温、辐照等恶劣工作环境。在有源相控阵雷达、电子战系统、5G通信、智能电网、4C产业等军民两用领域具有非常广阔的应用前景。
然而,为了达到目前通讯技术的要求,高线性、大功率的器件必不可少。我们所指的高线性主要是跨导能够在很大的栅压范围内保持一个较高 的峰值。而跨导在低场电压下主要受电容值的增大而影响,在高场电压下电容趋于饱和,此时跨导主要受迁移率降低的影响。目前的主流做法是增大势垒层厚度来减小沟道上的分压,在高的栅压下使沟道电子迁移率处于一个较高的水平;在器件中引入场板结构来调制栅边缘的电场峰值,使得沟道电场分部平坦化;采用双沟道结构使其器件在工作时随着栅压的增大沟道分步开启,第二沟道的开启来弥补在高栅压下跨导值降低的趋势;或者采用Fin-HEMT结构对栅源电容进行调制,使其在高场电压下具有电容增大的趋势来弥补迁移率降低的趋势。但是,这些方法都引入了多余的寄生参数,降低了跨导峰值,影响了器件频率特性。
目前,在国内和国际上,主要采用场板结构来调制器件电场分部,采用Fin结构改善器件核心图形系统(Core Graphics System,简称CGS),采用双沟道结构来进行多阈值调控,通过第二沟道的开启来补偿跨导降低的趋势。方法如下:
2005年A.Chini等人提出采用山下可是凹槽和金属场板结构等措施,在4H-SiC衬底上制备了一款可应用于C波段的高线性器件,场板位于栅上方从栅极中心到漏一端0.7μm处来调制栅下电场峰值。其中器件的跨导为260mS/mm,4GHz下连续波输出功率为18.8W/mm(PAE=43%),PAE峰值为74%(功率输出为6W/mm),IMD高达45dBc。参考文献Power and Linearity Characteristics of Field-Plated Recessed-Gate AlGaN/GaN HEMT.IEEE ELECTRON DEVICE LETTERS,VOL.25,NO.5,2005。
2006年,Palacios.Tomás等人提出了一种双沟道器件可以使跨导平坦化,该器件通过沟道在不同栅压下依次开启带来的多阈值和栅电容调制, 并且导致源漏电阻随IDS的增加而变化的幅度较单沟道器件有所变缓。最终制备出的器件跨导为0.95S/mm,f max达到40GHz,并在10GHz下的IMD高达30dBc。参考文献Use of Double-Channel Heterostructures to Improve the Access Resistance and Linearity in GaN-Based HEMTs.IEEE TRANSACTION ELECTRON DEVICE,VOL.53,NO.3,2006。
2017年,Kai Zhang等人采用Fin结构制备出具有更平的跨导曲线的器件,栅压跨导摆幅达到1.5V~1V,等效后的输出电流为1.5A/mm,跨导高达570mS/mm,f T/f Max为31/78GHz,IM3高达52dBc,较平面结构提高了5.5dBc。参考文献High-Linearity AlGaN/GaNFinFETsfor Microwave Power Applications.ELECTRON DEVICE LETTERS Vol.38 No.5 2017。
综上所述,当前,国际上高线性的GaN基器件的制作都是采用场板结构,双异质结材料和Fin-HEMT器件结构的方式,从电容或迁移率的方面来使跨导更加平坦,实现高线性功率输出。但是这些方法均存在以下不足:
1、当器件采用场板结构以后,由于在栅上方引入寄生电容,器件频率特性退化,无法工作在较高频率下;
2、器件采用双沟道以后,双异质结的引入很难控制材料组分,过高组分的背势垒会使得两个沟道相互影响,电子浓度降低;第二沟道距离表面过远,则会不受栅压控制成为漏电通道,变得更容易击穿;
3、器件采用Fin-HEMT之后,器件的有效沟道面积缩小,导致各项指标对半牺牲,并且引入过多的栅电容从而使得频率特性退化严重。
发明内容
为了解决现有技术中存在的上述问题,本发明提供了一种基于电荷分 布调控的高线性毫米波器件及其制作方法。本发明要解决的技术问题通过以下技术方案实现:
本发明实施例提供了一种基于电荷分布调控的高线性毫米波器件的制作方法,包括步骤:
S1、在外延基片上的两侧制作源电极7和漏电极8,其中,所述外延基片包括依次生长形成的衬底层1、AIN成核层2、GaN缓冲层3、AlN插入层4和AlGaN势垒层5;
S2、在所述AlGaN势垒层5上生长钝化层6;
S3、在所述钝化层6上的栅极区光刻形成渐变凹槽结构,其中,所述栅极区包括渐变凹槽区域901、栅脚区域902和栅帽区域903;
S4、在所述栅帽区域903上光刻形成栅电极图形;
S5、对所述栅电极图形蒸发栅金属制作栅电极9;
S6、在所述源电极7和所述漏电极8上制作金属互联层10,制作得到基于电荷分布调控的高线性毫米波器。
在一个具体实施方式中,所述步骤S1还包括:
S11、在所述AlGaN势垒层5上的两侧光刻源电极图形区域和漏电极图形区域;
S12、分别对所述源电极图形区域和所述漏电极图形区域进行蒸发金属处理,使得在所述AlGaN势垒层5上形成欧姆金属;
S13、将蒸发金属处理的所述外延基片进行热退火处理,使得所述源电极图形区域和所述漏电极图形区域内所述AlGaN势垒层5上的欧姆金属下沉至所述GaN缓冲层3,完成所述源电极8和所述漏电极9的制作。
在一个具体实施方式中,在所述步骤S3之前还包括:
依次从所述AlGaN势垒层5的两侧刻蚀到所述GaN外延层3的两侧,在所述GaN外延层3的两侧形成所述有源区电隔离结构。
在一个具体实施方式中,所述步骤S3包括:
S31、在所述钝化层6上涂布抗刻蚀光刻胶,形成胶层;
S32、在所述胶层上的栅极区第一侧至所述胶层上的栅极区中心,沿着栅宽方向设有多个第一曝光区间,沿着栅宽方向的多个所述第一曝光区间从所述栅极区第一侧至所述栅极区中心按照逐渐增大的预设剂量进行曝光,且在所述胶层上的栅极区第二侧至所述胶层上的栅极区中心,沿着栅宽方向设有多个第二曝光区间,沿着栅宽方向的多个所述第二曝光区间从所述栅极区第二侧至所述栅极区中心按照逐渐增大的预设剂量进行曝光,在所述胶层形成渐变凹槽的胶型结构;
S33、在所述渐变凹槽的胶型结构区域内刻蚀去除栅脚区域的钝化层6以及渐变凹槽区域的AlGaN势垒层5,在所述AlGaN势垒层5内形成渐变凹槽结构。
在一个具体实施方式中,所述预设剂量为4.7~7.0C/m 2
在一个具体实施方式中,所述步骤S6包括:
S61、在金属互联开孔区的源电极7和漏电极8上光刻金属互联区域;
S62、在所述源电极7和所述漏电极8上的金属互联区域上蒸发互联金属;
S63、对完成互联金属蒸发的外延基片进行剥离,制作得到基于电荷分布调控的高线性毫米波器件。
此外,本发明的另一个具体实施方式中,一种基于电荷分布调控的高线性毫米波器件,由上述实施方式的基于电荷分布调控的高线性毫米波器件的制作方法制得。
与现有技术相比,本发明的有益效果:
1.本发明利用电子束光刻胶的曝光性质与刻蚀技术的刻蚀比,在栅凹槽区域实现渐变深度的凹槽,通过不同AlGaN势垒层的厚度对栅下二维电子气(2DEG)密度进行渐变的分部调制,从而实现高线性,整个过程不引入寄生参数,安全可靠。
2.本发明对栅下AlGaN势垒层进行凹槽刻蚀,而其他区域AlGaN势垒层保持原有厚度,这样可以保证栅控能力的同时不降低器件输出电流。
3.本发明通过对栅下载流子密度的分部调制,实现了器件开启时的电流密度调控,将电流主要控制于器件的两侧,更有效地解决了器件在连续波工作时中心难散热的问题。
附图说明
图1是本发明的一种具有高线性毫米波器件的制备流程示意图;
图2a-图2g是本发明的一种具有高线性毫米波器件的制备方法示意图;
图3是本发明的一种具有高线性毫米波器件的三维立体结构示意图;
图4a-图4f是本发明的一种具有高线性毫米波器件的渐变凹槽结构的光刻侧视示意图。
具体实施方式
下面结合具体实施例对本发明做进一步详细的描述,但本发明的实施方式不限于此。
实施例一
本实施例制作渐变栅凹槽的GaN基高电子迁移率晶体管的初始材料为外延基片,所述外延基片由下向上依次包括衬底1、AlN成核层2、GaN缓冲层3、AlN插入层4和AlGaN势垒层5。
请参照图3,图3是本发明的一种具有高线性毫米波器件的三维立体结构示意图。
本实施例中所述衬底1的材料是厚度为400μm~500μm的绝缘蓝宝石或Si或SiC,AlN成核层2厚度为180nm,GaN缓冲层3厚度为1.5μm~2μm,AlN插入层4的厚度为1nm;AlGaN势垒层5的厚度为20nm~25nm,其中,铝组分为20%~30%,其表面上的栅电极9的渐变凹槽区域901沿栅长方向的长度为0.1μm~0.12μm,栅脚区域902的高度为120nm~200nm,栅帽区域903的宽度为360nm~540nm;渐变凹槽区域901部分的渐变凹槽结构深度沿栅宽方向变化范围为0nm~16nm;渐变凹槽区域901两侧的钝化层6的厚度对应栅脚区域902的高度。
本实施例选择在SiC衬底上制作凹槽深度为0~16nm,钝化层厚度为120nm的高线性GaN器件结构。
请参照图1,图1是本发明的一种具有高线性毫米波器件的制备流程示意图,制作的具体步骤如下:
步骤1、在外延基片的GaN缓冲层3上两侧制作源电极7和漏电极8,其中,所述外延基片包括依次生长形成的衬底1、AIN成核层2、GaN缓冲层3、AlN插入层4和AlGaN势垒层5。
步骤11、在所述AlGaN势垒层5上两侧光刻源电极图形区域和漏电极 图形区域。
首先,将所述外延基片放在200℃的热板上烘烤5min,以烘除外延基片水分;接下来,在所述AlGaN势垒层5上两侧进行剥离胶PMGI-SF6的涂胶和甩胶,在2000rpm的转速下其甩胶厚度为350nm,并将形成的甩胶厚度为350nm的外延基片放在200℃的热板上烘烤5min;接着,在剥离胶PMGI-SF6上进行光刻胶EPI621的涂胶和甩胶,在5000rpm的转速下其甩胶厚度为770nm,再将甩胶厚度为770nm的外延基片放在90℃的热板上烘烤1min;之后,将完成光刻胶EPI621的涂胶和甩胶后的外延基片放入步进式光刻机中对源电极区域和漏电极区域内的光刻胶EPI621进行曝光强度为240ms的曝光;最后,将完成曝光的外延基片放入显影液中约85s,待移除源电极区域和漏电极区域内的双层胶后,使用超纯水对其进行冲洗并使用氮气将其吹干,形成源电极7和漏电极8光刻图形。
步骤12、分别对所述源电极图形区域和所述漏电极图形区域进行蒸发金属处理,使得在所述AlGaN势垒层5上形成欧姆金属。
首先,将有源电极7和漏电极8光刻图形的外延基片放入等离子去胶机中进行底膜处理,其处理的时间为5min;接下来,将底膜处理后的外延基片放入电子束蒸发台上,在反应腔室真空度为2×10 -6Torr的条件下对制作完前一步骤的外延基片表面整体进行蒸发金属,其中,该金属是由下向上依次由Ti、Al、Ni和Au四层金属组成的金属堆栈结构,其中
Figure PCTCN2019076274-appb-000001
在源电极图形区域和漏电极图形区域内的金属为欧姆金属;之后,对完成欧姆金属蒸发的外延基片进行剥离工艺,按顺序依次放入丙酮溶液、剥离液、丙酮溶液和乙醇溶液中进行清洗,以 移除源电极图形区域和漏电极图形区域外的欧姆金属、光刻胶和剥离胶;最后,用超纯水冲洗移除源电极图形区域和漏电极图形区域外的欧姆金属、光刻胶和剥离胶的外延基片,并用氮气吹干。
步骤13、将完成蒸发金属处理的外延基片进行热退火处理,使得所述源电极图形区域和所述漏电极图形区域内所述AlGaN势垒层5上的欧姆金属下沉至所述GaN缓冲层3,完成所述源电极8和所述漏电极9的制作。
将完成步骤S12后的外延基片放入快速热退火炉中,在N 2环境下进行850℃、30s的快速热退火处理,以使得源电极图形区域和漏电极图形区域内AlGaN势垒层5上的欧姆金属电极下沉至GaN缓冲层3,从而在欧姆金属与缓冲层3之间形成欧姆接触,完成源电极7和漏电极8的制作,如图2a所示。
步骤2、在所述AlGaN势垒层5上制作有源区电隔离结构。
步骤21、在所述AlGaN势垒层5上光刻电隔离区域。
首先,将完成源电极7和漏电极8制作的外延基片放在200℃的热板上先烘烤5min;接着,在所述外延基片表面对抗刻蚀光刻胶EPI621进行转速为3500rpm的甩胶,形成厚度为400nm的胶层,并将甩胶后的外延基片放在90℃的热板上烘烤1min;之后,将烘烤后的外延基片放入步进式光刻机中对电隔离区域内的光刻胶进行曝光,曝光强度为260ms;最后,将完成曝光后的器件放入显影液EPD1000中60s,以移除电隔离区域内的光刻胶,对其进行超纯水冲洗和氮气吹干。
步骤22、依次从所述AlGaN势垒层(5)的两侧刻蚀到所述GaN外延层(3)的两侧,在所述GaN外延层(3)的两侧形成所述有源区电隔离结构。
利用感应耦合等离子(ICP)工艺以SF 6为刻蚀气体,依次刻蚀电隔离区域的AlGaN势垒层5、AlN插入层4和GaN外延层3,将器件的二维电子气(2DEG)刻断,在器件两边形成L形状,图2b中所示为形成的有源区的电隔离结构,本实施例电隔离区域刻蚀到GaN外延层3,以实现器件有源区的台面隔离,其总的刻蚀深度为120nm,刻蚀功率为80W,刻蚀时间为120s;之后,将刻断二维电子气后的外延基片依次放入顺序为丙酮溶液、剥离液、丙酮溶液和乙醇溶液中进行清洗,以移除电隔离区域外的光刻胶;最后,用超纯水冲洗清洗后的器件并用氮气吹干。如图2b所示。在具体实验中,在一个衬底上会形成多个器件,为了使器件之间互不干扰,将器件的二维电子气(2DEG)刻断,即将多个器件进行隔离。
步骤3、在所述AlGaN势垒层5上生长钝化层6。
具体的,将氮气吹干后的器件放入化学等离子增强化学气象淀积(PECVD)设备中,在功率为200W,SiH 4流量为100sccm,NH 4流量为100sccm,压力为600mTorr,温度为300℃的条件下,对AlGaN势垒层5表面进行时间为1h的钝化处理,形成120nm厚的SiN钝化层6,如图2c所示。
步骤4、在所述钝化层6上的栅极区光刻形成渐变凹槽结构,其中,所述栅极区包括渐变凹槽区域901、栅脚区域902和栅帽区域903。
请参见图4a-图4f,图4a-图4f是本实施例的一种具有高线性毫米波器件的渐变凹槽结构的光刻步骤侧视示意图;图4a是本实施例的一种具有高线性毫米波器件的光刻胶涂布侧视示意图;图4b是本实施例的一种具有 高线性毫米波器件的光刻胶曝光侧视示意图;图4c是本实施例的一种具有高线性毫米波器件的移除部分钝化层侧视示意图;图4d是本实施例的一种具有高线性毫米波器件的刻蚀去除栅脚区域的钝化层的侧视示意图;图4e是本实施例的一种具有高线性毫米波器件的移除渐变凹槽区域内的AlGaN势垒层的侧视示意图;图4f是本实施例的一种具有高线性毫米波器件的渐变凹槽结构的侧视示意图。其中,图4a-图4f中,11为胶层。
步骤41、在所述钝化层6上涂布抗刻蚀光刻胶,形成胶层,如图4a所示。
将步骤3制得的外延基片放在200℃的热板上烘烤5min;接着,再在烘烤后的外延基片表面对抗刻蚀电子束光刻胶PMMA进行转速为4000rpm的甩胶,形成厚度约为360nm的胶层,将甩胶后的外延基片放在180℃的热板上烘烤2min。
步骤42、在所述胶层上的栅极区第一侧至所述胶层上的栅极区中心,沿着栅宽方向设有多个第一曝光区间,沿着栅宽方向的多个所述第一曝光区间从所述栅极区第一侧至所述栅极区中心按照逐渐增大的预设剂量进行曝光,且在所述胶层上的栅极区第二侧至所述胶层上的栅极区中心,沿着栅宽方向设有多个第二曝光区间,沿着栅宽方向的多个所述第二曝光区间从所述栅极区第二侧至所述栅极区中心按照逐渐增大的预设剂量进行曝光,在所述胶层形成渐变凹槽的胶型结构,如图4b所示。
将完成甩胶并烘烤后的外延基片放入电子束光刻机(EBL)中对栅脚区域进行变剂量的TRG(Transitional Recessed Gate)高灵敏度曝光,其中栅脚区域的长度为100nm,宽度为50um,如图2d所示。
本实施例中,具体的一个示例,沿着栅宽方向设有渐变剂量的16组32个曝光区间,其剂量的变化范围为4.7~7.0(C/m 2)。本实施例认为曝光剂量4.7为沿着栅宽方向的多个所述第一曝光区间从所述栅极区第一侧至所述栅极区中心按照逐渐增大的预设剂量进行曝光的初始曝光剂量;且曝光剂量4.7还为沿着栅宽方向的多个所述第二曝光区间从所述栅极区第二侧至所述栅极区中心按照逐渐增大的预设剂量进行曝光的初始曝光剂量,曝光剂量7.0为栅极区中心的曝光剂量。
其中,曝光剂量在16组32个曝光区间内从4.7到7.0逐渐增大。
将完成TRG高灵敏度曝光后的外延基片放入对应的显影液中以移除渐变凹槽的胶型结构区域内的部分光刻胶,如图4c所示,即将完成曝光的外延基片放入显影液AR600-546中显影90s,再将其放入异丙醇中进行时间为30s的定影处理,最后对其进行氮气吹干,最终形成渐变凹槽的胶型结构,其剂量的变化范围为4.7~7.0(C/m 2)中,第一曝光区间对应的曝光剂量为4.7C/m 2时光刻胶厚度为90nm,第一曝光区间对应的曝光剂量为4.7C/m 2时光刻胶厚度为90nm,栅极中心曝光剂量为7C/m 2时光刻胶厚度为0nm。
步骤43、刻蚀去除所述栅脚区域902的钝化层6以及栅凹槽901区域的AlGaN势垒层5。
利用感应耦合等离子(ICP)刻蚀工艺以CF 4为刻蚀气体移除栅脚区域902内的SiN钝化层6,刻蚀的深度为120nm,上电极功率60W,下电极功率10W,CF 4流量25sccm,O 2流量10sccm,压力5mT,刻蚀时间约为240s,如图4d所示。
利用ICP刻蚀工艺以BCl 3为刻蚀气体移除渐变凹槽区域901内的AlGaN势垒层5,刻蚀的深度为16nm,上电极功率120W,下电极功率10W,BCl 3流量20sccm,Cl 2流量8sccm,压力5mT,刻蚀功率为40W,刻蚀时间约为8min,形成渐变凹槽结构。渐变曝光主视示意图如图4e和4f所示。
步骤5、在钝化层6上,利用电子光刻工艺光刻栅电极9的栅帽区域903。
步骤51、在完成步骤4后的外延基片的表面进行T型柵双层光刻胶的甩胶。
首先,将刻蚀去除所述栅脚区域902的钝化层6以及栅凹槽901区域的AlGaN势垒层5步骤后的外延基片放在200℃的热板上烘烤5min;其次,在烘烤后的器件表面对抗刻蚀电子束光刻胶PMMA-MAA进行转速为2000rpm的甩胶,形成厚度约为350nm的底端胶层,并将甩胶后制备的器件放在180℃的热板上烘烤2min;最后,在剥离胶PMMA-MAA胶表面对抗刻蚀电子束光刻胶PMMA进行转速为4000rpm的甩胶,形成厚度约为630nm的顶端胶层,并将完成甩胶形成厚度约为630nm的顶端胶层的器件放在150℃的热板上烘烤1min。
步骤52、将完成甩胶并烘烤后的器件放入电子束光刻机EBL中栅帽903目标区域内的光刻胶进行分无差别曝光,其中栅帽区域的长度为500nm,宽度为50um。如图2e所示。
步骤53、将完成曝光后的器件放入显影液MIBK:IPA=1:3中显影4min以达到完全显影的效果,最后对其进行异丙醇浸泡和氮气吹干。
步骤6、在所述栅帽区域上光刻形成栅电极图形。
步骤7、对栅电极图形蒸发栅金属制作栅电极9。
将有光刻形成栅电极图形的器件放入等离子去胶机中进行底膜处理,其功率为200W,O 2流量为50sccm,操作时间为30s。将底膜处理后的器件放入电子束蒸发台中,在反应腔室真空度为2×10 -6Torr的条件下对外延基片表面整体进行蒸发栅金属,该栅金属是由下向上依次由Ni、Au和Ni三层金属组成的金属堆栈结构,其中
Figure PCTCN2019076274-appb-000002
柵凹槽区域901、栅脚区域902与栅帽区域903的柵金属即为器件的栅电极9。如图2f所示。
步骤8、在所述源电极7和所述漏电极8上制作金属互联层10,制作得到基于电荷分布调控的高线性毫米波器。
步骤81、在金属互联开孔区的源电极7和漏电极8上光刻金属互联区域。
首先,将完成金属互联开孔刻蚀的器件放在200℃的热板上烘烤5min;其次,在金属互联开孔区的源电极8和漏电极9上进行剥离胶PMGI-SF6的涂胶和甩胶,其在转速4500rpm下剥离胶厚度为350nm,并将器件放在200℃的热板上烘烤5min;之后,在剥离胶上进行光刻胶EPI621的涂胶和甩胶,其在转速5000rpm下光刻胶厚度为770nm,并将器件放在90℃的热板上烘烤1min;再后来,将完成光刻胶EPI621的涂胶和甩胶的器件放入步进式光刻机中对金属互联区域内的光刻胶进行曝光;最后,将完成曝光的器件放入显影液中移除金属互联区域内的光刻胶和剥离胶,并对其进行超纯水冲洗和氮气吹干,形成金属互联光刻图 形。
步骤82、在所述源电极7和所述漏电极8上蒸发互联金属。
首先,将有金属互联光刻图形的器件放入等离子去胶机中在真空环境下进行底膜处理,其功率为200W,O 2流量为50sccm,处理时间为5min。
接着,将器件放入电子束蒸发台中,在反应腔室真空度为2×10 -6Torr的条件下,对制作完前一步骤的外延基片表面整体进行蒸发互联金属,其中,该互联金属是由下向上依次由厚度为
Figure PCTCN2019076274-appb-000003
的Ti和厚度为
Figure PCTCN2019076274-appb-000004
的Au组成的金属堆栈结构,位于金属互联区域内的金属即为金属互联层10。
步骤83、对完成互联金属蒸发的器件进行剥离,制作得到基于电荷分布调控的高线性毫米波器。
对完成互联金属蒸发的器件进行剥离,以移除金属互联层区域外的互联金属、光刻胶和剥离胶;最后,用超纯水冲洗器件并用氮气吹干,完成器件的制备。如图2g所示。
综上,一种基于电荷分布调制的高线性毫米波器件由上述方法制得。
本实施例利用电子束光刻胶的曝光性质与刻蚀技术的刻蚀比,在栅凹槽区域实现渐变深度的凹槽,通过不同AlGaN势垒层的厚度对栅下2DEG密度进行渐变的分部调制,从而实现高线性,整个过程不引入寄生参数,安全可靠。
本实施例对栅下AlGaN势垒层进行凹槽刻蚀,而其他区域AlGaN势垒层保持原有厚度,这样可以保证栅控能力的同时不降低器件输出电流。
本实施例通过对栅下载流子密度的分部调制,实现了器件开启时的电 流密度调控,将电流主要控制于器件的两侧,更有效地解决了器件在连续波工作时中心难散热的问题。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明,不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干简单推演或替换,都应当视为属于本发明的保护范围。

Claims (7)

  1. 一种基于电荷分布调控的高线性毫米波器件的制作方法,其特征在于,包括步骤:
    S1、在外延基片上的两侧制作源电极(7)和漏电极(8),其中,所述外延基片包括依次生长形成的衬底层(1)、AIN成核层(2)、GaN缓冲层(3)、AlN插入层(4)和AlGaN势垒层(5);
    S2、在所述AlGaN势垒层(5)上生长钝化层(6);
    S3、在所述钝化层(6)上的栅极区光刻形成渐变凹槽结构,其中,所述栅极区包括渐变凹槽区域(901)、栅脚区域(902)和栅帽区域(903);
    S4、在所述栅帽区域(903)上光刻形成栅电极图形;
    S5、对所述栅电极图形蒸发栅金属制作栅电极(9);
    S6、在所述源电极(7)和所述漏电极(8)上制作金属互联层(10),制作得到基于电荷分布调控的高线性毫米波器。
  2. 根据权利要求1所述的一种基于电荷分布调控的高线性毫米波器件的制作方法,其特征在于,所述步骤S1还包括:
    S11、在所述AlGaN势垒层(5)上的两侧光刻源电极图形区域和漏电极图形区域;
    S12、分别对所述源电极图形区域和所述漏电极图形区域进行蒸发金属处理,使得在所述AlGaN势垒层(5)上形成欧姆金属;
    S13、将蒸发金属处理的所述外延基片进行热退火处理,使得所述源电极图形区域和所述漏电极图形区域内所述AlGaN势垒层(5)上的欧姆金属下沉至所述GaN缓冲层(3),完成所述源电极(8)和所述漏电极(9)的制作。
  3. 根据权利要求1所述的一种基于电荷分布调控的高线性毫米波器件的制作方法,其特征在于,在所述步骤S3之前还包括:
    依次从所述AlGaN势垒层(5)的两侧刻蚀到所述GaN外延层(3)的两侧,在所述GaN外延层(3)的两侧形成有源区电隔离结构。
  4. 根据权利要求1所述的一种基于电荷分布调控的高线性毫米波器件的制作方法,其特征在于,所述步骤S3包括:
    S31、在所述钝化层(6)上涂布抗刻蚀光刻胶,形成胶层;
    S32、在所述胶层上的栅极区第一侧至所述胶层上的栅极区中心,沿着栅宽方向设有多个第一曝光区间,沿着栅宽方向的多个所述第一曝光区间从所述栅极区第一侧至所述栅极区中心按照逐渐增大的预设剂量进行曝光,且在所述胶层上的栅极区第二侧至所述胶层上的栅极区中心,沿着栅宽方向设有多个第二曝光区间,沿着栅宽方向的多个所述第二曝光区间从所述栅极区第二侧至所述栅极区中心按照逐渐增大的预设剂量进行曝光,在所述胶层形成渐变凹槽的胶型结构;
    S33、在所述渐变凹槽的胶型结构区域内刻蚀去除栅脚区域的钝化层(6)以及渐变凹槽区域的AlGaN势垒层(5),在所述AlGaN势垒层(5)内形成渐变凹槽结构。
  5. 根据权利要求4所述的一种基于电荷分布调控的高线性毫米波器件的制作方法,所述预设剂量为4.7~7.0C/m 2
  6. 根据权利要求1所述的一种基于电荷分布调控的高线性毫米波器件的制作方法,其特征在于,所述步骤S6包括:
    S61、在金属互联开孔区的源电极(7)和漏电极(8)上光刻金属互联区域;
    S62、在所述源电极(7)和所述漏电极(8)上的金属互联区域上蒸发互联金属;
    S63、对完成互联金属蒸发的外延基片进行剥离,制作得到基于电荷分 布调控的高线性毫米波器件。
  7. 一种基于电荷分布调控的高线性毫米波器件,其特征在于,所述基于电荷分布调控的高线性毫米波器件适用于权利要求1~6任一项所述的方法。
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CN111399338B (zh) * 2020-04-30 2023-03-28 合肥本源量子计算科技有限责任公司 一种光刻方法
CN114023819B (zh) * 2020-07-08 2023-07-04 英诺赛科(珠海)科技有限公司 电子装置
CN113555430B (zh) * 2021-07-07 2023-01-24 西安电子科技大学 一种通过渐变栅实现多阈值调制技术的hemt器件及制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102130160A (zh) * 2011-01-06 2011-07-20 西安电子科技大学 槽形沟道AlGaN/GaN增强型HEMT器件及制作方法
CN105655395A (zh) * 2015-01-27 2016-06-08 苏州捷芯威半导体有限公司 一种增强型高电子迁移率晶体管及其制作方法
CN107302022A (zh) * 2017-07-07 2017-10-27 西安电子科技大学 低损伤表面处理高效率器件及其制作方法
CN207250526U (zh) * 2017-07-27 2018-04-17 厦门市三安集成电路有限公司 一种三维栅介质结构的增强型功率晶体管

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150187925A1 (en) * 2013-12-30 2015-07-02 Enkris Semiconductor, Inc. Enhancement-mode device
JP6404697B2 (ja) * 2014-12-10 2018-10-10 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
CN105895686A (zh) * 2016-01-21 2016-08-24 苏州能讯高能半导体有限公司 高电子迁移率晶体管器件及其制造方法
CN106847895B (zh) * 2016-12-14 2019-10-11 西安电子科技大学 基于TiN/Cu/Ni栅电极的GaN基高电子迁移率晶体管及制作方法
CN107393959A (zh) * 2017-07-07 2017-11-24 西安电子科技大学 基于自对准栅的GaN超高频器件及制作方法
CN107958928A (zh) * 2017-11-20 2018-04-24 西安电子科技大学 一种基于横向沟道调制的增强型场效应晶体管及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102130160A (zh) * 2011-01-06 2011-07-20 西安电子科技大学 槽形沟道AlGaN/GaN增强型HEMT器件及制作方法
CN105655395A (zh) * 2015-01-27 2016-06-08 苏州捷芯威半导体有限公司 一种增强型高电子迁移率晶体管及其制作方法
CN107302022A (zh) * 2017-07-07 2017-10-27 西安电子科技大学 低损伤表面处理高效率器件及其制作方法
CN207250526U (zh) * 2017-07-27 2018-04-17 厦门市三安集成电路有限公司 一种三维栅介质结构的增强型功率晶体管

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