WO2019157820A1 - 具有复合栅的igbt芯片 - Google Patents

具有复合栅的igbt芯片 Download PDF

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WO2019157820A1
WO2019157820A1 PCT/CN2018/106117 CN2018106117W WO2019157820A1 WO 2019157820 A1 WO2019157820 A1 WO 2019157820A1 CN 2018106117 W CN2018106117 W CN 2018106117W WO 2019157820 A1 WO2019157820 A1 WO 2019157820A1
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region
gate
trench
igbt chip
composite
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PCT/CN2018/106117
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English (en)
French (fr)
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刘国友
朱春林
朱利恒
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株洲中车时代电气股份有限公司
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Priority to US16/969,604 priority Critical patent/US11329130B2/en
Publication of WO2019157820A1 publication Critical patent/WO2019157820A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6894—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having one gate at least partly in a trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/145—Emitter regions of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates

Definitions

  • the present invention relates to the field of semiconductor device technologies, and in particular, to an IGBT chip having a composite gate.
  • Insulated Gate Bipolar Transistor is a compound fully controlled voltage-driven power semiconductor device consisting of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET). Due to its reduced on-state voltage, current High density, high input impedance and fast response are widely used in rail transportation, smart grid, industrial frequency conversion and new energy development.
  • the gates of existing insulated gate bipolar transistors are typically planar gates or trench gates.
  • the gate of the insulated gate bipolar transistor (IGBT) is a planar gate
  • the insulated gate bipolar transistor (IGBT) is simple in fabrication process, requires less fabrication equipment, and has good pressure resistance of the planar gate; Since the planar gate channel region is on the surface and the channel density is limited by the chip surface area, the conductance modulation effect of the planar gate is weak, resulting in a high turn-on voltage drop.
  • the gate of the insulated gate bipolar transistor is a trench gate
  • the channel is converted from the lateral direction to the longitudinal direction, thereby realizing a one-dimensional current channel, effectively eliminating the JFET effect in the planar gate channel, and at the same time making the channel density not Restricted by the surface area of the chip, the cell density is greatly increased to greatly increase the current density of the chip; however, as the density of the trench gate increases, the saturation current of the chip is too large, which weakens the short-circuit performance of the chip, thereby affecting the safe working area of the chip. At the same time, it also reduces the voltage withstand capability of the chip.
  • IGBT insulated gate bipolar transistor
  • the technical problem to be solved by the present invention is that the existing insulated gate bipolar transistor chip cannot ensure a large voltage withstand capability and a wide safe working area while greatly increasing the current density of the chip.
  • the present invention provides an IGBT chip having a composite gate, comprising a wafer substrate and a plurality of sequentially arranged cells formed on an upper surface of the wafer substrate, the cells including two a mutually symmetric composite grid unit;
  • the composite gate unit includes a source region and a gate region disposed on the wafer substrate, and the gate region includes a planar gate region and a trench gate region disposed on both sides of the source region;
  • the trench gate region includes a trench gate region on the wafer substrate and an auxiliary sub-region above the trench gate region, the trench gate region including a wafer substrate disposed on the wafer substrate a trench, a first oxide layer disposed on an inner surface of the trench, and polysilicon filled in the trench to form a trench gate, the auxiliary sub-region including a second surface formed on an upper surface of the wafer substrate An oxide layer, polysilicon formed on the second oxide layer, and an insulating layer surrounding an outer surface of the polysilicon on the second oxide layer, the polysilicon in the trench being connected to the polysilicon of the auxiliary sub-region.
  • the planar gate region comprises a third oxide layer on an upper surface of the wafer substrate, polysilicon on the third oxide layer to form a planar gate, and a polysilicon surrounding the third oxide layer.
  • the insulating layer of the surface is not limited to, but not limited to, silicon dioxide, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon dioxide, silicon dioxide, silicon dioxide, silicon dioxide, and a polysilicon surrounding the third oxide layer.
  • the insulating layer of the surface is not limited to form a planar gate.
  • the source region comprises:
  • the first N+ region is located below the planar gate region, and the second N+ region is located below the trench gate auxiliary sub-region.
  • the source region further includes a metal layer covering the planar gate region, the trench gate region, and the P+ region.
  • the metal layer is in contact with the first N+ region and the second N+ region.
  • the P+ regions are in contact with the first N+ region and the second N+ region, respectively.
  • the planar gate is shorted to the trench gate.
  • the cells are in the shape of a regular hexagon, a square or an elongated strip, and the cells are sequentially arranged on the polysilicon.
  • the IGBT chip further includes a back structure formed on a lower surface of the wafer substrate, the back structure being a punch-through type, a non-punch-through type, or a soft feedthrough type.
  • An IGBT chip with a composite gate provided by an embodiment of the present invention is configured to have a gate in an IGBT chip as a composite gate, that is, the gate includes both a planar gate and a trench gate, so that the IGBT chip has both planar gate resistance
  • the middle of the two trench gates of the IGBT chip cell with the composite gate is a non-working area, and the electric field distribution of the source region is optimized by optimizing the size of the non-working region, thereby increasing the correspondence of the planar gate region.
  • the channel area and optimized current density distribution and thermal balance improve the reverse bias voltage and high temperature capability of the chip.
  • FIG. 1 is a top plan view showing an IGBT chip structure having a composite gate in Embodiment 1 of the present invention
  • FIG. 2 is a schematic cross-sectional structural view of the cell of FIG. 1 in the A-A' direction;
  • FIG. 3 is a top plan view showing an IGBT chip structure having a composite gate in Embodiment 2 of the present invention
  • FIG. 4 is a top plan view showing the structure of an IGBT chip having a composite gate in Embodiment 3 of the present invention.
  • Insulated gate bipolar transistors are widely used in various fields due to their low on-state voltage, high current density, high input impedance, and fast response.
  • the gates of existing insulated gate bipolar transistors are typically planar gates or trench gates.
  • Insulated gate bipolar transistor (IGBT) chip with planar gate is simple in fabrication process, low in requirements for fabrication equipment, and good in withstand voltage, but because the planar gate channel density is limited by the chip surface area, The pressure drop is high.
  • An insulated gate bipolar transistor (IGBT) chip with a trench gate can convert the channel from the lateral direction to the longitudinal direction, thereby realizing a one-dimensional current channel and greatly increasing the current density of the chip, but as the density of the trench gate increases, The chip saturation current is too large, which weakens the short circuit performance of the chip, thus affecting the safe working area of the chip.
  • IGBT insulated gate bipolar transistor
  • an embodiment of the present invention provides an IGBT chip having a composite gate.
  • FIG. 1 is a plan view showing the structure of an IGBT chip having a composite gate in the first embodiment of the present invention
  • FIG. 2 is a cross-sectional structural view showing the A-A' direction of the cell in FIG.
  • the IGBT chip having a composite gate of the present embodiment includes a wafer substrate 15 and a plurality of cells 16 formed on the upper surface of the wafer substrate 15, and the cells 16 are regular hexagons, cells 16 is arranged in a honeycomb shape on the wafer substrate 15.
  • the cell 16 includes two axisymmetric composite gate cells.
  • the composite gate unit includes a source region 3 and a gate region disposed on the wafer substrate 15, and the gate region includes a planar gate region 1 and a trench gate region 2 disposed on both sides of the source region 3.
  • the trench gate region 2 includes a trench gate region on the wafer substrate 15 and an auxiliary sub-region above the trench gate region.
  • the trench gate sub-region includes a trench disposed on the wafer substrate 15, a first oxide layer 10 disposed on the inner surface of the trench, and polysilicon 14 filled in the trench, and the polysilicon 14 in the trench is Form the trench gate.
  • the auxiliary sub-region includes a second oxide layer 11 formed on the upper surface of the wafer substrate 15, a polysilicon 14 formed on the second oxide layer 11, and an insulating layer surrounding the outer surface of the polysilicon 14 formed on the second oxide layer 11. 12.
  • the polysilicon 14 filled in the trench and the polysilicon 14 formed on the second oxide layer 11 are in contact with each other, and the two can be formed in the same process in the fabrication process of the IGBT chip to form an integrated structure.
  • the material of the first oxide layer 10 and the second oxide layer 11 is silicon dioxide; the material of the insulating layer 12 is also silicon dioxide.
  • the planar gate region 1 includes a third oxide layer 13 on the upper surface of the wafer substrate 15, polysilicon 14 on the third oxide layer 13, and an insulating layer 12 surrounding the outer surface of the polysilicon 14 on the third oxide layer 13.
  • the material of the insulating layer 12 and the third oxide layer 13 of the planar gate region 1 are also silicon dioxide.
  • planar gate and the trench gate are interconnected by metal, so that the planar gate and the trench gate together serve as the gate of the IGBT chip, and the planar gate and the trench gate are simultaneously turned on and off.
  • the trench gate region is a regular hexagon in the cell 16, the auxiliary sub-region is located at the center of the cell 16, forming a closed pattern at the center of the cell 16, and the source region 3 is disposed at the trench gate.
  • the planar gate region 1 is disposed on the periphery of the source region 3, that is, the single cell 16 is a planar gate region 1, a source region 3, and a trench gate region 2 from the outside to the inside. Since the cell 16 of the present embodiment is a regular hexagon, the shape formed at the periphery of the planar gate region 1 is a regular hexagon.
  • the embodiment has the auxiliary sub-region disposed at the center of the cell 16, effectively utilizing the non-working region formed by the trench gate region, and further optimizing the structure of the cell 16.
  • the shape of the trench gate region is not limited to the above-described regular hexagon. In other embodiments of the present invention, the shape of the trench gate region may also be a circular shape or other reasonable shape, and the present invention is not limited thereto.
  • the IGBT chip further includes a back structure disposed on a lower surface of the wafer substrate 15, and the back structure may be a punch-through type, a non-punch-through type, or a soft feedthrough type.
  • the source region 3 includes, in order from bottom to top, an N well region 4, a P well region 5, a P+ region 6, an N+ region, and a metal layer 9 disposed on the wafer substrate 15.
  • the P+ region 6 is disposed between the planar gate region 1 and the trench gate region 2, and the N+ region includes a first N+ region 7 and a second N+ region 8, respectively located above the P+ region 6 near the planar gate region 1
  • the P+ region 6 is in contact connection with the first N+ region 7 and the second N+ region 8, respectively, so that the IGBT chip of the embodiment is in operation, P+ region 6 and N+
  • the zone can realize the flow of holes and electrons.
  • the first N+ region 7 and the second N+ region 8 are located below the planar gate region 1 and the trench gate region auxiliary sub-region 2, respectively.
  • the P well region 5 is located below the P+ region 6; preferably, a portion of the P well region 5 is also located on both sides of the P+ region 6, such that a portion of the P well region 5 is located below the planar gate region 1 and to the left of the trench gate region 2. Or right.
  • the N well region 4 is located below the P well region 5; preferably, the partial N well region 4 is also located on both sides of the P well region 5, that is, the partial N well region 4 is also located below the planar gate region 1 and the trench gate region. 2 left or right.
  • the P well region 5 and the N well region 4 can be represented as a P well region 5 surrounding the P+ region 6, and the N well region 4 is disposed around the P well region 5.
  • the metal layer 9 covers the planar gate region 1, the trench gate region 2, and the exposed P+ region 6 between the planar gate region 1 and the trench gate region 2.
  • the metal layer 9 is the source and the metal
  • the layer 9 is in contact connection with the first N+ region 7 and the second N+ region 8, so that when the IGBT chip of the embodiment is in operation, the metal layer 9 can realize the flow of holes and electrons with the P+ region 6 and the N+ region, respectively.
  • the metal layer material is aluminum.
  • An IGBT chip with a composite gate provided by an embodiment of the present invention is configured such that the gate of the IGBT chip is a composite gate, that is, the gate region includes both a planar gate and a trench gate, thereby making the IGBT chip of the embodiment both It has the advantages of good planar voltage resistance and high skin hardness. It also has a trench gate to realize one-dimensional current channel, effectively eliminating the effect of the field effect transistor (JFET) effect in the planar channel. The channel density is not limited by the chip surface area. , greatly improve the advantages of chip current density.
  • the trench gate region 2 in this embodiment further includes a auxiliary sub-region, and the auxiliary sub-region is disposed at the center of the cell 16, effectively utilizing the non-working region formed by the trench gate region, further optimizing the cell 16
  • the two trench gates of the IGBT chip cell with the composite gate are non-working regions, and the electric field distribution of the source region is optimized by optimizing the size of the non-working region, thereby increasing the planar gate.
  • the area corresponds to the channel area, and optimizes the current density distribution and thermal balance, thereby improving the reverse bias voltage and high temperature capability of the chip.
  • FIG. 3 is a top plan view showing the structure of an IGBT chip having a composite gate in Embodiment 2 of the present invention.
  • the present embodiment re-limits only the shape, arrangement, and IGBT chip structure type of the cell 16 on the basis of the first embodiment.
  • the cells 16 are square, and the cells 16 are arranged in a matrix on the wafer substrate 15.
  • the trench gate region is square in the cell 16, the auxiliary sub-region is located at the center of the cell 16, forming a closed pattern at the center of the cell 16, and the source region 3 is disposed at the periphery of the trench gate region 2,
  • the planar gate region 1 is disposed at the periphery of the source region 3, that is, the single cell 16 is also a planar gate region 1, a source region 3, and a trench gate region 2 from the outside to the inside.
  • the shape formed at the periphery of the planar gate region 1 is a square.
  • the shape of the trench gate region is also not limited to the above square. In other embodiments of the present invention, the shape of the trench gate region may also be circular or other reasonable shape, and the present invention is not limited thereto.
  • the IGBT chip further includes a back structure disposed on a lower surface of the wafer substrate 15, and the back structure may be a punch-through type, a non-punch-through type, or a soft feedthrough type.
  • An IGBT chip with a composite gate provided by an embodiment of the present invention is configured such that the gate of the IGBT chip is a composite gate, that is, the gate region includes both a planar gate and a trench gate, thereby making the IGBT chip of the embodiment both It has the advantages of good planar voltage resistance and high skin hardness. It also has a trench gate to realize one-dimensional current channel, effectively eliminating the effect of the field effect transistor (JFET) effect in the planar channel. The channel density is not limited by the chip surface area. , greatly improve the advantages of chip current density.
  • the trench gate region 2 in this embodiment further includes a auxiliary sub-region, and the auxiliary sub-region is disposed at the center of the cell 16, effectively utilizing the non-working region formed by the trench gate region, further optimizing the cell 16
  • the two trench gates of the IGBT chip cell with the composite gate are non-working regions, and the electric field distribution of the source region is optimized by optimizing the size of the non-working region, thereby increasing the planar gate.
  • the area corresponds to the channel area, and optimizes the current density distribution and thermal balance, thereby improving the reverse bias voltage and high temperature capability of the chip.
  • FIG. 4 is a plan view showing the structure of an IGBT chip having a composite gate in Embodiment 3 of the present invention.
  • the present embodiment re-limits only the shape, arrangement, and IGBT chip structure type of the cell 16 on the basis of the first embodiment.
  • the cross-section of the cell 16 of the present embodiment is elongated, and the cells 16 are sequentially arranged in parallel on the wafer substrate 15.
  • the trench gate region, the auxiliary sub-region, the source region 3, and the planar gate region 1 are all elongated, arranged in order, that is, the single cell 16 is also a planar gate region 1 and a source region 3 And a trench gate region 2; the auxiliary sub-region is located between the two trench gate regions to form a closed pattern.
  • the shape of the trench gate region is also not limited to the above-mentioned elongated shape. In other embodiments of the present invention, the shape of the trench gate region may be other reasonable shapes, and the present invention is not limited thereto.
  • the IGBT chip bottom structure further includes a back structure disposed on a lower surface of the wafer substrate 15, and the back structure may be a punch-through type, a non-punch-through type, or a soft feedthrough type.
  • An IGBT chip with a composite gate provided by an embodiment of the present invention is configured such that the gate of the IGBT chip is a composite gate, that is, the gate region includes both a planar gate and a trench gate, thereby making the IGBT chip of the embodiment both It has the advantages of good planar voltage resistance and high skin hardness. It also has a trench gate to realize one-dimensional current channel, effectively eliminating the effect of the field effect transistor (JFET) effect in the planar channel. The channel density is not limited by the chip surface area. , greatly improve the advantages of chip current density.
  • the trench gate region 2 in this embodiment further includes a auxiliary sub-region, and the auxiliary sub-region is disposed at the center of the cell 16, effectively utilizing the non-working region formed by the trench gate region, further optimizing the cell 16
  • the two trench gates of the IGBT chip cell with the composite gate are non-working regions, and the electric field distribution of the source region is optimized by optimizing the size of the non-working region, thereby increasing the planar gate.
  • the area corresponds to the channel area, and optimizes the current density distribution and thermal balance, thereby improving the reverse bias voltage and high temperature capability of the chip.

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  • Electrodes Of Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种具有复合栅的IGBT芯片，包括若干复合栅单元；每一复合栅单元包括源极区(3)和栅极区，栅极区包括设置于源极区(3)两侧的平面栅极区(1)和沟槽栅极区(2)。将平面栅极和沟槽栅极复合于同一元胞(16)，可以大幅度提升芯片密度并保留沟槽栅低通耗、高电流密度和平面栅宽安全工作区的特性。

Description

具有复合栅的IGBT芯片
本申请要求享有2018年2月13日提交的名称为“具有复合栅的IGBT芯片”的中国专利申请CN201810149376.7的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及半导体器件技术领域，尤其涉及一种具有复合栅的IGBT芯片。
背景技术
绝缘栅双极型晶体管(IGBT)是由双极型三极管(BJT)和绝缘栅型场效应管(MOSFET)组成的复合全控型电压驱动式功率半导体器件，由于其具有通态压降低，电流密度大，输入阻抗高以及响应速度快等特点，被广泛应用于轨道交通、智能电网、工业变频以及新能源开发等领域。
现有的绝缘栅双极型晶体管(IGBT)的栅极通常为平面栅或沟槽栅。当绝缘栅双极型晶体管(IGBT)的栅极为平面栅时，则绝缘栅双极型晶体管(IGBT)制作工艺简单，对制成设备要求较低，且平面栅的耐压性较好；但由于平面栅沟道区在表面，沟道密度受到芯片表面积大小限制，因此平面栅的电导调制效应较弱，从而使得其导通压降较高。当绝缘栅双极型晶体管(IGBT)的栅极为沟槽栅时，将沟道由横向转化为纵向，从而实现一维电流通道，有效消除平面栅沟道中的JFET效应，同时使沟道密度不再受芯片表面积限制，大大提高元胞密度从而大幅度提升芯片电流密度；但随着沟槽栅密度的增加，芯片饱和电流过大，弱化了芯片的短路性能，从而影响了芯片的安全工作区，同时也降低了芯片的耐压能力。
因此，现如今亟需一种耐压能力大，同时又可以很好的避免芯片饱和电流过大，影响芯片的安全工作区的绝缘栅双极型晶体管(IGBT)芯片。
发明内容
本发明所要解决的技术问题是现有的绝缘栅双极型晶体管芯片不能在大幅度提升芯片电流密度的同时保证具有较大的耐压能力和宽安全工作区。
为了解决上述技术问题，本发明提供了一种具有复合栅的IGBT芯片，包括晶圆基片以及形成在所述晶圆基片的上表面若干个依次排列的元胞，所述元胞包括两个相互对称的 复合栅单元；
所述复合栅单元包括设置于所述晶圆基片上的源极区和栅极区，所述栅极区包括设置于所述源极区两侧的平面栅极区和沟槽栅极区；
所述沟槽栅极区包括位于所述晶圆基片上的沟槽栅子区以及位于所述沟槽栅子区上方的辅助子区，所述沟槽栅子区包括设置于所述晶圆基片上的沟槽、设置于所述沟槽内表面的第一氧化层以及填充于所述沟槽内形成沟槽栅极的多晶硅，所述辅助子区包括形成于所述晶圆基片上表面的第二氧化层、形成于所述第二氧化层上的多晶硅以及包围述第二氧化层上多晶硅外表面的绝缘层，所述沟槽内的多晶硅与所述辅助子区的多晶硅相连。
优选的是，所述平面栅极区包括位于所述晶圆基片上表面的第三氧化层、位于所述第三氧化层上形成平面栅极的多晶硅以及包围所述第三氧化层上多晶硅外表面的绝缘层。
优选的是，所述源极区包括：
设置于所述平面栅极区和所述沟槽栅极区之间的P+区；
设置于所述P+区上方两侧的第一N+区和第二N+区；
设置于所述P+区下的P阱区；
以及设置于所述P阱区下的N阱区。
优选的是，所述第一N+区位于所述平面栅极区下方，所述第二N+区位于沟槽栅极辅助子区下方。
优选的是，所述源极区还包括覆盖所述平面栅极区、所述沟槽栅极区以及所述P+区的金属层。
优选的是，所述金属层与所述第一N+区和第二N+区接触连接。
优选的是，所述P+区分别与所述第一N+区和第二N+区接触连接。
优选的是，所述平面栅极与所述沟槽栅极短接。
优选的是，所述元胞呈正六边形、正方形或长条形，所述元胞在所述多晶硅上依次排列。
优选的是，所述IGBT芯片还包括形成在所述晶圆基片的下表面的背部结构，所述背部结构为穿通型、非穿通型或软穿通型。
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：
应用本发明实施例提供的具有复合栅的IGBT芯片，通过将IGBT芯片中的栅极设置成复合栅，即栅极既包括平面栅又包括沟槽栅，从而使得该IGBT芯片既具有平面栅耐压性较好的优点，同时也具有沟槽栅提高元胞密度从而大幅度提升芯片电流密度的优点。同时本申请具有复合栅的IGBT芯片元胞的两个沟槽栅中间为非工作区，通过优化此非工作 区的大小，从而优化了源极区的电场分布，增大了平面栅极区对应的沟道面积，并优化了电流密度分布和热平衡，从而提升了芯片的反偏阻压和高温能力。
本发明的其它特征和优点将在随后的说明书中阐述，并且部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1示出了本发明实施例一中具有复合栅的IGBT芯片结构的俯视图；
图2示出了图1中的元胞的A-A＇方向的剖面结构示意图；
图3出了本发明实施例二中具有复合栅的IGBT芯片结构的俯视图；
图4出了本发明实施例三中具有复合栅的IGBT芯片结构的俯视图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
由于绝缘栅双极型晶体管(IGBT)具有通态压降低，电流密度大，输入阻抗高以及响应速度快等优点，因此被广泛应用于各个领域。现有的绝缘栅双极型晶体管(IGBT)的栅极通常为平面栅或沟槽栅。具有平面栅的绝缘栅双极型晶体管(IGBT)芯片制作工艺简单，对制成设备要求较低，且耐压性较好，但由于平面栅沟道密度受到芯片表面积大小限制，从而使得其导通压降较高。具有沟槽栅的绝缘栅双极型晶体管(IGBT)芯片可实现将沟道由横向转化为纵向，从而实现一维电流通道，大幅度提升芯片电流密度，但随着沟槽栅密度的增加，芯片饱和电流过大，弱化了芯片的短路性能，从而影响了芯片的安全工作区。
实施例一
为解决现有技术中存在的上述技术问题，本发明实施例提供了一种具有复合栅的IGBT芯片。
图1示出了本发明实施例一中具有复合栅的IGBT芯片结构的俯视图；图2示出了图 1中的元胞的A-A＇方向的剖面结构示意图。
参照图1和图2，本实施例具有复合栅的IGBT芯片包括晶圆基片15以及形成在晶圆基片15的上表面的若干个元胞16，元胞16为正六边形，元胞16呈蜂窝状排列于晶圆基片15上。元胞16包括两个轴对称的复合栅单元。
复合栅单元包括设置于晶圆基片15上的源极区3和栅极区，栅极区包括设置于源极区3两侧的平面栅极区1和沟槽栅极区2。
沟槽栅极区2包括位于晶圆基片15上的沟槽栅子区和位于沟槽栅子区上方的辅助子区。具体地，沟槽栅子区包括设置于晶圆基片15上的沟槽、设置于沟槽内表面上的第一氧化层10以及填充于沟槽内的多晶硅14，沟槽内的多晶硅14即构成沟槽栅极。辅助子区包括形成于晶圆基片15上表面的第二氧化层11、形成在第二氧化层11上的多晶硅14以及包围住形成在第二氧化层11上多晶硅14的外表面的绝缘层12。其中，填充于沟槽内的多晶硅14和形成在第二氧化层11上的多晶硅14接触相连，两者可在IGBT芯片制作过程中的同一工艺中形成，形成一体结构。优选地，第一氧化层10和第二氧化层11的材料为二氧化硅；绝缘层12的材料也均为二氧化硅。
平面栅极区1包括位于晶圆基片15上表面的第三氧化层13、位于第三氧化层13上的多晶硅14以及包围第三氧化层13上多晶硅14外表面的绝缘层12。优选地，平面栅极区1的绝缘层12和第三氧化层13的材料也均为二氧化硅。
平面栅极与沟槽栅极通过金属互联，使得平面栅极与沟槽栅极共同作为IGBT芯片的栅极，并实现平面栅极与沟槽栅极的同时开启与关断。
在本实施例中，沟槽栅子区在元胞16中为正六边形，辅助子区位于元胞16中心处，在元胞16中心形成封闭的图案，源极区3设置于沟槽栅极区2外围，平面栅极区1设置于源极区3外围，即单个元胞16从外到内依次为平面栅极区1、源极区3和沟槽栅极区2。由于本实施例的元胞16为正六边形，因此平面栅极区1外围形成的形状即为正六边形。与现有技术相比，本实施例将辅助子区设置于元胞16中心处，有效的利用了沟槽栅子区形成的非工作区，进一步优化了元胞16的结构。
需要说明的是，沟槽栅子区的形状不限于上述正六边形，在本发明的其他实施例中，沟槽栅子区的形状还可为圆形或其他合理的形状，本发明同样不限于此。优选地，IGBT芯片还包括设置于晶圆基片15的下表面的背部结构，背部结构可以为穿通型、非穿通型或软穿通型。
源极区3从下到上依次包括设置于晶圆基片15上的N阱区4、P阱区5、P+区6、N+区以及金属层9。具体地，P+区6设置于平面栅极区1和沟槽栅极区2之间，N+区包 括第一N+区7和第二N+区8，分别位于P+区6上方靠近平面栅极区1的一侧和靠近沟槽栅极区2的一侧，P+区6分别与第一N+区7和第二N+区8接触连接，以使得本实施例IGBT芯片在工作时，P+区6和N+区可实现空穴和电子流动。优选地，第一N+区7和第二N+区8分别位于平面栅极区1和沟槽栅极区辅助子区2下方。P阱区5位于P+区6下方；优选地，部分P阱区5还位于P+区6的两侧，即使得部分P阱区5位于平面栅极区1下方和沟槽栅极区2左侧或右侧。N阱区4位于P阱区5下方；优选地，部分N阱区4还位于P阱区5的两侧，即使得部分N阱区4也位于平面栅极区1下方和沟槽栅极区2左侧或右侧。上述P阱区5和N阱区4即可表示为P阱区5包围P+区6设置，N阱区4包围P阱区5设置。
金属层9覆盖于平面栅极区1、沟槽栅极区2以及平面栅极区1和沟槽栅极区2之间裸露出的P+区6上，金属层9即为源极，且金属层9与第一N+区7和第二N+区8接触连接，以使得本实施例IGBT芯片在工作时，金属层9可分别与P+区6和N+区实现空穴和电子的流动。优选地，金属层材料为铝。
应用本发明实施例提供的具有复合栅的IGBT芯片，通过将IGBT芯片中的栅极设置成复合栅，即使得栅极区既包括平面栅又包括沟槽栅，从而使得本实施例IGBT芯片既具有平面栅耐压性好、皮实度高的优点，同时也具有沟槽栅实现一维电流通道，有效消除平面沟道中场效应晶体管(JFET)效应的影响，沟道密度不受芯片表面积限制，大幅提升芯片电流密度的优点。同时本实施例中的沟槽栅极区2还包括辅助子区，辅助子区设置于元胞16中心处，有效的利用了沟槽栅子区形成的非工作区，进一步优化了元胞16的结构；同时本申请具有复合栅的IGBT芯片元胞的两个沟槽栅中间为非工作区，通过优化此非工作区的大小，从而优化了源极区的电场分布，增大了平面栅极区对应的沟道面积，并优化了电流密度分布和热平衡，从而提升了芯片的反偏阻压和高温能力。
实施例二
相应地，图3出了本发明实施例二中具有复合栅的IGBT芯片结构的俯视图。参照图3，本实施例在实施例一的基础上仅对元胞16的形状、排列方式以及IGBT芯片结构类型进行了重新的限定。
具体地，本实施例元胞16为正方形，元胞16呈矩阵状排列于晶圆基片15上。
更进一步地，沟槽栅子区在元胞16中为正方形，辅助子区位于元胞16中心处，在元胞16中心形成封闭的图案，源极区3设置于沟槽栅极区2外围，平面栅极区1设置于源极区3外围，即单个元胞16从外到内依次也为平面栅极区1、源极区3和沟槽栅极区2。 平面栅极区1外围形成的形状即为正方形。
需要说明的是，沟槽栅子区的形状同样不限于上述正方形，在本发明的其他实施例中，沟槽栅子区的形状还可为圆形或其他合理的形状，本发明同样不限于此。优选地，IGBT芯片还包括设置于晶圆基片15的下表面的背部结构，背部结构可以为穿通型、非穿通型或软穿通型。
应用本发明实施例提供的具有复合栅的IGBT芯片，通过将IGBT芯片中的栅极设置成复合栅，即使得栅极区既包括平面栅又包括沟槽栅，从而使得本实施例IGBT芯片既具有平面栅耐压性好、皮实度高的优点，同时也具有沟槽栅实现一维电流通道，有效消除平面沟道中场效应晶体管(JFET)效应的影响，沟道密度不受芯片表面积限制，大幅提升芯片电流密度的优点。同时本实施例中的沟槽栅极区2还包括辅助子区，辅助子区设置于元胞16中心处，有效的利用了沟槽栅子区形成的非工作区，进一步优化了元胞16的结构；同时本申请具有复合栅的IGBT芯片元胞的两个沟槽栅中间为非工作区，通过优化此非工作区的大小，从而优化了源极区的电场分布，增大了平面栅极区对应的沟道面积，并优化了电流密度分布和热平衡，从而提升了芯片的反偏阻压和高温能力。
实施例三
相应地，图4出了本发明实施例三中具有复合栅的IGBT芯片结构的俯视图。参照图4，本实施例在实施例一的基础上仅对元胞16的形状、排列方式以及IGBT芯片结构类型进行了重新的限定。
具体地，本实施例元胞16的横切面为长条形，元胞16依次平行排列于晶圆基片15上。
更进一步地，沟槽栅子区、辅助子区、源极区3以及平面栅极区1均为长条状，依次排列，即单个元胞16依次也为平面栅极区1、源极区3和沟槽栅极区2；辅助子区位于两个沟槽栅子区之间，形成封闭的图案。
需要说明的是，沟槽栅子区的形状同样不限于上述长条形，在本发明的其他实施例中，沟槽栅子区的形状还可为其他合理的形状，本发明同样不限于此。优选地，IGBT芯片底部结构还包括设置于晶圆基片15的下表面的背部结构，背部结构可以为穿通型、非穿通型或软穿通型。
应用本发明实施例提供的具有复合栅的IGBT芯片，通过将IGBT芯片中的栅极设置成复合栅，即使得栅极区既包括平面栅又包括沟槽栅，从而使得本实施例IGBT芯片既具有平面栅耐压性好、皮实度高的优点，同时也具有沟槽栅实现一维电流通道，有效消除平 面沟道中场效应晶体管(JFET)效应的影响，沟道密度不受芯片表面积限制，大幅提升芯片电流密度的优点。同时本实施例中的沟槽栅极区2还包括辅助子区，辅助子区设置于元胞16中心处，有效的利用了沟槽栅子区形成的非工作区，进一步优化了元胞16的结构；同时本申请具有复合栅的IGBT芯片元胞的两个沟槽栅中间为非工作区，通过优化此非工作区的大小，从而优化了源极区的电场分布，增大了平面栅极区对应的沟道面积，并优化了电流密度分布和热平衡，从而提升了芯片的反偏阻压和高温能力。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种具有复合栅的IGBT芯片，包括晶圆基片以及形成在所述晶圆基片的上表面若干个依次排列的元胞，所述元胞包括两个相互对称的复合栅单元；
    所述复合栅单元包括设置于所述晶圆基片上的源极区和栅极区，所述栅极区包括设置于所述源极区两侧的平面栅极区和沟槽栅极区；
    所述沟槽栅极区包括位于所述晶圆基片上的沟槽栅子区以及位于所述沟槽栅子区上方的辅助子区，所述沟槽栅子区包括设置于所述晶圆基片上的沟槽、设置于所述沟槽内表面的第一氧化层以及填充于所述沟槽内形成沟槽栅极的多晶硅，所述辅助子区包括形成于所述晶圆基片上表面的第二氧化层、形成于所述第二氧化层上的多晶硅以及包围所述第二氧化层上多晶硅外表面的绝缘层，所述沟槽内的多晶硅与所述辅助子区的多晶硅相连。
  2. 根据权利要求1所述的具有复合栅的IGBT芯片，其中，所述平面栅极区包括位于所述晶圆基片上表面的第三氧化层、位于所述第三氧化层上形成平面栅极的多晶硅以及包围所述第三氧化层上多晶硅外表面的绝缘层。
  3. 根据权利要求1所述的具有复合栅的IGBT芯片，其中，所述源极区包括：
    设置于所述平面栅极区和所述沟槽栅极区之间的P+区；
    设置于所述P+区上方两侧的第一N+区和第二N+区；
    设置于所述P+区下的P阱区；
    以及设置于所述P阱区下的N阱区。
  4. 根据权利要求3所述的具有复合栅的IGBT芯片，其中，所述第一N+区和所述第二N+区分别位于所述平面栅极区和沟槽栅极区的辅助子区下方。
  5. 根据权利要求4所述的具有复合栅的IGBT芯片，其中，所述源极区还包括覆盖所述平面栅极区、所述沟槽栅极区以及所述P+区的金属层。
  6. 根据权利要求5所述的具有复合栅的IGBT芯片，其中，所述金属层与所述第一N+区和第二N+区接触连接。
  7. 根据权利要求3所述的具有复合栅的IGBT芯片，其中，所述P+区分别与所述第一N+区和第二N+区接触连接。
  8. 根据权利要求4所述的具有复合栅的IGBT芯片，其中，所述P+区分别与所述第一N+区和第二N+区接触连接。
  9. 根据权利要求5所述的具有复合栅的IGBT芯片，其中，所述P+区分别与所述第一N+区和第二N+区接触连接。
  10. 根据权利要求6所述的具有复合栅的IGBT芯片，其中，所述P+区分别与所述第 一N+区和第二N+区接触连接。
  11. 根据权利要求2所述的具有复合栅的IGBT芯片，其中，所述平面栅极与所述沟槽栅极短接。
  12. 根据权利要求3所述的具有复合栅的IGBT芯片，其中，所述平面栅极与所述沟槽栅极短接。
  13. 根据权利要求4所述的具有复合栅的IGBT芯片，其中，所述平面栅极与所述沟槽栅极短接。
  14. 根据权利要求5所述的具有复合栅的IGBT芯片，其中，所述平面栅极与所述沟槽栅极短接。
  15. 根据权利要求6所述的具有复合栅的IGBT芯片，其中，所述平面栅极与所述沟槽栅极短接。
  16. 根据权利要求7所述的具有复合栅的IGBT芯片，其中，所述平面栅极与所述沟槽栅极短接。
  17. 根据权利要求1所述的具有复合栅的IGBT芯片，其中，所述元胞呈正六边形、正方形或长条形。
  18. 根据权利要求1所述的具有复合栅的IGBT芯片，其中，还包括形成在所述晶圆基片的下表面的背部结构，所述背部结构为穿通型、非穿通型或软穿通型。
  19. 据权利要求2所述的具有复合栅的IGBT芯片，其中，还包括形成在所述晶圆基片的下表面的背部结构，所述背部结构为穿通型、非穿通型或软穿通型。
  20. 据权利要求3所述的具有复合栅的IGBT芯片，其中，还包括形成在所述晶圆基片的下表面的背部结构，所述背部结构为穿通型、非穿通型或软穿通型。
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