CN111900202A - 一种沟槽栅igbt器件 - Google Patents
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
本发明公开一种沟槽栅IGBT器件,包括从下至上依次层叠设置的集电极金属层、集电区、场截止层、漂移区、沟槽结构和发射极金属层;所述沟槽结构包括假栅结构和栅极结构,其中假栅结构位于漂移区的上方侧面,栅极结构位于漂移区的上方中部;所述假栅结构包括窄部和宽部,且宽部位于窄部的下方;所述栅极结构与窄部之间的漂移区上方设有载流子存储层,载流子存储层的上方设有P型基区;所述P型基区的上方设有P+发射区与N+发射区,P+发射区、N+发射区分别与发射极金属层电连接。本发明有效地降低米勒电容,提高IGBT开关速度,降低IGBT开关损耗以及降低器件导通压降,同时兼顾改善IGBT的多种性能。
Description
技术领域
本发明涉及半导体功率器件技术领域,尤其涉及一种沟槽栅IGBT器件。
背景技术
绝缘栅双极型晶体管(IGBT)是一种MOS场效应与双极型晶体管复合的新型电力电子器件。它不但具有MOSFET输入电阻大、易于驱动、控制简单的优点;又具有双极型晶体管导通压降低、通态电流大的优点。现已成为现代电力电子电路中的核心元器件之一,广泛应用于交通、能源、工业、家用电器等领域。
从IGBT发明以来,人们不断致力于改善IGBT的特性,栅极结构从最初的平面型发展到沟槽结构。在IGBT的性能改善过程中,如何同时兼顾降低米勒电容、提高开关速度、降低开关损耗以及降低导通压降等是研究改善的重难点。
发明内容
本发明的目的是提供一种沟槽栅IGBT器件,有效地降低米勒电容,提高IGBT开关速度,降低IGBT开关损耗以及降低器件导通压降,同时兼顾改善IGBT的多种性能。
为实现上述目的,采用以下技术方案:
一种沟槽栅IGBT器件,包括从下至上依次层叠设置的集电极金属层、集电区、场截止层、漂移区、沟槽结构和发射极金属层;所述沟槽结构包括假栅结构和栅极结构,其中假栅结构位于漂移区的上方侧面,栅极结构位于漂移区的上方中部;所述假栅结构与发射极金属层电连接,栅极结构经第一介质层与发射极金属层隔离;所述假栅结构包括窄部和宽部,且宽部位于窄部的下方;所述栅极结构与窄部之间的漂移区上方设有载流子存储层,载流子存储层的上方设有P型基区;所述P型基区的上方设有P+发射区与N+发射区,P+发射区、N+发射区分别与发射极金属层电连接。
较佳地,所述宽部包括宽部电极和宽部介质层,宽部电极通过宽部介质层与漂移区隔离;所述窄部包括窄部电极和窄部介质层,窄部电极通过窄部介质层分别与漂移区、载流子存储层、P型基区隔离;所述宽部电极的宽度大于窄部电极的宽度,且宽部电极与窄部电极电连接。
较佳地,所述栅极结构位于假栅结构之间,栅极结构包括栅电极和栅介质层。
较佳地,所述栅电极的深度不小于窄部电极的深度,且不大于宽部电极的深度。
较佳地,所述栅电极的深度小于窄部电极的深度。
采用上述方案,本发明的有益效果是:
本案通过假栅结构的宽部电极和窄部电极对栅电极的屏蔽作用,有效地降低了米勒电容,提高了IGBT开关速度,降低了IGBT开关损耗。同时,利用假栅结构的宽部电极的电场屏蔽作用,可在不降低器件耐压基础上,提高载流子存储层浓度,从而提高发射极侧载流子浓度,降低器件导通压降。
附图说明
图1为本发明的栅电极为实施例1的剖面结构示意图;
图2为本发明的栅电极为实施例2的剖面结构示意图;
其中,附图标识说明:
1—集电极金属层,2—集电区,
3—场截止层,4—漂移区,
5—发射极金属层,6—假栅结构,
7/7’—栅极结构,8—载流子存储层,
9—P型基区,10—P+发射区,
11—N+发射区,12—第一介质层,
61—窄部,62—宽部,
71/71’—栅电极,72/72’—栅介质层,
611—窄部电极,612—窄部介质层,
621—宽部电极,622—宽部介质层。
具体实施方式
以下结合附图和具体实施例,对本发明进行详细说明。
参照图1至2所示,本发明提供一种沟槽栅IGBT器件,包括从下至上依次层叠设置的集电极金属层1、集电区2、场截止层3、漂移区4、沟槽结构和发射极金属层5;所述沟槽结构包括假栅结构6和栅极结构7/7’,其中假栅结构6位于漂移区4的上方侧面,栅极结构7/7’位于漂移区4的上方中部;所述假栅结构6包括窄部61和宽部62,且宽部62位于窄部61的下方;所述栅极结构6与窄部61之间的漂移区4上方设有载流子存储层8,载流子存储层8的上方设有P型基区9;载流子存储层8位于窄部介质层612之间,P型基区9下方,作为IGBT的载流子存储层。
所述P型基区9的上方设有P+发射区10与N+发射区11,P+发射区10、N+发射区11分别与发射极金属层5电连接。N+发射区11靠近栅介质层72/72’布置,P+发射区10靠近窄部介质层612布置,栅电极71/71’经第一介质层12与发射极金属层5隔离,第一介质层12延伸覆盖部分N+发射区11的上方,在保证N+发射区11与发射极金属层5电连接的同时,保证器件连接的整体性。
本实施例中以N型IGBT器件为例,参照图1-2所示,集电区2为P+集电区,场截止层3为N型场截止层,漂移区4为N型漂移区。
其中,所述宽部62包括宽部电极621和宽部介质层622,宽部电极621通过宽部介质层622与漂移区4隔离;所述窄部61包括窄部电极611和窄部介质层612,窄部电极611通过窄部介质层612分别与漂移区4、载流子存储层8、P型基区9隔离。
所述宽部电极621的宽度大于窄部电极611的宽度,宽部电极621与窄部电极611电连接,且宽部电极621、窄部电极611都与发射极金属层5电连接,假栅结构6与发射极等电位,有效屏蔽了栅电极71/71’的栅信号,从而大幅降低IGBT器件的米勒电容,提高器件开关速度,降低器件开关损耗。
同时,由于宽部电极621横向扩展,即宽部电极621的宽度大于窄部电极611的宽度,宽部电极621与栅电极71/71’的电场屏蔽作用,本案的IGBT器件可在不降低耐压的情况下,提高载流子存储层8的浓度,从而提高发射极侧载流子浓度,降低器件导通压降。
所述栅极结构7位于假栅结构6之间,其包括栅电极71/71’和栅介质层72/72’,栅电极71/71’通过栅介质层72/72’分别与漂移区4、载流子存储层8、P型基区9、N+发射区11隔离。具体地,栅电极71/71’可以采用以下两种实施方式:
实施例1:
如图1所示,栅电极71的深度不小于窄部电极611的深度,且不大于宽部电极621的深度,即栅电极71的底面深度超过窄部电极611的底面深度,且栅电极71的底面深度不超过宽部电极621的底面深度。当栅电极71的底面与宽部电极621的底面持平时,为栅电极71的最大深度,超过时不能满足耐压条件,且米勒电容会相应增大。
实施例2:
如图2所示,栅电极71’的深度小于窄部电极611的深度,此时栅电极71’位于窄部电极611之间,且位于宽部电极621上方。与实施例1相比较,本实施例的米勒电容更小。
以上仅为本发明的较佳实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。
Claims (5)
1.一种沟槽栅IGBT器件,其特征在于,包括从下至上依次层叠设置的集电极金属层、集电区、场截止层、漂移区、沟槽结构和发射极金属层;所述沟槽结构包括假栅结构和栅极结构,其中假栅结构位于漂移区的上方侧面,栅极结构位于漂移区的上方中部;所述假栅结构与发射极金属层电连接,栅极结构经第一介质层与发射极金属层隔离;所述假栅结构包括窄部和宽部,且宽部位于窄部的下方;所述栅极结构与窄部之间的漂移区上方设有载流子存储层,载流子存储层的上方设有P型基区;所述P型基区的上方设有P+发射区与N+发射区,P+发射区、N+发射区分别与发射极金属层电连接。
2.根据权利要求1所述的沟槽栅IGBT器件,其特征在于,所述宽部包括宽部电极和宽部介质层,宽部电极通过宽部介质层与漂移区隔离;所述窄部包括窄部电极和窄部介质层,窄部电极通过窄部介质层分别与漂移区、载流子存储层、P型基区隔离;所述宽部电极的宽度大于窄部电极的宽度,且宽部电极与窄部电极电连接。
3.根据权利要求2所述的沟槽栅IGBT器件,其特征在于,所述栅极结构位于假栅结构之间,栅极结构包括栅电极和栅介质层。
4.根据权利要求3所述的沟槽栅IGBT器件,其特征在于,所述栅电极的深度不小于窄部电极的深度,且不大于宽部电极的深度。
5.根据权利要求3所述的沟槽栅IGBT器件,其特征在于,所述栅电极的深度小于窄部电极的深度。
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US20200235231A1 (en) * | 2019-01-23 | 2020-07-23 | University Of Electronic Science And Technology Of China | Igbt device with mos controllable hole path |
CN212342635U (zh) * | 2020-09-07 | 2021-01-12 | 珠海市浩辰半导体有限公司 | 一种沟槽栅igbt器件 |
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US20200235231A1 (en) * | 2019-01-23 | 2020-07-23 | University Of Electronic Science And Technology Of China | Igbt device with mos controllable hole path |
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CN112510085A (zh) * | 2020-11-27 | 2021-03-16 | 广东美的白色家电技术创新中心有限公司 | 一种igbt器件及智能功率模块 |
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