CN111834450B - 一种集成齐纳二极管的soi ligbt器件 - Google Patents

一种集成齐纳二极管的soi ligbt器件 Download PDF

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CN111834450B
CN111834450B CN202010901059.3A CN202010901059A CN111834450B CN 111834450 B CN111834450 B CN 111834450B CN 202010901059 A CN202010901059 A CN 202010901059A CN 111834450 B CN111834450 B CN 111834450B
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魏杰
马臻
郗路凡
罗小蓉
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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    • H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring

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Abstract

本发明属于功率半导体技术领域，具体涉及一种集成齐纳二极管的SOI LIGBT器件。本发明相对于传统的LIGBT，新器件在发射极端的P阱区中引入一个齐纳二极管，其P型区域和器件发射极电气相连，其N型区域与P阱区通过浮空欧姆金属实现电气相连。当集电极电压不断增加，齐纳二极管会发生反向击穿导通，从而使得P阱区的电势被箝位；这不仅有利降低器件栅电容，导通时可以降低饱和电流以提高器件短路能力，关断时过程中可提供空穴抽取通路以降低关断时间和关断损耗。相对于传统LIGBT结构，本发明提供的LIGBT新结构获得更优的导通压降与关断损耗之间的折中关系，并提升器件抗短路能力。

Description

一种集成齐纳二极管的SOI LIGBT器件
技术领域
本发明属于功率半导体技术领域，具体涉及一种内部集成齐纳二极管的槽栅SOILIGBT。
背景技术
SOI基的横向绝缘栅双极型晶体管(Lateral Insulated Gate BipolarTransistor,LIGBT)是双极型器件的典型代表。由于其高输入阻抗、低导通压降、高耐压特性、介质隔离等特点，广泛应用于各种电力电子系统，成为中高压开关应用领域的关键半导体器件。
LIGBT器件在正向导通时，漂移区内发生电导调制效应而具有较小的导通压降，但同时关断时需要将漂移区中存储的大量载流子抽出，导致器件具有较大关断损耗。而降低器件导通压降的措施常常使器件有大的饱和电流，从而导致较差的短路安全工作区(Shortcircuit safe operating area,SCSOA)。因此，LIGBT的导通压降、关断损耗以及安全工作区之间存在折中关系。另外，发射极端浮空P阱区结构可以增强LIGBT载流子存储效应，但在开启过程中，浮空P区中积累的空穴引起的位移电流对栅电容充电，严重影响器件的开启特性。
发明内容
针对上述问题，本发明提出一种集成齐纳二极管的SOI LIGBT器件，在发射极端浮空P阱中引入齐纳二极管实现箝位作用，从而改善器件的性能。
本发明的技术方案是：一种集成齐纳二极管的SOI LIGBT器件，包括自下而上依次层叠设置的P衬底层1、介质埋层2和N型漂移区3；所述N型漂移区3上层两端分别具有发射极结构和集电极结构；
所述发射极结构包括P型阱区4、P型重掺杂区5及N型重掺杂区6，所述P型重掺杂区5和所述N型重掺杂区6交替排列于所述P型阱区4的上层，且外侧靠近集电极结构的是N型重掺杂区6，P型重掺杂区5的结深大于N型重掺杂区6的结深；所述P型重掺杂区5和N型重掺杂区6上表面的共同引出端为发射极；
所述集电极结构包括N型缓冲区13和P型集电区14；所述P型集电区14位于N型缓冲区13上层中部；所述P型集电区14上表面的引出端为集电极；
其特征在于，在P型阱区4上层，还具有槽栅结构和齐纳二极管；
所述槽栅结构包括控制槽栅结构和阻挡槽栅结构；所述控制槽栅结构由第一槽栅介质层71和位于第一槽栅介质层71中的第一多晶硅72组成，所述控制槽栅结构沿器件垂直方向依次贯穿N型重掺杂区6和P型阱区4后延伸至所述N型漂移区3中；所述阻挡槽栅结构由第二槽栅介质层81和位于第二槽栅介质层81中的第二多晶硅82组成，所述阻挡槽栅结构沿器件垂直方向贯穿所述P型阱区4延伸至所述N型漂移区3中，所述阻挡槽栅结构的一侧与最外侧的N型重掺杂区6接触，且控制槽栅结构和阻挡槽栅结构之间间隔有P型重掺杂区5；所述控制槽栅多晶硅72和所述阻挡槽栅多晶硅82的共同引出端为栅电极；阻挡槽栅结构的另一侧与齐纳二极管接触；
所述齐纳二极管结构包括P型区域9和N型区域10，所述P型区域9位于N型区域10上层一侧，且P型区域9与阻挡槽栅结构接触；所述P型阱区4与所述N型区域10通过导电材料11电气连接，所述P型区域9的引出端与发射极相连；在齐纳二极管与集电极结构之间的N型漂移区3上表面，还具有场氧层12，且场氧层12还沿P型阱区4和N型缓冲区13的上表面向两侧延伸。
进一步的所述的N型漂移区3上层还具有P型埋层15，所述P型埋层15与所述P型阱区4接触。
进一步的，所述器件采用的半导体材料为Si、SiC、SiGe、GaAs或GaN中的一种。
本发明的有益效果为，相对于传统LIGBT结构，本发明导通时改善了导通压降与关断损耗间的折中关系。齐纳二极管的引入降低了器件的密勒电容，提高了器件的开关速度。另外，还降低了饱和电流，提高了短路能力，扩大了安全工作区。
附图说明
图1为实施例1的结构示意图；
图2为实施例2的结构示意图；
具体实施方式
下面结合附图和实施例，详细描述本发明的技术方案：
实施例1
如图1所示，本例的具有集成齐纳二极管的槽栅SOI LIGBT与传统器件结构相比，在P阱区4中靠近N型漂移区3一侧集成有齐纳二极管。
本例的工作原理为：
在正向导通时，发射极端阻挡槽栅和控制槽栅起到物理阻挡作用，有利于提高漂移区载流子浓度，同时控制槽栅两侧及阻挡槽栅靠近发射极一侧均有沟道存在，可增大器件沟道密度以降低沟道区电阻，综合作用下器件Von可显著降低。随着阳极电压上升，齐纳二极管发生击穿，使得P阱区4处的电势被箝位，从而降低了密勒电容；同时齐纳二极管的击穿电流迅速增大，提供了空穴通路，使器件的饱和电流降低，从而提高器件的安全工作区。
器件关断过程中，随着阳极电压上升，齐纳二极管反向击穿导通，可以帮助抽取空穴以加快器件关断，从而降低关断损耗。
正向阻断状态下，齐纳二极管发生击穿使P阱区4的电势被箝位，可以保护槽栅电场，避免拐角处提前击穿，提高器件耐压。
实施例2
如图2所示，本例与实施例1中图1的区别在于，本例中N型漂移区3上表面引入一个P型埋层15，与P型阱区4侧面接触。本实施例中器件工作机理和实施例1区别在于：引入的P型埋层15与N型漂移区3之间相互耗尽，形成类似超结(Super junction，SJ)结构。在正向阻断状态时，本例中引入的P型埋层15可与耗尽N型漂移区3相互耗尽，从而优化器件的耐压。同时，器件关断时，P型埋层15和N型漂移区3相互抽取空穴和电子，可加速器件的耗尽，从而进一步降低关断时间，减小关断损耗。

Claims (2)

1.一种集成齐纳二极管的SOI LIGBT器件，包括自下而上依次层叠设置的P衬底层(1)、介质埋层(2)和N型漂移区(3)；所述N型漂移区(3)上层两端分别具有发射极结构和集电极结构；
所述发射极结构包括P型阱区(4)、P型重掺杂区(5)及N型重掺杂区(6)，所述P型重掺杂区(5)和所述N型重掺杂区(6)交替排列于所述P型阱区(4)的上层，且P型阱区(4)最外侧靠近集电极结构的是N型重掺杂区(6)，P型重掺杂区(5)的结深大于N型重掺杂区(6)的结深；所述P型重掺杂区(5)和N型重掺杂区(6)上表面的共同引出端为发射极；
所述集电极结构包括N型缓冲区(13)和P型集电区(14)；所述P型集电区(14)位于N型缓冲区(13)上层中部；所述P型集电区(14)上表面的引出端为集电极；
其特征在于，在P型阱区(4)上层，还具有槽栅结构和齐纳二极管；
所述槽栅结构包括控制槽栅结构和阻挡槽栅结构；所述控制槽栅结构由第一槽栅介质层(71)和位于第一槽栅介质层(71)中的第一多晶硅(72)组成，所述控制槽栅结构沿器件垂直方向依次贯穿N型重掺杂区(6)和P型阱区(4)后延伸至所述N型漂移区(3)中；所述阻挡槽栅结构由第二槽栅介质层(81)和位于第二槽栅介质层(81)中的第二多晶硅(82)组成，所述阻挡槽栅结构沿器件垂直方向贯穿所述P型阱区(4)延伸至所述N型漂移区(3)中，所述阻挡槽栅结构的一侧与最外侧的N型重掺杂区(6)接触，且控制槽栅结构和阻挡槽栅结构之间间隔有P型重掺杂区(5)；所述控制槽栅多晶硅(72)和所述阻挡槽栅多晶硅(82)的共同引出端为栅电极；阻挡槽栅结构的另一侧与齐纳二极管接触；
所述齐纳二极管包括P型区域(9)和N型区域(10)，所述P型区域(9)位于N型区域(10)上层一侧，且P型区域(9)与阻挡槽栅结构接触；所述P型阱区(4)与所述N型区域(10)通过导电材料(11)电气连接，所述P型区域(9)的引出端与发射极相连；在齐纳二极管与集电极结构之间的N型漂移区(3)上表面，还具有场氧层(12)，且场氧层(12)还沿P型阱区(4)和N型缓冲区(13)的上表面向两侧延伸。
2.根据权利要求1所述的一种集成齐纳二极管的SOI LIGBT器件，其特征在于，所述的N型漂移区(3)上层还具有P型埋层(15)，所述P型埋层(15)与所述P型阱区(4)接触。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10321857A (ja) * 1997-03-17 1998-12-04 Fuji Electric Co Ltd 高破壊耐量ｍｏｓ型半導体装置
US7897997B2 (en) * 2008-02-23 2011-03-01 Force Mos Technology Co., Ltd. Trench IGBT with trench gates underneath contact areas of protection diodes
CN104916636A (zh) * 2014-03-14 2015-09-16 富士电机株式会社 半导体装置
CN110416295A (zh) * 2019-08-30 2019-11-05 电子科技大学 一种沟槽型绝缘栅双极晶体管及其制备方法
CN110504308A (zh) * 2019-08-29 2019-11-26 电子科技大学 一种高速低损耗的多槽栅高压功率器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10321857A (ja) * 1997-03-17 1998-12-04 Fuji Electric Co Ltd 高破壊耐量ｍｏｓ型半導体装置
US7897997B2 (en) * 2008-02-23 2011-03-01 Force Mos Technology Co., Ltd. Trench IGBT with trench gates underneath contact areas of protection diodes
CN104916636A (zh) * 2014-03-14 2015-09-16 富士电机株式会社 半导体装置
CN110504308A (zh) * 2019-08-29 2019-11-26 电子科技大学 一种高速低损耗的多槽栅高压功率器件
CN110416295A (zh) * 2019-08-30 2019-11-05 电子科技大学 一种沟槽型绝缘栅双极晶体管及其制备方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MOS栅控高压功率器件电流输运模式及新结构研究;魏杰;《中国博士学位论文全文数据库 信息科技辑》;20190315;I135-18 *
Simulation Study of a Novel Snapback-Free and Low Turn-Off Loss Reverse-Conducting IGBT With Controllable Trench Gate;Jie Wei，Xiaorong Luo，Linhua Huang,Bo Zhang;《IEEE ELECTRON DEVICE LETTERS》;20180228;252-255 *

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