CN109585540B - 一种具有载流子存储层的平面栅igbt器件 - Google Patents

一种具有载流子存储层的平面栅igbt器件 Download PDF

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CN109585540B
CN109585540B CN201811473042.1A CN201811473042A CN109585540B CN 109585540 B CN109585540 B CN 109585540B CN 201811473042 A CN201811473042 A CN 201811473042A CN 109585540 B CN109585540 B CN 109585540B
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易波
李平
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University of Electronic Science and Technology of China
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Abstract

本发明涉及功率半导体领域，提供一种具有载流子存储层的平面栅IGBT器件，用以解决现有的具有载流子存储层的槽栅IGBT栅驱电荷过大、短路安全工作区较小以及CSL层浓度受限的问题。本发明将传统用于制作槽栅IGBT沟道的深槽与槽底部的P型埋层结合构成电场屏蔽结构，实现对载流子存储层电位的钳位，使得本发明IGBT的载流子存储层的浓度能够比传统IGBT高很多，能够具有更高的阴极注入效率，获得更优的导通压降和关断损耗的折中关系。同时，由于采用平面栅和电场屏蔽结构，本发明IGBT具有更低的栅驱动功耗和更低的饱和电流密度，从而提高了IGBT的安全工作区。

Description

一种具有载流子存储层的平面栅IGBT器件
技术领域
本发明涉及功率半导体领域，具体提供一种具有低导通压降，低驱动功耗和高短路安全工作区的快速关断特性的IGBT器件。
背景技术
IGBT折中了BJT的低导通压降和MOSFET快速开关的特点，因而被广泛应用于电力电子系统。根据IGBT栅的结构，可以将IGBT分为槽栅和平面栅两类；平面栅具有较低的栅驱动损耗，并且饱和电流密度较低，短路安全工作区较大，但是由于存在JEFT区，其导通压降较大；槽栅则消除了JEFT区，从而其导通压降较小，但是由于沟道密度较大，其栅驱动损耗较大，饱和电流密度较高，从而短路安全工作区较小。
同时，由于IGBT导通时阳极注入大量非平衡载流子来形成电导调制效应以降低导通压降；其关断时，漂移区的少数载流子需要一段时间才能消失，从而使得IGBT关断速度较慢。为了进一步优化IGBT导通压降和关断速度的折中关系，具有载流子存储层(CarrierStored：CSL)的IGBT被提出，如图4所示，该IGBT采用载流子存储层来提高IGBT阴极的注入效率，从而可以降低阳极的注入效率来获得相同的导通压降；这样，IGBT在关断时，由于阳极注入较低，关断时间被大大降低。对于如图4所示的具有载流子存储层的IGBT，随着CSL的浓度的提高，器件将获得更优的性能；但是，当CSL浓度超过一定值时，IGBT的耐压就会急剧下降，同时，如图4所示的槽栅结构沟道密度很大，这将增大IGBT的栅驱动电荷，并且导致IGBT饱和电流密度很高，使得IGBT的短路安全工作区极大地降低。为了提高CS L的浓度，具有浮空P埋层的槽栅IGBT被提出，如图5所示，该结构可以使得CSL的浓度进一步提高，有助于优化器件性能；但是该器件的栅驱动电荷和短路安全工作区并没有得到改善，并且CSL的浓度仍然不能过高，不然IGBT的击穿电压将急剧降低。进一步，一种具有自偏置PMOS钳位CSL层的结构被提出，如文献《Li P,Lyu X,Cheng J,et al.“A low on-state voltage andsaturation current TIGBT with self-biased pMOS,”IEEE Electron Devi ceLetters,2016,37(11):1470-1472》，该结构很好地解决的CSL层浓度不能过高的问题，但是由于仍然采用深槽作为IGBT的栅，所以IGBT的栅电荷密度仍然较高，弥勒电容较大。
发明内容
本发明的目的在于针对现有的具有载流子存储层的槽栅IGBT栅驱动电荷过大、短路安全工作区较小以及CSL浓度受限的问题，提出一种新型具有载流子存储层的平面栅IGBT。
为实现该目的，本发明采用的技术方案为：
一种具有载流子存储层的IGBT器件，包括：
耐压区1；
设置于耐压区1上的N型载流子存储层3与N型半导体层17；
设置于N型载流子存储层3上的N型JFET区2及与之相邻的P型基区6，且所述P型基区6同时位于N型半导体层17上；
设置在基区6内的N型阴极源区4及与之相邻的P型体接触区5；
设置于半导体上表面的一个深入至耐压区1的深槽，所述深槽贯穿所述体接触区5与P型基区6、且将N型载流子存储层3与N型半导体层17完全分隔；所述深槽下方设置有位于耐压区1中的P型埋层7，且P型埋层7与深槽底部相接触；所述深槽由槽壁介质层15和槽内导体16构成；
设置于半导体区上表面的栅氧化层10和阴极金属13，所述栅氧化层10覆盖了部分或全部N型JFET区2、部分P型基区6及部分阴极源区4，所述阴极金属13覆盖部分阴极源区4、体接触区5及深槽，且所述栅氧化层10与阴极金属13不接触；
设置于栅氧化层10上的重掺杂多晶硅11，设置于重掺杂多晶硅11上的作为栅电极金属12；
设置在耐压区1下的N型缓冲层9，设置在N型缓冲层9下的P型阳极区8，设置在P型阳极区8下的阳极金属14。
进一步的，所述N型半导体区17的掺杂浓度小于或等于所述N型载流子存储层3的掺杂浓度。
本发明的有益效果在于：
本发明提供一种具有载流子存储层的平面栅IGBT器件，将传统用于制作槽栅IGBT沟道的深槽与槽底部的P型埋层结合构成电场屏蔽结构，实现对载流子存储层电位的钳位；其钳位原理在于，当IGBT阳极电压升高时，N型区17的电位随之升高，由于N型区17掺杂较低，当N型区17的电位升高到一定值时，N型区17和槽壁15接触处的半导体表面首先发生反型，形成空穴沟道。P型埋层将通过自动开启的P型沟道和阴极连接在一起，漂移区产生的空穴电流将通过开启的P型沟道而流向阴极。由于绝大部分空穴电流不再流过反偏的由载流子存储层和P型基区构成的反偏PN结，从而，该PN结的反偏电压不再继续增加，击穿将不再提前发生在这个重掺杂的反偏PN结上；使得本发明IGBT的载流子存储层的浓度能够比传统IGBT高很多，能够具有更高的阴极注入效率，获得更低的导通压降。同时，由于载流子存储层电位被电场屏蔽结构很好地钳位，IGBT的nMOS沟道的漏极电位很低，从而本发明的IGBT在开启情况下具有较低的饱和电流密度，有利于提高IGBT的安全工作区。另外，由于深槽的电场屏蔽作用，可以使得平面栅IGBT的JFET区的掺杂浓度很大程度地提高，加上更高的载流子存储层浓度，从而使得平面栅IGBT的工作电流密度能够比槽栅IGBT更高，同时饱和电流密度却能更低。综上，本发明的IGBT具有平面栅IGBT低的饱和电流密度、低的栅驱动电荷以及槽栅IGBT低的导通压降的特性，且具有更好的导通压降和关断损耗的折中关系。
附图说明
图1为本发明实施例1中一种具有载流子存储层的平面栅IGBT元胞结构示意图。
图2为本发明实施例2中一种具有载流子存储层的平面栅IGBT元胞结构示意图。
图3为本发明实施例2中一种具有载流子存储层的平面栅IGBT元胞结构沿AA’的切面示意图。
图4为现有具有载流子存储层的槽栅IGBT元胞结构示意图。
图5为现有具有载流子存储层和浮空P埋层的槽栅IGBT元胞结构示意图。
具体实施方式
下面结合附图和实施例对本发明做进一步详细说明。
实施例1
本实施例提供一种具有载流子存储层的平面栅IGBT器件，其元胞结构如图1所示，包括：
作为耐压区的N型轻掺杂区1；
设置于耐压区1上的N型载流子存储层3与N型半导体层17；
设置于N型载流子存储层3上的N型JFET区2以及与N型JFET区2相邻的作为N沟道MOSFET的基区的P型半导体区6，所述P型半导体区6同时也设置于N型半导体区17之上；
设置在基区6内的作为阴极源区的N+型重掺杂区4以及作为体接触区的P+重掺杂区5；
设置于半导体上表面的一个深入至耐压区1的深槽，所述深槽贯穿所述P+重掺杂区5与P型半导体区6、且将N型载流子存储层3与N型半导体层17完全分隔；深槽由槽壁介质层15和槽内导体16构成；深槽底部的下方设置有位于耐压区1中的P型埋层7，且P型埋层7与槽壁介质层15相接触，深槽与P型埋层共同构成一个电场屏蔽结构的一部分；
设置于半导体(N型JFET区2与P型半导体区6)上表面的栅氧化层10和阴极金属13，所述栅氧化层10覆盖了部分或全部N型JFET区2、部分P型半导体区6及部分阴极源区4；所述阴极金属13覆盖部分阴极源区4、体接触区5及深槽(槽壁介质层15和槽内导体16)；
设置于栅氧化层10上的重掺杂多晶硅11，设置于重掺杂多晶硅11上的作为栅电极金属12；
设置于耐压区1下的N型缓冲层9，设置在N型缓冲层9下的P型阳极区8，设置在P型阳极区8下的阳极金属14。
上述平面栅IGBT器件中，深槽、P型埋层、N型半导体区17、位于17上的P型区6以及体接触区5和阴极金属13共同构成一个电场屏蔽结构。在耐压时，由于N型半导体区17掺杂较低，当阳极电压升高时，由P型埋层7、N型半导体区17、P型基区6以及深槽侧壁共同构成的一个PMOS的沟道将首先自动开启，耐压区产生的空穴电流将由P型沟道流向阴极。由于绝大部分空穴电流不再经过反偏的由载流子存储层3和基区6构成的PN结，所以该PN结反偏电压不再增加。因此，即使载流子存储层浓度很高，上述PN结也不会提前击穿。由于载流子存储层浓度极大程度地提高，本实施例将获得更优的导通压降和关断损耗的折中关系。又由于采用平面栅和上述钳位结构，不仅电子沟道密度降低，同时，IGBT中的MOS FET的漏极被钳位在较低电压，所以该IGBT将具有较低的饱和电流密度和更大的短路安全工作区。
实施例2
本实施例提供一种具有载流子存储层的平面栅IGBT器件，其元胞结构如图2所示，沿AA’的切面示意图如图3所示；
其与实施例1的不同在于：沟道电流的方向与深槽的侧壁平行或近似平行。
以上所述，仅为本发明的具体实施方式，本说明书中所公开的任一特征，除非特别叙述，均可被其他等效或具有类似目的的替代特征加以替换；所公开的所有特征、或所有方法或过程中的步骤，除了互相排斥的特征和/或步骤以外，均可以任何方式组合。

Claims (1)

1.一种具有载流子存储层的IGBT器件，包括：
耐压区（1）；
设置于耐压区上的N型载流子存储层（3）与N型半导体层（17）；
设置于N型载流子存储层（3）上的N型JFET区（2）及与之相邻的P型基区（6），且所述P型基区（6）同时位于N型半导体层（17）上；
设置在P型基区（6）内的N型阴极源区（4）及与之相邻的P型体接触区（5）；
设置于P型基区（6）上表面的一个深入至耐压区（1）的深槽，所述深槽贯穿所述体接触区（5）与P型基区（6）、且将N型载流子存储层（3）与N型半导体层（17）完全分隔；所述深槽下方设置有位于耐压区（1）中的P型埋层（7），且P型埋层与深槽底部相接触；所述深槽由槽壁介质层（15）和槽内导体（16）构成；
设置于N型JFET区（2）与P型基区（6）上表面的栅氧化层（10）和阴极金属（13），所述栅氧化层覆盖了部分或全部N型JFET区（2）、部分P型基区（6）及部分阴极源区（4），所述阴极金属覆盖部分阴极源区（4）、体接触区（5）及深槽，且所述栅氧化层（10）与阴极金属（13）不接触；
设置于栅氧化层（10）上的重掺杂多晶硅（11），设置于重掺杂多晶硅上的栅电极金属（12）；
设置在耐压区（1）下的N型缓冲层（9），设置在N型缓冲层下的P型阳极区（8），设置在P型阳极区下的阳极金属（14）；
所述N型半导体层（17）的掺杂浓度小于或等于所述N型载流子存储层（3）的掺杂浓度。
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