CN113990924A - 一种降低关断损耗的igbt结构 - Google Patents

一种降低关断损耗的igbt结构 Download PDF

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CN113990924A
CN113990924A CN202111245565.2A CN202111245565A CN113990924A CN 113990924 A CN113990924 A CN 113990924A CN 202111245565 A CN202111245565 A CN 202111245565A CN 113990924 A CN113990924 A CN 113990924A
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伍伟
李岩松
陈勇
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University of Electronic Science and Technology of China
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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Abstract

本发明提供了一种降低关断损耗的IGBT结构，该结构在常规IGBT结构的基础上，在IGBT背面增添栅极结构和N+型电子发射区。当IGBT关断时给背面栅施加高电压，形成电子通路。该电子通路可以起到短路P型集电区的效果，在IGBT关断时提供电子抽取通道，从而显著加快关断过程中N型漂移区的少数载流子抽取速度，改善IGBT关断过程中的电流拖尾现象，降低器件在关断过程中的能量损耗。

Description

一种降低关断损耗的IGBT结构
技术领域
本发明涉及半导体领域，具体涉及一种降低关断损耗的IGBT结构。
背景技术
IGBT，是由BJT(双极型三极管)和MOS(绝缘栅型场效应管)组成的复合全控型电压驱动式功率半导体器件。它的驱动功率小而饱和压降低，非常适合应用于直流电压为600V及以上的变流系统如交流电机、变频器、开关电源、照明电路、牵引传动等领域。随着新能源，混合动力汽车以及新型工业设备等领域的不断发展，其应用中对于高效的电源控制与电源分配的需求，使得IGBT模块的应用市场日渐增大。
IGBT在导通时，P型发射区和P型集电区都会向N型飘逸区注入大量空穴，增加器件的电导率，降低导通损耗。但在IGBT关断时，空穴的注入使得载流子无法快速完成消除，会造成电流的拖尾现象。电流拖尾无疑会增大器件的关断损耗。
发明内容
针对降低IGBT器件关断损耗的需求，本发明提供了一种降低关断损耗的IGBT结构。
本发明解决上述技术问题所采用的技术方案是：一种降低关断损耗的IGBT结构，其元胞结构包括P型集电区(1)，N型缓冲层(2)和N型漂移区(3)，载流子存储层(4)及P型基区(5)，所述P型基区(5)上设有N+型发射区(6)和P+型发射区(7)，N+型发射区(6)之间为由SiO2氧化层(8)和多晶硅(9)所构成的栅极结构。器件背面增添N+型高掺杂区(10)和一个由SiO2氧化层(11)和多晶硅(12)所构成的栅极结构。
本发明的技术方案相对常规IGBT结构，主要针对IGBT的背面结构进行改进，在器件背面增加N+型发射区和一个背面栅极结构，当IGBT处于开启状态时，背面栅加低电位。当器件关断时，背面栅加高电位，形成N沟道，提供电子抽取通路，减小器件关断损耗。
进一步地，所增加的N+型高掺杂区(10)厚度接近但小于P型集电区(1)的厚度。背面的栅极深度要大于P型集电区(1)的厚度，但小于P型集电区(1)加上N型缓冲层(2)的厚度。
进一步地，对所添加的背面栅极结构与正面的栅极结构进行独立控制。在IGBT正向导通时正面栅加高电位而背面栅接地，当IGBT关断时，正面栅加低电位，背面栅加高电位开启。
本发明的有益效果为：本发明提供了一种降低关断损耗的IGBT结构，该结构在常规IGBT结构的基础上，在IGBT背面增添栅极结构和N+型电子发射区。当IGBT关断时给背面栅施加高电压，形成电子通路。该电子通路可以起到短路P型集电区的效果，在IGBT关断时提供电子抽取通道，从而显著加快关断过程中N型漂移区的少数载流子抽取速度，改善IGBT关断过程中的电流拖尾现象，降低器件在关断过程中的能量损耗。
附图说明
图1为本发明的结构示意图；
图2为常规IGBT结构示意图；
图3为常规IGBT与本发明的关断过程电流变化示意图。
具体实施方式
下面对本发明的具体实施方式进行描述，以便于本技术领域的技术人员理解本发明，但应该清楚，本发明不限于具体实施方式的范围，对本技术领域的普通技术人员来讲，只要各种变化在所附的权利要求限定和确定的本发明的精神和范围内，这些变化是显而易见的，一切利用本发明构思的发明创造均在保护之列。
本发明提出了一种降低关断损耗的IGBT结构，其元胞结构包括P型集电区(1)，N型缓冲层(2)和N型漂移区(3)，载流子存储层(4)及P型基区(5)，所述P型基区(5)上设有N+型发射区(6)和P+型发射区(7)，N+型发射区(6)之间为由SiO2氧化层(8)和多晶硅(9)所构成的栅极结构。器件背面增添N+型高掺杂区(10)和一个由SiO2氧化层(11)和多晶硅(12)所构成的栅极结构。
本发明的方案相对常规IGBT结构，主要针对IGBT的背面结构进行改进，在器件背面增加N+型发射区和一个背面栅极结构。常规IGBT进入关断状态时，正面栅极接低电位，P型发射区的N型沟道消失，正面PN结反偏。但集电极接高电压，背面P型集电区和N型场截止层间的PN结正偏，由于N型漂移区中存在大量空穴，使得在关断时电流无法迅速减小至0，而是存在一个拖尾电流。本发明在器件背面增添N型高掺杂区和背面栅极结构，当IGBT关断时，背面栅极接高电位，在P型集电区中形成N沟道，将背面P型集电区和N型场截止层间的PN结短路，制造电子抽取通路，从而极大地提高了漂移区少子抽取效率，改善IGBT在关断过程中的电流拖尾现象，降低器件的关断损耗。
在一次实施例中，如图3所示，温度取室温，集电极电压为600V，监测本发明与常规IGBT的关断过程。观察到常规本发明的关断电流曲线相比常规IGBT，电流拖尾现象的改善效果明显，故说明本方案可以成功抑制电流拖尾现象，降低器件的关断损耗。
进一步地，所增加的N+型高掺杂区(10)厚度接近但小于P型集电区(1)的厚度。背面的栅极深度要大于P型集电区(1)的厚度，但小于P型集电区(1)加上N型缓冲层(2)的厚度。
进一步地，对所添加的背面栅极结构与正面的栅极结构进行独立控制。在IGBT正向导通时正面栅加高电位而背面栅不工作，当IGBT关断时，正面栅加低电位，背面栅加高电位开启。
综上所述，本发明提供了一种降低关断损耗的IGBT结构，该结构在常规IGBT结构的基础上，在IGBT背面增添栅极结构和N+型电子发射区。当IGBT关断时给背面栅施加高电压，形成电子通路。该电子通路可以起到短路P型集电区的效果，在IGBT关断时提供电子抽取通道，从而显著加快关断过程中N型漂移区的少数载流子抽取速度，改善IGBT关断过程中的电流拖尾现象，降低器件在关断过程中的能量损耗。

Claims (3)

1.一种降低关断损耗的IGBT结构，其元胞结构包括P型集电区(1)，N型缓冲层(2)和N型漂移区(3)，载流子存储层(4)及P型基区(5)，所述P型基区(5)上设有N+型发射区(6)和P+型发射区(7)，N+型发射区(6)之间为由SiO2氧化层(8)和多晶硅(9)所构成的栅极结构。器件背面增添N+型高掺杂区(10)和一个由SiO2氧化层(11)和多晶硅(12)所构成的栅极结构。
2.根据权利要求1所述的降低关断损耗的IGBT结构，其特征在于，器件的背面结构部分，所增加的N+型高掺杂区(10)厚度接近但小于P型集电区(1)的厚度。背面的栅极深度要大于P型集电区(1)的厚度，但小于P型集电区(1)加上N型缓冲层(2)的厚度。
3.根据权利要求1和2所述的降低关断损耗的IGBT结构，其特征在于，对所添加的背面栅极结构与正面的栅极结构进行独立控制。在IGBT正向导通时正面栅加高电位而背面栅接地，当IGBT关断时，正面栅加低电位，背面栅加高电位开启电子沟道。
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
CN114203810A (zh) * 2021-12-10 2022-03-18 电子科技大学 一种增加背面栅降低关断损耗的超高压igbt结构

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CN107799587A (zh) * 2017-10-20 2018-03-13 电子科技大学 一种逆阻型igbt及其制造方法
CN109065607A (zh) * 2018-08-20 2018-12-21 电子科技大学 一种双极型功率半导体器件及其制备方法
CN109585540A (zh) * 2018-12-04 2019-04-05 电子科技大学 一种具有载流子存储层的平面栅igbt器件
CN109686788A (zh) * 2018-11-20 2019-04-26 电子科技大学 一种具有载流子存储层的槽栅igbt器件
US20200235231A1 (en) * 2019-01-23 2020-07-23 University Of Electronic Science And Technology Of China Igbt device with mos controllable hole path
CN113437141A (zh) * 2021-06-24 2021-09-24 电子科技大学 一种具有多晶硅二极管栅极结构的浮空p区cstbt器件

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107799587A (zh) * 2017-10-20 2018-03-13 电子科技大学 一种逆阻型igbt及其制造方法
CN109065607A (zh) * 2018-08-20 2018-12-21 电子科技大学 一种双极型功率半导体器件及其制备方法
CN109686788A (zh) * 2018-11-20 2019-04-26 电子科技大学 一种具有载流子存储层的槽栅igbt器件
CN109585540A (zh) * 2018-12-04 2019-04-05 电子科技大学 一种具有载流子存储层的平面栅igbt器件
US20200235231A1 (en) * 2019-01-23 2020-07-23 University Of Electronic Science And Technology Of China Igbt device with mos controllable hole path
CN113437141A (zh) * 2021-06-24 2021-09-24 电子科技大学 一种具有多晶硅二极管栅极结构的浮空p区cstbt器件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114203810A (zh) * 2021-12-10 2022-03-18 电子科技大学 一种增加背面栅降低关断损耗的超高压igbt结构

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Application publication date: 20220128