CN116454127A - 一种低关断损耗的soi ligbt - Google Patents

一种低关断损耗的soi ligbt Download PDF

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CN116454127A
CN116454127A CN202310309447.6A CN202310309447A CN116454127A CN 116454127 A CN116454127 A CN 116454127A CN 202310309447 A CN202310309447 A CN 202310309447A CN 116454127 A CN116454127 A CN 116454127A
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陈兴欢
夏云
陈万军
孙瑞泽
刘超
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明属于功率半导体技术领域，特别涉及一种低关断损耗的SOI LIGBT。本发明将SOI LIGBT的耐压层设置为由N型漂移区(3)和P型漂移区(4)横向排列的形式，形成NP横向排列漂移区，从而NP横向排列漂移区使器件内部形成了肖克来二极管结构，此肖克来二极管由一个PNP晶体管(发射极：P+集电极，基极：N型漂移区，集电极：P型漂移区)和一个NPN晶体管(发射极：N型载流子存储层，基极：P型漂移区，集电极：N型漂移区)构成，从而实现了更低的关断损耗。

Description

一种低关断损耗的SOI LIGBT
技术领域
本发明属于功率半导体技术领域，特别涉及一种低关断损耗的SOI LIGBT(Lateral insulated gate bipolar transistor，横向绝缘栅双极型晶体管)结构。
背景技术
基于SOI(Silicon-on-insulator,绝缘衬底上的硅)技术的LIGBT具有出色的电流能力和隔离能力，在功率集成电路中越来越有竞争力。但是由漂移区中过剩载流子引起的关断损耗依然是SOI LIGBT面临的主要挑战。改变栅极、阴极结构来增强阴极侧载流子存储、改变阳极结构来减少阳极侧载流子积累，以及改变耐压层结构来加速漂移区内载流子的抽取等方法被采用于传统SOI LIGBT的优化，但是依然存在关断时电压上升慢的问题。
发明内容
本发明的目的，就是为了优化SOI LIGBT的导通压降与关断损耗，提出一种低关断损耗的SOI LIGBT。
本发明的技术方案：一种低关断损耗的SOI LIGBT，其元胞包括衬底结构、BOX结构、耐压层结构、集电极结构、发射极结构和栅极结构，所述衬底结构为硅衬底1；所述BOX结构为绝缘介质2；所述绝缘介质2位于硅衬底1的上表面；所述耐压层结构包括N型漂移区3和P型漂移区4，所述N型漂移区3和P型漂移区4并列设置于绝缘介质2上表面；所述集电极结构位于N型漂移区3远离P型漂移区4一侧的顶部，集电极结构包括N型阱区5、P+集电区6和集电极金属7；所述P+集电区6位于N型阱区5远离P型漂移区4一侧的顶部；所述集电极金属7位于P+集电区6上表面；所述集电极金属1的上表面引出端为器件的集电极C；
所述发射极结构位于P型漂移区4远离N型漂移区3一侧的顶部，发射极结构包括N型载流子存储层8、P型阱区9、N型发射区10、P型体接触区11和发射极金属12；所述N型载流子存储层8的下表面与P型漂移区4接触；所述P型阱区9位于N型载流子存储层8的上表面；所述N型发射区10和P型体接触区11位于P型阱区9的上表面，并且P型体接触区11位于远离N型漂移区3的一侧；所述发射极金属12位于N型发射区10和P型体接触区11的上表面；所述集电极金属12的上表面引出端为器件的集电极E；
所述栅极结构位于P型漂移区4中并且栅极结构的一侧与发射极结构靠近N型漂移区3的一侧接触，栅极结构为沟槽栅结构，包括导电材料13和绝缘介质14；所述导电材料13位于绝缘介质14内，其引出端为器件的栅极G；所述绝缘介质14的侧面与N型载流子存储层8、P型阱区9和N型发射区10接触；
耐压层包括N型漂移区3和P型漂移区4，两者呈现横向排列的形式，形成NP横向排列漂移区。
本发明的有益效果为，本发明的一种具有NP横向排列漂移区的SOI IGBT提高了器件关断时电压上升的速度，降低了关断损耗。
附图说明
图1是本发明的SOI LIGBT结构；
图2是本发明的SOI LIGBT等效电路；
图3是本发明的SOI LIGBT等效电路与结构对应图；
图4是常规SOI LIGBT结构；
图5是常规SOI LIGBT等效电路；
具体实施方式
下面结合附图对本发明进行详细的描述。
如图1所示，为本发明的一种具有NP横向排列漂移区的SOI IGBT结构，其等效电路如图2所示。图3将图2中的等效电路映射到了结构中。图4和图5分别为常规SOI IGBT结构和等效电路图。可以看出，本发明器件的NP横向排列漂移区使器件内部形成了一个肖克来(Shockley)二极管结构。此肖克来二极管由一个PNP晶体管(发射极：P+集电极6，基极：N型漂移区3)，集电极：P型漂移区4和一个NPN晶体管(发射极：N型载流子存储层8，基极：P型漂移区4，集电极：N型漂移区3)构成。
本发明器件工作原理如下：
耐压时：器件栅极关断，发射极接地和集电极接正电位。此时肖克来二极管中的NPN晶体管的发射极(N型载流子存储层8)是浮空的状态，因此这个肖克来二极管不会导通，此肖克来二极管耐压。电场主要由N型漂移区3和P型漂移区4这个结来承担。由于这个结远离器件表面，因此耐压时高电场位于体内，表面的栅极结构以及N型载流子存储层8处的电场均较低，器件因此可以取得高的耐压。
正向导通时：器件栅极开启，发射极接地和集电极接正电位。此时栅极沟道开启，肖克来二极管中的NPN晶体管的发射极(N型载流子存储层8)与N+发射极10相连，其不再浮空。因此随着阳极电压的增加，P+阳极11注入P型漂移区4的空穴逐渐使NPN晶体管(发射极：N型载流子存储层8，基极：P型漂移区4，集电极：N型漂移区3)开启，开启后的NPN晶体管注入到电子到N型漂移区3中，使PNP晶体管(发射极：P+集电极6，基极：N漂移区3，集电极：P型漂移区4)开启。最终肖克来二极管进入PNPN晶闸管导通模式。N型漂移区3以及4型漂移区5都存在电导调制效应，器件导通压降低。
关断时：器件栅极关断，发射极接地和集电极接正电位。此时栅极沟道从开启到关断，肖克来二极管中的NPN晶体管的发射极(N型载流子存储层8)断开与N+发射极10的连接，其重新进入浮空状态，肖克来二极管逐渐从PNPN晶闸管导通模式退出。由于耐压的N型漂移区3和P型漂移区4这个结位于漂移区内部，器件要耐压的话，电场需在此处建立。由于漂移区内有大量空穴载流子，需要将此PN结附近的空穴浓度降低才能使电场在此PN结建立，因此的话，位于P型漂移区内4的空穴在PN结处电场建立前已通过发射极排出，而位于N型漂移区3的空穴也降低了。从而在电场建立的时候，P型漂移区4内以及N型漂移区3内的载流子已急剧降低，并且耗尽区是往两个方向进行耗尽，因此的话，器件内电场建立速度更快，电压上升时间降低，从而器件关断损耗将降低。

Claims (1)

1.一种低关断损耗的SOI LIGBT，其元胞包括衬底结构、BOX结构、耐压层结构、集电极结构、发射极结构和栅极结构，所述衬底结构为硅衬底(1)；所述BOX结构为绝缘介质(2)；所述绝缘介质(2)位于硅衬底(1)的上表面；其特征在于，所述耐压层结构包括N型漂移区(3)和P型漂移区(4)，所述N型漂移区(3)和P型漂移区(4)并列设置于绝缘介质(2)上表面；所述集电极结构位于N型漂移区(3)远离P型漂移区(4)一侧的顶部，集电极结构包括N型阱区(5)、P+集电区(6)和集电极金属(7)；所述P+集电区(6)位于N型阱区(5)远离P型漂移区(4)一侧的顶部；所述集电极金属(7)位于P+集电区(6)上表面；所述集电极金属(1)的上表面引出端为器件的集电极(C)；
所述发射极结构位于P型漂移区(4)远离N型漂移区(3)一侧的顶部，发射极结构包括N型载流子存储层(8)、P型阱区(9)、N型发射区(10)、P型体接触区(11)和发射极金属(12)；所述N型载流子存储层(8)的下表面与P型漂移区(4)接触；所述P型阱区(9)位于N型载流子存储层(8)的上表面；所述N型发射区(10)和P型体接触区(11)位于P型阱区(9)的上表面，并且P型体接触区(11)位于远离N型漂移区(3)的一侧；所述发射极金属(12)位于N型发射区(10)和P型体接触区(11)的上表面；所述集电极金属(12)的上表面引出端为器件的集电极(E)；
所述栅极结构位于P型漂移区(4)中并且栅极结构的一侧与发射极结构靠近N型漂移区(3)的一侧接触，栅极结构为沟槽栅结构，包括导电材料(13)和绝缘介质(14)；所述导电材料(13)位于绝缘介质(14)内，其引出端为器件的栅极(G)；所述绝缘介质(14)的侧面与N型载流子存储层(8)、P型阱区(9)和N型发射区(10)接触；
所述N型漂移区(3)和P型漂移区(4)形成NP横向排列漂移区。
CN202310309447.6A 2023-03-28 2023-03-28 一种低关断损耗的soi ligbt Pending CN116454127A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117374108A (zh) * 2023-11-17 2024-01-09 湖南杰楚微半导体科技有限公司 一种soi ligbt器件及其制备方法
CN117374108B (zh) * 2023-11-17 2024-06-11 湖南杰楚微半导体科技有限公司 一种soi ligbt器件及其制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117374108A (zh) * 2023-11-17 2024-01-09 湖南杰楚微半导体科技有限公司 一种soi ligbt器件及其制备方法
CN117374108B (zh) * 2023-11-17 2024-06-11 湖南杰楚微半导体科技有限公司 一种soi ligbt器件及其制备方法

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