WO2019145827A1 - 半導体材料、および半導体装置 - Google Patents

半導体材料、および半導体装置 Download PDF

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WO2019145827A1
WO2019145827A1 PCT/IB2019/050375 IB2019050375W WO2019145827A1 WO 2019145827 A1 WO2019145827 A1 WO 2019145827A1 IB 2019050375 W IB2019050375 W IB 2019050375W WO 2019145827 A1 WO2019145827 A1 WO 2019145827A1
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Prior art keywords
transistor
conductor
oxide
insulator
substrate
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PCT/IB2019/050375
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English (en)
French (fr)
Japanese (ja)
Inventor
國武寛司
長塚修平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to US16/964,115 priority Critical patent/US12317600B2/en
Priority to CN201980008397.XA priority patent/CN111742408B/zh
Priority to KR1020207021838A priority patent/KR102912136B1/ko
Priority to JP2019567417A priority patent/JP7202319B2/ja
Publication of WO2019145827A1 publication Critical patent/WO2019145827A1/ja
Anticipated expiration legal-status Critical
Priority to JP2022206199A priority patent/JP7513694B2/ja
Priority to JP2024103524A priority patent/JP7715884B2/ja
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    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
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    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
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    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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Definitions

  • One embodiment of the present invention relates to a semiconductor material and a semiconductor device.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • a semiconductor circuit such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of a semiconductor device.
  • Display devices liquid crystal display devices, light emitting display devices, etc.
  • projection devices lighting devices
  • electro-optical devices power storage devices
  • storage devices semiconductor circuits
  • imaging devices electronic devices, and the like may have semiconductor devices in some cases. .
  • one embodiment of the present invention is not limited to the above technical field.
  • One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • Oxide semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
  • oxide semiconductor for example, not only single-component metal oxides such as indium oxide and zinc oxide but also multi-component metal oxides are known.
  • oxides of multi-element metals in particular, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.
  • Non-Patent Documents 1 to 3 a c-axis aligned crystalline (CAAC) structure and an nc (nanocrystalline) structure which are neither single crystal nor amorphous are found in an oxide semiconductor (see Non-Patent Documents 1 to 3) ).
  • Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure.
  • non-patent documents 4 and 5 show that even oxide semiconductors that are less crystalline than the CAAC structure and the nc structure have minute crystals.
  • Non-Patent Document 6 a transistor using IGZO as an active layer has an extremely low off current (see Non-Patent Document 6), and LSIs and displays utilizing the characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8) .
  • An object of one embodiment of the present invention is to suppress a charging phenomenon which leads to fluctuation of characteristics, deterioration of an element, or dielectric breakdown in a semiconductor device.
  • a charging phenomenon which leads to fluctuation of characteristics, deterioration of an element, or dielectric breakdown in a semiconductor device.
  • dielectric breakdown due to abnormal charging is a more serious problem.
  • An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long time.
  • An object of one embodiment of the present invention is to provide a semiconductor device including a transistor including an oxide semiconductor, in which electrical characteristics and reliability of the transistor are stable.
  • An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics.
  • An object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high productivity.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom.
  • An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high information writing speed.
  • An object of one embodiment of the present invention is to provide a novel semiconductor device.
  • One embodiment of the present invention is a transistor including a first conductor, a second conductor, a third conductor, and an oxide semiconductor over a substrate, a first diode element, and a second diode element. Diode element and the third diode element, and the charge charged in the transistor is transferred to the semiconductor substrate through the first diode element, the second diode element, or the third diode element. Do.
  • the first diode element, the second diode element, the third diode element, and the fourth diode element are electrically connected to the fourth conductor.
  • One embodiment of the present invention is a transistor including a first conductor, a second conductor, a third conductor, and an oxide semiconductor over a substrate, a first capacitor, and a second capacitor. The charge stored in the transistor is moved and fixed to the first capacitor, the second capacitor, or the third capacitor.
  • the first capacitor, the second capacitor, and the third capacitor are electrically connected to the fourth conductor.
  • the fourth conductor functions as a gate electrode of the transistor.
  • the semiconductor device includes two or more transistors.
  • One embodiment of the present invention includes a first transistor, a second transistor, a third transistor, and a fourth transistor on a substrate, and the fourth transistor is a first conductor, A second conductor, a third conductor, and an oxide semiconductor, wherein the first conductor is electrically connected to the semiconductor substrate through the first transistor, and the second conductor is , And the third conductor is electrically connected to the semiconductor substrate via the first transistor, and the fourth conductor is electrically connected to the semiconductor substrate via the first transistor. It is electrically connected to the semiconductor substrate through the transistor 1.
  • the first transistor, the second transistor, and the third transistor function as capacitive elements.
  • the first transistor, the second transistor, and the third transistor function as diode elements.
  • a semiconductor device in which deterioration or dielectric breakdown of a device is suppressed can be provided.
  • a semiconductor device capable of holding data for a long time can be provided.
  • the semiconductor device in a semiconductor device including a transistor including an oxide semiconductor, the semiconductor device can have stable electrical characteristics and reliability of the transistor.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a semiconductor device which can be miniaturized or highly integrated can be provided.
  • a semiconductor device with high productivity can be provided.
  • a semiconductor device with high design freedom can be provided.
  • a semiconductor device with high information writing speed can be provided.
  • a semiconductor device capable of suppressing power consumption can be provided.
  • a novel semiconductor device can be provided.
  • 7A and 7B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 7A and 7B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 7A and 7B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 7A and 7B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 7A and 7B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 7 is a top view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 7 is a top view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 7 is a top view of a semiconductor device according to one embodiment of the present invention.
  • 7A to 7C illustrate a structural example of a transistor according to one embodiment of the present invention.
  • 7A to 7C illustrate a structural example of a transistor according to one embodiment of the present invention.
  • FIG. 7A to 7C illustrate a structural example of a transistor according to one embodiment of the present invention.
  • 7A to 7C illustrate a structural example of a transistor according to one embodiment of the present invention.
  • FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention.
  • FIG. 18 is a cross-sectional view illustrating a structure of a memory device of one embodiment of the present invention.
  • 1A and 1B are a block diagram and a schematic view illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 1A and 1B are a block diagram and a schematic view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a schematic view of a memory device according to one embodiment of the present invention.
  • 5A and 5B illustrate an example of a display device and an example of a circuit configuration of a pixel.
  • FIG. 7 is a diagram for explaining an example of a circuit configuration of a pixel.
  • FIG. 6 is a diagram for explaining an example of the configuration of a drive circuit.
  • 5A and 5B illustrate an example of a display device.
  • 5A and 5B illustrate an example of a display device.
  • FIG. 8 is a diagram for explaining an example of a display module.
  • FIG. 7 illustrates an electronic device according to one embodiment of the present invention.
  • the size, layer thicknesses, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale.
  • the drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings.
  • the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated.
  • the hatch pattern may be the same and may not be particularly designated.
  • a transistor is an element having at least three terminals of a gate, a drain, and a source.
  • a region in which a channel is formed between the drain (drain terminal, drain region or drain electrode) and a source (source terminal, source region or source electrode) is provided, and a region and a source in which the drain and the channel are formed And the current can flow.
  • a region where a channel is formed refers to a region through which current mainly flows.
  • the functions of the source and the drain may be switched when adopting transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” can be used interchangeably.
  • the term “electrically connected” includes the case where they are connected via "something having an electrical function".
  • the “thing having an electrical function” is not particularly limited as long as it can transmit and receive electrical signals between connection targets.
  • “those having some electrical action” include electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitors, elements having various other functions, and the like.
  • the nitrided oxide refers to a compound having a higher content of nitrogen than oxygen.
  • oxynitride refers to a compound having a higher content of oxygen than nitrogen.
  • the content of each element can be measured, for example, using Rutherford Ackscattering Spectrum (RBS) or the like.
  • the "parallel” means the state by which two straight lines are arrange
  • substantially parallel means the state by which two straight lines are arrange
  • vertical means that two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
  • “substantially perpendicular” refers to a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.
  • a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen or oxygen, and in the case where the barrier film has conductivity, it is called a conductive barrier film.
  • the normally on characteristic of the transistor means that it is in the on state when there is no application of a potential by the power supply (0 V).
  • the normally-on characteristic of a transistor may be an electrical characteristic in which current (Id) flows between the drain and the source when the voltage (Vg) applied to the gate of the transistor is 0 V.
  • an oxide semiconductor is a type of metal oxide.
  • the metal oxide refers to an oxide having a metal element.
  • the metal oxide may exhibit insulation, semiconductivity, and conductivity depending on the composition and formation method.
  • a metal oxide which exhibits semiconductivity is referred to as a metal oxide semiconductor or an oxide semiconductor (also referred to as an oxide semiconductor or simply an OS).
  • a metal oxide exhibiting an insulating property is referred to as a metal oxide insulator or an oxide insulator.
  • a metal oxide which exhibits conductivity is called a metal oxide conductor or an oxide conductor. That is, a metal oxide used for a channel formation region or the like of a transistor can be called an oxide semiconductor.
  • Embodiment 1 a semiconductor device including a transistor including an oxide semiconductor which is one embodiment of the present invention will be described with reference to FIGS.
  • a transistor using an oxide semiconductor in order to prevent electrostatic breakdown, it is effective to secure a discharge path by a protection circuit configured using a diode element (protection diode) or a capacitance element (protection capacitance element). is there.
  • a protection circuit configured using a diode element (protection diode) or a capacitance element (protection capacitance element). is there.
  • a transistor including an oxide semiconductor and a diode element or a capacitor are provided over the same substrate.
  • FIG. 1D is a schematic view of a transistor 200 according to one embodiment of the present invention. Note that in FIG. 1D, some elements are omitted for clarity of the drawing.
  • the transistor 200 includes at least a gate 260 functioning as a gate, a region CH in which a channel is formed (hereinafter also referred to as a channel formation region), a region SR functioning as a source, and a drain. And an oxide 230 including the functional region DR.
  • the transistor 200 may also have a conductor 205 below the oxide 230.
  • the conductor 205 may have a function as a second gate.
  • the threshold voltage of the transistor 200 can be controlled by independently changing the potential applied to the conductor 205 without interlocking with the potential applied to the conductor 260.
  • the threshold voltage of the transistor 200 can be greater than 0 V and off current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no potential is applied.
  • the conductor 205 and the conductor 260 in an overlapping manner, when the same potential is applied to the conductor 260 and the conductor 205, an electric field generated from the conductor 260 and an electric field generated from the conductor 205 An electric field can be connected to cover a channel formation region formed in the oxide 230. That is, the channel formation region can be electrically surrounded by the electric field of the conductor 260 having a function as the first gate electrode and the electric field of the conductor 205 having a function as the second gate electrode.
  • a structure of a transistor which electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.
  • oxide 230 a metal oxide containing indium may be used.
  • In-M-Zn oxide element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, hafnium, tantalum, tungsten, or magnesium
  • metal oxides such as one or more selected from
  • an In-Ga oxide or an In-Zn oxide may be used as the oxide 230.
  • the transistor 200 using an oxide semiconductor in the region CH in which a channel is formed can provide a semiconductor device with low power consumption because leakage current is extremely small in the non-conduction state. Further, an oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200 included in a highly integrated semiconductor device.
  • a thin film transistor can be formed using a semiconductor thin film formed over a semiconductor substrate, a conductive substrate, or an insulating substrate.
  • a substrate provided with a conductor or a semiconductor on an insulating substrate, a substrate provided with a conductor or an insulator on a semiconductor substrate, or a substrate provided with a semiconductor or an insulator on a conductive substrate may be used.
  • those provided with elements on these substrates may be used. Examples of the element provided on the substrate include a capacitive element, an inductance element, a resistive element (a switch element, a light emitting element, a memory element, and the like).
  • each structure included in the transistor can be manufactured by repeatedly performing film formation of a film using a material suitable for each structure and processing for the film.
  • the above-mentioned film can be formed by, for example, sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or atomic layer deposition.
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • PLD pulsed laser deposition
  • atomic layer deposition The film is formed by using an atomic layer deposition (ALD) method or the like.
  • the CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Furthermore, it can be divided into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal Organic CVD) depending on the source gas used.
  • PECVD plasma enhanced CVD
  • TCVD thermal CVD
  • MOCVD Metal Organic CVD
  • etching As a method of processing and forming the film, there are dry etching, wet etching, and chemical mechanical polishing (also referred to as CMP) treatment.
  • CMP chemical mechanical polishing
  • plasma In order to perform fine processing as the device size is reduced, dry etching using plasma is generally used. On the other hand, even in dry etching, charge up may occur by plasma.
  • the wirings are divided to easily cause the wirings to be electrically floating. After being divided, each wiring is charged up in a subsequent process, which causes an electrostatic breakdown (ESD) of the element.
  • ESD electrostatic breakdown
  • the gate insulator is likely to be broken if different potentials are charged to each electrode of the transistor.
  • a discharge path is secured by a protective circuit which is formed using a diode (protective diode) or a capacitor.
  • the substrate 20 is placed on a grounded stage or the like. Therefore, the charge charged in the transistor 200 flows in the direction of the ground potential (GND) through the diode 10 and is eventually discharged.
  • GND ground potential
  • the potential is relative, and the magnitude is determined by the relative magnitude from the reference potential. Therefore, in the present specification, descriptions such as “ground”, “GND”, “ground” and the like do not necessarily mean that the potential is 0V.
  • “ground” or “GND” may be defined with reference to the lowest potential in the circuit.
  • “ground” or “GND” may be defined with reference to an intermediate potential in a circuit. Note that a positive potential or a negative potential is defined with reference to a potential such as “ground”, “GND”, or “ground”.
  • FIGS. 1B and 1C each illustrate an example of a cross-sectional view of a semiconductor device including the transistor 200 according to one embodiment of the present invention illustrated in FIG.
  • FIG. 1B is a cross-sectional view of the transistor 200 in the L-length direction
  • FIG. 1C is a cross-sectional view of the transistor 200 in the W-length direction. Note that in FIG. 1B and FIG. 1C, some elements are omitted for clarity of the drawing.
  • the semiconductor device includes at least a transistor 200 functioning as a transistor, a diode 10s, a diode 10d, a diode 10tg, and a diode 10bg.
  • the diode 10 (the diode 10s, the diode 10d, the diode 10tg, and the diode 10bg) includes the region 21 (the region 21s, the region 21d, the region 21tg, and the region 21bg) and the region 22 (the region 22s, the region 22d, and the region, respectively). 22tg, and region 22bg).
  • a plug electrically connected to one of the source and the drain of the transistor 200, a wiring 26s electrically connected to the plug, and a plug 24s electrically connected to the wiring 26s and the region 22s of the diode 10s.
  • the semiconductor device includes a plug electrically connected to the other of the source and the drain of the transistor 200, a wiring 26d electrically connected to the plug, and a plug 24d electrically connected to the wiring 26d and the region 22d of the diode 10d. .
  • the semiconductor device also includes a plug electrically connected to the conductor 260, a wiring 26tg electrically connected to the plug, and a plug 24tg electrically connected to the wiring 26tg and the region 22tg of the diode 10tg.
  • a p-type single crystal silicon substrate can be used as the substrate 20.
  • a part of the substrate 20 can be selectively conductive to form a so-called embedded diode.
  • the embedded diode can be used as the diode 10.
  • regions 21s, 21d, and 21tg which are thin p-type regions, are formed on the substrate 20, which is a p-type single crystal silicon substrate, and a region 22s, which is an n-type region, is formed thereon.
  • the diode 10s, the diode 10d, and the diode 10tg are formed.
  • the substrate 20 which is a p-type single crystal silicon substrate a region 21bg which is a thin n-type region is formed, and a p-type region is formed thereon, thereby forming the diode 10bg.
  • the thin p-type region may not necessarily be provided.
  • the regions 21 and 22 can be provided at the same time as the step of forming the Si transistor.
  • the diode 10s and the diode 10d are formed on the extension of the transistor 200 in the L-length direction, and the diode 10bg and the diode 10b on the extension of the transistor 200 in the W-length direction.
  • the diode 10tg is formed, the present invention is not limited to this configuration, and the layout can be appropriately changed according to the circuit design to be obtained.
  • the diode 10s, the diode 10d, the diode 10tg, and the diode 10bg can be provided as necessary.
  • the diode 10bg is unnecessary.
  • the conductive substrate is different from the semiconductor substrate, and it is difficult to provide a buried diode.
  • the transistor 200t including an oxide semiconductor, the transistor 200s functioning as a diode element or a capacitor, the transistor 200d, the transistor 200tg, and the transistor 200bg are manufactured over the same substrate. Therefore, the transistor 200s, the transistor 200d, the transistor 200tg, and the transistor 200bg are preferably provided simultaneously with the transistor 200t. That is, the transistor 200s, the transistor 200d, the transistor 200tg, and the transistor 200bg are arranged in the same layer as the transistor 200t.
  • a plurality of cell arrays (a cell array is a collection of a plurality of transistors) can be provided over the conductive substrate.
  • the transistor 200s, the transistor 200d, the transistor 200tg, and the transistor 200bg may function as a diode element or a capacitor element depending on a design to be obtained. For example, in the case of using a capacitive element, since there is no voltage range, it can be used for a power supply circuit or the like. On the other hand, in the cell array to be designed, when emphasis is placed on the response speed, a diode element may be used. A diode element or a capacitive element can be provided for each cell array provided over the same substrate.
  • examples of the conductive substrate that can be used for the substrate 20 include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, and the like.
  • a substrate having a metal nitride there is a substrate having a metal oxide, or the like.
  • the semiconductor substrate may be used with low resistance.
  • a p-type single crystal silicon substrate can be used after being p-typed.
  • the transistor 200s and the transistor 200d are formed on the extension of the transistor 200t in the L-length direction
  • the transistor 200bg and the transistor 200tg are formed on the extension of the transistor 200t in the W-length direction.
  • the present invention is not limited to this configuration, and the layout can be changed as appropriate according to the desired circuit design.
  • the transistor 200s, the transistor 200d, the transistor 200tg, and the transistor 200bg can be provided as necessary.
  • the transistor 200bg is unnecessary.
  • the number of transistors 200 may be smaller than the number of transistors 200.
  • at least one transistor 200 may be provided for the common wiring.
  • FIG. 2A is a circuit diagram of a semiconductor device including the transistor 200t according to one embodiment of the present invention.
  • the semiconductor device illustrated in FIG. 2A includes a plurality of transistors (a transistor 200 tg, a transistor 200 bg, a transistor 200 s, and a transistor 200 d) each functioning as a diode electrically connected to each electrode of the transistor 200 t.
  • the transistor 200 t is connected to the substrate 20 via each diode.
  • a conductive substrate is used as the substrate 20.
  • the substrate 20 is placed on a grounded stage or the like. Therefore, the charge charged in the transistor 200t flows toward the ground potential (GND) through the transistor 200tg, the transistor 200bg, the transistor 200s, and the transistor 200d, and therefore, is finally discharged.
  • GND ground potential
  • FIGS. 2B and 2C each illustrate an example of a cross-sectional view of a semiconductor device including the transistor 200t according to one embodiment of the present invention illustrated in FIG. 2A.
  • FIG. 2B is a cross-sectional view of the transistor 200t in the L-length direction
  • FIG. 2C is a cross-sectional view of the transistor 200t in the W-length direction. Note that in FIG. 2B and FIG. 2C, some elements are omitted for clarity of the figure.
  • a plug electrically connected to one of the source and the drain of the transistor 200s, a plug electrically connected to the conductor 260 of the transistor 200s, and a wiring 26s2 electrically connected to both the plugs are included.
  • a plug 24s electrically connecting the wiring 26s2 to the substrate 20 is provided.
  • the plug electrically connected to the other of the source and the drain of the transistor 200t, the wiring 26d1 electrically connected to the plug, and the wiring 26d1 electrically connected to one of the source and the drain of the transistor 200d Have a plug. Further, a plug electrically connected to the other of the source and the drain of the transistor 200d, a plug electrically connected to the conductor 260 of the transistor 200d, and a wiring 26d2 electrically connected to both plugs are included. In addition, it has a plug 24 d for electrically connecting the wiring 26 d 2 and the substrate 20.
  • a plug electrically connected to one of the source and the drain of the transistor 200bg, and a wiring 26bg2 electrically connected to the plug are included.
  • a plug 24 bg electrically connecting the wiring 26 bg 2 to the substrate 20 is provided.
  • each electrode of the transistor 200t functioning as a transistor is electrically connected to the conductive substrate 20 through the diode-connected transistor 200s, the transistor 200d, the transistor 200tg, and the transistor 200bg.
  • the transistor 200t including an oxide semiconductor
  • FIG. 3A is a circuit diagram of a semiconductor device including the transistor 200t according to one embodiment of the present invention.
  • the semiconductor device illustrated in FIG. 3A includes a plurality of transistors (a transistor 200 tg, a transistor 200 bg, a transistor 200 s, and a transistor 200 d) each functioning as a capacitor element electrically connected to each electrode of the transistor 200 t.
  • the transistor 200 t is connected to the substrate 20 through each capacitive element.
  • the transistors 200tg, 200bg, 200s, and 200d preferably have the same potential.
  • the other of the electrodes of the transistor 200tg, the transistor 200bg, the transistor 200s, and the transistor 200d functioning as a capacitor may be grounded through the substrate 20 using a conductive substrate.
  • FIGS. 3B and 3C each illustrate an example of a cross-sectional view of a semiconductor device including the transistor 200t according to one embodiment of the present invention illustrated in FIG. 3A.
  • FIG. 3B is a cross-sectional view of the transistor 200t in the L-length direction
  • FIG. 3C is a cross-sectional view of the transistor 200t in the W-length direction. Note that in FIG. 3B and FIG. 3C, some elements are omitted for clarity of the figure.
  • the semiconductor device includes at least a transistor 200t functioning as a transistor.
  • the transistor 200 s functions as a capacitor, the transistor 200 d, the transistor 200 tg, and the transistor 200 bg.
  • a plug electrically connected to one of the source and the drain of the transistor 200t, a wiring electrically connected to the plug 26s1, and a plug electrically connected to the wiring 26s1 and the oxide 230 of the transistor 200s. Have.
  • a plug electrically connected to the conductor 260 of the transistor 200s and a wiring 26s2 electrically connected to the plug are included.
  • a plug 24s electrically connecting the wiring 26s2 to the substrate 20 is provided.
  • a plug electrically connected to the other of the source and the drain of the transistor 200t, a wiring electrically connected to the plug 26d1, and a plug electrically connected to the wiring 26d1 and the oxide 230 of the transistor 200d Have.
  • a plug electrically connected to the conductor 260 of the transistor 200 d and a wiring 26 d 2 electrically connected to the plug are included.
  • it has a plug 24 d for electrically connecting the wiring 26 d 2 and the substrate 20.
  • the semiconductor device also includes a plug electrically connected to the conductor 260 of the transistor 200t, a wire 26tg1 electrically connected to the plug, and a plug electrically connected to the wire 26tg1 and the conductor 260 of the transistor 200tg.
  • the transistor further includes a plug electrically connected to the other of the source and the drain of the transistor 200tg, and a wiring 26tg2 electrically connected to the plug.
  • a plug 24 tg electrically connecting the wiring 26 tg 2 to the substrate 20 is provided.
  • the conductor 205 of the transistor 200t and the conductor 205 of the transistor 200bg are provided in common, the present invention is not limited to this structure, and can be changed as appropriate in accordance with the desired design.
  • each electrode of the transistor 200t functioning as a transistor is electrically connected to the conductive substrate 20 through the capacitively connected transistor 200s, the transistor 200d, the transistor 200tg, and the transistor 200bg.
  • the transistor 200s, the transistor 200d, the transistor 200tg, and the transistor 200bg are preferably provided simultaneously with the transistor 200t. Note that for the transistor 200s, the transistor 200d, the transistor 200tg, and the transistor 200bg, transistors of the same configuration provided in the same step as the transistor 200t may be used for capacitive connection.
  • the capacitor may be formed using a film included in the transistor 200t.
  • an oxide semiconductor that can be used as the oxide 230 can have a low electric resistance and can be used as a conductor. This can be called an OC (Oxide Conductor) electrode. Therefore, the transistor 200s, the transistor 200d, the transistor 200tg, and the transistor 200bg may be used as an electrode of a capacitor by converting the oxide 230 into a conductor.
  • the insulating substrate is difficult to provide a buried diode. Therefore, the transistor 200t including an oxide semiconductor, and the transistor 200s functioning as a diode element or a capacitor element, the transistor 200d, and the transistor 200tg are manufactured over the same substrate. Therefore, the transistor 200s, the transistor 200d, and the transistor 200tg are preferably provided simultaneously with the transistor 200t. That is, the transistor 200s, the transistor 200d, and the transistor 200tg are arranged in the same layer as the transistor 200t.
  • a plurality of cell arrays (a cell array is a collection of a plurality of transistors) can be provided over the conductive substrate.
  • the transistor 200s, the transistor 200d, the transistor 200tg, and the transistor 200bg may function as a diode element or a capacitor element depending on a design to be obtained.
  • a capacitive element since there is no voltage range, it can be used for a power supply circuit or the like.
  • a diode element may be used in the cell array to be designed.
  • a diode element or a capacitive element can be formed separately for each cell array provided on the same substrate.
  • the transistor 200tg, the transistor 200bg, the transistor 200s, and the transistor 200d may be electrically connected to the conductor 29 having a sufficient size.
  • the conductor 205 may be provided in common to be used as the conductor 29. In that case, after the semiconductor device is manufactured, the charges charged in the conductor 29 (conductor 205) may be discharged through a wiring connected to the conductor 205.
  • the conductor 29 (conductor 205) can be used as a second gate electrode by applying a suitable potential to the conductor 29 (conductor 205).
  • Examples of the insulating substrate that can be used for the substrate 20 include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate.
  • the transistor 200s and the transistor 200d are formed on the extension of the transistor 200t in the L length direction, and the transistor 200tg is formed on the extension of the transistor 200t in the W length direction.
  • the layout can be appropriately changed according to the desired circuit design.
  • the transistor 200s, the transistor 200d, and the transistor 200tg can be provided as needed.
  • the number of transistors 200 may be smaller than the number of transistors 200.
  • at least one transistor 200 may be provided for the common wiring.
  • FIG. 4A is a circuit diagram of a semiconductor device including the transistor 200t according to one embodiment of the present invention.
  • the semiconductor device illustrated in FIG. 4A includes a plurality of transistors (a transistor 200 tg, a transistor 200 s, and a transistor 200 d) each functioning as a diode electrically connected to each electrode of the transistor 200 t.
  • the transistor 200 t is connected to the conductor 29 through each diode.
  • the substrate 20 is an insulating substrate, and the conductor 29 is provided on the substrate 20.
  • the charge charged in the transistor 200 t is absorbed in the conductor 29 by flowing in the direction of the conductor 29 through the transistor 200 tg functioning as a diode, the transistor 200 s, and the transistor 200 d. Since the conductor 29 is sufficiently larger than the transistor 200t, the charge absorbed by the conductor 29 hardly causes potential fluctuation. Therefore, the charge absorbed by the conductor 29 is held by the conductor 29.
  • FIGS. 4B and 4C each illustrate an example of a cross-sectional view of a semiconductor device including the transistor 200t according to one embodiment of the present invention illustrated in FIG. 4A.
  • FIG. 4B is a cross-sectional view of the transistor 200t in the L-length direction
  • FIG. 4C is a cross-sectional view of the transistor 200t in the W-length direction. 4B and 4C, some elements are omitted for the sake of clarity of the figure.
  • the semiconductor device includes at least a transistor 200t functioning as a transistor.
  • the transistor 200s functioning as a diode, a transistor 200d, and a transistor 200tg are included.
  • a plug 24s electrically connecting the wiring 26s2 and the conductor 29 is provided.
  • the plug electrically connected to the other of the source and the drain of the transistor 200t, the wiring 26d1 electrically connected to the plug, and the wiring 26d1 electrically connected to one of the source and the drain of the transistor 200d Have a plug. Further, a plug electrically connected to the other of the source and the drain of the transistor 200d, a plug electrically connected to the conductor 260 of the transistor 200d, and a wiring 26d2 electrically connected to both plugs are included. In addition, a plug 24 d electrically connecting the wiring 26 d 2 and the conductor 29 is provided.
  • each electrode of the transistor 200t functioning as a transistor is electrically connected to the conductor 29 through the diode-connected transistor 200s, the transistor 200d, and the transistor 200tg.
  • the transistor 200t including an oxide semiconductor it is preferable to use a transistor with the same structure, which is provided in the same step as the transistor 200s functioning as a diode element, the transistor 200d, and the transistor 200tg.
  • FIG. 5A is a circuit diagram of a semiconductor device including the transistor 200t according to one embodiment of the present invention.
  • the semiconductor device illustrated in FIG. 5A includes a plurality of transistors (a transistor 200 tg, a transistor 200 s, and a transistor 200 d) each functioning as a capacitive element electrically connected to each electrode of the transistor 200 t.
  • the transistor 200 t is connected to the conductor 29 through each capacitive element.
  • the transistors 200tg, 200s, and 200d preferably have equal potentials. For that purpose, it is preferable to design so that capacitance values of the transistor 200tg functioning as a capacitor, the transistor 200s, and the transistor 200d become as large as possible. Further, conductors electrically connected to the other of the electrodes of the transistor 200tg functioning as a capacitor, the transistor 200s, and the transistor 200d may be provided in common.
  • FIGS. 5B and 5C each illustrate an example of a cross-sectional view of a semiconductor device including the transistor 200t according to one embodiment of the present invention illustrated in FIG. 5A.
  • FIG. 5B is a cross-sectional view of the transistor 200t in the L-length direction
  • FIG. 5C is a cross-sectional view of the transistor 200t in the W-length direction. 5 (B) and 5 (C), some elements are omitted for clarity of the figure.
  • the semiconductor device includes at least a transistor 200t functioning as a transistor.
  • the transistor 200 s functions as a capacitor, the transistor 200 d, and the transistor 200 tg.
  • a plug electrically connected to the conductor 260 of the transistor 200s and a wiring 26s2 electrically connected to the plug are included.
  • a plug 24s electrically connecting the wiring 26s2 and the conductor 29 is provided.
  • a plug electrically connected to the other of the source and the drain of the transistor 200t, a wiring electrically connected to the plug 26d1, and a plug electrically connected to the wiring 26d1 and the oxide 230 of the transistor 200d Have.
  • a plug electrically connected to the conductor 260 of the transistor 200 d and a wiring 26 d 2 electrically connected to the plug are included.
  • a plug 24 d electrically connecting the wiring 26 d 2 and the conductor 29 is provided.
  • the semiconductor device also includes a plug electrically connected to the conductor 260 of the transistor 200t, a wire 26tg1 electrically connected to the plug, and a plug electrically connected to the wire 26tg1 and the conductor 260 of the transistor 200tg.
  • the transistor further includes a plug electrically connected to the other of the source and the drain of the transistor 200tg, and a wiring 26tg2 electrically connected to the plug.
  • a plug 24 tg electrically connecting the wiring 26 tg 2 to the conductor 29 is provided.
  • each electrode of the transistor 200t functioning as a transistor is electrically connected to the capacitively connected transistor 200s, the transistor 200d, the transistor 200tg, and the conductor 29.
  • the transistor 200s, the transistor 200d, and the transistor 200tg are preferably provided simultaneously with the transistor 200t. Note that for the transistor 200s, the transistor 200d, and the transistor 200tg, transistors with the same configuration, which are provided in the same step as the transistor 200t, may be capacitively connected.
  • the capacitor may be formed using a film included in the transistor 200t.
  • an oxide semiconductor that can be used as the oxide 230 can have a low electric resistance and can be used as a conductor. This can be called an OC (Oxide Conductor) electrode. Therefore, the transistor 200s, the transistor 200d, and the transistor 200tg may be used as an electrode of a capacitor by converting the oxide 230 into a conductor.
  • the oxide 230 is used as an electrode of a capacitor in the drawing, the present invention is not limited to this structure.
  • the conductor may be used as an electrode.
  • the conductor 29 (the conductor 205)
  • the first gate electrode, the source electrode, and the drain of the transistor 200t are provided.
  • the conductor 29 (conductor 205) can be used as a second gate electrode by applying each voltage to the electrodes.
  • the protective diode element or the protective capacitor element is provided over the same substrate as the transistor element, the yield is improved, whereby the productivity of the semiconductor device can be improved.
  • the conductor 29 which holds a charge on an insulating substrate, the charge charged in the transistor 200 t can be absorbed and fixed to the conductor 29 or the protective capacitor element.
  • the conductor 29 is preferably larger than the transistor. As the conductor 29 is larger, potential fluctuation is less likely to occur even if the amount of absorbed charge is large. Therefore, by setting the conductor 29 to a sufficient size, a highly reliable semiconductor device can be provided.
  • the conductor 205 in common in the transistor 200t, the transistor 200s, the transistor 200d, and the transistor 200tg, when using the conductor 29 as the conductor 29, an appropriate potential is given to the conductor 29 (conductor 205). It is preferable because the conductor 29 (conductor 205) can be used as the second gate electrode.
  • FIGS. 6A to 8A are top views in the state in which the conductor 29 is provided on the substrate 20, and FIGS. 6B to 8B are conductive on the substrate 20.
  • the top view in the state which provided the several oxide 230 in the matrix form on the body 29 and the conductor 29 is shown.
  • 6C to 8C are cross-sectional views of a portion indicated by alternate long and short dash line A1-A2 in FIGS. 6B to 8B.
  • 6D to 8D are cross-sectional views of a portion indicated by alternate long and short dash lines A3-A4 in FIGS. 6B to 8B.
  • a single-sided conductor 29 common to a plurality of transistors can be used. Wiring resistance can be reduced by providing the conductor 29 on the entire surface.
  • conductor 29 has n linear regions overlapping with m number of oxides 230, and a shape in which n linear regions are electrically connected to each other It may be In particular, the linear region of the conductor 29 preferably overlaps with the channel formation region of the oxide 230. With this structure, in the case where the conductor 29 is used as the conductor 205 functioning as a second gate electrode, the probability of generation of unnecessary parasitic capacitance around the transistor can be reduced.
  • the conductor 29 has m linear regions overlapping with n oxides 230, and the m linear regions may be electrically connected. Good.
  • the linear region of the conductor 29 may be provided in a region overlapping with the oxide 230.
  • FIG. 9A, 9B, and 9C are top views in a state in which the conductor 29 is provided on the substrate 20.
  • FIG. 9A, 9B, and 9C are top views in a state in which the conductor 29 is provided on the substrate 20.
  • the conductor 29 may have a comb-like region. Further, as shown in FIG. 9B, the conductor 29 having a linear region does not necessarily have to be provided with a region to be electrically connected at the end region, but may be provided at any region of the conductor 29. It may have an electrical contact area. Also, for example, the conductor 29 may have a shape that allows one-stroke writing. As an example, as shown in FIG. 9C, the U-shape may be continuous.
  • FIG. 10A, FIG. 10B, and FIG. 10C the conductor 29 on the substrate 20, the plurality of oxides 230 arranged in a matrix on the conductor 29, and the plurality of oxides
  • the top view in the state which provided the several conductor 260 on the thing 230 is shown.
  • a plurality of conductors 260 are provided in stripes so as to intersect linear regions of the conductors 29. Is preferred.
  • the conductor 29 and the channel formation region of the oxide 230 and the channel formation region of the oxide 230 may overlap. With this structure, the probability that wiring resistance or parasitic capacitance will occur between the conductor 260 and the conductor 29 can be reduced.
  • the plurality of conductors 260 are oxides 230 And a region which intersects with the oxide 230.
  • the conductor 260 has a projecting region which extends from the linear region.
  • the peninsular region overlaps with the channel formation region of the oxide 230.
  • the plurality of conductors 260 may have a structure in which one conductor 260 is provided for the oxide 230 in two rows (two columns). Specifically, as shown in FIG. 10B, the conductor 260 has a region (also referred to as a cross) in which the straight line intersects with the straight line. With this structure, the probability that wiring resistance or parasitic capacitance will occur between the conductor 260 and the conductor 29 can be reduced.
  • FIG. 11 is a top view of a conductor 29 on a substrate, and a plurality of oxides 230 arranged in a matrix on the conductor 29.
  • two or more conductors 29 may be provided on the substrate 20.
  • a plurality of transistors arranged in an array can be provided over the conductor 29.
  • the conductors 29 do not have to have the same shape. As shown in FIG. 11B, the shape may be different depending on the design.
  • the structure shown in the structural example of the semiconductor device using the conductive substrate and the structural example of the semiconductor device using the insulating substrate may be used on the semiconductor substrate. Further, the structure shown in the structural example of the semiconductor device using the insulating substrate may be used on the conductive substrate.
  • a semiconductor device having a transistor with a large on current can be provided.
  • a semiconductor device having a transistor with low off current can be provided.
  • an oxide semiconductor can be formed by a sputtering method or the like and thus can be used for a transistor included in a highly integrated semiconductor device.
  • FIG. 12A is a top view of the transistor 200A.
  • FIG. 12B is a cross-sectional view of a portion indicated by dashed-dotted line L1-L2 in FIG. 12C is a cross-sectional view of a portion indicated by dashed-dotted line W1-W2 in FIG. 12A. Note that in the top view of FIG. 12A, some elements are omitted for clarity of the drawing.
  • the transistor 200A and the insulator 210 functioning as an interlayer film, the insulator 212, the insulator 214, the insulator 214, the insulator 216, the insulator 280, the insulator 282, and the insulating layer 284, Is shown.
  • a conductor 246 (a conductor 246a and a conductor 246b) which is electrically connected to the transistor 200A and functions as a contact plug, and a conductive layer 203 which functions as a wiring are shown.
  • the transistor 200A includes a conductor 260 functioning as a first gate (also referred to as a top gate) electrode (conductors 260a and 260b) and a conductor 205 functioning as a second gate (also referred to as bottom gate) electrode.
  • a conductor 260 functioning as a first gate (also referred to as a top gate) electrode (conductors 260a and 260b) and a conductor 205 functioning as a second gate (also referred to as bottom gate) electrode.
  • the conductor 205a and the conductor 205b The conductor 205a and the conductor 205b), the insulator 250 functioning as a first gate insulating layer, the insulating layer 220 functioning as a second gate insulating layer, the insulator 222, and the insulator 224, a channel An oxide 230 (an oxide 230a, an oxide 230b, and an oxide 230c) having a region where a region is to be formed, a conductor 242a functioning as one of a source or drain, and a conductor 242b functioning as the other of the source or drain And the insulator 274.
  • the insulator 210 and the insulator 212 function as interlayer films.
  • An insulator such as TiO 3 (BST) can be used in a single layer or a stack.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided.
  • silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 210 preferably functions as a barrier film which suppresses impurities such as water and hydrogen from entering the transistor 200A from the substrate side. Therefore, as the insulator 210, it is preferable to use an insulating material having a function of suppressing the diffusion of an impurity such as a hydrogen atom, a hydrogen molecule, a water molecule, or a copper atom (it is difficult for the impurity to permeate). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (the above-described oxygen is difficult to permeate).
  • an impurity such as a hydrogen atom, a hydrogen molecule, a water molecule, or a copper atom
  • oxygen for example, at least one of oxygen atoms, oxygen molecules, and the like
  • the insulator 210 may be used as the insulator 210.
  • impurities such as water and hydrogen from the substrate side to the transistor 200A side with respect to the insulator 210 can be suppressed.
  • the insulator 212 preferably has a dielectric constant lower than that of the insulator 210.
  • parasitic capacitance generated between wirings can be reduced.
  • the conductive layer 203 is formed to be embedded in the insulator 212.
  • the height of the top surface of the conductive layer 203 and the height of the top surface of the insulator 212 can be approximately the same.
  • the conductive layer 203 is illustrated as a single layer, the present invention is not limited to this.
  • the conductive layer 203 may have a stacked structure of two or more layers. Note that for the conductive layer 203, it is preferable to use a highly conductive conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 260 may function as a first gate electrode.
  • the conductor 205 may function as a second gate electrode.
  • the threshold voltage of the transistor 200A can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 and independently.
  • the threshold voltage of the transistor 200A can be larger than 0 V and the off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no potential is applied.
  • an electric field generated from the conductor 260 and an electric field generated from the conductor 205 can cover a channel formation region formed in the oxide 230.
  • the channel formation region can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode.
  • a structure of a transistor which electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.
  • the insulator 214 and the insulator 216 function as interlayer films in the same manner as the insulator 210 or the insulator 212.
  • the insulator 214 preferably functions as a barrier film which suppresses impurities such as water and hydrogen from entering the transistor 200A from the substrate side. With this structure, diffusion of an impurity such as water or hydrogen from the substrate side to the transistor 200A side with respect to the insulator 214 can be suppressed.
  • the insulator 216 preferably has a lower dielectric constant than the insulator 214. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • the conductor 205 functioning as a second gate electrode is in contact with the inner wall of the opening of the insulator 214 and the insulator 216, the conductor 205a is formed, and the conductor 205b is further formed inside.
  • the heights of the top surfaces of the conductors 205a and 205b and the top surface of the insulator 216 can be approximately the same.
  • the transistor 200A illustrates a structure in which the conductor 205a and the conductor 205b are stacked, the present invention is not limited to this.
  • the conductor 205 may be provided as a single layer or a stacked structure of three or more layers.
  • the conductor 205a it is preferable to use a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above-described impurities are less likely to be transmitted).
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one of oxygen atoms, oxygen molecules, and the like
  • the function of suppressing the diffusion of an impurity or oxygen is a function of suppressing the diffusion of any one or all of the impurity or the oxygen.
  • the conductor 205a has a function of suppressing the diffusion of oxygen
  • the conductor 205b can be suppressed from being oxidized to be lowered in conductivity.
  • the conductor 205 b is preferably formed using a highly conductive conductive material containing tungsten, copper, or aluminum as a main component. In that case, the conductive layer 203 may not necessarily be provided. Note that although the conductor 205 b is illustrated as a single layer, it may have a stacked structure, for example, a stack of titanium or titanium nitride and the above conductive material.
  • the insulating layer 220, the insulator 222, and the insulator 224 function as a second gate insulating layer.
  • the insulator 224 in contact with the oxide 230 preferably releases oxygen by heating.
  • oxygen released by heating may be referred to as excess oxygen.
  • the insulator 224 silicon oxide, silicon oxynitride, or the like may be used as appropriate.
  • an oxide material from which part of oxygen is released by heating is preferably used as the insulator 224.
  • the oxide from which oxygen is released by heating is a desorption amount of oxygen of at least 1.0 ⁇ 10 18 atoms / cm 3 , preferably 1 in terms of oxygen atom in TDS (thermal desorption spectroscopy) analysis. It is an oxide film having a concentration of not less than 0 ⁇ 10 19 atoms / cm 3 , more preferably not less than 2.0 ⁇ 10 19 atoms / cm 3 , or not less than 3.0 ⁇ 10 20 atoms / cm 3 .
  • the surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 400 ° C.
  • the insulator 222 preferably has a barrier property.
  • the insulator 222 functions as a layer which suppresses entry of an impurity such as hydrogen from the peripheral portion of the transistor 200A into the transistor 200A.
  • the insulator 222 is made of, for example, aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), It is preferable to use an insulator containing a so-called high-k material such as Ba, Sr) TiO 3 (BST) in a single layer or a laminate. As the miniaturization and higher integration of transistors progress, problems such as leakage current may occur due to thinning of the gate insulating layer. By using a high-k material for the insulator functioning as the gate insulating layer, the gate potential can be reduced at the time of operation of the transistor while maintaining the physical thickness.
  • a so-called high-k material such as Ba, Sr) TiO 3 (BST)
  • the insulating layer 220 is preferably thermally stable.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the insulator of high-k material with silicon oxide or silicon oxynitride and the insulator 222, the insulator 222 with a stacked structure which is thermally stable and has a high relative dielectric constant can be obtained.
  • FIG. 12 illustrates a stacked structure of three layers as the second gate insulating layer, but a single layer or a stacked structure of two or more layers may be used.
  • the invention is not limited to the laminated structure made of the same material, but may be a laminated structure made of different materials.
  • the oxide 230 which has a region functioning as a channel formation region includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b.
  • the oxide 230a under the oxide 230b diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed.
  • the oxide 230c over the oxide 230b diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.
  • the oxide 230 an oxide semiconductor which is a kind of metal oxide described below can be used.
  • the transistor 200A illustrated in FIG. 12 includes a region where the conductor 242 (the conductor 242a and the conductor 242b), the oxide 230c, the insulator 250, and the conductor 260 overlap with each other. With such a structure, a transistor with high on-state current can be provided. In addition, a transistor with high controllability can be provided.
  • One of the conductors 242 functions as a source electrode, and the other functions as a drain electrode.
  • a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, tungsten, or an alloy containing any of the metals as its main component can be used.
  • metal nitride films such as tantalum nitride are preferable because they have a barrier property to hydrogen or oxygen and high oxidation resistance.
  • a stacked structure of two or more layers may be employed.
  • a tantalum nitride film and a tungsten film may be stacked.
  • a titanium film and an aluminum film may be stacked.
  • a two-layer structure in which an aluminum film is laminated on a tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a tungsten film
  • a two-layer structure in which a copper film is stacked may be used.
  • a molybdenum nitride film a three-layer structure in which an aluminum film or a copper film is stacked on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed thereon.
  • a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.
  • a barrier layer may be provided over the conductor 242.
  • the barrier layer preferably uses a substance having a barrier property to oxygen or hydrogen.
  • a metal oxide for example, a metal oxide can be used.
  • an insulating film having a barrier property to oxygen or hydrogen such as aluminum oxide, hafnium oxide, or gallium oxide, is preferably used.
  • silicon nitride formed by a CVD method may be used.
  • the range of material selection of the conductor 242 can be expanded.
  • a material with low oxidation resistance such as tungsten or aluminum but high conductivity can be used.
  • a conductor which can be easily formed or processed can be used.
  • the insulator 250 functions as a first gate insulating layer.
  • the insulator 250 may have a stacked structure similarly to the second gate insulating layer.
  • the insulator functioning as the gate insulating layer has a stacked structure of a high-k material and a thermally stable material, the gate potential during transistor operation can be reduced while maintaining the physical thickness. It becomes.
  • a stacked structure with high thermal stability and high dielectric constant can be obtained.
  • a conductor 260 functioning as a first gate electrode includes a conductor 260a and a conductor 260b over the conductor 260a.
  • the conductor 260a is preferably a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms as the conductor 205a.
  • a conductive material having a function of suppressing the diffusion of oxygen eg, at least one of oxygen atom, oxygen molecule, and the like).
  • the conductor 260a has a function of suppressing the diffusion of oxygen
  • the material selectivity of the conductor 260b can be improved. That is, by including the conductor 260a, oxidation of the conductor 260b can be suppressed, and a decrease in conductivity can be prevented.
  • a conductive material having a function of suppressing diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide or the like is preferably used.
  • an oxide semiconductor that can be used as the oxide 230 can be used as the conductor 260a.
  • the conductor 260b by forming the conductor 260b by a sputtering method, the electric resistance value of the conductor 260a can be reduced to form a conductive layer. This can be called an OC (Oxide Conductor) electrode.
  • the conductor 260 functions as a wiring, it is preferable to use a conductor with high conductivity.
  • the conductor 260b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductor 260b may have a stacked structure, for example, a stack of titanium and titanium nitride and the above conductive material.
  • the insulator 274 is preferably provided so as to cover the top surface and the side surface of the conductor 260, the side surface of the insulator 250, and the side surface of the oxide 230c.
  • an insulating material having a function of suppressing diffusion of impurities such as water and hydrogen and oxygen can be used.
  • aluminum oxide or hafnium oxide is preferably used.
  • metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, silicon nitride oxide, silicon nitride, and the like can be used.
  • oxidation of the conductor 260 can be suppressed. Further, with the insulator 274, diffusion of an impurity such as water or hydrogen included in the insulator 280 into the transistor 200A can be suppressed.
  • the insulator 280, the insulator 282, and the insulating layer 284 function as interlayer films.
  • the insulator 282 preferably functions as a barrier insulating film which suppresses impurities such as water and hydrogen from entering the transistor 200A from the outside.
  • the insulator 280 and the insulating layer 284 preferably have lower dielectric constants than the insulator 282.
  • parasitic capacitance generated between wirings can be reduced.
  • the transistor 200A may be electrically connected to another structure through a plug or a wiring such as the conductor 246 embedded in the insulator 280, the insulator 282, and the insulating layer 284.
  • a conductive material such as a metal material, an alloy material, a metal nitride material, a metal oxide material, or the like can be used in a single layer or a stack similarly to the conductor 205.
  • a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity.
  • it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.
  • the conductivity as a wiring can be increased. While being held, diffusion of impurities from the outside can be suppressed.
  • an insulator 276 (an insulator 276a and an insulator 276b) having a barrier property may be provided between the conductor 246 and the insulator 280.
  • oxygen in the insulator 280 can be reacted with the conductor 246 to suppress oxidation of the conductor 246.
  • the range of material selection of the conductor used for the plug and the wiring can be expanded.
  • materials having low oxidation resistance, such as tungsten and aluminum, but having high conductivity can be used.
  • a conductor which can be easily formed or processed can be used.
  • a semiconductor device including a transistor with large on-state current can be provided.
  • a semiconductor device having a transistor with low off current can be provided.
  • the material used as the substrate there is no particular limitation on the material used as the substrate, but at least a heat resistance that can withstand the later heat treatment is required.
  • a single crystal semiconductor substrate made of silicon, silicon carbide or the like, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium or the like can be used as a substrate.
  • a semiconductor device such as a strained transistor or a FIN transistor provided on an SOI substrate or a semiconductor substrate can be used.
  • gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like applicable to a high electron mobility transistor (HEMT) may be used. That is, the substrate is not limited to a simple support substrate, and may be a substrate on which devices such as other transistors are formed.
  • a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used.
  • a flexible substrate flexible substrate
  • a transistor, a capacitor, or the like may be manufactured directly on the flexible substrate, or a transistor, a capacitor, or the like is manufactured on another manufacturing substrate, and then the flexible substrate is manufactured. It may be exfoliated or displaced. Note that in order to peel and transfer the manufacturing substrate to the flexible substrate, a peeling layer may be provided between the manufacturing substrate and the transistor, the capacitor, or the like.
  • the flexible substrate for example, metal, alloy, resin or glass, or fibers thereof can be used.
  • a flexible substrate used for the substrate for example, a material having a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 / K or less, 5 ⁇ 10 ⁇ 5 / K or less, or 1 ⁇ 10 ⁇ 5 / K or less may be used.
  • the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.
  • aramid is suitable as a flexible substrate because of its low coefficient of linear expansion.
  • the insulating layer is aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxide, silicon nitride oxide, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,
  • a material selected from neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate or the like is used in a single layer or laminated form. Alternatively, a material obtained by mixing a plurality of materials among an oxide material, a nitride material, an oxynitride material, and a nitride oxide material may be used.
  • the nitrided oxide refers to a compound having a higher content of nitrogen than oxygen.
  • oxynitride refers to a compound having a higher content of oxygen than nitrogen.
  • the content of each element can be measured, for example, using Rutherford Backscattering Spectroscopy (RBS) or the like.
  • the hydrogen concentration in the insulating layer is 2 ⁇ 10 20 atoms / cm 3 or less, preferably 5 ⁇ 10 19 atoms / cm 3 or less, in secondary ion mass spectrometry (SIMS). More preferably, it is 1 ⁇ 10 19 atoms / cm 3 or less, more preferably 5 ⁇ 10 18 atoms / cm 3 or less. In particular, it is preferable to reduce the hydrogen concentration in the insulating layer in contact with the semiconductor layer.
  • the nitrogen concentration in the insulating layer is 5 ⁇ 10 19 atoms / cm 3 or less, preferably 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less in SIMS. More preferably, it is 5 ⁇ 10 17 atoms / cm 3 or less.
  • At least a region in contact with the semiconductor layer of the insulating layer and a region in contact with at least the semiconductor layer of the insulating layer preferably have few defects. Typically, they are observed by an electron spin resonance (ESR) method. Less signal is preferable.
  • ESR electron spin resonance
  • the above-mentioned signal includes the E ′ center observed at a g value of 2.001. The E 'center is due to dangling bonds of silicon.
  • the spin density derived from the E ′ center is 3 ⁇ 10 17 spins / cm 3 or less, preferably 5 ⁇ 10 16 spins / cm 3 or less
  • a silicon oxide layer or a silicon oxynitride layer may be used.
  • signals derived from nitrogen dioxide may be observed.
  • the signal is divided into three signals by the nuclear spin of nitrogen, and each g value is 2.037 or more and 2.039 or less (referred to as the first signal), and the g value is 2.001 or more and 2.03.
  • the following referred to as a second signal
  • g values of 1.964 or more and 1.966 or less are observed.
  • an insulating layer in which a spin density of a signal derived from nitrogen dioxide (NO 2 ) is 1 ⁇ 10 17 spins / cm 3 or more and 1 ⁇ 10 18 spins / cm 3 or less.
  • NO 2 nitrogen dioxide
  • nitrogen oxides (NO x ) containing nitrogen dioxide (NO 2 ) form energy levels in the insulating layer.
  • the level is located in the energy gap of the oxide semiconductor layer. Therefore, when nitrogen oxide (NO x ) diffuses to the interface between the insulating layer and the oxide semiconductor layer, the level may trap electrons on the insulating layer side. As a result, trapped electrons remain in the vicinity of the interface between the insulating layer and the oxide semiconductor layer, which shifts the threshold voltage of the transistor in the positive direction. Therefore, when a film with a low content of nitrogen oxide is used as the insulating layer, the shift in threshold voltage of the transistor can be reduced.
  • a silicon oxynitride layer can be used as the insulating layer in which the amount of released nitrogen oxide (NO x ) is small.
  • the silicon oxynitride layer is a film in which the amount of released ammonia is larger than the amount of released nitrogen oxide (NO x ) in thermal desorption spectroscopy (TDS), and typically, ammonia is used.
  • the released amount is 1 ⁇ 10 18 pieces / cm 3 or more and 5 ⁇ 10 19 pieces / cm 3 or less. Note that the above release amount of ammonia is the total amount of the heat treatment temperature in TDS in the range of 50 ° C. to 650 ° C., or 50 ° C. to 550 ° C.
  • nitrogen oxides (NO x ) react with ammonia and oxygen in heat treatment, nitrogen oxides (NO x ) are reduced by using an insulating layer with a large amount of released ammonia.
  • At least one of the insulating layers in contact with the oxide semiconductor layer is preferably formed using an insulating layer from which oxygen is released by heating.
  • an insulating layer from which oxygen is released by heating is 1.0. It is preferable to use an insulating layer which is 10 18 atoms / cm 3 or more, 1.0 10 19 atoms / cm 3 or more, or 1.0 10 20 atoms / cm 3 or more.
  • oxygen released by heating is also referred to as “excess oxygen”.
  • the insulating layer containing excess oxygen can also be formed by performing treatment for adding oxygen to the insulating layer.
  • the process of adding oxygen can be performed by heat treatment in an oxidizing atmosphere, plasma treatment, or the like.
  • oxygen may be added using an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like.
  • the gas used for the process of adding oxygen include gases containing oxygen, such as oxygen gas such as 16 O 2 or 18 O 2 , nitrous oxide gas, and ozone gas.
  • the process of adding oxygen is also referred to as "oxygen doping process". Oxygen doping may be performed by heating the substrate.
  • a heat-resistant organic material such as polyimide, an acrylic resin, a benzocyclobutene resin, a polyamide, or an epoxy resin can be used.
  • organic materials low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), and the like can be used.
  • the insulating layer may be formed by stacking a plurality of insulating layers formed of any of these materials.
  • the siloxane-based resin corresponds to a resin including a Si-O-Si bond formed using a siloxane-based material as a starting material.
  • the siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent.
  • the organic group may have a fluoro group.
  • the method of forming the insulating layer is not particularly limited. Note that depending on the material used for the insulating layer, a firing step may be required. In this case, by combining the baking step of the insulating layer and another heat treatment step, a transistor can be efficiently manufactured.
  • Electrode Conductive materials for forming the electrode include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium and the like
  • a material containing one or more metal elements selected from the above can be used.
  • a semiconductor with high electrical conductivity typically a polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a conductive material containing the above metal element and oxygen may be used.
  • a conductive material containing the above metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide (ITO) indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc An oxide, indium gallium zinc oxide, or indium tin oxide doped with silicon may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • a plurality of conductive layers formed of the above materials may be stacked.
  • a stacked structure in which a material containing a metal element described above and a conductive material containing oxygen are combined may be used.
  • a stacked structure in which the material containing the metal element described above and the conductive material containing nitrogen are combined may be used.
  • a stacked structure in which the above-described material containing a metal element, the conductive material containing oxygen, and the conductive material containing nitrogen are combined may be used.
  • a stacked structure in which a conductive material containing nitrogen and a conductive material containing oxygen are combined may be used.
  • the conductive material containing oxygen is used as a semiconductor It is good to provide on the layer side. By providing the conductive material containing oxygen on the semiconductor layer side, oxygen released from the conductive material can be easily supplied to the semiconductor layer.
  • a conductive material having high embedding property such as tungsten or polysilicon may be used.
  • a conductive material having high embeddability and a barrier layer (diffusion prevention layer) such as a titanium layer, a titanium nitride layer, or a tantalum nitride layer may be used in combination.
  • an electrode may be called a "contact plug.”
  • a conductive material which hardly transmits impurities to an electrode in contact with the gate insulating layer is preferably used.
  • An example of the conductive material which is hard to transmit impurities is tantalum nitride.
  • the reliability of the transistor can be further enhanced. That is, the reliability of the storage device can be further enhanced.
  • semiconductor layer a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.
  • silicon, germanium, or the like can be used as the semiconductor material.
  • a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor, an organic semiconductor, or the like can be used.
  • a low molecular weight organic material having an aromatic ring, a ⁇ electron conjugated conductive polymer, or the like can be used.
  • a low molecular weight organic material having an aromatic ring, a ⁇ electron conjugated conductive polymer, or the like can be used.
  • rubrene, tetracene, pentacene, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene, polyparaphenylene vinylene and the like can be used.
  • semiconductor layers may be stacked. In the case of stacking semiconductor layers, semiconductors having different crystal states may be used, or semiconductor materials different from each other may be used.
  • the band gap of an oxide semiconductor which is a kind of metal oxide is 2 eV or more
  • the off current per ⁇ m of the channel width is less than 1 ⁇ 10 ⁇ 20 A, 1 ⁇ 10 ⁇ 22 A It can be less than, or less than 1 ⁇ 10 ⁇ 24 A. That is, the on / off ratio can be 20 digits or more.
  • a transistor in which an oxide semiconductor is used for a semiconductor layer has high withstand voltage between the source and the drain.
  • a transistor with high reliability can be provided.
  • a transistor with a large output voltage and high withstand voltage can be provided.
  • a storage device with high reliability can be provided.
  • a memory device with a large output voltage and high withstand voltage can be provided.
  • a transistor in which silicon having crystallinity is used for a semiconductor layer in which a channel is formed is also referred to as a “crystalline Si transistor”.
  • Crystalline Si transistors are easier to obtain relatively higher mobility than OS transistors.
  • OS transistors it is difficult to realize extremely low off current like OS transistors. Therefore, it is important to properly use the semiconductor material used for the semiconductor layer in accordance with the purpose and application.
  • an OS transistor and a crystalline Si transistor may be used in combination depending on the purpose and application.
  • the oxide semiconductor layer is preferably formed by a sputtering method.
  • the oxide semiconductor layer is preferably formed by a sputtering method because the density of the oxide semiconductor layer can be increased.
  • a rare gas typically, argon
  • oxygen or a mixed gas of a rare gas and oxygen may be used as a sputtering gas.
  • high purification of the sputtering gas is also required.
  • an oxygen gas or a rare gas which is used as a sputtering gas is a gas which is highly purified to a dew point of ⁇ 60 ° C. or less, preferably ⁇ 100 ° C. or less.
  • the oxide semiconductor layer is formed by a sputtering method
  • Metal oxide An oxide semiconductor which is a kind of metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to them, aluminum, gallium, yttrium, tin and the like are preferably contained. In addition, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like may be contained.
  • the oxide semiconductor contains indium, an element M, and zinc.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.
  • the element M a plurality of the aforementioned elements may be combined in some cases.
  • metal oxides having nitrogen may also be collectively referred to as metal oxides.
  • a metal oxide having nitrogen may be referred to as metal oxynitride.
  • An oxide semiconductor which is a kind of metal oxide can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor for example, c-axis aligned crystalline oxide semiconductor (CAAC-OS), polycrystalline oxide semiconductor, nanocrystalline oxide semiconductor (nc-OS), pseudo amorphous oxide semiconductor (a-like) OS: amorphous-like oxide semiconductor), amorphous oxide semiconductor, and the like.
  • the CAAC-OS has c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction to form a strained crystal structure.
  • distortion refers to a portion where the orientation of the lattice arrangement changes between the region in which the lattice arrangement is aligned and the region in which another lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.
  • the nanocrystals are based on hexagons, but may not be regular hexagons and may be non-hexagonal. Moreover, distortion may have a lattice arrangement such as pentagon and heptagon.
  • the CAAC-OS it is difficult to confirm clear crystal grain boundaries (also referred to as grain boundaries) even in the vicinity of strain. That is, it is understood that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, or that the bonding distance between atoms is changed due to metal element substitution. It is for.
  • a CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer containing element M, zinc and oxygen (hereinafter referred to as (M, Zn) layer) are stacked. It tends to have a structure (also referred to as a layered structure).
  • In layer a layer containing indium and oxygen
  • M, Zn zinc and oxygen
  • indium and the element M can be substituted with each other, and when the element M in the (M, Zn) layer is substituted with indium, it can also be expressed as an (In, M, Zn) layer.
  • indium in the In layer is substituted with the element M, it can also be represented as an (In, M) layer.
  • CAAC-OS is a highly crystalline metal oxide. On the other hand, it is difficult to confirm clear crystal grain boundaries in CAAC-OS, so it can be said that the decrease in electron mobility due to crystal grain boundaries does not easily occur. In addition, since the crystallinity of the metal oxide may be lowered due to the mixing of impurities, generation of defects, or the like, CAAC-OS can also be said to be a metal oxide with few impurities or defects (such as oxygen vacancies). Therefore, the metal oxide having a CAAC-OS has stable physical properties. Therefore, a metal oxide having a CAAC-OS is resistant to heat and has high reliability.
  • the nc-OS has periodicity in atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • nc-OS has no regularity in crystal orientation among different nanocrystals. Therefore, no orientation can be seen in the entire film. Therefore, the nc-OS may not be distinguished from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.
  • the a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a wrinkle or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • a metal oxide with low carrier density is preferably used for the transistor.
  • the impurity concentration in the metal oxide film may be lowered to lower the density of defect states.
  • a low impurity concentration and a low density of defect levels are referred to as high purity intrinsic or substantially high purity intrinsic.
  • the metal oxide has a carrier density of less than 8 ⁇ 10 11 / cm 3 , preferably less than 1 ⁇ 10 11 / cm 3 , more preferably less than 1 ⁇ 10 10 / cm 3 , and 1 ⁇ 10 ⁇ 9 / cm 3. It should be cm 3 or more.
  • the trap state density may also be low.
  • the charge trapped in the trap level of the metal oxide may take a long time to disappear and behave as if it were fixed charge. Therefore, a transistor including a metal oxide with a high trap state density in a channel formation region may have unstable electrical characteristics.
  • the impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon or carbon in the metal oxide and the concentration of silicon or carbon in the vicinity of the interface with the metal oxide are 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the metal oxide contains an alkali metal or an alkaline earth metal
  • a defect level may be formed to generate a carrier. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to be normally on. For this reason, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide.
  • the concentration of alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen in the channel formation region is preferably reduced as much as possible.
  • the nitrogen concentration in the metal oxide is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less, in SIMS. Preferably, it is 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in the metal oxide reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons that are carriers may be generated.
  • a part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor in which a metal oxide containing hydrogen is used for a channel formation region is likely to be normally on. For this reason, hydrogen in the metal oxide is preferably reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm. It is less than 3 and more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • a thin film with high crystallinity As the metal oxide used for the semiconductor of the transistor, the stability or the reliability of the transistor can be improved.
  • the thin film include thin films of single crystal metal oxides or thin films of polycrystalline metal oxides.
  • a high temperature or laser heating step is required to form a thin film of monocrystalline metal oxide or a thin film of polycrystalline metal oxide on a substrate. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.
  • Non-Patent Document 1 and Non-Patent Document 2 In-Ga-Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was discovered in 2009.
  • CAAC-IGZO has c-axis orientation, that crystal grain boundaries are not clearly confirmed, and that it can be formed on a substrate at low temperature.
  • a transistor using CAAC-IGZO is reported to have excellent electrical characteristics and reliability.
  • nc-IGZO In-Ga-Zn oxide having an nc structure was discovered (see Non-Patent Document 3).
  • nc-IGZO has periodicity in atomic arrangement in a minute area (for example, an area of 1 nm or more and 3 nm or less) and regularity in crystal orientation is not observed between different areas. There is.
  • Non-Patent Document 4 and Non-Patent Document 5 show the transition of the average crystal size by the irradiation of an electron beam to the thin films of the above-described CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity.
  • a low crystalline IGZO thin film crystalline IGZO of about 1 nm has been observed even before electron beam irradiation. Therefore, it is reported here that in IGZO, the presence of a completely amorphous structure could not be confirmed.
  • the thin film of CAAC-IGZO and the thin film of nc-IGZO have high stability to electron beam irradiation as compared with the thin film of IGZO having low crystallinity. Therefore, it is preferable to use a thin film of CAAC-IGZO or a thin film of nc-IGZO as a semiconductor of the transistor.
  • a transistor using a metal oxide has extremely low leakage current in the non-conductive state.
  • the off-state current per 1 ⁇ m channel width of the transistor is on the order of yA / ⁇ m (10 ⁇ 24 A / ⁇ m).
  • a low power consumption CPU or the like to which a characteristic that a leak current of a transistor using a metal oxide is low is disclosed (see Non-Patent Document 7).
  • Non-Patent Document 8 application to a display device of a transistor using a characteristic that the leakage current of a transistor using a metal oxide is low has been reported (see Non-Patent Document 8).
  • the displayed image is switched several tens of times per second.
  • the number of times of switching images per second is called a refresh rate.
  • the refresh rate may be referred to as a drive frequency.
  • Such fast screen switching which is difficult for human eyes to perceive, is considered as the cause of eye fatigue. Therefore, it has been proposed to reduce the number of image rewrites by reducing the refresh rate of the display device.
  • power consumption of the display device can be reduced by driving with a lower refresh rate.
  • Such a driving method is called idling stop (IDS) driving.
  • IDS idling stop
  • the discovery of the CAAC structure and the nc structure contributes to the improvement of the electrical characteristics and reliability of a transistor using a metal oxide having a CAAC structure or an nc structure, as well as to the cost reduction and the throughput improvement of the manufacturing process.
  • researches on application of the transistor to a display device and an LSI using the characteristic that the leakage current of the transistor is low have been advanced.
  • An insulating material for forming an insulating layer, a conductive material for forming an electrode, or a semiconductor material for forming a semiconductor layer can be formed by sputtering, spin coating, chemical vapor deposition (CVD) (thermal CVD). Method, metal organic chemical vapor deposition (MOCVD) method, plasma enhanced CVD (PECVD) method, high density plasma CVD (high density plasma CVD) method, low pressure CVD (LPCVD) method, APCVD (atmospheric pressure CVD) method, etc.
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • PECVD plasma enhanced CVD
  • high density plasma CVD high density plasma CVD
  • LPCVD low pressure CVD
  • APCVD atmospheric pressure CVD
  • ALD Atomic Layer Deposition
  • MBE Molecular Beam Epitaxy
  • P It can be formed using LD (Pulsed Laser Deposition) method, dip method, spray application method, droplet discharge method (ink jet method etc.), printing method (screen printing, offset printing etc.) or the like.
  • the plasma CVD method provides high quality films at relatively low temperatures.
  • a film formation method which does not use plasma at the time of film formation such as MOCVD method, ALD method, or thermal CVD method
  • damage to a formation surface is less likely to occur.
  • a wiring, an electrode, an element (eg, a transistor or a capacitor), and the like included in a memory device may be charged up by receiving charge from plasma.
  • wirings, electrodes, elements, and the like included in the memory device may be broken by the stored charge.
  • the yield of the memory device can be increased.
  • plasma damage does not occur during film formation, a film with few defects can be obtained.
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed unlike a film forming method in which particles released from a target or the like are deposited. Therefore, the film forming method is less susceptible to the shape of the object to be processed, and has good step coverage.
  • the ALD method since the ALD method has excellent step coverage and uniformity of thickness, it is suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method may be preferably used in combination with another deposition method such as a CVD method having a high deposition rate.
  • the CVD method and the ALD method can control the composition of the obtained film by the flow rate ratio of the source gas.
  • a film having any composition can be formed depending on the flow rate ratio of the source gas.
  • a film whose composition is continuously changed can be formed by changing the flow ratio of the source gas while forming the film.
  • the gas which does not contain chlorine it is preferable to use the gas which does not contain chlorine as source gas.
  • FIG. 13A is a top view of the transistor 200B.
  • 13B is a cross-sectional view of a portion indicated by dashed-dotted line L1-L2 in FIG. 13A.
  • 13C is a cross-sectional view of a portion indicated by dashed-dotted line W1-W2 in FIG. 13A. Note that in the top view of FIG. 13A, some elements are omitted for clarity of the drawing.
  • the transistor 200B is a modification of the transistor 200A. Therefore, in order to prevent repetition of the description, points different from the transistor 200A are mainly described.
  • the oxide 230 c, the insulator 250, and the conductor 260 are provided in the opening portion provided in the insulator 280 with the insulator 274 interposed therebetween.
  • the oxide 230c, the insulator 250, and the conductor 260 are disposed between the conductor 242a and the conductor 242b.
  • the oxide 230 c is preferably provided in the opening provided in the insulator 280 via the insulator 274.
  • the insulator 274 has a barrier property, diffusion of impurities from the insulator 280 into the oxide 230 can be suppressed.
  • the insulator 250 functions as a first gate insulating layer.
  • the insulator 250 is preferably provided in the opening provided in the insulator 280 through the oxide 230 c and the insulator 274.
  • An insulator 274 is disposed between the insulator 280 and the transistor 200B.
  • an insulating material which has a function of suppressing diffusion of water, impurities such as hydrogen, and oxygen can be used.
  • impurities such as hydrogen, and oxygen
  • aluminum oxide or hafnium oxide is preferably used.
  • metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, silicon nitride oxide, silicon nitride, and the like can be used.
  • the insulator 274 With the insulator 274, diffusion of impurities such as water and hydrogen which the insulator 280 has into the oxide 230b through the oxide 230c and the insulator 250 can be suppressed. Further, oxidation of the conductor 260 can be suppressed by excess oxygen contained in the insulator 280.
  • FIG. 14A is a top view of the transistor 200C.
  • FIG. 14B is a cross-sectional view of a portion indicated by dashed-dotted line L1-L2 in FIG. 14C is a cross-sectional view of a portion indicated by dashed-dotted line W1-W2 in FIG. 14A. Note that in the top view of FIG. 14A, some elements are omitted for clarity of the drawing.
  • the transistor 200C is a modification of the transistor 200B. Therefore, in order to prevent repetition of the description, points different from the transistor 200B are mainly described.
  • the conductive layer 247a is disposed between the conductor 242a and the oxide 230b, and the conductive layer 247b is disposed between the conductor 242b and the oxide 230b.
  • the conductor 242a extends beyond the top surface of the conductive layer 247a (conductive layer 247b) and the side surface on the conductor 260 side, and has a region in contact with the top surface of the oxide 230b.
  • the conductive layer 247 a conductor that can be used for the conductor 242 may be used.
  • the thickness of the conductive layer 247 is preferably at least larger than that of the conductor 242.
  • the transistor 200C illustrated in FIG. 14 can bring the conductor 242 closer to the conductor 260 than the transistor 200B.
  • the conductor 260 can be overlapped with the end of the conductor 242 a and the end of the conductor 242 b. Accordingly, the substantial channel length of the transistor 200C can be shortened, and the on current and the operating frequency can be improved.
  • the conductive layer 247a (conductive layer 247b) is preferably provided so as to overlap with the conductor 242a (conductor 242b). With such a structure, the conductive layer 247a (conductive layer 247b) functions as a stopper and the oxide 230b is over-etched in etching for forming an opening in which the conductor 246a (conductor 246b) is embedded. It can prevent.
  • the transistor 200C illustrated in FIG. 14 may have a structure in which the insulating layer 245 is provided on and in contact with the insulating layer 244.
  • the insulating layer 244 preferably functions as a barrier insulating film which suppresses impurities such as water and hydrogen and excess oxygen from entering the transistor 200C from the insulator 280 side.
  • an insulator that can be used for the insulating layer 244 can be used.
  • a nitride insulator such as aluminum nitride, titanium nitride, silicon nitride, or silicon nitride oxide may be used, for example.
  • the transistor 200C illustrated in FIG. 14 may be provided with the conductor 205 in a single-layer structure, unlike the transistor 200B illustrated in FIG.
  • an insulating film to be the insulator 216 is formed on the patterned conductor 205, and the upper portion of the insulating film is subjected to chemical mechanical polishing (CMP) or the like until the upper surface of the conductor 205 is exposed. It may be removed by using.
  • CMP chemical mechanical polishing
  • the average surface roughness (Ra) of the top surface of the conductor 205 may be 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less. Accordingly, the planarity of the insulating layer formed over the conductor 205 can be improved and crystallinity of the oxide 230 b and the oxide 230 c can be improved.
  • FIG. 15A is a top view of the transistor 200D.
  • FIG. 15B is a cross-sectional view of a portion indicated by dashed-dotted line L1-L2 in FIG.
  • FIG. 15C is a cross-sectional view of a portion indicated by dashed-dotted line W1-W2 in FIG. Note that in the top view of FIG. 15A, some elements are omitted for clarity of the drawing.
  • the transistor 200D is a modified example of the above transistor. Therefore, in order to prevent repetition of the description, points different from the above transistor are mainly described.
  • the conductor 205 functioning as a second gate also functions as a wiring.
  • the insulator 250 is provided over the oxide 230 c, and the metal oxide 252 is provided over the insulator 250.
  • the conductor 260 is provided over the metal oxide 252, and the insulating layer 270 is provided over the conductor 260.
  • the insulating layer 271 is provided over the insulating layer 270.
  • the metal oxide 252 preferably has a function of suppressing oxygen diffusion.
  • the metal oxide 252 which suppresses the diffusion of oxygen between the insulator 250 and the conductor 260 the diffusion of oxygen to the conductor 260 is suppressed. That is, a reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Further, oxidation of the conductor 260 by oxygen can be suppressed.
  • the metal oxide 252 may function as part of the first gate electrode.
  • an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide 252.
  • the electric resistance value of the metal oxide 252 can be reduced to form a conductive layer.
  • the metal oxide 252 may function as part of the first gate insulating layer. Therefore, in the case of using silicon oxide, silicon oxynitride, or the like for the insulator 250, it is preferable that the metal oxide 252 be a metal oxide which is a high-k material having a high dielectric constant. With the laminated structure, a laminated structure stable to heat and having a high dielectric constant can be obtained. Therefore, while maintaining the physical film thickness, it is possible to reduce the gate potential applied during the operation of the transistor. In addition, the equivalent oxide thickness (EOT) of the insulating layer which functions as a gate insulating layer can be reduced.
  • EOT equivalent oxide thickness
  • the metal oxide 252 is illustrated as a single layer in the transistor 200D, a stacked-layer structure of two or more layers may be employed.
  • a metal oxide which functions as a part of the first gate electrode and a metal oxide which functions as a part of the first gate insulating layer may be stacked.
  • the on current of the transistor 200D can be improved without weakening the influence of the electric field from the conductor 260.
  • the physical thickness of the insulator 250 and the metal oxide 252 makes it possible to maintain the distance between the conductor 260 and the oxide 230, thereby achieving conductivity. Leakage current between the body 260 and the oxide 230 can be suppressed. Therefore, by providing the laminated structure of the insulator 250 and the metal oxide 252, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be facilitated. Can be adjusted accordingly.
  • the oxide semiconductor that can be used for the oxide 230 can be used as the metal oxide 252 by reducing its resistance.
  • a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like can be used.
  • hafnium oxide an oxide containing aluminum and hafnium (hafnium aluminate), or the like which is an insulating layer containing an oxide of one or both of aluminum and hafnium is preferably used.
  • hafnium aluminate has higher heat resistance than hafnium oxide. Therefore, it is preferable because it is difficult to crystallize in a thermal history (thermal budget) in a later step.
  • the metal oxide 252 is not an essential component. It may be appropriately designed according to the transistor characteristics to be obtained.
  • the insulating layer 270 may be formed using an insulating material having a function of suppressing permeation of water, impurities such as hydrogen, and oxygen.
  • an insulating material having a function of suppressing permeation of water, impurities such as hydrogen, and oxygen For example, aluminum oxide or hafnium oxide is preferably used.
  • impurities such as water and hydrogen from above the insulating layer 270 can be prevented from being mixed into the oxide 230 through the conductor 260 and the insulator 250.
  • the insulating layer 271 functions as a hard mask.
  • the side surface of the conductor 260 is substantially vertical, specifically, the angle between the side surface of the conductor 260 and the substrate surface is 75 degrees or more and 100 degrees or less, Preferably, it can be 80 degrees or more and 95 degrees or less.
  • the insulating layer 271 may also function as a barrier layer by using an insulating material having a function of suppressing permeation of impurities such as water and hydrogen and oxygen. In that case, the insulating layer 270 may not be provided.
  • the transistor 200D has a region 231a and a region 231b in part of the exposed surface of the oxide 230b.
  • One of the region 231a or the region 231b functions as a source region, and the other functions as a drain region.
  • the regions 231a and 231b can be formed, for example, by introducing an impurity element such as phosphorus or boron onto the surface of the exposed oxide 230b by using ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like.
  • impurity element refers to an element other than the main component element.
  • a metal film is formed, and then heat treatment is performed to diffuse the elements contained in the metal film into the oxide 230 b to form the region 231 a and the region 231 b.
  • the region 231a and the region 231b may be referred to as an "impurity region” or a "low resistance region”.
  • the region 231a and the region 231b can be formed in a self-aligned manner.
  • the parasitic capacitance can be reduced because the region 231a or the region 231b and the conductor 260 do not overlap.
  • an offset region is not formed between the channel formation region and the source or drain region (the region 231a or the region 231b).
  • an offset region may be provided between the channel formation region and the source region or the drain region.
  • the offset region is a region where the electric resistivity is high, and is a region where the introduction of the impurity element described above is not performed.
  • the formation of the offset region can be realized by introducing the above-described impurity element after the formation of the insulating layer 275.
  • the insulating layer 275 also functions as a mask in the same manner as the insulating layer 271 and the like.
  • the impurity element is not introduced into the region of the oxide 230 b overlapping with the insulating layer 275, and the electrical resistivity of the region can be kept high.
  • the transistor 200D includes an insulating layer 275 over the side surfaces of the insulating layer 270, the conductor 260, the metal oxide 252, the insulator 250, and the oxide 230c.
  • the insulating layer 275 is preferably an insulator with a low relative dielectric constant.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes is preferably used for the insulating layer 275 because an excess oxygen region can be easily formed in the insulating layer 275 in a later step.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the insulating layer 275 preferably has a function of diffusing oxygen.
  • the transistor 200D includes the insulator 274 over the insulating layer 275 and the oxide 230.
  • the insulator 274 is preferably deposited by sputtering. By using the sputtering method, an insulator with few impurities such as water and hydrogen can be formed. For example, aluminum oxide may be used as the insulator 274.
  • an oxide film formed by a sputtering method may extract hydrogen from a deposition target structure.
  • the insulator 274 absorbs hydrogen and water from the oxide 230 and the insulating layer 275, whereby the concentration of hydrogen in the oxide 230 and the insulating layer 275 can be reduced.
  • FIG. 1 An example of a semiconductor device (storage device) using a capacitor which is one embodiment of the present invention is illustrated in FIG.
  • the transistor 200 is provided above the transistor 300
  • the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.
  • Each of the conductors included in the transistor 200 is preferably electrically connected to the diode element described in the above embodiment or the transistor functioning as a capacitor.
  • the diode 10s is shown representatively in FIGS. 16 and 17, the present invention is not limited to this structure. Depending on the performance of the semiconductor device to be obtained, it is preferable to design as appropriate using the structure described in the above embodiment.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has low off-state current, stored data can be held for a long time by using the transistor for the memory device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, power consumption of the memory device can be sufficiently reduced.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300.
  • the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • the memory device illustrated in FIG. 16 can form a memory cell array by being arranged in a matrix.
  • the transistor 300 is provided over the substrate 311 and functions as a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and a source region or a drain region. It has low resistance region 314a and low resistance region 314b.
  • the transistor 300 may be either p-channel or n-channel.
  • the semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape.
  • the conductor 316 is provided to cover the side surface and the top surface of the semiconductor region 313 with the insulator 315 interposed therebetween.
  • the conductor 316 may use a material for adjusting a work function.
  • Such a transistor 300 is also referred to as a FIN type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulator which functions as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion.
  • a semiconductor film having a convex shape may be formed by processing the SOI substrate.
  • transistor 300 illustrated in FIG. 16 is an example and is not limited to the structure, and an appropriate transistor may be used depending on the circuit configuration and the driving method.
  • the capacitive element 100 is provided above the transistor 200.
  • the capacitor 100 includes the conductor 110 functioning as a first electrode, the conductor 120 functioning as a second electrode, and the insulator 130 functioning as a dielectric.
  • the conductor 112 provided over the conductor 246 and the conductor 110 can be formed at the same time.
  • the conductor 112 has a function as a plug electrically connected to the capacitor 100, the transistor 200, or the transistor 300, or a wiring.
  • the conductor 112 and the conductor 110 each have a single-layer structure in FIG. 16, the structure is not limited to this structure, and a stacked structure of two or more layers may be used. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor having high adhesion to a conductor having a barrier property and a conductor having high conductivity may be formed.
  • the insulator 130 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, hafnium nitride Or the like may be used, and they can be provided in a stack or a single layer.
  • the capacitive element 100 can secure a sufficient capacity by having an insulator with a high dielectric constant (high-k), and by having an insulator with a large dielectric strength, the dielectric strength can be improved, and the capacitance can be increased.
  • the electrostatic breakdown of the element 100 can be suppressed.
  • an insulator of a high dielectric constant (high-k) material (a material with a high relative dielectric constant), an oxide having gallium oxide, hafnium oxide, zirconium oxide, aluminum and hafnium, an oxynitride having aluminum and hafnium And oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon is added, carbon and nitrogen are materials having high dielectric strength (materials having low dielectric constant) There is silicon oxide added, silicon oxide having pores, or a resin.
  • a wiring layer provided with an interlayer film, a wiring, a plug and the like may be provided between the respective structures. Also, a plurality of wiring layers can be provided depending on the design.
  • a conductor having a function as a plug or a wiring may be provided with the same reference numeral collectively as a plurality of structures.
  • the wiring and the plug electrically connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as an interlayer film.
  • the conductor 328 electrically connected to the capacitor 100 or the transistor 200, the conductor 330, and the like are embedded. Note that the conductor 328 and the conductor 330 function as a plug or a wiring.
  • the insulator functioning as an interlayer film may function as a planarization film covering the uneven shape below it.
  • the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance the planarity.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided over the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked and provided.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wire.
  • the conductor 218, a conductor (conductor 205) included in the transistor 200, and the like are embedded.
  • the conductor 218 has a function as a plug electrically connected to the capacitor 100 or the transistor 300, or a wiring.
  • an insulator 150 is provided over the conductor 120 and the insulator 130.
  • an insulator which can be used as an interlayer film, an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, a metal nitride oxide, or the like can be given.
  • the material may be selected depending on the function of the insulator.
  • the insulator 216, the insulator 212, the insulator 352, the insulator 354, and the like preferably include an insulator with a low dielectric constant.
  • the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having voids. It is preferable to have a resin or the like.
  • the insulator may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide having voids. It is preferable to have a laminated structure of and a resin. Silicon oxide and silicon oxynitride are thermally stable, and thus, when combined with a resin, a stacked structure with a thermally stable and low dielectric constant can be obtained. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate or acrylic.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium
  • An insulator containing lanthanum, neodymium, hafnium or tantalum may be used in a single layer or a stack.
  • a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium
  • a material containing one or more metal elements selected from ruthenium and the like can be used.
  • a semiconductor with high electrical conductivity typically a polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a metal material for example, as the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like, a metal material, an alloy material, a metal nitride material, a metal oxide material, or the like formed of any of the above materials
  • the conductive material of can be used in a single layer or a laminate. It is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.
  • an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor.
  • the insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and the conductor provided in the insulator having the excess oxygen region.
  • the insulator 224 and the transistor 200 can be sealed by the insulator 222 having a barrier property, the insulator 254, and the insulator 274.
  • the insulator 276c is in contact with the conductor 246c and part of the insulator 280, and suppresses the diffusion of impurities such as water or hydrogen and oxygen contained in the insulator 280 into the conductor 246c. Can.
  • the insulator 276c by providing the insulator 276c, absorption of excess oxygen of the insulator 280 by the conductor 246c can be suppressed. Further, with the insulator 276c, diffusion of hydrogen, which is an impurity, into the transistor 200 through the conductor 246c can be suppressed.
  • an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen can be used as the insulator 276c.
  • an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen can be used.
  • aluminum oxide or hafnium oxide is preferably used.
  • metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • FIG. 17 An example of a memory device using the semiconductor device of one embodiment of the present invention is illustrated in FIG.
  • the memory device illustrated in FIG. 17 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 illustrated in FIG.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300.
  • the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the back gate of the transistor 200.
  • the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • the wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the back gate of the transistor 400, and the wiring 1010 is a drain of the transistor 400 And are electrically connected.
  • the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.
  • the memory device shown in FIG. 17 can form a memory cell array by being arranged in a matrix as in the memory device shown in FIG. Note that one transistor 400 can control the second gate voltage of the plurality of transistors 200. Therefore, the number of transistors 400 may be smaller than that of the transistors 200.
  • the transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel.
  • the transistor 400 includes a conductor 460 functioning as a first gate electrode, a conductor 405 (conductors 405 a and 405 b) functioning as a second gate electrode, and an insulator 222 functioning as a gate insulating layer.
  • the conductor 405 is in the same layer as the conductor 205.
  • the oxide 431a and the oxide 432a are in the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are in the same layer as the oxide 230b.
  • the conductor 442 is the same layer as the conductor 242.
  • the oxide 430c is the same layer as the oxide 230c.
  • the insulator 450 is the same layer as the insulator 250.
  • the conductor 460 is the same layer as the conductor 260.
  • the oxide 430c can be formed by processing an oxide film to be the oxide 230c.
  • dicing lines (sometimes referred to as scribe lines, dividing lines, or cutting lines) provided when a plurality of semiconductor devices are taken out in chip form by dividing a large-area substrate into semiconductor elements will be described.
  • a dividing method for example, after a groove (dicing line) for dividing a semiconductor element is first formed in a substrate, it may be cut at a dicing line to divide (divide) into a plurality of semiconductor devices.
  • the insulator 274 may be formed after an opening is provided in the insulator 222 and the insulator 216 in the vicinity of the memory cell including the plurality of transistors 200 and a region serving as a dicing line provided on the outer edge of the transistor 400. .
  • the insulator 214 is in contact with the insulator 274.
  • the insulator 215 and the insulator 274 may be formed using the same material and the same method. Adhesion can be improved by providing the insulator 215 and the insulator 274 using the same material and the same method. For example, silicon nitride is preferably used.
  • the insulator 224, the transistor 200, and the transistor 400 can be surrounded by the insulator 215 and the insulator 274. Since the insulator 215 and the insulator 274 have a function of suppressing diffusion of oxygen, hydrogen, and water, the substrate is divided in each of the circuit regions in which the semiconductor element described in this embodiment is formed. Accordingly, even when processed into a plurality of chips, impurities such as hydrogen or water can be prevented from being mixed from the side direction of the divided substrate and diffused into the transistor 200 and the transistor 400.
  • excess oxygen in the insulator 224 can be prevented from diffusing to the insulator 274 and the insulator 215. Accordingly, excess oxygen in the insulator 224 is efficiently supplied to the transistor 200 or the oxide in which the channel in the transistor 400 is formed.
  • the oxygen can reduce oxygen vacancies in the oxide in which a channel in the transistor 200 or the transistor 400 is formed. Accordingly, the oxide in which the channel in the transistor 200 or the transistor 400 is formed can be an oxide semiconductor with low density of defect states and stable characteristics. That is, variation in the electrical characteristics of the transistor 200 or the transistor 400 can be suppressed, and the reliability can be improved.
  • Embodiment 4 a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are applied using FIGS. 18 and 19.
  • the storage device (hereinafter sometimes referred to as an OS memory device) will be described.
  • the OS memory device is a storage device including at least a capacitor and an OS transistor which controls charge and discharge of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a non-volatile memory.
  • FIG. 18A shows an example of the configuration of the OS memory device.
  • the memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470.
  • Peripheral circuit 1411 includes row circuit 1420, column circuit 1430, output circuit 1440, and control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like.
  • the precharge circuit has a function of precharging the wiring.
  • the sense amplifier has a function of amplifying a data signal read from the memory cell.
  • the wiring is a wiring connected to a memory cell included in the memory cell array 1470, which will be described in detail later.
  • the amplified data signal is output as the data signal RDATA to the outside of the storage device 1400 through the output circuit 1440.
  • the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.
  • the storage device 1400 is externally supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 as a power supply voltage. Further, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
  • the address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit.
  • the control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for row decoders and column decoders.
  • CE is a chip enable signal
  • WE is a write enable signal
  • RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and another control signal may be input as necessary.
  • Memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings.
  • the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC provided in one column, and the like.
  • the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, and the like.
  • FIG. 18A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane
  • the present embodiment is not limited to this.
  • the memory cell array 1470 may be provided so as to overlap with part of the peripheral circuit 1411.
  • a sense amplifier may be provided so as to overlap below the memory cell array 1470.
  • [DOSRAM] 19A to 19C show an example of the circuit configuration of a memory cell of a DRAM.
  • a DRAM using one single capacitive element type memory cell per one OS transistor may be referred to as a DOSRAM.
  • the memory cell 1471 illustrated in FIG. 19A includes a transistor M1 and a capacitor CA.
  • the transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.
  • the first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 Is connected to the wiring BGL.
  • the second terminal of the capacitive element CA is connected to the wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. It is preferable to apply a low level potential to the wiring CAL at the time of data writing and reading.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1471 and can change the circuit configuration.
  • the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL.
  • the memory cell MC may be a memory cell including a single gate transistor, that is, a transistor M1 having no back gate.
  • the transistor described in the above embodiment can be used as the transistor M1.
  • the leak current of the transistor M1 can be made very low. That is, since the written data can be held for a long time by the transistor M1, the frequency of refresh of the memory cell can be reduced. In addition, the refresh operation of the memory cell can be made unnecessary.
  • the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.
  • the bit line when the sense amplifier is provided to overlap below the memory cell array 1470, the bit line can be shortened.
  • the bit line capacitance can be reduced, and the storage capacitance of the memory cell can be reduced.
  • [NOSRAM] 19D to 19H show circuit configuration examples of a gain cell type memory cell of one one-capacitance element for two transistors.
  • a memory cell 1474 illustrated in FIG. 19D includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • the first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 Is connected to the wiring BGL.
  • the second terminal of the capacitive element CB is connected to the wiring CAL.
  • the first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, holding data, and reading data, it is preferable to apply a low level potential to the wiring CAL.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1474, and the configuration of the circuit can be changed as appropriate.
  • the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL.
  • the memory cell MC may be a memory cell including a single-gate transistor, that is, a transistor M2 which does not have a back gate.
  • the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into one wiring BIL.
  • the transistor described in the above embodiment can be used as the transistor M2.
  • the leakage current of the transistor M2 can be made very low.
  • the frequency of refresh of the memory cell can be reduced.
  • the refresh operation of the memory cell can be made unnecessary.
  • the memory cell 1474 can hold multilevel data or analog data. The same applies to memory cells 1475 to 1477.
  • the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor).
  • the conductivity type of the Si transistor may be n-channel or p-channel.
  • the Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read out transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be provided by being stacked on the transistor M3, so that the area occupied by the memory cell can be reduced and high integration of the memory device can be achieved.
  • the transistor M3 may be an OS transistor.
  • an OS transistor is used for the transistor M2 and the transistor M3, the memory cell array 1470 can be configured using only n-type transistors.
  • FIG. 19H shows an example of a gain cell type memory cell of one one capacitance element for three transistors.
  • the memory cell 1478 illustrated in FIG. 19H includes the transistors M4 to M6 and the capacitor CC.
  • the capacitive element CC is appropriately provided.
  • the memory cell 1478 is electrically connected to the wiring BIL, the wiring RWL, the wiring WWL, the wiring BGL, and the wiring GNDL.
  • the wiring GNDL is a wiring for applying a low level potential. Note that the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.
  • the transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.
  • the transistor M5 and the transistor M6 may be n-channel Si transistors or p-channel Si transistors, respectively.
  • the transistors M4 to M6 may be OS transistors.
  • the memory cell array 1470 can be configured using only n-type transistors.
  • the transistor described in the above embodiment can be used as the transistor M4.
  • the leak current of the transistor M4 can be made very low.
  • peripheral circuit 1411 the memory cell array 1470, and the like described in this embodiment are not limited to the above. Arrangements or functions of these circuits and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as needed.
  • FIG. 1200 An example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown using FIG.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system on chip
  • the chip 1200 includes a central processing unit (CPU) 1211, a graphics processing unit (GPU) 1212, one or more analog operation units 1213, one or more memory controllers 1214, one or more Interface 1215, one or more network circuits 1216, and the like.
  • CPU central processing unit
  • GPU graphics processing unit
  • analog operation units 1213 one or more analog operation units 1213
  • memory controllers 1214 one or more memory controllers 1214
  • Interface 1215 one or more network circuits 1216, and the like.
  • the chip 1200 is provided with a bump (not shown), and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in FIG. 20B. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.
  • PCB printed circuit board
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222.
  • a storage device such as a DRAM 1221 and a flash memory 1222.
  • the DOS RAM described in the above embodiment can be used for the DRAM 1221.
  • the NOSRAM described in the above embodiment can be used for the flash memory 1222.
  • the CPU 1211 preferably has a plurality of CPU cores.
  • the GPU 1212 preferably has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the memory the aforementioned NOSRAM or DOSRAM can be used.
  • the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum operation. By providing the image processing circuit and the product-sum operation circuit using the oxide semiconductor of the present invention in the GPU 1212, image processing and product-sum operation can be performed with low power consumption.
  • the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between memories of the CPU 1211 and the GPU 1212, And, after the calculation by the GPU 1212, transfer of the calculation result from the GPU 1212 to the CPU 1211 can be performed at high speed.
  • the analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum operation circuit may be provided in the analog operation unit 1213.
  • the memory controller 1214 has a circuit functioning as a controller of the DRAM 1221 and a circuit functioning as an interface of the flash memory 1222.
  • the interface 1215 includes an interface circuit with an external connection device such as a display device, a speaker, a microphone, a camera, and a controller.
  • the controller includes a mouse, a keyboard, a game controller, and the like.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface or the like can be used.
  • the network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also have circuitry for network security.
  • LAN Local Area Network
  • the circuits can be formed in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing processes, and the chip 1200 can be manufactured at low cost.
  • the PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be referred to as a GPU module 1204.
  • the GPU module 1204 has a chip 1200 using SoC technology, so its size can be reduced. Moreover, since it is excellent in image processing, it is suitable to use for portable electronic devices, such as a smart phone, a tablet terminal, a laptop PC, and a portable (not stationary) game machine.
  • a deep neural network DNN
  • CNN convolutional neural network
  • RNN recursive neural network
  • DBM deep layer Boltzmann machine
  • the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module, since a technique such as DBN can be performed.
  • the semiconductor device described in the above embodiment is, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording and reproducing device, a navigation system, etc.)
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device described in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • FIG. 21 schematically shows some configuration examples of the removable storage device.
  • the semiconductor device described in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.
  • FIG. 21A is a schematic view of a USB memory.
  • the USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104.
  • the substrate 1104 is housed in a housing 1101.
  • the memory chip 1105 and the controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1105 or the like of the substrate 1104.
  • FIG. 21 (B) is a schematic view of the appearance of the SD card
  • FIG. 21 (C) is a schematic view of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111, a connector 1112 and a substrate 1113.
  • the substrate 1113 is housed in a housing 1111.
  • the memory chip 1114 and the controller chip 1115 are attached to the substrate 1113.
  • the capacity of the SD card 1110 can be increased.
  • a wireless chip provided with a wireless communication function may be provided over the substrate 1113.
  • data can be read and written from the memory chip 1114 by wireless communication between the host device and the SD card 1110.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1114 or the like of the substrate 1113.
  • FIG. 21D is a schematic view of the appearance of the SSD
  • FIG. 21E is a schematic view of the internal structure of the SSD.
  • the SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153.
  • the substrate 1153 is housed in a housing 1151.
  • the memory chip 1154, the memory chip 1155, and the controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used.
  • the capacity of the SSD 1150 can be increased.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1154 or the like of the substrate 1153.
  • a display device and a display module will be described as an example of a semiconductor device using a transistor disclosed in this specification and the like.
  • a transistor using an acid semiconductor described using the transistor 200 or the like may be hereinafter referred to as an OS transistor.
  • FIG. 22A is a block diagram for explaining a configuration example of the display device 500.
  • a display device 500 illustrated in FIG. 22A includes a driver circuit 511, a driver circuit 521a, a driver circuit 521b, and a display region 531.
  • the driver circuit 511, the driver circuit 521a, and the driver circuit 521b may be collectively referred to as a "driver circuit” or a "peripheral driver circuit”.
  • the driver circuit 521a and the driver circuit 521b can function as, for example, a scanning line driver circuit.
  • the driver circuit 511 can function as, for example, a signal line driver circuit. Note that only one of the driver circuit 521 a and the driver circuit 521 b may be provided. In addition, any circuit may be provided at a position facing the driver circuit 511 with the display area 531 interposed therebetween.
  • the display area 531 has a plurality of pixels 532 arranged in a matrix.
  • the pixel 532 includes a pixel circuit 534 and a display element.
  • full color display can be realized by causing the three pixels 532 to function as one pixel.
  • Each of the three pixels 532 controls the transmittance, the reflectance, the emitted light amount, and the like of red light, green light, or blue light.
  • the color of the light controlled by the three pixels 532 is not limited to the combination of red, green and blue, and may be yellow, cyan and magenta.
  • the pixel 532 for controlling white light may be added to the pixels for controlling red light, green light, and blue light, and the four pixels 532 may be collectively functioned as one pixel.
  • the luminance of the display region can be increased.
  • by increasing the number of pixels 532 to be functioned as one pixel and appropriately using red, green, blue, yellow, cyan, and magenta in combination it is possible to widen the reproducible color gamut.
  • a display device 500 capable of performing display with so-called full high-definition (also referred to as “2K resolution”, “2K1K”, “2K”, etc.) resolution can be realized. Further, for example, by arranging the pixels in a matrix of 3840 ⁇ 2160, a display device 500 capable of displaying at a resolution of so-called ultra high vision (also referred to as “4K resolution”, “4K2K”, “4K”, etc.) is realized.
  • full high-definition also referred to as “2K resolution”, “2K1K”, “2K”, etc.
  • ultra high vision also referred to as “4K resolution”, “4K2K”, “4K”, etc.
  • a display device 500 capable of displaying at a resolution of so-called super high vision (also referred to as “8K resolution”, “8K4K”, “8K”, etc.) is realized.
  • so-called super high vision also referred to as “8K resolution”, “8K4K”, “8K”, etc.
  • a display device 500 capable of displaying at a resolution of 16K or 32K.
  • the wiring 535 _ g (g is a natural number greater than or equal to 1 and less than p) in the g-th row corresponds to q pixels 532 disposed in the g row among the plurality of pixels 532 disposed in p rows and q columns in the display region 531. And electrically connected. Further, the wiring 536 h in the h-th column (h is a natural number of 1 or more and q or less) is electrically connected to p pixels 532 arranged in the h-column among the pixels 532 arranged in the p-row and q-column. Connected
  • the display device 500 can have various forms or have various display elements.
  • display elements include EL (electroluminescent) elements (organic EL elements, inorganic EL elements, or EL elements containing organic and inorganic substances), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (Transistor emitting light according to current) Electron emission device, Liquid crystal device, Electron ink, Electrophoresis device, Grating light valve (GLV), Display device using MEMS (micro-electro-mechanical system), Digital micro mirror Device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interferometric modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electro wetting Child, piezoceramic display, display using carbon nanotubes, etc., by electrical or magnetic action, those having contrast, brightness, reflectance, a display medium such as transmittance changes.
  • quantum dots may be used
  • An example of a display device using an EL element is an EL display.
  • a display device using an electron emission element there is a field emission display (FED) or a surface-conduction electron-emitter display (SED).
  • An example of a display device using quantum dots is a quantum dot display.
  • Examples of a display device using a liquid crystal element include a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct view liquid crystal display, projection liquid crystal display) and the like.
  • Examples of a display device using an electronic ink, an electronic powder fluid (registered trademark), or an electrophoretic element include electronic paper.
  • the display device may be a plasma display panel (PDP). Further, the display device may be a retina scanning projection device.
  • part or all of the pixel electrodes may have a function as a reflective electrode.
  • part or all of the pixel electrode may have aluminum, silver, or the like.
  • a storage circuit such as an SRAM can be provided under the reflective electrode. This further reduces power consumption.
  • graphene or graphite may be provided below an electrode of the LED or a nitride semiconductor.
  • Graphene or graphite may have a plurality of layers stacked to form a multilayer film.
  • a nitride semiconductor for example, an n-type GaN semiconductor layer having a crystal can be easily formed thereon.
  • a p-type GaN semiconductor layer or the like having a crystal can be provided thereon to form an LED.
  • an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor layer having a crystal.
  • the GaN semiconductor layer included in the LED may be deposited by MOCVD. However, by providing graphene, the GaN semiconductor layer included in the LED can also be deposited by a sputtering method.
  • FIG. 22B, 22C, 23A, and 23B illustrate examples of circuit structures that can be used for the pixel 532.
  • FIG. 22B, 22C, 23A, and 23B illustrate examples of circuit structures that can be used for the pixel 532.
  • the pixel circuit 534 illustrated in FIG. 22B includes the transistor 461, the capacitor 463, the transistor 468, and the transistor 464.
  • the pixel circuit 534 illustrated in FIG. 22B is electrically connected to the light-emitting element 469 which can function as a display element.
  • An OS transistor can be used for the transistor 461, the transistor 468, and the transistor 464.
  • an OS transistor is preferably used for the transistor 461.
  • One of the source and the drain of the transistor 461 is electrically connected to the wiring 536 _ h. Further, the gate of the transistor 461 is electrically connected to the wiring 535 _g. A video signal is supplied from the wiring 536_h.
  • the transistor 461 has a function of controlling writing of the video signal to the node 465.
  • One of the pair of electrodes of the capacitive element 463 is electrically connected to the node 465, and the other is electrically connected to the node 467.
  • the other of the source and the drain of the transistor 461 is electrically connected to the node 465.
  • the capacitor element 463 has a function as a storage capacitor which holds data written to the node 465.
  • One of the source or the drain of the transistor 468 is electrically connected to the potential supply line VL_a, and the other is electrically connected to the node 467.
  • the gate of transistor 468 is electrically connected to node 465.
  • One of the source or the drain of the transistor 464 is electrically connected to the potential supply line V 0, and the other is electrically connected to the node 467. Further, the gate of the transistor 464 is electrically connected to the wiring 535 _g.
  • One of the anode or the cathode of the light emitting element 469 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the node 467.
  • an organic electroluminescent element also referred to as an organic EL element
  • the light emitting element 469 is not limited to this, and for example, an inorganic EL element formed of an inorganic material may be used.
  • the high power supply potential VDD is applied to one of the potential supply line VL_a or the potential supply line VL_b, and the low power supply potential VSS is applied to the other.
  • the driver circuit 521a and / or the driver circuit 521b sequentially selects the pixels 532 in each row, turns on the transistor 461 and the transistor 464, and outputs a video signal.
  • the pixel 532 whose data is written to the node 465 is held by turning off the transistor 461 and the transistor 464. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 468 is controlled in accordance with the potential of the data written to the node 465, and the light emitting element 469 emits light with luminance according to the amount of current flowing. Images can be displayed by sequentially performing this on a row-by-row basis.
  • a transistor having a back gate may be used as the transistor 461, the transistor 464, and the transistor 468.
  • Gates of the transistors 461 and 464 illustrated in FIG. 23A are electrically connected to a back gate. Therefore, the gate and the back gate always have the same potential.
  • the back gate of the transistor 468 is electrically connected to the node 467. Thus, the back gate is always at the same potential as the node 467.
  • the above-described OS transistor can be used for at least one of the transistor 461, the transistor 468, and the transistor 464.
  • the pixel circuit 534 illustrated in FIG. 22C includes a transistor 461 and a capacitor 463.
  • the pixel circuit 534 illustrated in FIG. 22C is electrically connected to a liquid crystal element 462 which can function as a display element. It is preferable to use an OS transistor for the transistor 461.
  • the potential of one of the pair of electrodes of the liquid crystal element 462 is appropriately set in accordance with the specification of the pixel circuit 534.
  • a common potential (common potential) may be supplied to one of the pair of electrodes of the liquid crystal element 462 or may be the same potential as a capacitor line CL described later.
  • a different potential may be applied to each of the pixels 532 in one of the pair of electrodes of the liquid crystal element 462.
  • the other of the pair of electrodes of the liquid crystal element 462 is electrically connected to the node 466.
  • the alignment state of the liquid crystal element 462 is set by data written to the node 466.
  • TN Transmission Nematic
  • STN Super Twisted Nematic
  • VA Mode
  • ASM Analy Symmetric Aligned Micro-cell
  • OCB Optically Compensated Birefringence
  • FLC Fluoroelectric Liquid Crystal
  • AFLC AntiFerroelectric Liquid Crystal
  • MVA Mobility Vehicle
  • PVA Powerned Vertical Alignment
  • IPS Packet Frame
  • FFS Frequency F
  • TBA Transverse B) nd Alignment
  • a driving method of the display device in addition to the above-described driving method, there are an ECB (Electrically Controlled Birefringence) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, a guest host mode, and the like.
  • ECB Electrically Controlled Birefringence
  • PDLC Polymer Dispersed Liquid Crystal
  • PNLC Polymer Network Liquid Crystal
  • guest host mode a guest host mode
  • the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.
  • thermotropic liquid crystal low molecular liquid crystal
  • polymer liquid crystal polymer dispersed liquid crystal
  • ferroelectric liquid crystal antiferroelectric liquid crystal, or the like
  • liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.
  • liquid crystal exhibiting a blue phase which does not use an alignment film may be used.
  • the blue phase is one of the liquid crystal phases, and is a phase which appears immediately before the cholesteric liquid phase is changed to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer to improve the temperature range.
  • the liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed of 1 msec or less, has optical isotropy, does not require alignment processing, and has a small viewing angle dependency.
  • multi-domaining or multi-domain design in which a pixel is divided into several regions (sub-pixels), and molecules are designed to be inclined in different directions.
  • the specific resistance of the liquid crystal material is 1 ⁇ 10 9 ⁇ ⁇ cm or more, preferably 1 ⁇ 10 11 ⁇ ⁇ cm or more, and more preferably 1 ⁇ 10 12 ⁇ ⁇ cm or more.
  • the value of the specific resistance in this specification be a value measured at 20 degreeC.
  • one of the source and the drain of the transistor 461 is electrically connected to the wiring 536 h, and the other is electrically connected to the node 466.
  • the gate of the transistor 461 is electrically connected to the wiring 535 _g.
  • a video signal is supplied from the wiring 536_h.
  • the transistor 461 has a function of controlling writing of a video signal to the node 466.
  • One of the pair of electrodes of the capacitor 463 is electrically connected to a wiring to which a specific potential is supplied (hereinafter referred to as a capacitor line CL), and the other is electrically connected to the node 466.
  • a capacitor line CL a wiring to which a specific potential is supplied
  • the value of the potential of the capacitor line CL is appropriately set in accordance with the specification of the pixel circuit 534.
  • the capacitor element 463 has a function as a storage capacitor which holds data written to the node 466.
  • the pixel circuit 534 in each row is sequentially selected by the driver circuit 521a and / or the driver circuit 521b, and the transistor 461 is turned on.
  • the pixel circuit 534 in which the video signal is written to the node 466 is held as the transistor 461 is turned off. An image can be displayed in the display area 531 by sequentially performing this for each row.
  • a transistor having a back gate may be used as the transistor 461.
  • the gate of the transistor 461 illustrated in FIG. 23B is electrically connected to the back gate. Therefore, the gate and the back gate always have the same potential.
  • FIG. 24A shows a configuration example of the drive circuit 511.
  • FIG. The drive circuit 511 includes a shift register 512, a latch circuit 513, and a buffer 514.
  • FIG. 24B shows a configuration example of the drive circuit 521a.
  • the drive circuit 521 a includes a shift register 522 and a buffer 523.
  • the drive circuit 521 b can also be configured the same as the drive circuit 521 a.
  • the start pulse SP, the clock signal CLK, and the like are input to the shift register 512 and the shift register 522.
  • part or all of a driver circuit including a shift register can be integrally formed over the same substrate as a pixel portion, whereby a system on panel can be formed.
  • a sealant 4005 is provided so as to surround the pixel portion 4002 provided over the first substrate 4001, and the pixel 402 is sealed with the sealant 4005 and the second substrate 4006.
  • a driver circuit 4003 and a scan line driver circuit 4004 are mounted. Further, various signals and potentials supplied to the signal line driver circuit 4003, the scan line driver circuit 4004, or the pixel portion 4002 are supplied from an FPC 4018a (FPC: flexible printed circuit) and an FPC 4018b.
  • a sealant 4005 is provided so as to surround the pixel portion 4002 provided over the first substrate 4001 and the scan line driver circuit 4004.
  • a second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004.
  • the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the display element by the first substrate 4001, the sealant 4005, and the second substrate 4006.
  • a single crystal semiconductor or a polycrystalline semiconductor is provided on a separately prepared substrate in a region different from the region surrounded by the sealant 4005 on the first substrate 4001.
  • the signal line drive circuit 4003 formed in FIG. In FIGS. 25B and 25C, various signals and potentials are supplied to the signal line driver circuit 4003, the scan line driver circuit 4004, or the pixel portion 4002 from an FPC 4018.
  • FIGS. 25B and 25C illustrate an example in which the signal line driver circuit 4003 is separately formed and mounted on the first substrate 4001; however, the present invention is not limited to this structure.
  • the scan line driver circuit may be separately formed and mounted, or part of the signal line driver circuit or only part of the scan line driver circuit may be separately formed and mounted.
  • FIG. 25A shows an example of mounting the signal line driver circuit 4003 and the scanning line driver circuit 4004 by COG
  • FIG. 25B shows an example of mounting the signal line driver circuit 4003 by COG
  • (C) is an example in which the signal line driver circuit 4003 is mounted by TCP.
  • the display device may include a panel in which the display element is sealed and a module in which an IC or the like including a controller is mounted on the panel.
  • the pixel portion and the scan line driver circuit provided over the first substrate include a plurality of transistors, and the OS transistor described in the above embodiment can be applied.
  • FIG. 26A and FIG. 26B are cross-sectional views showing the cross-sectional configuration of the portion shown by the dashed line N1-N2 in FIG. 25B.
  • FIG. 26A illustrates an example of a liquid crystal display device using a liquid crystal element as a display element.
  • FIG. 26B is an example of a light-emitting display device (also referred to as “EL display device”) using a light-emitting element as a display element.
  • EL display device also referred to as “EL display device”
  • the display devices illustrated in FIGS. 26A and 26B each include an electrode 4015, and the electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive layer 4019.
  • the electrode 4015 is electrically connected to the wiring 4014 through an opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.
  • the electrode 4015 is formed of the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed of the same conductive layer as the source electrode and the drain electrode of the transistor 4010 and the transistor 4011.
  • the pixel portion 4002 and the scan line driver circuit 4004 which are provided over the first substrate 4001 have a plurality of transistors, and are included in the pixel portion 4002 in FIGS. 26A and 26B.
  • the transistor 4010 and the transistor 4011 included in the scan line driver circuit 4004 are illustrated.
  • An insulating layer 4112 is provided over the transistor 4010 and the transistor 4011 in FIG. 26A, and a partition 4510 is formed over the insulating layer 4112 in FIG. 26B.
  • the transistor 4010 and the transistor 4011 are provided over the insulating layer 4102.
  • the transistor 4010 and the transistor 4011 each have an electrode 4017 formed over the insulating layer 4103, and the insulating layer 4112 is formed over the electrode 4017.
  • the electrode 4017 can function as a back gate electrode.
  • the transistors described in the above embodiments can be used for the transistors 4010 and 4011.
  • An OS transistor is preferably used as the transistor 4010 and the transistor 4011.
  • the OS transistor has suppressed electrical characteristic fluctuation and is electrically stable. Therefore, the display device of this embodiment shown in FIGS. 26A and 26B can be a highly reliable display device.
  • the OS transistor can reduce the current value (off current value) in the off state. Therefore, the holding time of an electric signal such as an image signal can be extended, and the writing interval can be set long in the power on state. Thus, the frequency of the refresh operation can be reduced, which leads to an effect of suppressing power consumption.
  • the OS transistor can also obtain relatively high field effect mobility, it can be driven at high speed. Therefore, by using the OS transistor in the driver circuit portion or the pixel portion of the display device, a high quality image can be provided. In addition, since the driver circuit portion or the pixel portion can be separately manufactured over the same substrate, the number of components of the display device can be reduced.
  • the display devices illustrated in FIGS. 26A and 26B each include a capacitor 4020.
  • the capacitor 4020 includes an electrode 4021 formed in the same step as the gate electrode of the transistor 4010, and an electrode formed in the same step as the source electrode and the drain electrode.
  • the respective electrodes overlap with each other through the insulating layer 4103.
  • the capacitance of a capacitor provided in a pixel portion of a display device is set so as to hold charge for a predetermined period, in consideration of leakage current or the like of a transistor provided in the pixel portion.
  • the capacitance of the capacitor may be set in consideration of the off current of the transistor and the like.
  • the capacitance of the capacitor can be set to 1/3 or less, and further 1/5 or less of the liquid crystal capacitance.
  • formation of a capacitor can be omitted.
  • a liquid crystal element 4013 which is a display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008.
  • a liquid crystal layer 4030 includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008.
  • an insulating layer 4032 and an insulating layer 4033 which function as alignment films are provided so as to sandwich the liquid crystal layer 4008.
  • the second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other through the liquid crystal layer 4008.
  • the spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. There is. A spherical spacer may be used.
  • an optical member such as a black matrix (light shielding layer), a polarization member, a retardation member, an anti-reflection member, and the like may be provided as appropriate.
  • a polarization substrate and a retardation substrate may be used.
  • a backlight, a sidelight, or the like may be used as a light source.
  • the display devices illustrated in FIGS. 26A and 26B each include an insulating layer 4111 and an insulating layer 4104.
  • As the insulating layer 4111 and the insulating layer 4104 an insulating layer which hardly transmits an impurity element is used. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, entry of impurities from the outside can be prevented. Further, when the insulating layer 4111 and the insulating layer 4104 are in contact with each other on the outside of the pixel portion 4002, the effect of preventing entry of impurities from the outside can be enhanced.
  • the insulating layer 4104 may be formed using, for example, the same material and method as the insulating layer 210.
  • the insulating layer 4111 may be formed using, for example, the same material and method as the insulator 282.
  • a light-emitting element (also referred to as “EL element”) using electroluminescence can be applied.
  • An EL element has a layer containing a light-emitting compound (also referred to as “EL layer”) between a pair of electrodes.
  • EL layer a layer containing a light-emitting compound
  • EL elements are distinguished depending on whether the light emitting material is an organic compound or an inorganic compound, and in general, the former is called an organic EL element and the latter is called an inorganic EL element.
  • the organic EL element In the organic EL element, electrons are injected from one electrode and holes are injected from the other electrode to the EL layer by applying a voltage. Then, the carriers (electrons and holes) recombine to form an excited state of the light emitting organic compound, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light emitting element is referred to as a current excitation light emitting element.
  • the EL layer is a substance having a high hole injection property, a substance having a high hole transport property, a hole blocking material, a substance having a high electron transport property, a substance having a high electron injection property, or a bipolar other than a light emitting compound. It may have a polar substance (a substance having a high electron transporting property and a hole transporting property) or the like.
  • the EL layer can be formed by an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film-type inorganic EL element according to the element configuration.
  • the dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission utilizing a donor level and an acceptor level.
  • the thin film type inorganic EL element has a structure in which the light emitting layer is sandwiched by dielectric layers and further sandwiched by electrodes, and the light emission mechanism is localized light emission utilizing inner shell electron transition of metal ions.
  • an organic EL element is described as a light emitting element.
  • one of at least a pair of electrodes may be transparent in order to extract light emission.
  • a transistor and a light emitting element are formed over the substrate, and top emission (top emission) structure in which light emission is extracted from the surface opposite to the substrate, or bottom emission (bottom emission) structure in which light emission is extracted from the surface of the substrate.
  • top emission (top emission) structure in which light emission is extracted from the surface opposite to the substrate
  • bottom emission (bottom emission) structure in which light emission is extracted from the surface of the substrate
  • a light emitting element 4513 which is a display element is electrically connected to the transistor 4010 provided in the pixel portion 4002.
  • the structure of the light-emitting element 4513 is a stacked structure of the first electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031, but is not limited to this structure.
  • the structure of the light emitting element 4513 can be changed as appropriate in accordance with the direction of light extracted from the light emitting element 4513 or the like.
  • the partition 4510 is formed using an organic insulating material or an inorganic insulating material.
  • the light emitting layer 4511 may be composed of a single layer. Also, a plurality of layers may be stacked.
  • a protective layer may be formed over the second electrode layer 4031 and the partition 4510 so that oxygen, hydrogen, moisture, carbon dioxide, and the like do not enter the light-emitting element 4513.
  • the protective layer silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be formed.
  • a filler 4514 is provided in a space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005 and sealed.
  • a protective film such as a laminated film or an ultraviolet curable resin film
  • a cover material which has high airtightness and low degassing so as not to be exposed to the outside air.
  • an ultraviolet curable resin or a thermosetting resin in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) etc. can be used.
  • the filler 4514 may contain a desiccant.
  • sealant 4005 a glass material such as a glass frit, a cured resin such as a two-component mixed resin that cures at normal temperature, a photocurable resin, or a thermosetting resin can be used.
  • the sealant 4005 may contain a desiccant.
  • an optical film such as a polarizing plate or a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate ( ⁇ / 4 plate, ⁇ / 2 plate), or a color filter may be provided on the emission surface of the light emitting element. You may provide suitably.
  • an antireflective film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare processing can be performed to diffuse reflected light and reduce reflection due to the unevenness of the surface.
  • light with high color purity can be extracted by forming the light-emitting element with a microcavity structure.
  • reflection can be reduced, and the visibility of a display image can be enhanced.
  • first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, and the like) which apply voltage to the display element, the direction of light to be extracted, the location where the electrode layer is provided, and Translucency and reflectivity may be selected depending on the pattern structure of the electrode layer.
  • the first electrode layer 4030 and the second electrode layer 403 are indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium containing titanium oxide
  • a light-transmitting conductive material such as tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.
  • the first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta) , Chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), metals such as silver (Ag), or alloys thereof, or It can be formed using one or more of metal nitrides.
  • the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer).
  • a conductive high molecule also referred to as a conductive polymer.
  • a so-called ⁇ electron conjugated conductive high molecule can be used.
  • polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.
  • a protective circuit for protecting the driver circuit is preferably provided.
  • the protection circuit is preferably configured using a non-linear element.
  • a highly reliable display device can be provided.
  • the reliability of the display device can be further improved.
  • a high-definition and large-area display can be provided, and a display device with high display quality can be provided.
  • a display device with reduced power consumption can be provided.
  • a display module will be described as an example of a semiconductor device using the above-described OS transistor.
  • the display module 6000 shown in FIG. 27 includes a touch sensor 6004 connected to the FPC 6003 between the upper cover 6001 and the lower cover 6002, a display panel 6006 connected to the FPC 6005, a backlight unit 6007, a frame 6009, and a printed circuit board 6010. , Battery 6011. Note that the backlight unit 6007, the battery 6011, the touch sensor 6004, and the like may not be provided.
  • the semiconductor device of one embodiment of the present invention can be used for, for example, a touch sensor 6004, a display panel 6006, an integrated circuit mounted on a printed substrate 6010, or the like.
  • a touch sensor 6004 a display panel 6006, an integrated circuit mounted on a printed substrate 6010, or the like.
  • the display device described above can be used for the display panel 6006.
  • the shapes and dimensions of the upper cover 6001 and the lower cover 6002 can be appropriately changed in accordance with the size of the touch sensor 6004, the display panel 6006, and the like.
  • the touch sensor 6004 can overlap with a display panel 6006 using a resistive film capacitive touch sensor or a capacitance capacitive touch sensor. It is also possible to add a touch sensor function to the display panel 6006. For example, an electrode for a touch sensor may be provided in each pixel of the display panel 6006 to add a capacitive touch panel function. Alternatively, an optical sensor can be provided in each pixel of the display panel 6006 to add an optical touch sensor function or the like. In addition, when it is not necessary to provide the touch sensor 6004, the touch sensor 6004 can be omitted.
  • the backlight unit 6007 has a light source 6008.
  • the light source 6008 may be provided at an end of the backlight unit 6007 and a light diffusion plate may be used. In the case of using a light emitting display device or the like for the display panel 6006, the backlight unit 6007 can be omitted.
  • the frame 6009 has a function as an electromagnetic shield for blocking an electromagnetic wave generated from the printed circuit board 6010 as well as a protective function of the display panel 6006.
  • the frame 6009 may have a function as a heat sink.
  • the printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal, and a clock signal.
  • the power supply for supplying power to the power supply circuit may be a battery 6011 or a commercial power supply. When a commercial power source is used as the power source, the battery 6011 can be omitted.
  • members such as a polarizing plate, a retardation plate, and a prism sheet may be additionally provided in the display module 6000.
  • This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
  • FIG. 28 illustrates a specific example of an electronic device provided with a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention.
  • the GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices.
  • the electronic devices include, for example, television devices, desktop or notebook personal computers, monitors for computers, etc., large-sized game machines such as digital signage (Digital Signage), pachinko machines, etc.
  • digital signage Digital Signage
  • pachinko machines large-sized game machines
  • electronic devices equipped with screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound reproduction devices, etc. may be mentioned.
  • artificial intelligence can be mounted on an electronic device by providing the integrated circuit or the chip according to one embodiment of the present invention to the electronic device.
  • the electronic device of one embodiment of the present invention may have an antenna. By receiving the signal with the antenna, display of images, information, and the like can be performed on the display portion.
  • the antenna may be used for contactless power transmission.
  • the electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow, humidity, inclination, vibration, odor or infrared.
  • the electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function of displaying date or time, etc., a function of executing various software (programs), wireless communication A function, a function of reading a program or data recorded in a recording medium, or the like can be provided.
  • FIG. 28 shows an example of the electronic device.
  • FIG. 28A shows a mobile phone (smart phone) which is a type of information terminal.
  • the information terminal 5500 includes a housing 5510 and a display portion 5511.
  • a touch panel is provided in the display portion 5511 as an input interface, and a button is provided in the housing 5510.
  • the information terminal 5500 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • an application using artificial intelligence for example, an application that recognizes voice and displays the contents of conversation on the display unit 5511, recognizes characters, figures, and the like input by a user on a touch panel provided on the display unit 5511; An application displayed on the display portion 5511, an application for performing biometric authentication such as fingerprint or voiceprint, and the like can be given.
  • a desktop information terminal 5300 is illustrated in FIG.
  • the desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • applications using artificial intelligence include design support software, text correction software, and menu automatic generation software.
  • new artificial intelligence can be developed.
  • the artificial intelligence is applied to the information terminal other than the smartphone and the desktop information terminal.
  • an information terminal other than a smart phone and a desktop information terminal for example, a PDA (Personal Digital Assistant), a notebook information terminal, a work station, etc. may be mentioned.
  • PDA Personal Digital Assistant
  • FIG. 28C shows an electric refrigerator-freezer 5800 which is an example of the electric appliance.
  • the electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803 and the like.
  • an electric refrigerator-freezer 5800 having artificial intelligence can be realized.
  • the electric refrigerator-freezer 5800 is automatically stored in the electric refrigerator-freezer 5800, which automatically generates a menu based on the food stored in the electric refrigerator-freezer 5800, the expiration date of the food, etc. It can have a function of automatically adjusting to the temperature according to the food.
  • an electric refrigerator-freezer has been described as an electric appliance, but as another electric appliance, for example, a vacuum cleaner, an electronic oven, an electronic oven, a rice cooker, a water heater, an IH cooker, a water server, an air conditioner Air conditioners, washing machines, dryers, audio visual equipment, etc.
  • FIG. 28D illustrates a portable game console 5200 which is an example of the game console.
  • the portable game machine includes a housing 5201, a display portion 5202, a button 5203, and the like.
  • a low-power consumption portable game device 5200 can be realized. Further, since low power consumption can reduce heat generation from the circuit, it is possible to reduce the influence of heat generation on the circuit itself, peripheral circuits, and modules.
  • a portable game device 5200 having artificial intelligence can be realized.
  • expressions such as the progress of the game, the speech and behavior of characters appearing on the game, and the phenomena occurring on the game are determined by the program that the game has, but by applying artificial intelligence to the portable game machine 5200
  • the expression which is not limited to the program of the game becomes possible. For example, it is possible to express that the behavior of a character appearing on the game changes depending on the content the player asks, the progress of the game, and the time of day.
  • FIG. 28D illustrates a portable game console as an example of a game console; however, a game console to which the GPU or the chip of one embodiment of the present invention is applied is not limited to this.
  • a game machine to which the GPU or chip of one embodiment of the present invention is applied for example, a home-use stationary game machine, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), a sports facility Pitching machines for batting practice.
  • the GPU or chip of one embodiment of the present invention can be applied to an automobile that is a mobile body and the driver seat area of the automobile.
  • FIG. 28 (E1) shows a car 5700 which is an example of a moving body
  • FIG. 28 (E2) shows a periphery of a windshield in a room of the car.
  • FIG. 28E1 illustrates a display panel 5704 attached to a pillar, in addition to the display panel 5701 attached to a dashboard, the display panel 5702, and the display panel 5703.
  • the display panel 5701 to the display panel 5703 can provide various other information such as a speedometer, a tachometer, a travel distance, a fuel gauge, gear conditions, settings of an air conditioner, and the like.
  • display items, layouts, and the like displayed on the display panel can be appropriately changed in accordance with the user's preference, and design can be enhanced.
  • the display panels 5701 to 5703 can also be used as lighting devices.
  • the display panel 5704 By projecting an image from an imaging device (not shown) provided in the automobile 5700 on the display panel 5704, it is possible to complement the view (dead angle) blocked by the pillar. That is, by displaying an image from an imaging device provided outside the automobile 5700, a blind spot can be compensated to enhance safety. In addition, by displaying an image that complements the invisible part, it is possible to check the safety more naturally and without discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used for an autonomous driving system of a car 5700. Moreover, the said chip
  • a car is described as an example of a mobile body, but the mobile body is not limited to a car.
  • the moving object a train, a monorail, a ship, a flying object (a helicopter, a drone, a plane, a rocket) and the like can also be mentioned, and the chip of one embodiment of the present invention is applied to these moving objects.
  • a system using artificial intelligence can be provided.
  • the GPU or chip of one embodiment of the present invention can be applied to a broadcast system.
  • FIG. 28F schematically shows data transmission in the broadcast system. Specifically, FIG. 28F shows a path until the radio wave (broadcast signal) transmitted from the broadcast station 5680 reaches the television receiver (TV) 5600 of each home.
  • the TV 5600 includes a receiver (not shown), and the broadcast signal received by the antenna 5650 is transmitted to the TV 5600 through the receiver.
  • the antenna 5650 is a UHF (Ultra High Frequency) antenna.
  • a BS ⁇ 110 ° CS antenna, a CS antenna, or the like can be used as the antenna 5650.
  • the radio wave 5675A and the radio wave 5675B are broadcast signals for ground wave broadcasting, and the radio wave tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B.
  • Each household can view terrestrial TV broadcast on the TV 5600 by receiving the radio wave 5675 B by the antenna 5650.
  • the broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 28F, and may be satellite broadcasting using artificial satellites, data broadcasting by optical communication, or the like.
  • the above-described broadcast system may be a broadcast system using artificial intelligence by applying the chip of one embodiment of the present invention.
  • compression of the broadcast data is performed by the encoder, and when the antenna 5650 receives the broadcast data, the decoder of the receiving apparatus included in the TV 5600 Restoration is performed.
  • artificial intelligence for example, in motion compensation prediction which is one of compression methods of an encoder, it is possible to recognize a display pattern included in a display image.
  • intra-frame prediction using artificial intelligence can also be performed.
  • image interpolation processing such as up conversion can be performed in restoration of broadcast data by the decoder.
  • the above-described broadcast system using artificial intelligence is suitable for ultra high definition television (UHDTV: 4K, 8K) broadcast where the amount of broadcast data is increased.
  • the TV 5600 may be provided with a recording device having artificial intelligence.
  • a recording device having artificial intelligence it is possible to automatically record a program according to the user's preference by making the recording device learn the user's preference to the artificial intelligence.
  • the electronic device described in this embodiment the function of the electronic device, the application example of artificial intelligence, the effect thereof, and the like can be combined with the description of other electronic devices as appropriate.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Electroluminescent Light Sources (AREA)
  • Non-Volatile Memory (AREA)
PCT/IB2019/050375 2018-01-25 2019-01-17 半導体材料、および半導体装置 Ceased WO2019145827A1 (ja)

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US16/964,115 US12317600B2 (en) 2018-01-25 2019-01-17 Semiconductor material and semiconductor device
CN201980008397.XA CN111742408B (zh) 2018-01-25 2019-01-17 半导体材料及半导体装置
KR1020207021838A KR102912136B1 (ko) 2018-01-25 2019-01-17 반도체 재료 및 반도체 장치
JP2019567417A JP7202319B2 (ja) 2018-01-25 2019-01-17 半導体材料、および半導体装置
JP2022206199A JP7513694B2 (ja) 2018-01-25 2022-12-23 半導体装置
JP2024103524A JP7715884B2 (ja) 2018-01-25 2024-06-27 半導体装置

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CN111742408B (zh) 2024-05-28
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US20210036025A1 (en) 2021-02-04
CN111742408A (zh) 2020-10-02
KR102912136B1 (ko) 2026-01-14
JP7715884B2 (ja) 2025-07-30
JP2023026505A (ja) 2023-02-24
JP2024124441A (ja) 2024-09-12
JP7202319B2 (ja) 2023-01-11
JP7513694B2 (ja) 2024-07-09

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