WO2019129104A1 - 一种膜层套孔及阵列基板制备方法 - Google Patents

一种膜层套孔及阵列基板制备方法 Download PDF

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Publication number
WO2019129104A1
WO2019129104A1 PCT/CN2018/124050 CN2018124050W WO2019129104A1 WO 2019129104 A1 WO2019129104 A1 WO 2019129104A1 CN 2018124050 W CN2018124050 W CN 2018124050W WO 2019129104 A1 WO2019129104 A1 WO 2019129104A1
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Prior art keywords
layer
light absorbing
hole
photoresist
preparing
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PCT/CN2018/124050
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English (en)
French (fr)
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齐鹏博
陈叶凯
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武汉华星光电技术有限公司
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Publication of WO2019129104A1 publication Critical patent/WO2019129104A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70691—Handling of masks or workpieces
    • G03F7/70733—Handling masks and workpieces, e.g. exchange of workpiece or mask, transport of workpiece or mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to the field of display panel manufacturing, and in particular, to a film layer sleeve and an array substrate preparation method.
  • LTPS TFT low temperature polysilicon thin film transistor
  • a hole-punching process is often used, that is, after the preparation of the thin film transistor is completed, a planarization layer is prepared on the surface of the thin film transistor, and the layers after the planarization layer are all opened in the planarization layer. Make a set of holes on the basis.
  • the photoresist layer When making the hole, it is necessary to apply a photoresist layer on the surface of the layer above the planarization layer, and the photoresist layer fills the opening of the planarization layer, and when the hole is made, the exposed area of the photoresist is located in the opening of the planarization layer.
  • the sum of the height of the photoresist in the opening of the planarization layer and the height of the photoresist layer on the surface of the layer on the planarization layer is larger, and the thickness of the photoresist layer is larger, and the control precision of the exposure line width is higher. If it is low, it will cause unevenness in the line width of the sleeve, which will affect the quality of the array substrate.
  • the thickness of the photoresist layer in the exposed area is large, which may affect the control precision of the exposure line width, and the requirement of the uniformity of the line width of the hole cannot be achieved.
  • the invention provides a method for preparing a film layer sleeve, which can reduce the thickness of the photoresist layer in the exposed region when the film layer is formed, so as to solve the thickness of the photoresist layer in the exposed region when the film layer is formed in the prior art. Large, will affect the exposure line width control accuracy, can not achieve the need for the uniformity of the hole line width.
  • the invention provides a method for preparing a film sleeve, the method comprising the following steps:
  • the S40 includes:
  • a light absorbing layer is disposed in the first through hole; an upper surface of the light absorbing layer is flush with a surface of the second film layer outside the first through hole, or a height of an upper surface of the light absorbing layer exceeds a surface of the second film layer outside the first through hole;
  • a photoresist pattern is defined on a surface of the photoresist layer, and the photoresist pattern is correspondingly located above the light absorption layer;
  • the thickness of the photoresist layer is less than the thickness of the light absorbing layer.
  • the photoresist layer has a thickness of 1.5 um to 2.5 um.
  • the light absorbing layer is prepared using a light absorbing material having a high etching rate.
  • the light absorbing material is a deep ultraviolet light absorbing oxide.
  • the S403 includes: performing exposure processing on the photoresist layer using a photomask, and then performing development processing on the photoresist layer to obtain the photoresist pattern.
  • the invention also provides another method for preparing a film sleeve, the method comprising the following steps:
  • the S40 includes:
  • a photoresist pattern is defined on a surface of the photoresist layer, and the photoresist pattern is correspondingly located above the light absorption layer;
  • the thickness of the photoresist layer is less than the thickness of the light absorbing layer.
  • the photoresist layer has a thickness of 1.5 um to 2.5 um.
  • the light absorbing layer is prepared using a light absorbing material having a high etching rate.
  • the light absorbing material is a deep ultraviolet light absorbing oxide.
  • the S403 includes: performing exposure processing on the photoresist layer using a photomask, and then performing development processing on the photoresist layer to obtain the photoresist pattern.
  • a method for fabricating an array substrate comprising:
  • the S50 includes:
  • a photoresist pattern is defined on a surface of the photoresist layer, and the photoresist pattern is correspondingly located above the light absorbing layer;
  • the upper surface of the light absorbing layer is flush with the surface of the passivation layer outside the first through hole, or the upper surface of the light absorbing layer is higher than the first through hole The surface of the passivation layer.
  • the light absorbing layer is prepared using a light absorbing material having a high etching rate.
  • the invention has the beneficial effects that: when preparing the film sleeve hole, the base hole is filled into the substrate material before coating the photoresist layer, so as to prevent the photoresist material from being deposited in the base hole when the photoresist layer is coated
  • the thickness of the regional photoresist is large, so that the thickness of the photoresist layer can be reduced, thereby improving the precision of the control of the line width of the sleeve hole, and achieving the uniformity of the line width of the hole; to solve the problem of the exposed area in the prior art when making the hole of the film layer
  • the thickness of the photoresist layer is large, which will affect the accuracy of the exposure line width control, and the need for uniformity of the line width of the hole can not be achieved.
  • FIG. 1 is a flow chart of a method for preparing a film sleeve hole according to the present invention.
  • FIGS. 2a to 2e are schematic structural diagrams of a method for preparing a film layer hole according to the present invention.
  • FIG. 3 is a flow chart of a method for preparing an array substrate of the present invention.
  • 4a to 4e are schematic structural diagrams of a method for preparing an array substrate according to the present invention.
  • the invention is directed to the prior art manufacturing process of the film layer, the thickness of the photoresist layer in the exposed region is large, the control accuracy of the exposure line width is affected, and the technical problem of the uniformity of the hole width is not realized, and the embodiment can solve the problem.
  • the defect is directed to the prior art manufacturing process of the film layer, the thickness of the photoresist layer in the exposed region is large, the control accuracy of the exposure line width is affected, and the technical problem of the uniformity of the hole width is not realized, and the embodiment can solve the problem. The defect.
  • the present invention provides a method for preparing a film sleeve, the method comprising the following steps:
  • the metal layer is made of a material such as molybdenum, tantalum, aluminum or tungsten, and may be prepared by a sputtering process; for example, when the first film layer is a semiconductor layer,
  • the semiconductor layer is made of a material such as silicon oxide, silicon nitride or silicon oxynitride, and can be prepared by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition; for example, when the first film layer is a resin layer, It is prepared by a coating process.
  • PECVD plasma enhanced chemical vapor deposition
  • a second through hole is formed on a surface of the second film layer, the second through hole is located in the first through hole, and is connected to the substrate; the first through hole and the second through hole Filled with a metal material, the surface of the second film layer is prepared with a metal layer, the metal layer connecting the metal material in the first through hole and the second through hole, and thus the metal on the surface of the substrate Layer connectivity.
  • the substrate is only used as a substrate of the first film layer, and the substrate may be a functional film layer; for example, the substrate is an interlayer insulating layer of a thin film transistor, and the first film layer A planarization layer prepared on the surface of the interlayer insulating layer.
  • the first through hole penetrates the first film layer and is connected to the substrate.
  • the thickness of the second film layer is smaller than the thickness of the first film layer, and the second film layer is formed on the first film layer, the inner wall of the first through hole, and the first a through hole corresponding to the surface of the substrate.
  • the second through hole is formed in the first through hole, and the second through hole is formed in a region where the second film layer is connected to the substrate.
  • the S40 includes:
  • a light absorbing layer is disposed in the first through hole.
  • a photoresist pattern is defined on a surface of the photoresist layer, and the photoresist pattern is correspondingly located above the light absorption layer.
  • the S403 includes: performing exposure processing on the photoresist layer using a photomask, and then performing development processing on the photoresist layer to obtain the photoresist pattern.
  • a masking plate is used to deposit a certain height of the light absorbing material in the first through hole, thereby forming a light absorbing layer in the first through hole; when the photoresist layer is exposed, the light is irradiated. Passing through the photoresist layer and reaching the surface of the film layer under the exposed area of the photoresist layer, the light may be reflected on the surface of the film layer to cause repeated exposure to the photoresist layer.
  • the photoresist layer is double-exposed to affect the line width of the photoresist pattern.
  • the filling height of the light absorbing layer is not lower than the height of the second film layer outside the first through hole, for example, the upper surface of the light absorbing layer and the second film layer outside the first through hole
  • the upper surface is flush, or the upper surface height of the light absorbing layer exceeds the surface of the second film layer outside the first through hole, such that the photoresist layer corresponds to the thickness of the region of the light absorbing layer and other regions
  • the thickness is uniform, so as to reduce the thickness of the region of the photoresist layer corresponding to the light absorbing layer as much as possible, and to increase the exposure focus average value, and further improve the exposure line width control precision.
  • the light absorbing material of the light absorbing layer adopts DUO (DUV) with faster etching rate than photoresist.
  • Light Absorbing Oxide a material that can be removed with the photoresist layer in the subsequent stripping process of the photoresist layer.
  • the photoresist pattern After forming the photoresist pattern, the light absorbing layer and the second film layer are etched by the photoresist pattern to form the second via hole; finally, the photoresist layer and the light absorbing layer are removed Layer; complete the preparation of the membrane sleeve.
  • the thickness of the photoresist layer is smaller than the thickness of the light absorbing layer.
  • the thickness of the photoresist layer is reduced by increasing the thickness of the light absorbing layer.
  • the photoresist layer has a thickness of 1.5 um to 2.5 um.
  • a substrate 101 is prepared, and a surface of the substrate 101 is prepared with a first film layer 102.
  • the first film layer 102 is formed with a first through hole 103, a surface of the first film layer 102 and the surface.
  • a second film layer 104 is prepared in the first through hole 103.
  • a light absorbing layer 105 is disposed in the first through hole 103, and a photoresist layer 106 is prepared on the surface of the second film layer 104 and the surface of the light absorbing layer 105.
  • a photoresist pattern 108 is defined on the surface of the photoresist layer 106 by using a mask 107.
  • the light absorbing layer 105 and the second film layer 104 are etched by the photoresist pattern 108.
  • the light absorbing layer 105 and the photoresist layer 106 are removed to obtain a second via 109.
  • the present invention further provides a method for fabricating an array substrate, the method comprising:
  • the S50 includes:
  • a light absorbing layer is disposed in the first through hole.
  • a photoresist pattern is defined on a surface of the photoresist layer, and the photoresist pattern is correspondingly located above the light absorption layer.
  • the array substrate preparation process provided by the present invention includes:
  • a substrate 201 is formed.
  • a surface of the substrate 201 is provided with a thin film transistor layer 202.
  • a surface of the thin film transistor layer 202 is prepared with a planarization layer 203.
  • the planarization layer 203 is provided with a first via hole 204.
  • the surface of the planarization layer 203 outside the first via hole 204 is prepared with a transparent metal layer 205, and a passivation layer 206 is prepared in the surface of the transparent metal layer 205 and the first via hole 204.
  • a light absorbing layer 207 is disposed in the first through hole 204, and a photoresist layer 208 is prepared on the surface of the passivation layer 206 and the surface of the light absorbing layer 207.
  • a photoresist pattern 210 is defined on the surface of the photoresist layer 208 by using a mask 209.
  • the light absorbing layer 207 and the passivation layer 206 in the first via hole 204 are etched by the photoresist pattern 210.
  • the light absorbing layer 207 and the photoresist layer 208 are removed to obtain a second via hole 211.
  • the preparation principle of the method for preparing the array substrate of the preferred embodiment is the same as the preparation principle of the method for preparing the film layer hole of the preferred embodiment.
  • the preparation principle of the method for preparing the film sleeve hole of the above preferred embodiment I will not repeat them here.

Abstract

本发明提供一种膜层套孔制备方法，制备膜层套孔时，在涂布光阻层之前将基础孔填入衬底材料，以避免在涂布光阻层时，光阻材料沉积在基础孔内导致该区域光阻厚度较大，从而可减小光阻层厚度，进而提高套孔线宽控制精准性。

Description

一种膜层套孔及阵列基板制备方法 技术领域
本发明涉及显示面板制造领域，尤其涉及一种膜层套孔及阵列基板制备方法。
 背景技术
在LTPS TFT（低温多晶硅薄膜晶体管）工艺流程中，常使用套孔工艺方法，即薄膜晶体管制备完成后，在薄膜晶体管表面制备平坦化层，平坦化层之后的层别均在平坦化层开孔的基础上制作套孔。
在制作套孔时，需要在平坦化层之上的层别表面涂布光阻层，光阻层将填满平坦化层开孔，制作套孔时，光阻曝光区域位于平坦化层开孔上方，则所述平坦化层开孔内的光阻高度与所述平坦化层之上的层别表面的光阻层高度之和较大，光阻层厚度越大，曝光线宽控制精度越低，将会导致套孔线宽出现不均一现象，进而影响阵列基板的品质。
综上所述，现有技术中在制作膜层套孔时，曝光区域的光阻层厚度较大，会影响曝光线宽控制精度，不能实现套孔线宽均一性的需求。
 技术问题
本发明提供一种膜层套孔制备方法，能够减小制作膜层套孔时曝光区域的光阻层厚度，以解决现有技术在制作膜层套孔时，曝光区域的光阻层厚度较大，会影响曝光线宽控制精度，不能实现套孔线宽均一性的需求。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种膜层套孔制备方法，所述方法包括以下步骤：
S10，提供一基板；
S20，在所述基板表面制备第一膜层，并在所述第一膜层上形成第一通孔；
S30，在所述第一膜层表面和所述第一通孔内制备第二膜层；
S40，在所述第二膜层表面形成第二通孔，所述第二通孔位于所述第一通孔内，且连接所述基板；
其中，所述S40包括：
S401，在所述第一通孔内设置吸光层；所述吸光层的上表面与所述第一通孔外的所述第二膜层表面平齐，或者所述吸光层的上表面高度超过所述第一通孔外的所述第二膜层表面；
S402，在所述第二膜层表面和所述吸光层表面制备光阻层；
S403，在所述光阻层表面定义光阻图案，所述光阻图案对应位于所述吸光层上方；
S404，利用所述光阻图案对所述吸光层和所述第二膜层进行蚀刻，得到所述第二通孔；
S405，去除所述光阻层和所述吸光层。
根据本发明一优选实施例，所述光阻层的厚度小于所述吸光层的厚度。
根据本发明一优选实施例，所述光阻层的厚度为1.5um～2.5um。
根据本发明一优选实施例，所述吸光层采用具有高蚀刻率的吸光材料制备。
根据本发明一优选实施例，所述吸光材料为深紫外光吸光氧化物。
根据本发明一优选实施例，所述S403包括：使用光罩在所述光阻层上进行曝光处理，然后对所述光阻层进行显影处理，得到所述光阻图案。
本发明还提供另一种膜层套孔制备方法，所述方法包括以下步骤：
S10，提供一基板；
S20，在所述基板表面制备第一膜层，并在所述第一膜层上形成第一通孔；
S30，在所述第一膜层表面和所述第一通孔内制备第二膜层；
S40，在所述第二膜层表面形成第二通孔，所述第二通孔位于所述第一通孔内，且连接所述基板；
其中，所述S40包括：
S401，在所述第一通孔内设置吸光层；
S402，在所述第二膜层表面和所述吸光层表面制备光阻层；
S403，在所述光阻层表面定义光阻图案，所述光阻图案对应位于所述吸光层上方；
S404，利用所述光阻图案对所述吸光层和所述第二膜层进行蚀刻，得到所述第二通孔；
S405，去除所述光阻层和所述吸光层。
根据本发明一优选实施例，所述光阻层的厚度小于所述吸光层的厚度。
根据本发明一优选实施例，所述光阻层的厚度为1.5um～2.5um。
根据本发明一优选实施例，所述吸光层采用具有高蚀刻率的吸光材料制备。
根据本发明一优选实施例，所述吸光材料为深紫外光吸光氧化物。
根据本发明一优选实施例，所述S403包括：使用光罩在所述光阻层上进行曝光处理，然后对所述光阻层进行显影处理，得到所述光阻图案。
依据上述发明目的，提出一种阵列基板制备方法，所述方法包括：
S10，提供一基板，并在所述基板表面制备薄膜晶体管；
S20，在所述薄膜晶体管表面制备平坦化层，并在所述平坦化层表面开设第一通孔；
S30，在所述平坦化层表面制备透明金属层；
S40，在所述透明金属层表面与所述第一通孔内制备钝化层；
S50，在所述钝化层表面形成第二通孔，所述第二通孔位于所述第一通孔内，且连接所述薄膜晶体管；
其中，所述S50包括：
S501，在所述第一通孔内设置吸光层；
S502，在所述钝化层表面和所述吸光层表面制备光阻层；
S503，在所述光阻层表面定义光阻图案，所述光阻图案对应位于所述吸光层上方；
S504，利用所述光阻图案对所述吸光层和所述钝化层进行蚀刻，得到所述第二通孔；
S505，去除所述光阻层和所述吸光层。
根据本发明一优选实施例，所述吸光层的上表面与所述第一通孔外的所述钝化层表面平齐，或者所述吸光层的上表面高度超过所述第一通孔外的所述钝化层表面。
根据本发明一优选实施例，所述吸光层采用具有高蚀刻率的吸光材料制备。
 有益效果
本发明的有益效果为：制备膜层套孔时，在涂布光阻层之前将基础孔填入衬底材料，以避免在涂布光阻层时，光阻材料沉积在基础孔内导致该区域光阻厚度较大，从而可减小光阻层厚度，进而提高套孔线宽控制精准性，实现套孔线宽均一性；以解决现有技术在制作膜层套孔时，曝光区域的光阻层厚度较大，会影响曝光线宽控制精度，不能实现套孔线宽均一性的需求。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图
图1为本发明膜层套孔制备方法流程图。
图2a至2e为本发明膜层套孔制备方法流程结构示意图。
图3为本发明阵列基板制备方法流程图。
图4a至4e为本发明阵列基板制备方法流程结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的膜层套孔制作工艺，曝光区域的光阻层厚度较大，会影响曝光线宽控制精度，不能实现套孔线宽均一性的需求的技术问题，本实施例能够解决该缺陷。
如图1所示，本发明提供一种膜层套孔制备方法，所述方法包括以下步骤：
S10，提供一基板。
S20，采用溅射工艺、等离子增强化学气相沉积法（PECVD）或涂布工艺在所述基板表面制备第一膜层，并采用蚀刻工艺在所述第一膜层上形成第一通孔；例如，当所述第一膜层为金属层，所述金属层由钼、铌、铝或钨等材料构成，可采用溅射工艺制备；又如，当所述第一膜层为半导体层，所述半导体层由氧化硅、氮化硅、氮氧化硅等材质构成，可采用等离子增强化学气相沉积法（PECVD）或化学气相沉积法制备；又如，当所述第一膜层为树脂层，则采用涂布工艺制备。
S30，在所述第一膜层表面和所述第一通孔内制备第二膜层，根据所述第二膜层的材质选择对应的制备方式。
S40，在所述第二膜层表面形成第二通孔，所述第二通孔位于所述第一通孔内，且连接所述基板；所述第一通孔与所述第二通孔内填充有金属材料，所述第二膜层表面制备有金属层，所述金属层连接所述第一通孔与所述第二通孔内的金属材料，从而与位于所述基板表面的金属层连通。
在所述S10中，所述基板仅作为所述第一膜层的衬底，所述基板可以为功能膜层；例如，所述基板为薄膜晶体管的间绝缘层，则所述第一膜层为制备于所述间绝缘层表面的平坦化层。
在所述S20中，所述第一通孔贯穿所述第一膜层，与所述基板连接。
在所述S30中，所述第二膜层的厚度小于所述第一膜层的厚度，所述第二膜层形成在所述第一膜层、所述第一通孔内壁以及所述第一通孔对应的所述基板表面。
在所述S40中，所述第二通孔制备于所述第一通孔内，所述第二通孔形成于所述第二膜层连接所述基板的区域。
具体的，所述S40包括：
S401，在所述第一通孔内设置吸光层。
S402，在所述第二膜层表面和所述吸光层表面制备光阻层。
S403，在所述光阻层表面定义光阻图案，所述光阻图案对应位于所述吸光层上方。
所述S403包括：使用光罩在所述光阻层上进行曝光处理，然后对所述光阻层进行显影处理，得到所述光阻图案。
S404，利用所述光阻图案对所述吸光层和所述第二膜层进行蚀刻，得到所述第二通孔。
S405，去除所述光阻层和所述吸光层。
上述方案中，利用掩膜版，在所述第一通孔内沉积一定高度的吸光材料，进而在所述第一通孔内形成吸光层；当对所述光阻层进行曝光时，光照会穿过所述光阻层并到达所述光阻层曝光区域下方的膜层表面，受该膜层材质影响，光照可能在该膜层表面形成反光而造成对所述光阻层的重复曝光，进而影响对所述光阻层的曝光精度；在所述光阻层曝光区域的下方设置吸光层，光照穿过所述光阻层后被所述吸光层吸收，所述吸光层可避免光照穿过所述光阻层后反光，进而造成所述光阻层被二次曝光，影响光阻图案的线宽。
所述吸光层的填充高度不低于所述第一通孔外的所述第二膜层的高度，例如，所述吸光层的上表面与第一通孔外的所述第二膜层的上表面平齐，或者所述吸光层的上表面高度超过所述第一通孔外的所述第二膜层表面，使得所述光阻层对应于所述吸光层的区域的厚度与其他区域的厚度均匀，从而尽可能的减小所述光阻层对应于所述吸光层的区域的厚度，以及提高曝光对焦平均值，进一步提高曝光线宽控制精度。
优选的，所述吸光层的吸光材料采用蚀刻速率较光阻快的DUO（DUV Light Absorbing Oxide，深紫外光吸光氧化物）材料，其可以在后续光阻层的剥离工艺中随光阻层一起去除。
当形成所述光阻图案之后，利用所述光阻图案对所述吸光层及所述第二膜层进行蚀刻，以形成所述第二通孔；最后去除所述光阻层和所述吸光层；完成膜层套孔的制备。
优选的，所述光阻层的厚度小于所述吸光层的厚度。通过增加吸光层厚度，来减小光阻层厚度。
优选的，所述光阻层的厚度为1.5um～2.5um。
本发明提供的套孔制备流程包括：
如图2a所示，包括基板101，所述基板101表面制备有第一膜层102，所述第一膜层102上形成有第一通孔103，所述第一膜层102表面和所述第一通孔103内制备有第二膜层104。
如图2b所示，所述第一通孔103内设置有吸光层105，所述第二膜层104表面和所述吸光层105表面制备有光阻层106。
如图2c所示，利用掩膜版107，在所述光阻层106表面定义光阻图案108。
如图2d所示，利用所述光阻图案108对所述吸光层105及所述第二膜层104进行蚀刻。
如图2e所示，去除所述吸光层105及所述光阻层106，得到第二通孔109。
如图3所示，本发明还提出一种阵列基板制备方法，所述方法包括：
S10，提供一基板，并在所述基板表面制备薄膜晶体管。
S20，在所述薄膜晶体管表面制备平坦化层，并在所述平坦化层表面开设第一通孔。
S30，在所述平坦化层表面制备透明金属层。
S40，在所述透明金属层表面与所述第一通孔内制备钝化层。
S50，在所述钝化层表面形成第二通孔，所述第二通孔位于所述第一通孔内，且连接所述薄膜晶体管。
其中，所述S50包括：
S501，在所述第一通孔内设置吸光层。
S502，在所述钝化层表面和所述吸光层表面制备光阻层。
S503，在所述光阻层表面定义光阻图案，所述光阻图案对应位于所述吸光层上方。
S504，利用所述光阻图案对所述吸光层和所述钝化层进行蚀刻，得到所述第二通孔。
S505，去除所述光阻层和所述吸光层。
本发明提供的阵列基板制备流程包括：
如图4a所示，包括基板201，所述基板201表面制备有薄膜晶体管层202，所述薄膜晶体管层202表面制备有平坦化层203，所述平坦化层203表面开设有第一通孔204，所述第一通孔204之外的所述平坦化层203表面制备有透明金属层205，所述透明金属层205表面与所述第一通孔204内制备有钝化层206。
如图4b所示，所述第一通孔204内设置有吸光层207，所述钝化层206表面和所述吸光层207表面制备有光阻层208。
如图4c所示，利用掩膜版209，在所述光阻层208表面定义光阻图案210。
如图4d所示，利用所述光阻图案210对所述吸光层207及所述第一通孔204内的所述钝化层206进行蚀刻。
如图4e所示，去除所述吸光层207及所述光阻层208，得到第二通孔211。
本优选实施例阵列基板的制备方法的制备原理跟上述优选实施例的膜层套孔的制备方法的制备原理一致，具体可参考上述优选实施例的膜层套孔的制备方法的制备原理，此处不再做赘述。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (15)

  1. 一种膜层套孔制备方法，所述方法包括以下步骤：
    S10，提供一基板；
    S20，在所述基板表面制备第一膜层，并在所述第一膜层上形成第一通孔；
    S30，在所述第一膜层表面和所述第一通孔内制备第二膜层；
    S40，在所述第二膜层表面形成第二通孔，所述第二通孔位于所述第一通孔内，且连接所述基板；
    其中，所述S40包括：
    S401，在所述第一通孔内设置吸光层；所述吸光层的上表面与所述第一通孔外的所述第二膜层表面平齐，或者所述吸光层的上表面高度超过所述第一通孔外的所述第二膜层表面；
    S402，在所述第二膜层表面和所述吸光层表面制备光阻层；
    S403，在所述光阻层表面定义光阻图案，所述光阻图案对应位于所述吸光层上方；
    S404，利用所述光阻图案对所述吸光层和所述第二膜层进行蚀刻，得到所述第二通孔；
    S405，去除所述光阻层和所述吸光层。
  2. 根据权利要求1所述的方法，其中，所述光阻层的厚度小于所述吸光层的厚度。
  3. 根据权利要求2所述的方法，其中，所述光阻层的厚度为1.5um～2.5um。
  4. 根据权利要求1所述的方法，其中，所述吸光层采用具有高蚀刻率的吸光材料制备。
  5. 根据权利要求4所述的方法，其中，所述吸光材料为深紫外光吸光氧化物。
  6. 根据权利要求1所述的方法，其中，所述S403包括：使用光罩在所述光阻层上进行曝光处理，然后对所述光阻层进行显影处理，得到所述光阻图案。
  7. 一种膜层套孔制备方法，所述方法包括以下步骤：
    S10，提供一基板；
    S20，在所述基板表面制备第一膜层，并在所述第一膜层上形成第一通孔；
    S30，在所述第一膜层表面和所述第一通孔内制备第二膜层；
    S40，在所述第二膜层表面形成第二通孔，所述第二通孔位于所述第一通孔内，且连接所述基板；
    其中，所述S40包括：
    S401，在所述第一通孔内设置吸光层；
    S402，在所述第二膜层表面和所述吸光层表面制备光阻层；
    S403，在所述光阻层表面定义光阻图案，所述光阻图案对应位于所述吸光层上方；
    S404，利用所述光阻图案对所述吸光层和所述第二膜层进行蚀刻，得到所述第二通孔；
    S405，去除所述光阻层和所述吸光层。
  8. 根据权利要求7所述的方法，其中，所述光阻层的厚度小于所述吸光层的厚度。
  9. 根据权利要求8所述的方法，其中，所述光阻层的厚度为1.5um～2.5um。
  10. 根据权利要求7所述的方法，其中，所述吸光层采用具有高蚀刻率的吸光材料制备。
  11. 根据权利要求10所述的方法，其中，所述吸光材料为深紫外光吸光氧化物。
  12. 根据权利要求1所述的方法，其中，所述S403包括：使用光罩在所述光阻层上进行曝光处理，然后对所述光阻层进行显影处理，得到所述光阻图案。
  13. 一种阵列基板制备方法，所述方法包括：
    S10，提供一基板，并在所述基板表面制备薄膜晶体管；
    S20，在所述薄膜晶体管表面制备平坦化层，并在所述平坦化层表面开设第一通孔；
    S30，在所述平坦化层表面制备透明金属层；
    S40，在所述透明金属层表面与所述第一通孔内制备钝化层；
    S50，在所述钝化层表面形成第二通孔，所述第二通孔位于所述第一通孔内，且连接所述薄膜晶体管；
    其中，所述S50包括：
    S501，在所述第一通孔内设置吸光层；
    S502，在所述钝化层表面和所述吸光层表面制备光阻层；
    S503，在所述光阻层表面定义光阻图案，所述光阻图案对应位于所述吸光层上方；
    S504，利用所述光阻图案对所述吸光层和所述钝化层进行蚀刻，得到所述第二通孔；
    S505，去除所述光阻层和所述吸光层。
  14. 根据权利要求13所述的方法，其中，所述吸光层的上表面与所述第一通孔外的所述钝化层表面平齐，或者所述吸光层的上表面高度超过所述第一通孔外的所述钝化层表面。
  15. 根据权利要求13所述的方法，其中，所述吸光层采用具有高蚀刻率的吸光材料制备。
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