WO2019100412A1 - 阵列基板以及显示装置 - Google Patents

阵列基板以及显示装置 Download PDF

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Publication number
WO2019100412A1
WO2019100412A1 PCT/CN2017/113247 CN2017113247W WO2019100412A1 WO 2019100412 A1 WO2019100412 A1 WO 2019100412A1 CN 2017113247 W CN2017113247 W CN 2017113247W WO 2019100412 A1 WO2019100412 A1 WO 2019100412A1
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Prior art keywords
metal
signal transmission
transmission line
array substrate
thin film
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PCT/CN2017/113247
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English (en)
French (fr)
Inventor
赵瑜
金元仲
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武汉华星光电半导体显示技术有限公司
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Priority to US15/580,390 priority Critical patent/US10593660B2/en
Publication of WO2019100412A1 publication Critical patent/WO2019100412A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, and to a display device including the array substrate.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • a Thin Film Transistor (TFT) array substrate is an important component of a flat panel display device, and has a feature in which a matrix is arranged in a region surrounded by a plurality of data lines and a plurality of scanning lines that intersect each other.
  • a plurality of pixels having a liquid crystal capacitor and a thin film transistor for performing a display operation, the thin film transistor being turned on by a response gate voltage to load a data signal onto the pixel.
  • ESD electrostatic discharge
  • a grounding wire is designed on the periphery of the array substrate to discharge static electricity to the ground, usually by passing signal transmission lines (such as data lines and scanning lines) through static electricity.
  • the release element is connected to the ground wire.
  • a current limiting element such as a current limiting resistor to the signal transmission line.
  • the prior art is generally formed by patterning a semiconductor layer or a gate metal layer or other metal film layer on the array substrate.
  • the blocking is large, and a good current limiting effect can be achieved, but the semiconductor layer generally has poor heat dissipation performance, and the current limiting resistor is easily burned.
  • a current limiting resistor formed by patterning a gate metal layer or other metal film layer it has good heat dissipation performance, but due to metal The resistance is small and does not function to protect the large current.
  • the present invention provides an array substrate which can effectively prevent damage to devices such as signal transmission lines caused by large currents generated during electrostatic discharge.
  • An array substrate includes a peripheral circuit region including a first metal layer, a first insulating layer and a second metal layer sequentially formed on a base substrate, wherein a signal transmission line is disposed in the driving circuit region, Wherein the signal transmission line is connected in series with a finite flow unit, the current limiting unit comprising M first metal lines arranged in a spaced apart manner in the first metal layer and mutually formed in the second metal layer N strips of second metal lines, the M first metal lines and the N second metal lines are alternately connected in series by via holes provided in the first insulating layer; wherein, M And N are integers greater than one, respectively.
  • the length of the first metal wire is 5 to 10 ⁇ m, and the length of the second metal wire is 5 to 10 ⁇ m.
  • the distance between two adjacent first metal wires is 2 to 5 ⁇ m, and the length of two adjacent second metal wires is 2 to 5 ⁇ m.
  • the number M of the first metal wires is: 10 ⁇ M ⁇ 20, and the number N of the second metal wires is: 10 ⁇ N ⁇ 20.
  • the number M of the first metal lines and the number N of the second metal lines are equal, or the number M of the first metal lines is different from the number N of the second metal lines by one.
  • the signal transmission line is connected to an electrostatic discharge unit, and the electrostatic discharge unit includes an N-type thin film transistor and a P-type thin film transistor, and a source of the N-type thin film transistor and a source of the P-type thin film transistor are respectively connected to a first connection point on the signal transmission line, a gate and a drain of the N-type thin film transistor are connected to each other and connected to a first discharge connection line, and a gate and a drain of the P-type thin film transistor are connected and connected to each other Go to the second discharge connection line.
  • the electrostatic discharge unit includes an N-type thin film transistor and a P-type thin film transistor, and a source of the N-type thin film transistor and a source of the P-type thin film transistor are respectively connected to a first connection point on the signal transmission line, a gate and a drain of the N-type thin film transistor are connected to each other and connected to a first discharge connection line, and a gate and a drain of the P-type thin film transistor are connected and connected to each other
  • one of the current limiting units is connected in series on the signal transmission line on both sides of the first connection point.
  • the array substrate includes a display area, wherein the display area is provided with an array of pixel units, and the signal transmission line extends into the display area for inputting a display signal to the pixel unit;
  • the transmission line includes a data line and a scan line.
  • the signal transmission line is disposed in the first metal layer, or the signal transmission line is disposed in the second metal layer.
  • the present invention also provides a display device comprising the array substrate as described above.
  • An array substrate provided in an embodiment of the present invention is configured by forming a plurality of metal lines alternately in series in two metal layers to form an inductor element similar to a spiral winding as a current limiting unit connected in series on the signal transmission line. It has a sufficiently large resistance value and has good thermal conductivity, does not burn out due to thermal energy, and can effectively avoid damage to devices such as signal transmission lines caused by large current generated during electrostatic discharge. Further, the current limiting unit is formed as a structure of a spirally wound inductive component, and further has a function of a DC blocking AC and a low frequency blocking high frequency to better protect the circuit device on the array substrate.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is an equivalent circuit diagram of an electrostatic discharge unit connected to a signal transmission line in an embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional structural view of an array substrate in an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a current limiting unit in an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a display device according to an embodiment of the present invention.
  • FIG. 1 shows a layout structure of the array substrate.
  • the array substrate includes a display area 1 and a peripheral circuit area 2 located around the periphery of the display area 1.
  • the display area 1 is provided with a pixel unit arranged in an array and a signal transmission line 3 electrically connecting the pixel unit to the peripheral circuit area 2, the signal transmission line 3 including a data line Dx and a scan line Gx
  • the data line Dx and the scan line Gx are criss-crossed in the display area 1.
  • the thin film transistors are disposed in the pixel unit, and each of the thin film transistors is provided with a corresponding gate, a source and a drain, an insulating layer and an active layer.
  • the driving circuit area 2 is provided with a signal transmission line 3 extending from the display area 1, and the signal transmission line 3 (in FIG. 1 one of the scanning lines Gx is taken as an example)
  • An electrostatic discharge unit 4 is connected to the electrostatic discharge unit 4, and the electrostatic discharge unit 4 includes an N-type thin film transistor 41 and a P-type thin film transistor 42.
  • the source of the N-type thin film transistor 41 and the source of the P-type thin film transistor 42 are respectively Connected to the first connection point 3a on the signal transmission line 3, the gate and the drain of the N-type thin film transistor 41 are connected to each other and connected to the first discharge connection line 43, the gate of the P-type thin film transistor 42 The drain and the drain are connected to each other and to the second discharge connection line 44.
  • the electrostatic discharge unit 4 is configured to safely release static electricity accumulated on the signal transmission line 3, prevent static electricity from being input into the display area 1 along the signal transmission line 3, to the signal transmission line 3 itself, and Other devices in display area 1 caused damage.
  • the drive circuit region 2 is placed, and the signal transmission line 3 is connected in series with the constant current unit 5.
  • one of the current limiting units 5 is connected in series on the signal transmission line 3 on both sides of the first connection point 3a.
  • the array substrate includes a plurality of functional thin film layers disposed in sequence, specifically including a semiconductor layer 20, a second insulating layer 30, a first metal layer 40, and a first layer formed on the base substrate 10 in sequence.
  • the thin film transistor, the signal transmission line (data line and the scan line) in the display area 1, and the thin film transistor in the electrostatic discharge unit 4 are all formed in the above plurality of functional thin film layers by a patterning process.
  • the semiconductor layer 20 is used in a patterning process to form an active layer of a thin film transistor for patterning a gate electrode of the thin film transistor and a scan line, the second metal layer 60 A pattern is formed to form a source drain and a data line of the thin film transistor. Further, the current limiting unit 5 is also formed in the above plurality of functional film layers by a patterning process.
  • the material of the first metal layer 40 and the second metal layer 60 is a single metal layer of Cr, W, Ti, Ta, Mo, Al or Cu, or is Cr, W, Ti, Ta, Mo.
  • the material of the first insulating layer 50 and the second insulating layer 30 may be a single layer structure of SiO x or SiN x or a composite insulating layer composed of a combination of SiO x and SiN x .
  • the base substrate 10 may be a glass substrate, and the semiconductor layer 20 may be amorphous silicon (a-Si).
  • the current limiting unit 5 is formed in the first metal layer 40, the first insulating layer 50, and the second metal layer 60.
  • the current limiting unit 5 includes M first metal wires 41 arranged in the first metal layer 40 and spaced apart from each other and formed in the second metal layer 60 .
  • N second metal wires 61 spaced apart from each other, the M first metal wires 41 and the N second metal wires 61 are alternately arranged by the via holes 51 provided in the first insulating layer 50 Concatenated, where M and N are each an integer greater than one.
  • the number M of the first metal lines and the number N of the second metal lines are equal, or the number M of the first metal lines is different from the number N of the second metal lines by one.
  • the number M of the first metal lines and the number N of the second metal lines are specifically set according to actual needs. In a more preferred embodiment, the values of M and N are selected to be between 10 and 20.
  • the first metal layer 40 is provided with first to Mth first metal wires 41 spaced apart from each other, and the second metal layer 60 is provided with first to Nth second rows arranged at intervals
  • the metal wire 61 has a specific connection structure of the current limiting unit 5: one end of the first first metal wire 41 is connected to the signal transmission line 3, and the other end is connected to the first second metal wire through the via 51.
  • the other end of the first second metal wire 61 is connected to one end of the second first metal wire 41 through the via 51, and the other end of the second first metal wire 41 is reconnected through the via 51.
  • the length of the first metal wire 41 may be set to 5 to 10 ⁇ m
  • the length of the second metal wire 61 may be set to 5 to 10 ⁇ m
  • the length of 61 is approximately equal.
  • the pitch of the adjacent two first metal wires 41 may be set in the range of 2 to 5 ⁇ m
  • the pitch of the adjacent two of the second metal wires 61 is also set in the range of 2 to 5 ⁇ m.
  • an inductance element similar to a spiral winding is formed as a current limiting unit connected in series on the signal transmission line, which has a sufficiently large resistance. Value and good thermal conductivity, will not burn out due to thermal energy, can effectively Avoid large currents generated during electrostatic discharge to damage devices such as signal transmission lines.
  • the current limiting unit is formed as a structure of a spirally wound inductive component, and further has a function of a DC blocking AC and a low frequency blocking high frequency to better protect the circuit device on the array substrate.
  • the embodiment further provides a display device in which the array substrate provided by the embodiment of the present invention is used.
  • the display device can be, for example, a thin film transistor liquid crystal display device (TFT-LCD) or an organic electroluminescence display device (OLED).
  • TFT-LCD thin film transistor liquid crystal display device
  • OLED organic electroluminescence display device
  • the array substrate provided by the embodiment of the present invention can make the display device have more advantages than the prior art. Excellent electrostatic discharge performance and improved product quality.
  • the thin film transistor liquid crystal display device is taken as an example.
  • the liquid crystal display device includes a liquid crystal panel 100 and a backlight module 200 .
  • the liquid crystal panel 100 is disposed opposite to the backlight module 200 .
  • the display 200 provides a display light source to the liquid crystal panel 100 to cause the liquid crystal panel 100 to display an image.
  • the liquid crystal panel 100 includes an array substrate 101 and a filter substrate 102 disposed opposite to each other, and further includes a liquid crystal layer 103 between the array substrate 101 and

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板，包括外围电路区（2），外围电路区（2）包括依次形成于衬底基板上的第一金属层（40）、第一绝缘层（50）和第二金属层（60），外围电路区（2）中设置有信号传输线（3），其中，信号传输线（3）上串联有限流单元（5），限流单元（5）包括形成于第一金属层（40）中的相互间隔排列的M条第一金属线（41）以及形成于第二金属层（60）中的相互间隔排列的N条第二金属线（61），M条第一金属线（41）和N条第二金属线（61）通过设置在第一绝缘层（50）中的过孔（51）相互交替地依次串接；其中，M和N分别为大于1的整数。

Description

阵列基板以及显示装置 技术领域
本发明涉及显示器技术领域,尤其涉及一种阵列基板，还涉及包含所述阵列基板的显示装置。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。
薄膜晶体管(Thin Film Transistor，TFT)阵列基板是平板显示装置的重要组成部分，其具有如下特征：在由相互交叉的多条数据线和多条扫描线所围成的区域内排列有矩阵状的多个像素，像素具有进行显示操作的液晶电容器和薄膜晶体管，薄膜晶体管通过响应栅极电压而导通，以将数据信号加载到像素上。
在阵列基板的制作过程中，由于制作设备难免会与阵列基板相接触，一些静电将不可避免地产生并积累在阵列基板上。当静电积累到一定程度，在金属图形的尖端等静电比较容易积聚的部位引发静电放电(Electro-Static discharge，ESD)的现象，发生在金属导线部分容易导致传输导线的短路或断路，发生在显示区域容易导致薄膜晶体管击穿而失去原有的开关功能，影响产品的生产良率。
为了有效地将阵列基板中积累的静电进行释放，现有技术中，会在阵列基板的外围设计接地线，从而将静电对地放电，通常是将信号传输线(例如数据线和扫描线)通过静电释放元件连接到接地线。进一步地，为了避免在静电放电时产生的大电流对信号传输线的损坏，通常还需要在信号传输线上串联限流元件，例如限流电阻。对于所述限流电阻的设置，现有技术中通常是通过图案化阵列基板上的半导体层或栅极金属层或其他金属膜层形成。在使用半导体层图案化形成的限流电阻时，其阻止较大，可以起到良好的限流作用，但是半导体层通常散热性能较差，极易导致所述限流电阻烧毁。在使用栅极金属层或其他金属膜层图案化形成的限流电阻时，其具有较好的散热性能，但是由于金属 电阻较小而起不到防护大电流的作用。
因此，现有技术还有待于改进和发展。
发明内容
有鉴于此，本发明提供了一种阵列基板，其可以有效地避免在静电放电时产生的大电流对信号传输线等器件造成损坏。
为了实现上述的目的，本发明采用了如下的技术方案：
一种阵列基板，包括外围电路区，所述外围电路区包括依次形成于衬底基板上的第一金属层、第一绝缘层和第二金属层，所述驱动电路区中设置有信号传输线，其中，所述信号传输线上串联有限流单元，所述限流单元包括形成于所述第一金属层中的相互间隔排列的M条第一金属线以及形成于所述第二金属层中的相互间隔排列的N条第二金属线，所述M条第一金属线和所述N条第二金属线通过设置在所述第一绝缘层中的过孔相互交替地依次串接；其中，M和N分别为大于1的整数。
其中，所述第一金属线的长度为5～10μm，所述第二金属线的长度为5～10μm。
其中，相邻两条所述第一金属线的间距为2～5μm，相邻两条所述第二金属线的长度为2～5μm。
其中，所述第一金属线的数量M为：10≤M≤20，所述第二金属线的数量N为：10≤N≤20。
其中，所述第一金属线的数量M和所述第二金属线的数量N相等，或者是，所述第一金属线的数量M与所述第二金属线的数量N相差1。
其中，所述信号传输线连接有静电释放单元，所述静电释放单元包括N型薄膜晶体管和P型薄膜晶体管，所述N型薄膜晶体管的源极和所述P型薄膜晶体管的源极分别连接到所述信号传输线上的第一连接点，所述N型薄膜晶体管的栅极和漏极相互连接并连接到第一放电连接线，所述P型薄膜晶体管的栅极和漏极相互连接并连接到第二放电连接线。
其中，所述信号传输线上、位于所述第一连接点的两侧分别串联有一个所述限流单元。
其中，所述阵列基板包括显示区，所述显示区中设置有阵列排布的像素单元，所述信号传输线延伸至所述显示区中，用于向所述像素单元输入显示信号；所述信号传输线包括数据线和扫描线。
其中，所述信号传输线设置于所述第一金属层中，或者是，所述信号传输线设置于所述第二金属层中。
本发明还提供了一种显示装置，包括如上所述的阵列基板。
本发明实施例中提供的一种阵列基板，通过在两层金属层中设置多条金属线相互交替地依次串接，形成类似于螺旋绕线的电感元件作为串联在信号传输线上的限流单元，其具有足够大的电阻值并且具有良好的导热性能，不会因为热能而烧毁，可以有效地避免在静电放电时产生的大电流对信号传输线等器件造成损坏。进一步地，该限流单元形成为螺旋绕线的电感元件的结构，其还具有通直流阻交流、通低频阻高频的作用，更好地保护阵列基板上的电路器件。
附图说明
图1是本发明实施例提供的阵列基板的布局结构示意图；
图2是本发明实施例中静电释放单元与信号传输线连接的等效电路图；
图3是本发明实施例中的阵列基板的截面结构示意图；
图4是本发明实施例中的限流单元的结构示意图；
图5是本发明实施例提供的显示装置的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的，并且本发明并不限于这些实施方式。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。
本实施例提供了一种阵列基板，图1示出了所述阵列基板的布局结构示意 图，如图1所示，该阵列基板包括显示区1和位于所述显示区1周边的外围电路区2。其中，所述显示区1中设置有阵列排布的像素单元和将所述像素单元电性连接至所述外围电路区2的信号传输线3，所述信号传输线3包括数据线Dx和扫描线Gx，所述数据线Dx和扫描线Gx在所述显示区1中纵横交错。其中，所述像素单元中设置的薄膜晶体管，每个薄膜晶体管设置有相应的栅极、源漏极、绝缘层和有源层。
其中，参阅图1和图2，所述驱动电路区2中设置有从所述显示区1中延伸出来的信号传输线3，所述信号传输线3(图1中以其中的一条扫描线Gx为例)上连接有静电释放单元4，所述静电释放单元4包括N型薄膜晶体管41和P型薄膜晶体管42，所述N型薄膜晶体管41的源极和所述P型薄膜晶体管42的源极分别连接到所述信号传输线3上的第一连接点3a，所述N型薄膜晶体管41的栅极和漏极相互连接并连接到第一放电连接线43，所述P型薄膜晶体管42的栅极和漏极相互连接并连接到第二放电连接线44。所述静电释放单元4用于将积累在所述信号传输线3的静电进行安全释放，防止静电沿着所述信号传输线3输入到所述显示区1中、对所述信号传输线3本身以及所述显示区1中其他器件造成损坏。进一步地，为了避免在静电放电时产生的大电流对所述信号传输线3的损坏，位于所述驱动电路区2中，所述信号传输线3上串联有限流单元5。在本实施例中，所述信号传输线3上、位于所述第一连接点3a的两侧分别串联有一个所述限流单元5。
其中，如图3所示，所述阵列基板包括依次设置的多个功能薄膜层，具体包括依次形成在衬底基板10上的半导体层20、第二绝缘层30、第一金属层40、第一绝缘层50和第二金属层60。其中，所述显示区1中的薄膜晶体管、信号传输线(数据线和扫描线)以及所述静电释放单元4中的薄膜晶体管都是通过图案化工艺在以上多个功能薄膜层中形成的。例如，所述半导体层20用于图案化工艺形成薄膜晶体管的有源层，所述第一金属层40用于图案化形成所述薄膜晶体管的栅极以及扫描线，所述第二金属层60用于图案化形成所述薄膜晶体管的源漏极以及数据线。进一步地，所述限流单元5也是通过图案化工艺在以上多个功能薄膜层中形成的。
其中，所述第一金属层40和所述第二金属层60的材料为Cr、W、Ti、Ta、Mo、Al或Cu的单层金属层，或者是Cr、W、Ti、Ta、Mo、Al和Cu中的任意两种或两种以上的金属组合构成的复合金属层。所述第一绝缘层50和所述第二 绝缘层30的材料可以为SiOx或SiNx的单层结构，或者是有SiOx和SiNx的组合构成的复合绝缘层。所述衬底基板10可以采用玻璃基板，所述半导体层20可以采用非晶硅(a-Si)。
在本实施例中，所述限流单元5是形成在所述第一金属层40、第一绝缘层50和第二金属层60中。具体地，如图4所示，所述限流单元5包括形成于所述第一金属层40中的相互间隔排列的M条第一金属线41以及形成于所述第二金属层60中的相互间隔排列的N条第二金属线61，所述M条第一金属线41和所述N条第二金属线61通过设置在所述第一绝缘层50中的过孔51相互交替地依次串接，其中，M和N分别为大于1的整数。
其中，所述第一金属线的数量M和所述第二金属线的数量N相等，或者是，所述第一金属线的数量M与所述第二金属线的数量N相差1。其中，所述第一金属线的数量M和所述第二金属线的数量N根据实际需要具体设定。在较为优选的技术方案中，M和N选择的数值范围是10～20之间。
参阅图4，以M＝N+1为例，即，所述第一金属线的数量M比所述第二金属线的数量N多一条。其中，所述第一金属层40中设置有相互间隔排列的第1至第M条第一金属线41，所述第二金属层60中设置有相互间隔排列的第1至第N条第二金属线61，则所述限流单元5的具体连接结构为：第1条第一金属线41的一端连接至所述信号传输线3，另一端通过过孔51连接至第1条第二金属线61的一端，第1条第二金属线61的另一端则通过过孔51连接至第2条第一金属线41的一端，第2条第一金属线41的另一端通过过孔51再连接至第2条第二金属线61的一端，以此类推，直至第N条第二金属线61的通过过孔51连接至第M条第一金属线41的一端，最后第M条第一金属线41的另一端再连接至信号传输线3，由此获得一个类似于螺旋绕线电感的限流单元5串联在所述信号传输线3上。
其中，所述第一金属线41的长度可以设置为5～10μm，所述第二金属线61的长度可以设置为5～10μm，所述第一金属线41的长度和所述第二金属线61的长度大致相等。相邻两条所述第一金属线41的间距可以设置在2～5μm的范围内，相邻两条所述第二金属线61的间距也是设置在2～5μm的范围内。
以上实施例中，通过在两层金属层中设置多条金属线相互交替地依次串接，形成类似于螺旋绕线的电感元件作为串联在信号传输线上的限流单元，其具有足够大的电阻值并且具有良好的导热性能，不会因为热能而烧毁，可以有效地 避免在静电放电时产生的大电流对信号传输线等器件造成损坏。进一步地，该限流单元形成为螺旋绕线的电感元件的结构，其还具有通直流阻交流、通低频阻高频的作用，更好地保护阵列基板上的电路器件。
本实施例还提供了一种显示装置，其中采用了本发明实施例提供的阵列基板。该显示装置例如可以是薄膜晶体管液晶显示装置(TFT-LCD)或有机电致发光显示装置(OLED)，采用了本发明实施例提供的阵列基板，可以使得显示装置相比于现有技术具有更优的静电释放性能，提高产品品质。具体地，以薄膜晶体管液晶显示装置为例，参阅图5，该液晶显示装置包括液晶面板100及背光模组200，所述液晶面板100与所述背光模组200相对设置，所述背光模组200提供显示光源给所述液晶面板100，以使所述液晶面板100显示影像。其中，液晶面板100包括相对设置的阵列基板101和滤光基板102，还包括位于阵列基板101和滤光基板102之间的液晶层103。其中，阵列基板101即采用了本发明实施例提供的阵列基板。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (20)

  1. 一种阵列基板，包括外围电路区，所述外围电路区包括依次形成于衬底基板上的第一金属层、第一绝缘层和第二金属层，所述驱动电路区中设置有信号传输线，其中，所述信号传输线上串联有限流单元，所述限流单元包括形成于所述第一金属层中的相互间隔排列的M条第一金属线以及形成于所述第二金属层中的相互间隔排列的N条第二金属线，所述M条第一金属线和所述N条第二金属线通过设置在所述第一绝缘层中的过孔相互交替地依次串接；其中，M和N分别为大于1的整数。
  2. 根据权利要求1所述的阵列基板，其中，所述第一金属线的长度为5～10μm，所述第二金属线的长度为5～10μm。
  3. 根据权利要求2所述的阵列基板，其中，相邻两条所述第一金属线的间距为2～5μm，相邻两条所述第二金属线的长度为2～5μm。
  4. 根据权利要求1所述的阵列基板，其中，所述第一金属线的数量M为：10≤M≤20，所述第二金属线的数量N为：10≤N≤20。
  5. 根据权利要求4所述的阵列基板，其中，所述第一金属线的数量M和所述第二金属线的数量N相等，或者是，所述第一金属线的数量M与所述第二金属线的数量N相差1。
  6. 根据权利要求1所述的阵列基板，其中，所述信号传输线连接有静电释放单元，所述静电释放单元包括N型薄膜晶体管和P型薄膜晶体管，所述N型薄膜晶体管的源极和所述P型薄膜晶体管的源极分别连接到所述信号传输线上的第一连接点，所述N型薄膜晶体管的栅极和漏极相互连接并连接到第一放电连接线，所述P型薄膜晶体管的栅极和漏极相互连接并连接到第二放电连接线。
  7. 根据权利要求6所述的阵列基板，其中，所述信号传输线上、位于所述第一连接点的两侧分别串联有一个所述限流单元。
  8. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括显示区，所述显示区中设置有阵列排布的像素单元，所述信号传输线延伸至所述显示区中，用于向所述像素单元输入显示信号；所述信号传输线包括数据线和扫描线。
  9. 根据权利要求1所述的阵列基板，其中，所述信号传输线设置于所述第 一金属层中。
  10. 根据权利要求1所述的阵列基板，其中，所述信号传输线设置于所述第二金属层中。
  11. 一种显示装置，包括阵列基板，所述阵列基板包括外围电路区，所述外围电路区包括依次形成于衬底基板上的第一金属层、第一绝缘层和第二金属层，所述驱动电路区中设置有信号传输线，其中，所述信号传输线上串联有限流单元，所述限流单元包括形成于所述第一金属层中的相互间隔排列的M条第一金属线以及形成于所述第二金属层中的相互间隔排列的N条第二金属线，所述M条第一金属线和所述N条第二金属线通过设置在所述第一绝缘层中的过孔相互交替地依次串接；其中，M和N分别为大于1的整数。
  12. 根据权利要求11所述的显示装置，其中，所述第一金属线的长度为5～10μm，所述第二金属线的长度为5～10μm。
  13. 根据权利要求12所述的显示装置，其中，相邻两条所述第一金属线的间距为2～5μm，相邻两条所述第二金属线的长度为2～5μm。
  14. 根据权利要求11所述的显示装置，其中，所述第一金属线的数量M为：10≤M≤20，所述第二金属线的数量N为：10≤N≤20。
  15. 根据权利要求14所述的显示装置，其中，所述第一金属线的数量M和所述第二金属线的数量N相等，或者是，所述第一金属线的数量M与所述第二金属线的数量N相差1。
  16. 根据权利要求11所述的显示装置，其中，所述信号传输线连接有静电释放单元，所述静电释放单元包括N型薄膜晶体管和P型薄膜晶体管，所述N型薄膜晶体管的源极和所述P型薄膜晶体管的源极分别连接到所述信号传输线上的第一连接点，所述N型薄膜晶体管的栅极和漏极相互连接并连接到第一放电连接线，所述P型薄膜晶体管的栅极和漏极相互连接并连接到第二放电连接线。
  17. 根据权利要求16所述的显示装置，其中，所述信号传输线上、位于所述第一连接点的两侧分别串联有一个所述限流单元。
  18. 根据权利要求11所述的显示装置，其中，所述阵列基板包括显示区，所述显示区中设置有阵列排布的像素单元，所述信号传输线延伸至所述显示区 中，用于向所述像素单元输入显示信号；所述信号传输线包括数据线和扫描线。
  19. 根据权利要求11所述的显示装置，其中，所述信号传输线设置于所述第一金属层中。
  20. 根据权利要求11所述的显示装置，其中，所述信号传输线设置于所述第二金属层中。
PCT/CN2017/113247 2017-11-21 2017-11-28 阵列基板以及显示装置 WO2019100412A1 (zh)

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