WO2019085949A1 - 基板、面板、检测装置以及对准检测方法 - Google Patents

基板、面板、检测装置以及对准检测方法 Download PDF

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Publication number
WO2019085949A1
WO2019085949A1 PCT/CN2018/113080 CN2018113080W WO2019085949A1 WO 2019085949 A1 WO2019085949 A1 WO 2019085949A1 CN 2018113080 W CN2018113080 W CN 2018113080W WO 2019085949 A1 WO2019085949 A1 WO 2019085949A1
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WIPO (PCT)
Prior art keywords
pin
alignment
signal connection
pins
signal
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Application number
PCT/CN2018/113080
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English (en)
French (fr)
Inventor
赵普查
张国庆
白晓鹏
王伟峰
党延斌
郭志鑫
王星亮
陈浩田
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/466,328 priority Critical patent/US11232727B2/en
Publication of WO2019085949A1 publication Critical patent/WO2019085949A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • Embodiments of the present disclosure relate to a substrate, a panel, a detecting device, and an alignment detecting method.
  • the display panel or the substrate (including the mother board) in the preparation process is usually tested by a detecting device, and in this stage, whether the display panel or the substrate in the preparation process is broken can be detected. , such as a bad point, for example, this phenomenon can lead to defects such as bright spots or dark spots.
  • the lighting test phase is very important for the control of the display panel or substrate quality.
  • At least one embodiment of the present disclosure provides a substrate including: a plurality of first signal connection pins disposed side by side in parallel and at least one first alignment detection pin; at least one first alignment detection pin is located at the plurality of At least one side of the first signal connection pins in the direction in which they are arranged is arranged in parallel with the first signal connection pins.
  • the substrate provided by at least one embodiment of the present disclosure further includes a working area, the working area is provided with a plurality of signal lines arranged in parallel with each other; each of the first signal connection pins has a first end and a second end, A first end of each of the first signal connection pins is electrically coupled to one of the signal lines.
  • the number of the first alignment detecting pins located on each side of the plurality of first signal connection pins is 1.
  • the first alignment detecting pin is suspended.
  • the conductivity of the material of the first alignment detecting pin is greater than the conductivity of the material of the first signal connection pin.
  • At least one embodiment of the present disclosure also provides a panel comprising the substrate of any of the above.
  • At least one embodiment of the present disclosure further provides a detecting apparatus including a plurality of second signal connection pins and a plurality of second alignment detection pins arranged side by side in parallel; a plurality of second alignment detection pins are located in the At least one side of the plurality of second signal connection pins in the direction in which they are arranged is disposed in parallel with the second signal connection pin.
  • the detecting apparatus further includes a testing circuit and a matching circuit.
  • Each of the second signal connection pins has a first end and a second end, and the test circuit is electrically connected to the first end of the second signal connection pin and sends a test for the second signal connection pin a signal; a bit circuit electrically connected to the second bit detection pin and transmitting a bit signal for the second bit detection pin and receiving a bit detection result signal from the second bit detection pin .
  • the second signal connection pin is configured to receive a detection signal from the test circuit
  • the second alignment detection pin is configured to receive from the The alignment signal of the bit circuit and the back detection result signal are returned.
  • the detecting device provided by at least one embodiment of the present disclosure further includes a control device, wherein the control device is configured to control opening and closing of the test circuit and the matching circuit, and control the test circuit to
  • the second signal connection pin issues a test signal and controls the alignment circuit to issue a registration signal to the second parity detection pin.
  • the number of the second alignment detecting pins located on each side of the plurality of second signal connection pins is 3;
  • the second alignment detecting pin in the middle of the one side of the second alignment detecting pin is configured to receive a registration signal from the alignment circuit, and correspondingly located in the middle
  • the second parity detecting pin on both sides of the second parity detecting pin is used to transmit a registration detection result signal.
  • the number of the second alignment detecting pins on each side of the two sides of the second signal connection pin is 2; Two of the second bit detection pins of the second signal connection pin are for receiving a registration signal from the alignment circuit, and correspondingly, two of the second signal connection pins away from the second signal connection pin a second bit detection pin is configured to transmit a bit detection result signal; or two of the second bit detection pins remote from the second signal connection pin are used to receive a bit alignment from the bit circuit The signal, correspondingly, the two second alignment detection pins adjacent to the second signal connection pin are used to transmit a registration detection result signal.
  • the conductivity of the material of the second alignment detecting pin is greater than the conductivity of the material of the second signal connecting pin.
  • At least one embodiment of the present disclosure further provides an alignment detecting method, the method comprising: providing the substrate to be tested provided by any one of the above embodiments of the present disclosure; providing the detecting device provided by any of the above embodiments of the present disclosure; The measuring substrate and the detecting device are in contact with each other to electrically connect the plurality of first signal connecting pins on the substrate to be tested and the plurality of second signal connecting pins on the detecting device in a one-to-one correspondence And electrically connecting each of the first bit detection pins to at least one of the second bit detection pins; before applying a detection signal to a plurality of the second signal connection pins
  • the two-bit detection pin inputs a registration signal, and performs bit detection to detect whether the plurality of first signal connection pins and the plurality of second signal connection pins are aligned accurately.
  • a plurality of the second alignment detecting pins are equally spaced and have a first spacing between adjacent second alignment detecting pins. At least one of the first alignment detection pins has a width greater than the first pitch.
  • a plurality of the first signal connection pins are periodically arranged and a second pitch is adjacent between the adjacent first signal connection pins.
  • the plurality of second signal connection pins are periodically arranged and the adjacent second signal connection pins have a third pitch, the second pitch being equal to the third pitch;
  • the first bit detection pin and the second bit detection pin adjacent thereto have a fourth a pitch; the fourth pitch is less than or equal to the second pitch.
  • the first alignment detecting pins located on each side of the plurality of first signal connection pins in the arrangement direction thereof The number is 1, and the number of the second alignment detecting pins on each side of the plurality of second signal connection pins is 3; wherein, the plurality of second signal connections are located Of the three of the second bit detection pins on each side of the pin, the first bit detection pin is electrically connected to the second bit detection pin located in the middle, in the middle Determining that there is no feedback of the alignment detection result signal on the second parity detecting pin on both sides of the second parity detecting pin, determining that the plurality of first signal connecting pins are connected to the plurality of second signals Pin alignment is accurate;
  • the first alignment detection pin is in the middle of the middle
  • the second alignment detecting pin is electrically connected, and is also electrically connected to one of the second alignment detecting pins on both sides of the second alignment detecting pin located in the middle, the two sides of the The one of the second bit detection pins feeds back the bit detection result signal, and determines that the plurality of first signal connection pins are inaccurately aligned with the plurality of second signal connection pins.
  • the first alignment detection lead on each side of the plurality of first signal connection pins on both sides in the arrangement direction thereof The number of the legs is 1, and the number of the second alignment detecting pins on each side of the second signal connection pin on both sides in the arrangement direction thereof is 2;
  • the second alignment detection pin adjacent to the second signal connection pin is located in two of the second alignment detection pins located on each side of the plurality of second signal connection pins
  • the pin is electrically connected to the first parity detecting pin, and the second alignment detecting pin away from the second signal connecting pin has no feedback of the alignment detection result signal, thereby determining the plurality of a signal connection pin is aligned with the plurality of second signal connection pins;
  • the two second bit detection pins of one of the two sides of the second signal connection pin are electrically connected to the first parity detection pin, away from the second signal connection. Determining the alignment detection result signal by one of the two second alignment detection pins of the pin, determining that the alignment of the plurality of first signal connection pins and the plurality of second signal connection pins is inaccurate ;
  • the two second bit detection pins away from the second signal connection pin are electrically connected to the first parity detection pin, and the two are close to the second signal connection pin. Determining the feedback of the bit detection result signal on the second bit detection pin, determining that the plurality of first signal connection pins are aligned with the plurality of second signal connection pins;
  • the two second alignment detection pins on the same side of the second signal connection pin are electrically connected to the first alignment detection pin, and close to the second signal connection pin.
  • One of the two second bit detection pins feeds back the bit detection result signal, and then determines that the plurality of first signal connection pins and the plurality of second signal connection pins are inaccurately aligned.
  • the alignment detection result signal is an electrical signal.
  • the electrical signal is a current.
  • FIG. 1 is a schematic diagram of a detecting device connected to a substrate signal to detect a substrate
  • FIG. 2A is a schematic plan view showing a planar structure of a substrate according to an embodiment of the present disclosure
  • 2B is a schematic plan view showing another substrate according to an embodiment of the present disclosure.
  • 3A is a schematic plan view showing a structure of a detecting device according to an embodiment of the present disclosure
  • FIG. 3B is a schematic structural diagram of another detecting device according to an embodiment of the present disclosure.
  • FIG. 3C is a schematic structural diagram of still another detecting apparatus according to an embodiment of the present disclosure.
  • FIGS. 4A-4C are schematic diagrams of an alignment detection method according to an embodiment of the present disclosure.
  • 5A-5C are schematic diagrams of another alignment detecting method according to an embodiment of the present disclosure.
  • 6A-6C are schematic diagrams showing still another alignment detecting method according to an embodiment of the present disclosure.
  • FIGS. 7A-7C are schematic diagrams of still another alignment detecting method according to an embodiment of the present disclosure.
  • Figure 8 is a partially enlarged schematic view of the signal connection area of Figure 4B;
  • FIG. 9 is a partially enlarged schematic view of the alignment detecting area in FIG. 4B.
  • both sides of the plurality of first signal connection pins in the embodiment of the present disclosure refer to two sides of the plurality of first signal connection pins in the arrangement direction thereof; the plurality of first signals Each side of the connection pin refers to each side of the plurality of first signal connection pins in the direction in which they are arranged; the width and the pitch mentioned in the embodiments of the present disclosure refer to the direction of the plurality of pins The width and spacing on the top.
  • the display substrate including the display mother board
  • the display panel itself included in the display panel is usually tested by the detecting device to detect whether the display substrate or the display panel is broken or broken. Dots, etc., such as defects that result in bright or dark spots.
  • FIG. 1 is a schematic diagram of a detecting device that is in signal connection with a substrate to detect the substrate.
  • the detecting device 24 is provided with a plurality of second signal connecting pins 21, and the substrate 25 is provided with a plurality of first signal connecting pins 22.
  • a plurality of signal lines are further disposed on the substrate 25 for controlling the operating states of the respective working units of the substrate 25.
  • the first signal connection pin 22 is electrically connected in one-to-one correspondence with the signal line on the substrate 25.
  • the second signal connection pin 21 needs to be electrically connected to the first signal connection pin 22 in one-to-one correspondence.
  • the second signal connection pin 21 receives an electrical signal from the detection device 24 that is conducted to the signal line on the substrate 25 via the first signal connection pin 22 on the substrate 25.
  • the substrate 25 can be located in a panel, the panel can also include a backlight, the backlight is illuminated, and the panel is illuminated.
  • the panel does not require a backlight, for example, an external light source located outside the panel, or each of the working units in the panel is provided with a light-emitting element that controls the light-emitting state of the light-emitting element.
  • the signal line control panel on the substrate it is possible to detect the illumination of the panel, for example, to detect the presence or absence of bright spots or dark spots, thereby detecting whether each signal line is malfunctioning.
  • misalignment may cause adjacent signal lines to be electrically connected through the second signal connection pin 21 to cause a short circuit.
  • the signal line, the second signal connection pin 21 and the first signal connection pin 22 have a small width dimension and the adjacent second signal connection pin 21 and the adjacent first
  • the spacing between the signal connection pins 22 is small, for example, the width of the signal line, the first signal connection pin, and the second signal connection pin, and the adjacent first signal connection pin and the adjacent second signal
  • the spacing between the connection pins can reach the micron level, for example, 60 to 80 ⁇ m, and the above-mentioned short circuit problem caused by the misalignment is more likely to occur.
  • At least one embodiment of the present disclosure provides a substrate including: a plurality of first signal connection pins and at least one first alignment detection pin disposed side by side in parallel.
  • the at least one first bit detection pin is located on at least one side of the plurality of first signal connection pins in the direction in which they are arranged, and is disposed in parallel with the first signal connection pin.
  • At least one embodiment of the present disclosure provides a panel including the substrate provided by any of the above embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a detecting apparatus including a plurality of second signal connection pins and a plurality of second alignment detection pins arranged side by side in parallel, and a plurality of second alignment detection pins are located in the plurality of At least one side of the second signal connection pin in the direction in which it is arranged is disposed in parallel with the second signal connection pin.
  • At least one embodiment of the present disclosure further provides an alignment detecting method, the method comprising: providing a substrate provided by an embodiment of the present disclosure; providing a detecting device provided by an embodiment of the present disclosure; contacting the substrate and the detecting device with each other for And connecting a plurality of first signal connection pins on the substrate to the plurality of second signal connection pins of the detecting device in a one-to-one correspondence, and electrically connecting each of the first alignment detection pins and the at least one second pair
  • the bit detection pin is electrically connected; before the detection signal is applied to the second signal connection pin, the registration signal is input to the second parity detection pin, and the bit detection is performed to detect the plurality of first signal connection pins and Whether the second signal connection pin is aligned correctly.
  • FIG. 2A is a schematic structural diagram of a substrate according to an embodiment of the present disclosure
  • FIG. 2B is a schematic structural diagram of another substrate according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a substrate including a plurality of first signal connection pins arranged in parallel and at least one first alignment detection pin, at least one first alignment detection pin being located in a plurality of first signals At least one side of the connection pin in the direction in which it is arranged is arranged in parallel with the first signal connection pin.
  • the substrate 9 includes a base substrate 7, a plurality of first signal connection pins 101 and a first alignment detection pin 1201 disposed in parallel on the base substrate 7.
  • the plurality of first signal connection pins 101 may be equally spaced, for example, the spacing between adjacent two first signal connection pins 101 is the second pitch L2.
  • the first alignment detecting pin 1201 and the first alignment detecting pin 1202 may be respectively located on both sides of the plurality of first signal connection pins 101 in the arrangement direction thereof.
  • the first parity detecting pin 1201 and the first alignment detecting pin 1202 are arranged in parallel with the plurality of first signal connection pins 101.
  • Each of the first signal connection pins 101 has a first end and a second end opposite to the first end, the first end is for signal connection with the working area 16 of the substrate 9, and the second end is for detecting and detecting during the detecting process.
  • the second signal connection pin signal on the device is connected to receive the detection signal from the detecting device to detect the operation of the substrate 9.
  • the first alignment detecting pin 1201 and the first alignment detecting pin 1202 are configured to perform the first signal connection pin 101 and the second signal connection pin on the detecting device before performing the above operation detection on the substrate 9. Alignment detection to detect whether the two are aligned accurately, preventing short-circuit problems caused by inaccurate alignment of the two, thereby preventing damage to signal lines and other devices on the substrate.
  • a plurality of signal lines 8 arranged in parallel with each other are provided in the working area 16 of the substrate 9.
  • the first end of the first signal connection pin 101 is electrically coupled to the signal line 8 in the working area 16.
  • the first end of each of the first signal connection pins 101 may be electrically connected to one signal line 8, and the first signal connection pin 101 may be a pin of the signal line 8.
  • the first signal connection pin 101 and the signal line 8 may also be integrally formed.
  • the integral molding means that the materials of the two are the same and there is no seam between the two.
  • the signal line 8 may be a gate line, a data line, a touch line, or a touch electrode.
  • the first signal connection pin 101 receives an electrical signal from the detecting device, which is conducted to the signal line 8 on the substrate 9 to detect whether the operating state of the signal line 8 is normal.
  • the number of first parity detecting pins on each side of the plurality of first signal connection pins 101 is at least 1.
  • the number of the first alignment detecting pins on each side of the plurality of first signal connection pins 101 is 1, so that the structure of the substrate 9 can be made simple, and the first alignment detecting pins are The number is as small as possible, and the area occupied by the periphery of the substrate 9 can be reduced, which is advantageous for a device using the substrate (for example, a display device) having a narrow bezel.
  • the first parity detection pin 1201/1202 is left floating.
  • the dangling setting means that the first registration detecting pin 1201/1202 is not electrically connected to any other device in a non-operating state (ie, in a state where no alignment detection is performed).
  • the first parity detecting pin 1201/1202 is used for An adjacent second bit detection pin on the detecting device is electrically connected, and a loop is formed with the adjacent second bit detecting pin, so that the adjacent second bit detecting pin can feed back an electrical signal.
  • the electrical signal can be detected, so the electrical signal can be used as a signal that is inaccurate in alignment.
  • a first alignment detecting pin may be disposed on both sides of the first signal connection pin 101.
  • one first alignment detecting pin is disposed on both sides of the first signal connection pin 101.
  • a first alignment detecting pin 1201 may be disposed only on one side of the first signal connection pin 101, and the first signal connection pin 101 may be further disposed. The first registration detection pin is not set on one side.
  • the first bit detection pin is specifically disposed on one side or one side of the first signal connection pin 101, and the specific number of the first bit detection pin can be based on the first alignment detection pin on the substrate
  • the arrangement of the alignment detecting pins on the matching detecting device is determined, which is not limited herein.
  • the conductivity of the material of the first alignment detection pin 1201/1202 may be greater than the conductivity of the material of the first signal connection pin 101.
  • the conductivity of the material of the first alignment detecting pin 1201/1202 is large, so that when the alignment between the first signal connection pin 101 and the second signal connection pin on the detecting device is inaccurate during the alignment detection process
  • the resistance of the formed loop is small, and the feedback electrical signal can be detected more easily, so that the problem of inaccurate alignment can be more sensitively determined.
  • the materials of the first signal connection pin 101 and the first alignment detection pins 1201/1202 may be metal materials. For example, copper, aluminum, copper alloy or aluminum alloy.
  • the material of the first signal connection pin 101 may be aluminum or titanium, etc.
  • the first alignment detection pin 1201/1202 may be formed of copper or the like having a conductivity higher than that of aluminum and titanium.
  • the materials of the first alignment detecting pin 1201/1202 and the first signal connection pin 101 may be the same.
  • the material of the first signal connection pin 101 and the first alignment detection pin 1201/1202 is not limited to the above description, and the embodiment of the present disclosure does not limit this.
  • the width of the first signal connection pin 101 is small and the spacing between adjacent first signal connection pins may be on the order of micrometers, for example, 60 to 80 ⁇ m, to be suitable for a substrate having a smaller size.
  • Embodiments of the present disclosure also provide a panel including any of the above substrates.
  • the panel provided by the embodiment of the present disclosure may be, for example, a light emitting panel or a display panel or the like.
  • the detecting device When the detecting device is used to detect the working condition of the panel, for example, whether the detecting panel has a problem of poor operation, the panel can be matched with the detecting device before the working condition is detected, and the first signal connection on the panel is cited.
  • the second signal connection pin on the foot and the detecting device performs the alignment detection to detect whether the two are aligned accurately, preventing the short circuit problem caused by the inaccurate alignment of the two, thereby preventing damage to the signal line on the substrate and Other devices.
  • the panel may be a display panel, for example, the display panel may be a liquid crystal display panel and an organic light emitting display panel.
  • the panel when it is a liquid crystal display panel, it may further include a backlight.
  • Embodiments of the present disclosure also provide a detecting apparatus including a plurality of second signal connection pins and a plurality of second alignment detection pins arranged side by side in parallel.
  • the plurality of second alignment detecting pins are located on at least one side of the plurality of second signal connection pins in the arrangement direction thereof, and are arranged in parallel with the second signal connection pins.
  • the detecting device provided by the embodiment of the present disclosure can cooperate with the substrate to be detected before detecting the working condition of the substrate, and the first signal connecting pin on the substrate and the second signal connecting pin on the detecting device are paired. Bit detection to detect whether the two are aligned accurately, to prevent short-circuit problems caused by inaccurate alignment of the two, thereby preventing damage to signal lines and other devices on the substrate.
  • FIG. 3A is a schematic plan view of a detecting device according to an embodiment of the present disclosure.
  • FIG. 3B is a schematic plan view of another detecting device according to an embodiment of the present disclosure, and
  • FIG. 3C is a schematic diagram of an embodiment of the present disclosure.
  • the detecting device 10 includes a plurality of second signal connection pins 102 and a plurality of second alignment detecting pins 2 arranged side by side in parallel.
  • the plurality of second signal connection pins 102 may be equally spaced, and the spacing between the adjacent two second signal connection pins 102 is the third pitch L3.
  • the plurality of second alignment detecting pins 2 may be located on both sides of the plurality of second signal connection pins 102 in the direction in which they are arranged, for example, the second alignment detecting pins 201/202/203 are located in multiple a second signal connection pin 102 on a first side in the direction in which it is arranged, and a second alignment detection pin 204/205/206 located on a second side of the plurality of second signal connection pins 102 in the direction in which they are arranged .
  • a plurality of second alignment detecting pins 2 are arranged in parallel with the plurality of second signal connection pins 102.
  • Each of the second signal connection pins 102 has a first end and a second end opposite the first end.
  • the first end is for receiving the detection signal from the detecting device, and the second end is for connecting with the first signal connection pin on the substrate to detect the working condition of the substrate.
  • the second alignment pin 2 is configured to perform alignment detection on the second signal connection pin 102 and the first signal connection pin on the substrate before detecting the above operation of the substrate to detect whether the two are aligned. Accurate to prevent short-circuit problems caused by inaccurate alignment of the two, thus preventing damage to signal lines and other devices on the substrate.
  • the detecting device 10 further includes a test circuit 3 and a registration circuit 4.
  • the test circuit 3 is electrically coupled to the first terminal of the second signal connection pin 102 and transmits a test signal, such as an electrical signal, to the second signal connection pin 102.
  • a test signal such as an electrical signal
  • the second end of the second signal connection pin 102 is connected to the first signal connection pin on the substrate.
  • the second signal connection pin 102 receives the test signal from the detecting device 10, that is, receives the test signal sent by the test circuit 3, and conducts the test signal to the substrate to detect the operation of the substrate.
  • the test circuit 3 and the registration circuit 4 are disposed on the printed circuit board 6.
  • the bit circuit 4 is electrically connected to the second bit detection pin 2 and can transmit a bit signal to the second bit detection pin 2. Before the detection of the operation of the substrate, the registration circuit 4 transmits a registration signal, such as an electrical signal, to the second alignment detection pin 2, and the second alignment detection pin 2 receives the alignment signal from the detection device 10, The second signal connection pin 102 is detected to be aligned with the first signal connection pin on the substrate.
  • a registration signal such as an electrical signal
  • the number of second parity detecting pins on each side of the plurality of second signal connection pins 102 is three.
  • the second bit detection pin 202/205 located in the middle is for receiving the alignment signal from the registration circuit, and correspondingly, in the middle
  • the second pair of detection pins 201/203/204/206 on both sides of the second bit detection pin 202/205 are used to transmit a registration detection result signal.
  • the registration circuit 4 transmits a detection signal to the second alignment detecting pin 202/205 located in the middle.
  • the second signal connection pin 102 is aligned with the first signal connection pin on the substrate, for example, the second parity detection pin 202/205 is electrically connected to the first alignment detection pin on the substrate. Without a loop, the second parity detection pin 201/203/204/206 does not feed back an electrical signal.
  • the second signal connection pin 102 is inaccurately aligned with the first signal connection pin on the substrate, for example, when the substrate is shifted to the left in FIG.
  • the adjacent second alignment detection pin 2 For example, the second parity detection pin 201 and the second alignment detection pin 202, or the second alignment detection pin 204 and the second alignment detection pin 205, are detected by the first alignment on the substrate.
  • the pin is electrically connected, and simultaneously forms a loop together with the first align detection pin on the substrate, and the second align detection pin 201 and the second align detection pin 204 feed back an electrical signal, that is, the second alignment detection
  • the pin 201 and the second parity detecting pin 204 return the alignment detection result signal.
  • the electrical signal can be detected, so the electrical signal can be used as a registration detection result signal, indicating that the alignment detection structure is inaccurate.
  • the registration circuit 4 can receive the alignment detection result signal from the second alignment detection pin 201, and can instruct the tester to move the substrate to the right side in order to accurately align.
  • the registration circuit 4 may include an ammeter in series with the second alignment detection pin 201, which is capable of detecting the alignment detection result signal. That is, if the current meter detects the current, it means that the registration result is inaccurate; if the current meter does not detect the current, it means that the registration result is accurate.
  • the substrate is offset to the right side in FIG.
  • the pin 205 is electrically connected through the first alignment detecting pin on the substrate and forms a loop together with the first alignment detecting pin on the substrate, so that the second alignment detecting pin 203 or/and the second pair
  • the bit detection pin 206 feeds back the electrical signal, that is, the second alignment detection pin 203 and the second alignment detection pin 206 return the alignment detection result signal, and can instruct the tester to move the substrate to the left side for accurate Counterpoint.
  • the detecting device 10 further comprises a control device 5, wherein the control device 5 is configured to control the opening and closing of the test circuit 3 and the registration circuit 4, and to control the test circuit 3 to send a test signal to the second signal connection pin 102, for example
  • the electrical signal, and the control register circuit 4 issues a registration signal, such as an electrical signal, to the second parity detection pin 2.
  • the control device 5 can be a control circuit, a programmable controller, a microcontroller, a microprocessor, or the like.
  • the specific type and structure of the control device 5 those skilled in the art can make selections with reference to conventional techniques.
  • the plurality of second alignment detecting pins 2 may be located only on one side of the plurality of second signal connection pins 102 in the direction in which they are arranged.
  • the second alignment detecting pins 201/202/203 are both located on one side of the plurality of second signal connection pins 102.
  • the other structure and operation principle of the detecting device 10 shown in Fig. 3B are the same as those shown in Fig. 3A, please refer to the above description.
  • this example differs from the example shown in FIG. 3A in that a second alignment detection lead is located on each side of the two sides of the second signal connection pin 102.
  • the number of feet is 2.
  • two second parity detection pins 202/203 proximate to the second signal connection pin 102 are for receiving a registration signal from the alignment circuit, and correspondingly, two of the second signal connection pins 102
  • the two-pair detection pin 201/204 is used to transmit a registration detection result signal.
  • the working principle is similar to the example shown in Figure 3A.
  • the registration circuit 4 includes an ammeter respectively connected in series with the second alignment detection pin 201 and an ammeter connected in series with the second alignment detection pin 204 for detecting the second alignment detection pin 201 and the Whether there is current on the second parity detecting pin 204, the alignment detection result is judged accordingly.
  • the two second bit detection pins 202/203 near the second signal connection pin 102 receive the detection signal from the registration circuit 4.
  • the second signal connection pin 102 is aligned with the first signal connection pin on the substrate, for example, only the second parity detection pin 202/203 is electrically connected to the alignment detection pin on the substrate, and the configuration is not completed. In the loop, the second parity detection pin 201/204 does not feed back an electrical signal.
  • the alignment detection result is that the alignment is accurate.
  • the adjacent second The alignment detection pin 201/202 is electrically connected through the first alignment detection pin on the substrate, and forms a loop together with the first alignment detection pin on the substrate, and the second alignment detection pin 201 is fed back.
  • the electrical signal that is, the second parity detecting pin 201 returns the alignment detection result signal, and the electrical signal can be detected.
  • the alignment detection result is inaccurate in alignment and can guide the tester to move the substrate to the right side for accurate alignment.
  • the adjacent second alignment detection pin 203/204 is electrically connected through the first alignment detection pin on the substrate. And forming a loop together with the first align detection pin on the substrate, and causing the second align detection pin 204 to feed back the electrical signal, that is, the second align detection pin 204 returns the alignment detection result signal.
  • the electrical signal can be detected.
  • the alignment detection result is inaccurate in alignment, and the tester can be instructed to move the substrate to the left side. In order to accurately match the position.
  • the alignment detecting principle of the detecting device shown in FIG. 3C may further be: two second alignment detecting pins 201/204 remote from the second signal connecting pin 102 for receiving the alignment from the matching circuit. Signals, correspondingly, two second alignment detection pins 202/203 proximate to the second signal connection pin 102 are used to transmit a registration detection result signal.
  • the registration circuit 4 includes an ammeter in series with the second alignment detection pin 202 and an ammeter in series with the second alignment detection pin 203.
  • the two second bit detection pins 201/204 remote from the second signal connection pin 102 receive the detection signal from the registration circuit 4.
  • the two second parity detection pins 202/203 near the second signal connection pin 102 do not feed back an electrical signal, for example, an ammeter in series with the second parity detection pin 202 and a second pair If the current is not detected by the current meter connected in series with the bit detection pin 203, the alignment detection result is that the alignment is accurate.
  • the second signal connection pin 102 is inaccurately aligned with the first signal connection pin on the substrate, for example, when the first signal connection pin 101 is shifted to the left in FIG.
  • the adjacent second The alignment detection pin 203/204 is electrically connected through the first alignment detection pin on the substrate, and forms a loop together with the first alignment detection pin on the substrate, and the second alignment detection pin 203 is fed back.
  • the electrical signal that is, the second parity detecting pin 203, returns the alignment detection result signal.
  • the electrical signal can be detected. For example, if the current meter connected in series with the second alignment detecting pin 203 detects the current, the alignment detection result is inaccurate in alignment, and can guide the tester to move the substrate to the right side. In order to accurately match the position.
  • the adjacent second alignment detection pin 201/202 is electrically connected through the first alignment detection pin on the substrate.
  • a circuit is formed together with the first align detection pin on the substrate, and the second align detection pin 202 is fed back an electrical signal, that is, the second align detection pin 202 returns the alignment detection result signal.
  • the electrical signal can be detected.
  • a current meter connected in series with the second parity detecting pin 202 detects a current, indicating that the alignment detection result is inaccurate, and can guide the tester to move the substrate to the left side. In order to accurately match the position.
  • the conductivity of the material of the second alignment detecting pin 2 is greater than the conductivity of the material of the second signal connection pin 102.
  • the conductivity of the material of the second parity detecting pin 2 is large, so that when the second signal connecting pin 102 is inaccurately aligned with the first signal connecting pin on the substrate during the alignment detecting process, The loop resistance is small, and the feedback electrical signal can be detected more easily, so that the problem of inaccurate alignment can be more sensitively determined.
  • the materials of the second signal connection pin 102 and the second alignment detection pin 2 may be metal materials. For example, copper, aluminum, copper alloy or aluminum alloy.
  • the material of the second signal connection pin 102 may be aluminum or titanium, etc.
  • the second alignment detection pin 2 may be formed of a metal having a conductivity higher than that of aluminum and titanium.
  • the materials of the second bit detection pin 2 and the second signal connection pin 102 may be the same.
  • the materials of the second signal connection pin 102 and the second alignment detection pin 2 are not limited to the above description, and the embodiment of the present disclosure does not limit this.
  • At least one embodiment of the present disclosure further provides an alignment detecting method, the method comprising: providing any one of the substrates of the present disclosure and any one of the detecting devices; and contacting the substrate and the detecting device with each other in order to a signal connection pin is electrically connected to the plurality of second signal connection pins on the detecting device in a one-to-one correspondence, and each of the first bit detection pins is electrically connected to the at least one second bit detection pin; Before applying a detection signal to the second signal connection pin, inputting a registration signal to the second parity detection pin to perform alignment detection to detect a plurality of first signal connection pins and a plurality of second signal connection pins Whether the alignment is accurate.
  • the alignment detecting method provided by the embodiment of the present disclosure can perform the alignment detection on the first signal connection pin on the substrate and the second signal connection pin on the detecting device before detecting the working condition of the substrate to detect Whether the two are aligned accurately prevents short-circuit problems caused by inaccurate alignment of the two, thereby preventing damage to signal lines and other devices on the substrate.
  • FIGS. 4A-4C are schematic diagrams of an alignment detection method according to an embodiment of the present disclosure
  • FIGS. 5A-5C are schematic diagrams of another alignment detection method provided by an embodiment of the present disclosure
  • FIGS. 6A-6C are implementations of the present disclosure.
  • Another schematic diagram of an alignment detection method is provided by the example.
  • FIGS. 7A-7C are schematic diagrams of still another alignment detection method provided by an embodiment of the present disclosure.
  • a substrate provided by an embodiment of the present disclosure is provided.
  • the first alignment detecting pin is located on both sides of the plurality of first signal connection pins 101 in the arrangement direction thereof, and the number of the first alignment detection pins on each side is 1 .
  • a detecting device in any of the above examples of the present disclosure is provided.
  • the second alignment detecting pin 2 is located on both sides of the plurality of second signal connection pins 102, and the number of the second alignment detecting pins 2 on each side is three.
  • the plurality of first signal connection pins 101 on the substrate are overlapped with the plurality of second signal connection pins 102 of the detecting device in one-to-one correspondence for electrical connection.
  • the controller 5 controls the registration circuit 4 to input a registration signal to the second parity detection pin 202/205, for example, the alignment signal is an electrical signal. Alignment detection to detect whether the plurality of first signal connection pins 101 and the plurality of second signal connection pins 102 are aligned accurately, that is, the plurality of first signal connection pins 101 and the plurality of second signal connection pins 102 Are you aligned one by one?
  • the alignment detection result signal may be an electrical signal, and it is determined whether the plurality of first signal connection pins and the plurality of second signal connection pins are accurately aligned by detecting whether there is current on the second parity detection pin.
  • the registration circuit 4 includes an ammeter in series with the second alignment detection pin 201/203/204/206, respectively, for detecting the second parity detection pin 201/203/204 during the alignment detection process. Is there any electrical signal feedback on /206? The result of the registration detection is judged based on the display result of the ammeter.
  • the first parity detection pin 1201 and the second alignment detection pin are pressed.
  • the second alignment detecting pin 202 in the middle of the arrangement direction is directly in contact with and electrically connected, and the second alignment detecting pin 205 is in direct contact with the first alignment detecting pin 1202 to be electrically connected.
  • the second parity detecting pin 201/203/204/206 is in a non-conducting state, and no electrical signal is fed back, and the current meter connected in series with the second parity detecting pin 201/203/204/206 is displayed. No current.
  • the result of the registration detection is that the alignment is accurate, and the operation of the substrate can be detected.
  • the second alignment detecting pin 202/205 located in the middle is electrically connected to the second alignment detecting pin 201 and the second alignment detecting pin respectively located on the two sides of the plurality of second signal connecting pins 102, respectively.
  • FIG. 8 is an enlarged schematic view of a portion 14 of the signal connection region of FIG. 4B
  • FIG. 9 is an enlarged schematic view of a portion 15 of the alignment detection region of FIG. 4B.
  • the adjacent second alignment detection pins 201/202 are both aligned with the first alignment.
  • the detection pin 1201 is in direct contact and electrically connected, and the adjacent second alignment detection pins 204/205 are all in direct contact with the first alignment detection pin 1202 to be electrically connected.
  • the second parity detecting pin 201/202 forms a loop with the first parity detecting pin 1201
  • the second alignment detecting pin 204/205 forms a loop with the first alignment detecting pin 1202, so the second The bit detection pin 201 and the second bit detection pin 204 feed back an electrical signal, that is, the second bit detection pin 201/204 returns a registration detection result signal.
  • the galvanometer connected in series with the second parity detecting pin 201/204 displays a current
  • the galvanometer connected in series with the second parity detecting pin 203/206 displays no current, which indicates that the alignment detection result is inaccurate
  • the first signal connection pin is offset to the left side in FIG. 4B, and can guide the tester to move the substrate to the right side for accurate alignment.
  • the adjacent second alignment detection pins 203/202 are both aligned with the first alignment detection pin 1201.
  • the first and second adjacent bit detection pins 206/205 are electrically connected to each other by direct contact and electrical connection.
  • the second parity detecting pin 203/202 forms a loop with the first parity detecting pin 1201
  • the second alignment detecting pin 206/205 forms a loop with the first alignment detecting pin 1202 bit detecting pin. Therefore, the second parity detecting pin 203 and the second parity detecting pin 206 feed back an electrical signal, that is, the second parity detecting pin 203/206 returns a registration detection result signal.
  • the galvanometer in series with the second align detection pin 203/206 shows current, and the galvanometer in series with the second align detection pin 201/204 shows no current. This means that the registration detection result is inaccurate, and the first signal connection pin is offset to the right in FIG. 4C, and can guide the tester to move the substrate to the left side for accurate alignment.
  • the registration result is inaccurate, the relative position of the first signal connection pin and the second signal connection pin is adjusted according to the obtained result, and the registration detection is performed again. Until the alignment detection result is accurate, the working condition of the substrate is detected. This prevents short-circuit problems caused by inaccurate alignment of the first signal connection pin and the second signal connection pin, thereby further preventing damage to the signal lines and other devices on the substrate.
  • the first alignment detecting pin 1201 may also be located only in the direction in which the plurality of first signal connection pins 101 are arranged. One side, and one first alignment detecting pin 1201 is disposed on this side.
  • the second parity detecting pin 2 is also located only on one side of the plurality of second signal connecting pins 102, and the number of the second pair detecting pins 2 on the side is 3.
  • the registration circuit 4 includes an ammeter in series with the second alignment detection pin 201/203 for detecting whether there is an electrical signal on the second alignment detection pin 201/203 during the alignment detection process. Feedback. The result of the registration detection is judged based on the display result of the ammeter.
  • the first parity detection pin 1201 and the second parity detection pin 2 are pressed.
  • the second alignment detecting pin 202 whose alignment direction is located in the middle is in direct contact and electrically connected.
  • the second parity detecting pin 201/203 is in a non-conducting state, and no electrical signal is fed back, and the current meter connected in series with the second parity detecting pin 201/203 indicates no current. That is, there is no feedback of the alignment detection result signal on the second alignment detecting pin 201/203 on both sides of the second alignment detecting pin 202 located in the middle.
  • the result of the registration detection is that the alignment is accurate, and the operation of the substrate can be detected.
  • the galvanometer connected in series with the second align detection pin 201 displays a current
  • the galvanometer connected in series with the second align detection pin 203 displays no current, which indicates that the alignment detection result is inaccurate, and the first signal
  • the connection pins are offset to the left in Figure 5B and can direct the tester to move the substrate to the right for accurate alignment.
  • the adjacent second alignment detection pins 203/202 are both aligned with the first alignment detection pin 1201. Direct contact and electrical connection.
  • the second parity detecting pin 203/202 forms a loop with the first parity detecting pin 1201, so the second parity detecting pin 203 and the second alignment detecting pin 206 feed back an electrical signal, that is, the second The alignment detection pin 203/206 returns the alignment detection result signal.
  • the galvanometer connected in series with the second align detection pin 203 displays a current
  • the galvanometer connected in series with the second align detection pin 201 displays no current, which indicates that the alignment detection result is inaccurate, and the first signal
  • the connection pins are offset to the right in Figure 5C and can direct the tester to move the substrate to the left for accurate alignment.
  • the first alignment detecting pin in the substrate, may be located on both sides of the plurality of first signal connection pins 101 in the direction in which they are arranged And the number of the first parity detection pins on each side is 1.
  • the second alignment detecting pin 2 is located on both sides of the second signal connection pin 102 in the arrangement direction thereof, and the number of the second alignment detecting pin 2 on each side Is 2.
  • the registration circuit 4 includes an ammeter in series with the second parity detection pin 201/204, respectively, for detecting whether there is electrical signal feedback on the second parity detection pin 201/204 during the alignment detection. The result of the registration detection is judged based on the display result of the ammeter.
  • the two second alignment detection leads adjacent to the second signal connection pins 102
  • the pins are respectively electrically connected to the first parity detecting pin, that is, the second alignment detecting pin 202 is in direct contact with the first alignment detecting pin 1201 and is electrically connected, and the second alignment detecting pin 203 is first
  • the alignment detecting pin 1202 is in direct contact and electrically connected.
  • the second parity detecting pin 201/204 is in a non-conducting state, and no electrical signal is fed back, and the current meter connected in series with the second parity detecting pin 201/204 displays no current. That is, there is no feedback of the alignment detection result signal on the two second alignment detection pins 201/204 remote from the second signal connection pin 102.
  • the alignment detection result is that the alignment is accurate, and the substrate can be operated. Situation detection.
  • the two second alignment detecting pins 201/202 located on the same side of the second signal connection pin 102 are electrically connected in direct contact with the first alignment detecting pin 1201.
  • the second alignment detecting pin 201/202 forms a loop with the first alignment detecting pin 1201, so the second alignment detecting pin 201 feeds back an electrical signal.
  • the second parity detection pin 204 is in a non-conducting state and does not feed back an electrical signal.
  • the galvanometer in series with the second align detection pin 201 displays current, and the galvanometer in series with the second align detection pin 204 shows no current. That is, one of the two second bit detection pins away from the second signal connection pin 102 feeds back the alignment detection result signal, which indicates that the registration result is inaccurate, and the first signal connection pin is shown in FIG. 6B.
  • the left side offset in the middle can guide the tester to move the substrate to the right side for accurate alignment.
  • the second parity detecting pin 203/204 forms a loop with the first parity detecting pin 1202, so the second parity detecting pin 204 feeds back an electrical signal.
  • the second parity detecting pin 201 is in a non-conducting state and does not feed back an electrical signal.
  • the galvanometer connected in series with the second align detection pin 204 displays a current
  • the galvanometer connected in series with the second align detection pin 201 displays no current, which indicates that the alignment detection result is inaccurate
  • the A signal connection pin is offset to the right in Figure 6C and can direct the tester to move the substrate to the left for accurate alignment.
  • the registration circuit 4 includes an ammeter respectively connected in series with the second alignment detecting pin 202/203, with Whether there is electrical signal feedback on the second parity detection pin 202/203 during the detection of the registration detection process. The result of the registration detection is judged based on the display result of the ammeter.
  • the second second alignment detection is performed away from the second signal connection pins 102.
  • the pins are electrically connected to the first bit detection pin, that is, the second bit detection pin 201 is in direct contact with the first bit detection pin 1201 and is electrically connected, and the second bit detection pin 204 and the second The pair of bit detection pins 1202 are in direct contact and electrically connected.
  • the second parity detecting pin 202/203 is in a non-conducting state, and no electrical signal is fed back, and the current meter connected in series with the second parity detecting pin 202/203 indicates no current. That is, there is no feedback of the alignment detection result signal on the two second alignment detection pins 202/203 of the second signal connection pin 102.
  • the alignment detection result is that the alignment is accurate, and the substrate can be operated. Situation detection.
  • the two second alignment detecting pins 203/204 located on the same side of the second signal connection pin 102 are in direct contact with the first alignment detecting pin 1202 to be electrically connected.
  • the second alignment detecting pin 203/204 forms a loop with the first alignment detecting pin 1202, so the second alignment detecting pin 203 feeds back an electrical signal.
  • the second parity detecting pin 202 is in a non-conducting state and does not feed back an electrical signal.
  • the galvanometer in series with the second align detection pin 203 shows a current
  • the galvanometer in series with the second align detection pin 202 shows no current. That is, one of the two second bit detection pins close to the second signal connection pin 102 feeds back the registration detection result signal, which indicates that the registration result is inaccurate, and the first signal connection pin is shown in FIG. 7B.
  • the left side offset in the middle can guide the tester to move the substrate to the right side for accurate alignment.
  • the second parity detecting pin 201/202 forms a loop with the first parity detecting pin 1201, so the second parity detecting pin 202 feeds back an electrical signal.
  • the second parity detecting pin 203 is in a non-conducting state and does not feed back an electrical signal.
  • the galvanometer connected in series with the second align detection pin 202 displays a current
  • the galvanometer connected in series with the second align detection pin 203 shows no current, which indicates that the alignment detection result is inaccurate
  • the A signal connection pin is offset to the right in Figure 7C and can direct the tester to move the substrate to the left for accurate alignment.
  • the second alignment detection pins are equally spaced and have a first pitch between adjacent second alignment detection pins, and at least one first alignment detection pin has a greater than The width of a pitch.
  • the second alignment detection pins are equally spaced and have a first pitch L1 between the adjacent second alignment detection pins, the first alignment detection pin
  • the width of 1201/1202 is W, and W is greater than L1.
  • a plurality of first signal connection pins 101 are periodically arranged and have a second pitch L2 between adjacent first signal connection pins
  • a plurality of The second signal connection pins 102 are periodically arranged and the adjacent second signal connection pins have a third pitch L3 between them
  • the second pitch L2 is equal to the third pitch L3.
  • the widths of the plurality of first signal connection pins 101 are equal to the widths of the plurality of second signal connection pins 102, so the first pitch L1 is equal to the third pitch L3.
  • the widths of the plurality of first signal connection pins 101 are not equal to the widths of the plurality of second signal connection pins 102, the first pitch L1 and the third pitch L3 are not equal.
  • the first alignment detection pin 1201 and The adjacent second alignment detecting pins 201 have a fourth pitch L4 therebetween.
  • the fourth pitch L4 is less than or equal to the second pitch L2.
  • the number of the first aligning pin and the second aligning pin is not limited to the number shown in the example given, as long as the embodiment of the present disclosure is provided. Examples of the principle of the registration detection method are all included in the technical solution of the present disclosure.

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Abstract

一种基板(9)、面板、检测装置(10)以及对准检测方法。该基板(9)包括：多个并排平行设置的第一信号连接引脚(101)和至少一个第一对位检测引脚(1201,1202)，至少一个第一对位检测引脚(1201,1202)位于多个第一信号连接引脚(101)的在其排列方向上的至少一侧，与第一信号连接引脚(101)平行布置。检测装置(10)包括多个并排平行设置的第二信号连接引脚(102)和多个第二对位检测引脚(2/201/202/203/204/205/206),多个第二对位检测引脚(2/201/202/203/204/205/206)位于多个第二信号连接引脚(102)的在其排列方向上的至少一侧，与第二信号连接引脚(102)平行布置。将该检测装置(10)与基板(9)彼此对准接触的过程中，可以检测第一信号连接引脚(101)与第二信号连接引脚(102)是否对位准确，防止因其对位不准而造成的短路问题。

Description

基板、面板、检测装置以及对准检测方法
本申请要求于2017年11月01日递交的中国专利申请第201711058191.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种基板、面板、检测装置以及对准检测方法。
背景技术
在显示面板的生产领域中，通常要通过检测设备对制备过程中的显示面板或基板(包括母板)进行点灯测试，在此阶段中可以检测出制备过程中的显示面板或基板是否有断线、坏点等现象，例如，该现象会导致亮点或暗点等缺陷。点灯测试阶段对于显示面板或基板品质的管控非常重要。
发明内容
本公开至少一实施例提供一种基板，其包括：多个并排平行设置的第一信号连接引脚和至少一个第一对位检测引脚；至少一个第一对位检测引脚位于所述多个第一信号连接引脚的在其排列方向上的至少一侧，与所述第一信号连接引脚平行布置。
例如，本公开至少一实施例提供的基板还包括工作区域，所述工作区域设置有多条彼此平行布置的信号线；每一个所述第一信号连接引脚具有第一端和第二端，每一个所述第一信号连接引脚的第一端与一条所述信号线电连接。
例如，在本公开至少一实施例提供的基板中，位于所述多个第一信号连接引脚的每一侧的所述第一对位检测引脚的个数为1。
例如，在本公开至少一实施例提供的基板中，所述第一对位检测引脚悬空设置。
例如，在本公开至少一实施例提供的基板中，所述第一对位检测引脚的材料的电导率大于所述第一信号连接引脚的材料的电导率。
本公开至少一实施例还提供一种面板，其包括上述任一项所述的基 板。
本公开至少一实施例还提供一种检测装置，其包括多个并排平行设置的第二信号连接引脚和多个第二对位检测引脚；多个第二对位检测引脚位于所述多个第二信号连接引脚的在其排列方向上的至少一侧，与所述第二信号连接引脚平行布置。
例如，本公开至少一实施例提供的检测装置还包括测试电路和对位电路。每一个所述第二信号连接引脚具有第一端和第二端，所述测试电路与所述第二信号连接引脚的第一端电连接并为所述第二信号连接引脚发送测试信号；对位电路与所述第二对位检测引脚电连接并为所述第二对位检测引脚发送对位信号以及接收来自所述第二对位检测引脚的对位检测结果信号。
例如，在本公开至少一实施例提供的检测装置中，所述第二信号连接引脚配置为接收来自所述测试电路的检测信号，所述第二对位检测引脚配置为接收来自所述对位电路的所述对位信号以及回传所述对位检测结果信号。
例如，本公开至少一实施例提供的检测装置还包括控制装置，其中，所述控制装置配置为控制所述测试电路和所述对位电路的开启与关闭，并控制所述测试电路向所述第二信号连接引脚发出测试信号以及控制所述对位电路向所述第二对位检测引脚发出对位信号。
例如，在本公开至少一实施例提供的检测装置中，位于所述多个第二信号连接引脚的每一侧的所述第二对位检测引脚的个数为3；在所述每一侧的所述第二对位检测引脚排列方向上，位于中间的所述第二对位检测引脚用于接收来自所述对位电路的对位信号，相应地，位于所述中间的第二对位检测引脚的两侧的所述第二对位检测引脚用于发送对位检测结果信号。
例如，在本公开至少一实施例提供的检测装置中，位于所述第二信号连接引脚的两侧的每一侧的所述第二对位检测引脚的个数为2；靠近所述第二信号连接引脚的2个所述第二对位检测引脚用于接收来自所述对位电路的对位信号，相应地，远离所述第二信号连接引脚的2个所述第二对位检测引脚用于发送对位检测结果信号；或者，远离所述第二信号连接引脚 的2个所述第二对位检测引脚用于接收来自所述对位电路的对位信号，相应地，靠近所述第二信号连接引脚的2个所述第二对位检测引脚用于发送对位检测结果信号。
例如，在本公开至少一实施例提供的检测装置中，所述第二对位检测引脚的材料的电导率大于所述第二信号连接引脚的材料的电导率。
本公开至少一实施例还提供一种对准检测方法，该方法包括：提供本公开上述任一实施例提供的待测基板；提供本公开上述任一实施例提供的检测装置；将所述待测基板和所述检测装置彼此接触，以将所述待测基板上的多个第一信号连接引脚与所述检测装置上的多个第二信号连接引脚一一对应搭接以电连接，以及将每个所述第一对位检测引脚与至少一个所述第二对位检测引脚电连接；在给多个所述第二信号连接引脚施加检测信号之前，给所述第二对位检测引脚输入对位信号，进行对位检测，以检测所述多个第一信号连接引脚与所述多个第二信号连接引脚是否对位准确。
例如，在本公开至少一实施例提供的对准检测方法中，多个所述第二对位检测引脚等间距排布且相邻的第二对位检测引脚之间具有第一间距，至少一个所述第一对位检测引脚具有大于所述第一间距的宽度。
例如，在本公开至少一实施例提供的对准检测方法中，多个所述第一信号连接引脚呈周期排布且相邻的所述第一信号连接引脚之间具有第二间距，多个第二信号连接引脚呈周期排布且相邻的所述第二信号连接引脚之间具有第三间距，所述第二间距与所述第三间距相等；当所述多个第一信号连接引脚与所述多个第二信号连接引脚对位准确时，所述第一对位检测引脚和与之相邻的所述第二对位检测引脚之间具有第四间距；所述第四间距小于或者等于所述第二间距。
例如，在本公开至少一实施例提供的对准检测方法中，位于所述多个第一信号连接引脚的在其排列方向上的每一侧的所述第一对位检测引脚的个数均为1，且位于所述多个第二信号连接引脚的每一侧的所述第二对位检测引脚的个数均为3；其中，在位于所述多个第二信号连接引脚的每一侧的3个所述第二对位检测引脚中，所述第一对位检测引脚与位于中间的所述第二对位检测引脚电连接，位于所述中间的第二对位检测引脚两侧的所述第二对位检测引脚上没有对位检测结果信号的反馈，则确定所述多个 第一信号连接引脚与所述多个第二信号连接引脚对位准确；
其中，在位于所述多个第二信号连接引脚的每一侧的3个所述第二对位检测引脚中，所述第一对位检测引脚在与所述位于中间的所述第二对位检测引脚电连接的同时，还与位于所述中间的第二对位检测引脚两侧的所述第二对位检测引脚之一电连接，所述两侧的所述第二对位检测引脚之一反馈对位检测结果信号，则确定所述多个第一信号连接引脚与所述多个第二信号连接引脚对位不准确。
例如，在本公开至少一实施例提供的对准检测方法中，位于所述多个第一信号连接引脚的在其排列方向上的两侧的每一侧的所述第一对位检测引脚的个数均为1，且位于所述第二信号连接引脚的在其排列方向上的两侧的每一侧的所述第二对位检测引脚的个数均为2；
其中，在位于所述多个第二信号连接引脚的每一侧的2个所述第二对位检测引脚中，靠近所述第二信号连接引脚的所述第二对位检测引脚与所述第一对位检测引脚电连接，远离所述第二信号连接引脚的所述第二对位检测引脚上没有对位检测结果信号的反馈，则确定所述多个第一信号连接引脚与所述多个第二信号连接引脚对位准确；
其中，所述第二信号连接引脚的两侧中的一侧的2个所述第二对位检测引脚均与所述第一对位检测引脚电连接，远离所述第二信号连接引脚的2个所述第二对位检测引脚之一反馈对位检测结果信号，则确定所述多个第一信号连接引脚与所述多个第二信号连接引脚对位不准确；
其中，远离所述第二信号连接引脚的2个所述第二对位检测引脚与所述第一对位检测引脚电连接，靠近所述第二信号连接引脚的2个所述第二对位检测引脚上没有对位检测结果信号的反馈，则确定所述多个第一信号连接引脚与所述多个第二信号连接引脚对位准确；
其中，位于所述第二信号连接引脚的的同一侧的2个所述第二对位检测引脚均与所述第一对位检测引脚电连接，靠近所述第二信号连接引脚的2个所述第二对位检测引脚之一反馈对位检测结果信号，则确定所述多个第一信号连接引脚与所述多个第二信号连接引脚对位不准确。
例如，在本公开至少一实施例提供的对准检测方法中，所述对位检测结果信号为电信号。
例如，在本公开至少一实施例提供的该对准检测方法中，所述电信号为电流。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是一种检测装置与一种基板信号连接以对基板进行检测的示意图；
图2A为本公开一实施例提供的一种基板的平面结构示意图；
图2B为本公开一实施例提供的另一种基板的平面结构示意图；
图3A为本公开一实施例提供的一种检测装置的平面结构示意图；
图3B为本公开一实施例提供的另一种检测装置的平面结构示意图；
图3C为本公开一实施例提供的又一种检测装置的平面结构示意图；
图4A-4C为本公开一实施例提供的一种对准检测方法示意图；
图5A-5C为本公开一实施例提供的另一种对准检测方法示意图；
图6A-6C为本公开一实施例提供的又一种对准检测方法示意图；
图7A-7C为本公开一实施例提供的再一种对准检测方法示意图；
图8为图4B中的信号连接区局部放大示意图；以及
图9为图4B中的对位检测区局部放大示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包 含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开所使用的附图的尺寸并不是严格按实际比例绘制，第一信号连接结构和第二信号连接结构的个数也不是限定为图中所示的数量，各个结构的具体的尺寸和数量可以根据实际需要进行确定。本公开的实施例中所描述的附图仅是结构示意图。
需要说明的是，本公开的实施例中的多个第一信号连接引脚的两侧，均是指多个第一信号连接引脚的在其排列方向上的两侧；多个第一信号连接引脚的每一侧均是指多个第一信号连接引脚的在其排列方向上的每一侧；本公开的实施例中所提及的宽度以及间距均指多个引脚排列方向上的宽度以及间距。
在面板例如显示面板的生产过程中，通常要通过检测装置对显示面板所包括的显示基板(包括显示母板)或显示面板本身进行测试，以检测出显示基板或显示面板是否有断线、坏点等，例如导致亮点或暗点的缺陷。
图1是一种检测装置与一种基板进行信号连接以对该基板进行检测的示意图。如图1所示，检测装置24上设置有多个第二信号连接引脚21，基板25上设置有多个第一信号连接引脚22。基板25上还设置有多条信号线(图未示出)，用于控制基板25各个工作单元的工作状态。第一信号连接引脚22与基板25上的信号线一一对应电连接。在检测过程中，需要将第二信号连接引脚21与第一信号连接引脚22一一对应电连接。在电连接后，第二信号连接引脚21接收来自检测装置24的电信号，该电信号经由基板25上的第一信号连接引脚22传导至基板25上的信号线。例如，基板25可以位于面板中，面板还可以包括背光源，点亮背光源，面板被点亮。例如，面板不需要背光源，例如，提供位于面板外部的外部光源，或者面板中的各个工作单元设置有发光元件，信号线控制发光元件的发光状态。通过基板上的信号线控制面板，可以检测面板的发光情况，例如检测有无亮点或暗点，从而检测出各个信号线是否工作不良。
但是，在检测过程中，当将多个第二信号连接引脚21与多个第一信号连接引脚22一一对应进行信号连接时，容易出现两者对位不准的问题。 如图1中的信号连接区23所示，对位不准可能造成相邻的信号线通过第二信号连接引脚21电连接从而发生短路。此时，当从检测装置输入检测信号之后，容易损坏信号线以及基板25上的其他工作器件。尤其对于尺寸较小的基板或面板，信号线、第二信号连接引脚21以及第一信号连接引脚22的宽度尺寸较小且相邻的第二信号连接引脚21以及相邻的第一信号连接引脚22之间的间距较小，例如，信号线、第一信号连接引脚以及第二信号连接引脚的宽度尺寸以及相邻的第一信号连接引脚以及相邻的第二信号连接引脚之间的间距可达到微米级，例如60～80μm，此时更容易产生上述对不准导致的短路问题。
本公开至少一实施例提供一种基板，其包括：多个并排平行设置的第一信号连接引脚和至少一个第一对位检测引脚。至少一个第一对位检测引脚位于多个第一信号连接引脚的在其排列方向上的至少一侧，与第一信号连接引脚平行布置。
本公开至少一实施例提供一种面板，其包括本公开上述任一实施例提供的基板。
本公开至少一实施例还提供一种检测装置，其包括多个并排平行设置的第二信号连接引脚和多个第二对位检测引脚，多个第二对位检测引脚位于多个第二信号连接引脚的在其排列方向上的至少一侧，与第二信号连接引脚平行布置。
本公开至少一实施例还提供一种对准检测方法，该方法包括：提供本公开一实施例提供的基板；提供本公开一实施例提供的检测装置；将基板和检测装置彼此接触，以为了将基板上的多个第一信号连接引脚与检测装置的多个第二信号连接引脚一一对应搭接以电连接，以及将每个第一对位检测引脚与至少一个第二对位检测引脚电连接；在给第二信号连接引脚施加检测信号之前，给第二对位检测引脚输入对位信号，进行对位检测，以检测多个第一信号连接引脚与多个第二信号连接引脚是否对位准确。
例如，图2A为本公开一实施例提供的一种基板的结构示意图，图2B为本公开一实施例提供的另一种基板的结构示意图。
本公开的实施例提供一种基板，其包括多个并排平行设置的第一信号连接引脚和至少一个第一对位检测引脚，至少一个第一对位检测引脚位于多个第一信号连接引脚的在其排列方向上的至少一侧，与第一信号连接引 脚平行布置。
示范性地，如图2A所示，基板9包括衬底基板7、设置于衬底基板7上的多个并排平行设置的第一信号连接引脚101和第一对位检测引脚1201、第一对位检测引脚1202。例如，多个第一信号连接引脚101可以等间距排列，例如，相邻的两个第一信号连接引脚101之间的间距为第二间距L2。第一对位检测引脚1201和第一对位检测引脚1202可以分别位于多个第一信号连接引脚101的在其排列方向上的两侧。第一对位检测引脚1201和第一对位检测引脚1202与多个第一信号连接引脚101平行布置。每一个第一信号连接引脚101具有第一端和与第一端相对的第二端，第一端用于与基板9的工作区域16信号连接，第二端可用于在检测过程中与检测装置上的第二信号连接引脚信号连接，以接收来自检测装置的检测信号，对基板9进行工作情况检测。第一对位检测引脚1201和第一对位检测引脚1202用于在对基板9进行上述工作情况检测之前，对第一信号连接引脚101与检测装置上的第二信号连接引脚进行对位检测，以检测两者是否对位准确，防止因这两者对位不准确而造成的短路问题，从而防止因此而损坏基板上的信号线以及其他器件。
例如，在基板9的工作区域16内设置有多条彼此平行布置的信号线8。第一信号连接引脚101的第一端与工作区域16内的信号线8电连接。例如，每一个第一信号连接引脚101的第一端可以与一条信号线8电连接，第一信号连接引脚101可以是信号线8的引脚。例如，第一信号连接引脚101和信号线8也可以一体成型。该一体成型是指这两者的材料相同且这两者之间无接缝。例如，信号线8可以是栅线、数据线、触控线或触控电极等。第一信号连接引脚101接收来自检测装置的电信号，该电信号传导至基板9上的信号线8，以检测信号线8的工作状态是否正常。
例如，位于多个第一信号连接引脚101的每一侧的第一对位检测引脚的个数至少为1。例如，位于多个第一信号连接引脚101的每一侧的第一对位检测引脚的个数为1，这样可以使基板9的结构简单，并且，第一对位检测引脚的个数尽量少，可以减小其在基板9周边占用的面积，有利于采用该基板的装置(例如显示装置)具有较窄的边框。
例如，第一对位检测引脚1201/1202悬空设置。悬空设置是指第一对位检测引脚1201/1202在非工作状态下(即，不进行对位检测的状态下) 不与任何其他器件电连接。在对位检测的过程中，如下所述，当第一信号连接引脚101与检测装置上的第二信号连接引脚对位不准确时，第一对位检测引脚1201/1202用于将检测装置上相邻的第二对位检测引脚电连接，同时与该相邻的第二对位检测引脚形成回路，而使该相邻的第二对位检测引脚能反馈电信号，该电信号能够被检测到，因此该电信号可以作为对位不准确的信号。
在本公开的一个示例中，例如，如图2A所示，可以在第一信号连接引脚101的两侧均设置有第一对位检测引脚。例如在第一信号连接引脚101的两侧均设置有1个第一对位检测引脚。在本公开的另一个示例中，如图2B所示，也可以只在第一信号连接引脚101的一侧设置一个第一对位检测引脚1201，而第一信号连接引脚101的另一侧不设置第一对位检测引脚。第一对位检测引脚具体设置于第一信号连接引脚101的两侧还是一侧，以及第一对位检测引脚的具体个数，可以根据与基板上的第一对位检测引脚配合的检测装置上的对位检测引脚的布置方式来确定，在此不作限定。
例如，第一对位检测引脚1201/1202的材料的电导率可以大于第一信号连接引脚101的材料的电导率。第一对位检测引脚1201/1202的材料的电导率较大可以使得在对位检测过程中，当第一信号连接引脚101与检测装置上的第二信号连接引脚对位不准确时，所形成的回路的电阻较小，反馈电信号能够更容易地被检测到，从而能够更敏感地判断出对位不准确的问题。例如，第一信号连接引脚101和第一对位检测引脚1201/1202的材料都可以是金属材料。例如铜、铝、铜合金或者铝合金等。例如，第一信号连接引脚101的材料可以为铝或钛等，第一对位检测引脚1201/1202可以由电导率比铝和钛的电导率大的铜等形成。当然，在一些示例中，第一对位检测引脚1201/1202和第一信号连接引脚101的材料也可以相同。第一信号连接引脚101和第一对位检测引脚1201/1202的材料不限于上述描述，本公开的实施例对此不作限定。
例如，第一信号连接引脚101的宽度尺寸较小且相邻的第一信号连接引脚之间的间距可以是微米级，例如60～80μm，以适用于尺寸较小的基板。
本公开的实施例还提供一种面板，该面板包括上述任意一种基板。本公开的实施例提供的面板，例如，可以为发光面板或显示面板等。当采用检测装置对面板的工作情况进行检测时，例如，检测面板是否有工作不良 的问题，在对工作情况进行检测之前，该面板可以与检测装置相配合，对面板上的第一信号连接引脚与检测装置上的第二信号连接引脚进行对位检测，以检测两者是否对位准确，防止因这两者对位不准确而造成的短路问题，从而防止损坏基板上的信号线以及其他器件。
例如，该面板可以为显示面板，例如，该显示面板可以为液晶显示面板和有机发光显示面板。例如，该面板为液晶显示面板时，其还可以包括背光源。
本公开的实施例还提供一种检测装置，其包括多个并排平行设置的第二信号连接引脚和多个第二对位检测引脚。多个第二对位检测引脚位于多个第二信号连接引脚的在其排列方向上的至少一侧，与第二信号连接引脚平行布置。
本公开的实施例提供的检测装置在对基板的工作情况进行检测之前，可以与待检测基板互相配合，对基板上的第一信号连接引脚与检测装置上的第二信号连接引脚进行对位检测，以检测两者是否对位准确，防止因这两者对位不准确而造成的短路问题，从而防止损坏基板上的信号线以及其他器件。
图3A为本公开的实施例提供的一种检测装置的平面结构示意图，图3B为本公开的实施例提供的另一种检测装置的平面结构示意图，图3C为本公开的实施例提供的又一种检测装置的平面结构示意图。
示范性地，如图3A所示，检测装置10包括多个并排平行设置的第二信号连接引脚102和多个第二对位检测引脚2。例如，多个第二信号连接引脚102可以等间距排列，相邻的两个第二信号连接引脚102之间的间距为第三间距L3。例如，多个第二对位检测引脚2可以位于多个第二信号连接引脚102的在其排列方向上的两侧，例如，第二对位检测引脚201/202/203位于多个第二信号连接引脚102的在其排列方向上的第一侧，第二对位检测引脚204/205/206位于多个第二信号连接引脚102的在其排列方向上的第二侧。多个第二对位检测引脚2与多个第二信号连接引脚102平行布置。每一个第二信号连接引脚102具有第一端和与第一端相对的第二端。第一端用于接收来自检测装置的检测信号，第二端用于与基板上的第一信号连接引脚连接，以对基板的工作情况进行检测。第二对位引脚2用于在对基板的上述工作情况进行检测之前，对第二信号连接引脚102与基板上的第 一信号连接引脚进行对位检测，以检测两者是否对位准确，防止因这两者对位不准确造成的短路问题，从而防止损坏基板上的信号线以及其他器件。
例如，检测装置10还包括测试电路3和对位电路4。测试电路3与第二信号连接引脚102的第一端电连接并为第二信号连接引脚102发送测试信号，例如电信号。对基板的工作情况进行检测时，第二信号连接引脚102的第二端与基板上的第一信号连接引脚连接。例如，第二信号连接引脚102接收来自检测装置10的测试信号，即接收测试电路3所发送的测试信号，并将该测试信号传导至基板，以对基板的工作情况进行检测。例如，测试电路3和对位电路4设置于印刷电路板6上。
对位电路4与第二对位检测引脚2电连接并可以为第二对位检测引脚2发送对位信号。在对基板的工作情况进行检测之前，对位电路4向第二对位检测引脚2发送对位信号，例如电信号，第二对位检测引脚2接收来自检测装置10的对位信号，以检测第二信号连接引脚102与基板上的第一信号连接引脚是否对位准确。
例如，位于多个第二信号连接引脚102的每一侧的第二对位检测引脚的个数为3。例如，在每一侧的第二对位检测引脚102的排列方向上，位于中间的第二对位检测引脚202/205用于接收来自对位电路的对位信号，相应地，位于中间的第二对位检测引脚202/205的两侧的第二对位检测引脚201/203/204/206用于发送对位检测结果信号。
例如，在对位检测过程中，对位电路4向位于中间的第二对位检测引脚202/205发送检测信号。当第二信号连接引脚102与基板上的第一信号连接引脚对位准确时，例如，第二对位检测引脚202/205与基板上的第一对位检测引脚电连接，构不成回路，第二对位检测引脚201/203/204/206不反馈电信号。当第二信号连接引脚102与基板上的第一信号连接引脚对位不准确时，例如，当基板向图3A中的左侧偏移时，相邻的第二对位检测引脚2，例如，第二对位检测引脚201和第二对位检测引脚202，或者第二对位检测引脚204和第二对位检测引脚205，会通过基板上的第一对位检测引脚电连接，同时与基板上的第一对位检测引脚共同形成回路，而使第二对位检测引脚201和第二对位检测引脚204反馈电信号，即第二对位检测引脚201和第二对位检测引脚204回传对位检测结果信号。该电信号能够被检测到，因此该电信号可以作为对位检测结果信号，标志着对位检测 结构为对位不准确。此时，对位电路4可以接收来自第二对位检测引脚201的对位检测结果信号，并可以指导测试者将基板向右侧移动，以便于准确对位。例如，对位电路4可以包括一个与第二对位检测引脚201串联的电流计，能够检测出该对位检测结果信号。即如果电流计检测到电流，则表示对位检测结果为对位不准确；如果电流计未检测到电流，则表示对位检测结果为对位准确。又例如，当基板向图3A中的右侧偏移时，第二对位检测引脚203和第二对位检测引脚202，或者第二对位检测引脚206和第二对位检测引脚205，会通过基板上的第一对位检测引脚电连接，并与基板上的第一对位检测引脚共同形成回路，而使得第二对位检测引脚203或/和第二对位检测引脚206反馈电信号，即第二对位检测引脚203和第二对位检测引脚206回传对位检测结果信号，并可以指导测试者将基板向左侧移动，以便于准确对位。
例如，检测装置10还包括控制装置5，其中，控制装置5配置为控制测试电路3和对位电路4的开启与关闭，并控制测试电路3向第二信号连接引脚102发出测试信号，例如电信号，以及控制对位电路4向第二对位检测引脚2发出对位信号，例如电信号。例如，控制装置5可以为控制电路、可编程控制器、单片机、微处理器等。对于控制装置5的具体类型和结构，本领域技术人员可参考常规技术进行选择。
例如，多个第二对位检测引脚2可以仅位于多个第二信号连接引脚102的在其排列方向上的一侧。例如，如图3B所示，第二对位检测引脚201/202/203均位于多个第二信号连接引脚102的一侧。图3B所示的检测装置10的其他结构和工作原理均与图3A所示的相同，请参考上述描述。
例如，在另一个示例中，如图3C所示，本示例与图3A所示的示例不同之处为：位于第二信号连接引脚102的两侧的每一侧的第二对位检测引脚的个数为2。例如，靠近第二信号连接引脚102的两个第二对位检测引脚202/203用于接收来自对位电路的对位信号，相应地，远离第二信号连接引脚102的两个第二对位检测引脚201/204用于发送对位检测结果信号。工作原理与图3A所示的示例相似。例如，对位电路4包括分别与第二对位检测引脚201串联的电流计以及与第二对位检测引脚204串联的电流计，分别用于检测第二对位检测引脚201和第二对位检测引脚204上是否有电流，据此判断对位检测结果。例如，在对位检测过程中，靠近第二信号连 接引脚102的2个第二对位检测引脚202/203接收来自对位电路4的检测信号。当第二信号连接引脚102与基板上的第一信号连接引脚对位准确时，例如，只有第二对位检测引脚202/203与基板上的对位检测引脚电连接，构不成回路，第二对位检测引脚201/204不反馈电信号。例如，与第二对位检测引脚201串联的电流计以及与第二对位检测引脚204串联的电流计均未检测到电流，则对位检测结果为已对位准确。当第二信号连接引脚102与基板上的第一信号连接引脚对位不准确时，例如，当第一信号连接引脚101向图3C中的左侧偏移时，相邻的第二对位检测引脚201/202会通过基板上的第一对位检测引脚电连接，并与基板上的第一对位检测引脚共同形成回路，而使第二对位检测引脚201反馈电信号，即第二对位检测引脚201回传对位检测结果信号，该电信号能够被检测到，例如，与第二对位检测引脚201串联的电流计检测到电流，则对位检测结果为对位不准确，并可以指导测试者将基板向右侧移动，以便于准确对位。又例如，当第一信号连接引脚101向图3C中的右侧偏移时，相邻的第二对位检测引脚203/204会通过基板上的第一对位检测引脚电连接，并与基板上的第一对位检测引脚共同形成回路，而使第二对位检测引脚204反馈电信号，即第二对位检测引脚204回传对位检测结果信号。该电信号能够被检测到，例如，与第二对位检测引脚204串联的电流计检测到电流，则对位检测结果为对位不准确，并可以指导测试者将基板向左侧移动，以便于准确对位。
又例如，图3C所示的检测装置的对位检测原理还可以是：远离第二信号连接引脚102的两个第二对位检测引脚201/204用于接收来自对位电路的对位信号，相应地，靠近第二信号连接引脚102的两个第二对位检测引脚202/203用于发送对位检测结果信号。例如，对位电路4包括分别与第二对位检测引脚202串联的电流计以及与第二对位检测引脚203串联的电流计。例如，在对位检测过程中，远离第二信号连接引脚102的两个第二对位检测引脚201/204接收来自对位电路4的检测信号。当第二信号连接引脚102与基板上的第一信号连接引脚对位准确时，例如，只有第二对位检测引脚201/204与基板上的第一对位检测引脚电连接，构不成回路，靠近第二信号连接引脚102的两个第二对位检测引脚202/203不反馈电信号，例如，与第二对位检测引脚202串联的电流计以及与第二对位检测引脚203串联的电流计均未检测到电流，则对位检测结果为已对位准确。当 第二信号连接引脚102与基板上的第一信号连接引脚对位不准确时，例如，当第一信号连接引脚101向图3C中的左侧偏移时，相邻的第二对位检测引脚203/204会通过基板上的第一对位检测引脚电连接，同时与基板上的第一对位检测引脚共同形成回路，而使第二对位检测引脚203反馈电信号，即第二对位检测引脚203回传对位检测结果信号。该电信号能够被检测到，例如，与第二对位检测引脚203串联的电流计检测到电流，则对位检测结果为对位不准确，并可以指导测试者将基板向右侧移动，以便于准确对位。又例如，当第一信号连接引脚101向图3C中的右侧偏移时，相邻的第二对位检测引脚201/202会通过基板上的第一对位检测引脚电连接，同时与基板上的第一对位检测引脚共同形成回路，而使第二对位检测引脚202反馈电信号，即第二对位检测引脚202回传对位检测结果信号。该电信号能够被检测到，例如，与第二对位检测引脚202串联的电流计检测到电流，表示对位检测结果为对位不准确，并可以指导测试者将基板向左侧移动，以便于准确对位。
例如，第二对位检测引脚2的材料的电导率大于第二信号连接引脚102的材料的电导率。第二对位检测引脚2的材料的电导率较大可以使得在对位检测过程中，当第二信号连接引脚102与基板上的第一信号连接引脚对位不准确时，所形成的回路电阻较小，反馈的电信号能够更容易地被检测到，从而能够更敏感地判断出对位不准确的问题。例如，第二信号连接引脚102和第二对位检测引脚2的材料都可以是金属材料。例如，铜、铝、铜合金或者铝合金等。例如，第二信号连接引脚102的材料可以为铝或钛等，第二对位检测引脚2可以由铜等电导率比铝和钛的电导率大的金属形成。当然，在一些示例中，第二对位检测引脚2和第二信号连接引脚102的材料也可以相同。第二信号连接引脚102和第二对位检测引脚2的材料不限于上述描述，本公开的实施例对此不作限定。
本公开至少一实施例还提供一种对准检测方法，该方法包括：提供本公开上述任一基板和上述任一检测装置；将基板与检测装置彼此接触，以为了将基板上的多个第一信号连接引脚与检测装置上的多个第二信号连接引脚一一对应搭接以电连接，以及每个第一对位检测引脚与至少一个第二对位检测引脚电连接；在给第二信号连接引脚施加检测信号之前，给第二对位检测引脚输入对位信号，进行对位检测，以检测多个第一信号连接引 脚与多个第二信号连接引脚是否对位准确。
本公开的实施例提供的对准检测方法可以在对基板的工作情况进行检测之前，对基板上的第一信号连接引脚与检测装置上的第二信号连接引脚进行对位检测，以检测两者是否对位准确，防止因这两者对位不准确而造成的短路问题，从而防止损坏基板上的信号线以及其他器件。
图4A-4C为本公开的实施例提供的一种对准检测方法示意图，图5A-5C为本公开的实施例提供的另一种对准检测方法示意图，图6A-6C为本公开的实施例提供的又一种对准检测方法示意图，图7A-7C为本公开的实施例提供的再一种对准检测方法示意图。
示范性地，如图4A-4C所示，提供本公开一实施例提供的基板。在该基板中，第一对位检测引脚位于多个第一信号连接引脚101的在其排列方向上的两侧，且位于每一侧的第一对位检测引脚的个数为1。提供本公开上述任一示例中的检测装置。在该检测装置中，第二对位检测引脚2位于多个第二信号连接引脚102的两侧，且位于每一侧的第二对位检测引脚2的个数为3。将基板上的多个第一信号连接引脚101与检测装置的多个第二信号连接引脚102一一对应搭接以电连接。
在给第二信号连接引脚102施加检测信号之前，通过控制器5控制对位电路4给第二对位检测引脚202/205输入对位信号，例如，该对位信号为电信号，进行对位检测，以检测多个第一信号连接引脚101与多个第二信号连接引脚102是否对位准确，即多个第一信号连接引脚101与多个第二信号连接引脚102是否一一对准。
例如，可以通过检测检测装置上相邻的第二对位检测引脚是否通过第一对位检测引脚实现电连接来判断多个第一信号连接引脚与多个第二信号连接引脚是否准确对位。例如，对位检测结果信号可以为电信号，通过检测第二对位检测引脚上是否有电流来判断多个第一信号连接引脚与多个第二信号连接引脚是否准确对位。
示范性地，对位电路4包括分别与第二对位检测引脚201/203/204/206串联的电流计，用于检测对位检测过程中第二对位检测引脚201/203/204/206上是否有电信号反馈。根据电流计的显示结果来判断对位检测结果。
例如，如图4A所示，当多个第一信号连接引脚101与多个第二信号 连接引脚102对位准确时，第一对位检测引脚1201与按第二对位检测引脚2的排列方向位于中间的第二对位检测引脚202直接接触而电连接，第二对位检测引脚205与第一对位检测引脚1202直接接触而电连接。此时，第二对位检测引脚201/203/204/206处于非导通状态，均不反馈电信号，与第二对位检测引脚201/203/204/206串联的电流计均显示无电流。即位于中间的第二对位检测引脚202/205两侧的第二对位检测引脚201/203/204/206上没有对位检测结果信号的反馈。此时，对位检测结果为已对位准确，可以进行基板的工作情况检测。
当多个第一信号连接引脚101与多个第二信号连接引脚102对位不准确时，第一对位检测引脚1201/1202在与按第二对位检测引脚2的排列方向位于中间的第二对位检测引脚202/205电连接的同时，还分别与位于多个第二信号连接引脚102两侧的第二对位检测引脚201和第二对位检测引脚204电连接，第二对位检测引脚201和第二对位检测引脚204反馈对位检测结果信号；或者还分别与位于多个第二信号连接引脚102两侧的第二对位检测引脚203和第二对位检测引脚206电连接，第二对位检测引脚203和第二对位检测引脚206反馈对位检测结果信号。图8为图4B中的信号连接区局部14的放大示意图，图9为图4B中的对位检测区局部15的放大示意图。例如，结合图4B、图8和图9，当第一信号连接引脚101向图4B中的左侧偏移时，相邻的第二对位检测引脚201/202均与第一对位检测引脚1201直接接触而电连接，相邻的第二对位检测引脚204/205均与第一对位检测引脚1202直接接触而电连接。此时，第二对位检测引脚201/202与第一对位检测引脚1201形成回路，第二对位检测引脚204/205与第一对位检测引脚1202形成回路，所以第二对位检测引脚201和第二对位检测引脚204反馈电信号，即第二对位检测引脚201/204回传对位检测结果信号。与第二对位检测引脚201/204串联的电流计显示有电流，与第二对位检测引脚203/206串联的电流计显示无电流，这表示对位检测结果为对位不准确，且第一信号连接引脚向图4B中的左侧偏移，并可以指导测试者将基板向右侧移动，以便于准确对位。
例如，如图4C所示，当第一信号连接引脚101向图4C中的右侧偏移时，相邻的第二对位检测引脚203/202均与第一对位检测引脚1201直接接触而电连接，相邻的第二对位检测引脚206/205均与第一对位检测引脚 1202直接接触而电连接。此时，第二对位检测引脚203/202与第一对位检测引脚1201形成回路，第二对位检测引脚206/205与第一对位检测引脚1202位检测引脚形成回路，所以第二对位检测引脚203和第二对位检测引脚206反馈电信号，即第二对位检测引脚203/206回传对位检测结果信号。与第二对位检测引脚203/206串联的电流计显示有电流，与第二对位检测引脚201/204串联的电流计显示无电流。这表示对位检测结果为对位不准确，且第一信号连接引脚向图4C中的右侧偏移，并可以指导测试者将基板向左侧移动，以便于准确对位。
当对位检测结果为对位不准确时，根据所得到的结果，定向调整第一信号连接引脚与第二信号连接引脚的相对位置，再次进行对位检测。直到对位检测结果为已对位准确，再对基板的工作情况进行检测。这样可以防止因第一信号连接引脚与第二信号连接引脚对位不准确而造成的短路问题，从而进一步防止损坏基板上的信号线以及其他器件。
例如，在本公开的另一个示例中，如图5A-5C所示，在基板中，第一对位检测引脚1201也可以只位于多个第一信号连接引脚101的在其排列方向上的一侧，且在这一侧设置1个第一对位检测引脚1201。相应地，在检测装置中，第二对位检测引脚2也只位于多个第二信号连接引脚102的一侧，且位于这一侧的第二对位检测引脚2的个数为3。
在本示例中，对位电路4包括分别与第二对位检测引脚201/203串联的电流计，用于检测对位检测过程中第二对位检测引脚201/203上是否有电信号反馈。根据电流计的显示结果来判断对位检测结果。
如图5A所示，当多个第一信号连接引脚101与多个第二信号连接引脚102对位准确时，第一对位检测引脚1201与按第二对位检测引脚2的排列方向位于中间的第二对位检测引脚202直接接触而电连接。此时，第二对位检测引脚201/203处于非导通状态，均不反馈电信号，与第二对位检测引脚201/203串联的电流计均显示无电流。即位于中间的第二对位检测引脚202两侧的第二对位检测引脚201/203上没有对位检测结果信号的反馈。此时，对位检测结果为已对位准确，可以进行基板的工作情况检测。
当多个第一信号连接引脚101与多个第二信号连接引脚102对位不准确时，例如，如图5B所示，当第一信号连接引脚101向图4B中的左侧偏移时，相邻的第二对位检测引脚201/202均与第一对位检测引脚1201直接 接触而电连接。此时，第二对位检测引脚201/202与第一对位检测引脚1201形成回路，所以第二对位检测引脚201反馈电信号。与第二对位检测引脚201串联的电流计显示有电流，与第二对位检测引脚203串联的电流计显示无电流，这表示对位检测结果为对位不准确，且第一信号连接引脚向图5B中的左侧偏移，并可以指导测试者将基板向右侧移动，以便于准确对位。
例如，如图5C所示，当第一信号连接引脚101向图5C中的右侧偏移时，相邻的第二对位检测引脚203/202均与第一对位检测引脚1201直接接触而电连接。此时，第二对位检测引脚203/202与第一对位检测引脚1201形成回路，所以第二对位检测引脚203和第二对位检测引脚206反馈电信号，即第二对位检测引脚203/206回传对位检测结果信号。与第二对位检测引脚203串联的电流计显示有电流，与第二对位检测引脚201串联的电流计显示无电流，这表示对位检测结果为对位不准确，且第一信号连接引脚向图5C中的右侧偏移，并可以指导测试者将基板向左侧移动，以便于准确对位。
例如，在本公开的另一个示例中，如图6A-6C所示，在基板中，第一对位检测引脚可以位于多个第一信号连接引脚101的在其排列方向上的两侧，且每一侧的第一对位检测引脚的个数为1。相应地，在检测装置中，第二对位检测引脚2位于第二信号连接引脚102的在其排列方向上的两侧，且每一侧的第二对位检测引脚2的个数为2。
例如，对位电路4包括分别与第二对位检测引脚201/204串联的电流计，用于检测对位检测过程中第二对位检测引脚201/204上是否有电信号反馈。根据电流计的显示结果来判断对位检测结果。
如图6A所示，例如，当多个第一信号连接引脚101与多个第二信号连接引脚102对位准确时，靠近第二信号连接引脚102的两个第二对位检测引脚分别与第一对位检测引脚电连接，即第二对位检测引脚202与第一对位检测引脚1201直接接触而电连接，同时，第二对位检测引脚203与第一对位检测引脚1202直接接触而电连接。此时，第二对位检测引脚201/204处于非导通状态，均不反馈电信号，与第二对位检测引脚201/204串联的电流计均显示无电流。即远离第二信号连接引脚102的两个第二对位检测引脚201/204上没有对位检测结果信号的反馈，此时，对位检测结果为已对位准确，可以进行基板的工作情况检测。
当多个第一信号连接引脚101与多个第二信号连接引脚102对位不准确时，例如，如图6B所示，当第一信号连接引脚101向图6B中的左侧偏移时，位于第二信号连接引脚102的同一侧的两个第二对位检测引脚201/202均与第一对位检测引脚1201直接接触而电连接。此时，第二对位检测引脚201/202与第一对位检测引脚1201形成回路，所以第二对位检测引脚201反馈电信号。第二对位检测引脚204处于非导通状态，不反馈电信号。所以，与第二对位检测引脚201串联的电流计显示有电流，与第二对位检测引脚204串联的电流计显示无电流。即远离第二信号连接引脚102的两个第二对位检测引脚之一反馈对位检测结果信号，这表示对位检测结果为对位不准确，且第一信号连接引脚向图6B中的左侧偏移，并可以指导测试者将基板向右侧移动，以便于准确对位。
例如，如图6C所示，当第一信号连接引脚101向图6C中的右侧偏移时，位于第二信号连接引脚102的同一侧的两个第二对位检测引脚203/204均与第一对位检测引脚1202直接接触而电连接。此时，第二对位检测引脚203/204与第一对位检测引脚1202形成回路，所以第二对位检测引脚204反馈电信号。第二对位检测引脚201处于非导通状态，不反馈电信号。所以，与第二对位检测引脚204串联的电流计显示有电流，与第二对位检测引脚201串联的电流计显示无电流，这表示对位检测结果为对位不准确，且第一信号连接引脚向图6C中的右侧偏移，并可以指导测试者将基板向左侧移动，以便于准确对位。
在本公开的另一个示例中，例如，在图7A-7C所示的对位检测方法中，例如，对位电路4包括分别与第二对位检测引脚202/203串联的电流计，用于检测对位检测过程中第二对位检测引脚202/203上是否有电信号反馈。根据电流计的显示结果来判断对位检测结果。
如图7A所示，例如，当多个第一信号连接引脚101与多个第二信号连接引脚102对位准确时，靠远离第二信号连接引脚102的两个第二对位检测引脚分别与第一对位检测引脚电连接，即第二对位检测引脚201与第一对位检测引脚1201直接接触而电连接，同时，第二对位检测引脚204与第一对位检测引脚1202直接接触而电连接。此时，第二对位检测引脚202/203处于非导通状态，均不反馈电信号，与第二对位检测引脚202/203串联的电流计均显示无电流。即靠近第二信号连接引脚102的两个第二对 位检测引脚202/203上没有对位检测结果信号的反馈，此时，对位检测结果为已对位准确，可以进行基板的工作情况检测。
当多个第一信号连接引脚101与多个第二信号连接引脚102对位不准确时，例如，如图7B所示，当第一信号连接引脚101向图7B中的左侧偏移时，位于第二信号连接引脚102的同一侧的两个第二对位检测引脚203/204均与第一对位检测引脚1202直接接触而电连接。此时，第二对位检测引脚203/204与第一对位检测引脚1202形成回路，所以第二对位检测引脚203反馈电信号。第二对位检测引脚202处于非导通状态，不反馈电信号。所以，与第二对位检测引脚203串联的电流计显示有电流，与第二对位检测引脚202串联的电流计显示无电流。即靠近第二信号连接引脚102的两个第二对位检测引脚之一反馈对位检测结果信号，这表示对位检测结果为对位不准确，且第一信号连接引脚向图7B中的左侧偏移，并可以指导测试者将基板向右侧移动，以便于准确对位。
例如，如图7C所示，当第一信号连接引脚101向图7C中的右侧偏移时，位于第二信号连接引脚102的同一侧的两个第二对位检测引脚201/202均与第一对位检测引脚1201直接接触而电连接。此时，第二对位检测引脚201/202与第一对位检测引脚1201形成回路，所以第二对位检测引脚202反馈电信号。第二对位检测引脚203处于非导通状态，不反馈电信号。所以，与第二对位检测引脚202串联的电流计显示有电流，与第二对位检测引脚203串联的电流计显示无电流，这表示对位检测结果为对位不准确，且第一信号连接引脚向图7C中的右侧偏移，并可以指导测试者将基板向左侧移动，以便于准确对位。
例如，在本公开的示例中，第二对位检测引脚等间距排布且相邻的第二对位检测引脚之间具有第一间距，至少一个第一对位检测引脚具有大于第一间距的宽度。例如，在图4A-4C所示的示例中，第二对位检测引脚等间距排布且相邻的第二对位检测引脚之间具有第一间距L1，第一对位检测引脚1201/1202的宽度均为W，W大于L1。这样可以保证当出现上述对位不准确的情况时，第一对位检测引脚1201能够同时与相邻的两个第一对位检测引脚同时接触以电连接，以反馈表示对位不准的检测结果信号。
在本公开的示例中，例如，如图4A-4C所示，多个第一信号连接引脚101呈周期排布且相邻的第一信号连接引脚之间具有第二间距L2，多个第 二信号连接引脚102呈周期排布且相邻的第二信号连接引脚之间具有第三间距L3，第二间距L2与第三间距L3相等。如此，当多个第一信号连接引脚101与多个第二信号连接引脚102对准时，不容易出现由于第二间距L2或第三间距L3过小而形成短路。这里多个第一信号连接引脚101的宽度与多个第二信号连接引脚102的宽度相等，所以第一间距L1与第三间距L3相等。当多个第一信号连接引脚101的宽度与多个第二信号连接引脚102的宽度不相等时，则第一间距L1与第三间距L3不相等。
示范性地，在图4A中，当将多个第一信号连接引脚101与多个第二信号连接引脚102一一对应搭接以电连接之后，第一对位检测引脚1201和与之相邻的第二对位检测引脚201之间具有第四间距L4。第四间距L4小于等于第二间距L2。当第一信号连接引脚101偏移量为L2时，会形成短路，此时第一对位检测引脚1201的偏移量也为L2，L2小于L4能够保证第一对位检测引脚1201与第二对位检测引脚201接触上以形成回路，从而使第二对位检测引脚201反馈对位不准的检测结果信号，能够保证将这种对位不准确检测出来，以防止第一信号连接引脚101与第二信号连接引脚102由于短路对基板造成的伤害。
需要说明的是，在本公开的实施例中，第一对位引脚和第二对位引脚的个数不限定为所给出的示例中所示的数量，只要运用本公开实施例提供的对位检测方法的原理的示例，均包含在本公开的技术方案中。
以上仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种基板，包括：
    多个并排平行设置的第一信号连接引脚；
    至少一个第一对位检测引脚，位于所述多个第一信号连接引脚的在其排列方向上的至少一侧，与所述第一信号连接引脚平行布置。
  2. 根据权利要求1所述的基板，还包括工作区域，其中，所述工作区域设置有多条彼此平行布置的信号线；
    每一个所述第一信号连接引脚具有第一端和第二端，每一个所述第一信号连接引脚的第一端与一条所述信号线电连接。
  3. 根据权利要求1或2所述的基板，其中，位于所述多个第一信号连接引脚的每一侧的所述第一对位检测引脚的个数为1。
  4. 根据权利要求1-3任一所述的基板，其中，所述第一对位检测引脚悬空设置。
  5. 根据权利要求1-4任一所述的基板，其中，所述第一对位检测引脚的材料的电导率大于所述第一信号连接引脚的材料的电导率。
  6. 一种面板，包括权利要求1-5任一所述的基板。
  7. 一种检测装置，包括：
    多个并排平行设置的第二信号连接引脚；
    多个第二对位检测引脚，位于所述多个第二信号连接引脚的在其排列方向上的至少一侧，与所述第二信号连接引脚平行布置。
  8. 根据权利要求7所述的检测装置，还包括：
    测试电路，其中，每一个所述第二信号连接引脚具有第一端和第二端，所述测试电路与所述第二信号连接引脚的第一端电连接并为所述第二信号连接引脚发送测试信号；以及
    对位电路，与所述第二对位检测引脚电连接并为所述第二对位检测引脚发送对位信号以及接收来自所述第二对位检测引脚的对位检测结果信号。
  9. 根据权利要求8所述的检测装置，其中，所述第二信号连接引脚配置为接收来自所述测试电路的测试信号，所述第二对位检测引脚配置为 接收来自所述对位电路的所述对位信号以及回传所述对位检测结果信号。
  10. 根据权利要求8或9所述的检测装置，还包括控制装置，其中，所述控制装置配置为控制所述测试电路和所述对位电路的开启与关闭，并控制所述测试电路向所述第二信号连接引脚发出测试信号以及控制所述对位电路向所述第二对位检测引脚发出对位信号。
  11. 根据权利要求7-10任一所述的检测装置，其中，位于所述多个第二信号连接引脚的每一侧的所述第二对位检测引脚的个数为3；
    其中，在所述每一侧的所述第二对位检测引脚排列方向上，位于中间的所述第二对位检测引脚用于接收来自所述对位电路的对位信号，相应地，位于所述中间的第二对位检测引脚的两侧的所述第二对位检测引脚用于发送对位检测结果信号。
  12. 根据权利要求7-10任一所述的检测装置，其中，位于所述第二信号连接引脚的两侧的每一侧的所述第二对位检测引脚的个数为2；
    其中，靠近所述第二信号连接引脚的2个所述第二对位检测引脚用于接收来自所述对位电路的对位信号，相应地，远离所述第二信号连接引脚的2个所述第二对位检测引脚用于发送对位检测结果信号；
    或者，远离所述第二信号连接引脚的2个所述第二对位检测引脚用于接收来自所述对位电路的对位信号，相应地，靠近所述第二信号连接引脚的2个所述第二对位检测引脚用于发送对位检测结果信号。
  13. 根据权利要求7-12任一所述的检测装置，其中，所述第二对位检测引脚的材料的电导率大于所述第二信号连接引脚的材料的电导率。
  14. 一种对准检测方法，该方法包括：
    提供权利要求1-5任一所述的基板；
    提供权利要求7-13任一所述的检测装置；
    将所述基板和所述检测装置彼此接触，以将所述基板上的多个第一信号连接引脚与所述检测装置上的多个第二信号连接引脚一一对应搭接以电连接，以及将每个所述第一对位检测引脚与至少一个所述第二对位检测引脚电连接；
    在给多个所述第二信号连接引脚施加检测信号之前，给所述第二对位检测引脚输入对位信号，进行对位检测，以检测所述多个第一信号连接引 脚与所述多个第二信号连接引脚是否对位准确。
  15. 根据权利要求14所述的对准检测方法，其中，多个所述第二对位检测引脚等间距排布且相邻的第二对位检测引脚之间具有第一间距，至少一个所述第一对位检测引脚具有大于所述第一间距的宽度。
  16. 根据权利要求15所述的对准检测方法，其中，多个所述第一信号连接引脚呈周期排布且相邻的所述第一信号连接引脚之间具有第二间距，多个第二信号连接引脚呈周期排布且相邻的所述第二信号连接引脚之间具有第三间距，所述第二间距与所述第三间距相等；
    当所述多个第一信号连接引脚与所述多个第二信号连接引脚对位准确时，所述第一对位检测引脚和与之相邻的所述第二对位检测引脚之间具有第四间距；
    其中，所述第四间距小于或者等于所述第二间距。
  17. 根据权利要求14-16任一所述的对准检测方法，其中，位于所述多个第一信号连接引脚的在其排列方向上的每一侧的所述第一对位检测引脚的个数均为1，且位于所述多个第二信号连接引脚的每一侧的所述第二对位检测引脚的个数均为3；
    其中，在位于所述多个第二信号连接引脚的每一侧的3个所述第二对位检测引脚中，所述第一对位检测引脚与按所述第二对位检测引脚的排列方向位于中间的所述第二对位检测引脚电连接，位于所述中间的第二对位检测引脚两侧的所述第二对位检测引脚上没有对位检测结果信号的反馈，则确定所述多个第一信号连接引脚与所述多个第二信号连接引脚对位准确；
    其中，在位于所述多个第二信号连接引脚的每一侧的3个所述第二对位检测引脚中，所述第一对位检测引脚在与按所述第二对位检测引脚的排列方向位于中间的所述第二对位检测引脚电连接的同时，还与位于所述中间的第二对位检测引脚两侧的所述第二对位检测引脚之一电连接，所述两侧的所述第二对位检测引脚之一反馈对位检测结果信号，则确定所述多个第一信号连接引脚与所述多个第二信号连接引脚对位不准确。
  18. 根据权利要求14-16任一所述的对准检测方法，其中，位于所述多个第一信号连接引脚的在其排列方向上的两侧的每一侧的所述第一对位 检测引脚的个数均为1，且位于所述第二信号连接引脚的在其排列方向上的两侧的每一侧的所述第二对位检测引脚的个数均为2；
    其中，在位于所述多个第二信号连接引脚的每一侧的2个所述第二对位检测引脚中，靠近所述第二信号连接引脚的所述第二对位检测引脚与所述第一对位检测引脚电连接，远离所述第二信号连接引脚的所述第二对位检测引脚上没有对位检测结果信号的反馈，则确定所述多个第一信号连接引脚与所述多个第二信号连接引脚对位准确；
    其中，位于所述第二信号连接引脚的同一侧的2个所述第二对位检测引脚均与所述第一对位检测引脚电连接，远离所述第二信号连接引脚的2个所述第二对位检测引脚之一反馈对位检测结果信号，则确定所述多个第一信号连接引脚与所述多个第二信号连接引脚对位不准确；
    其中，远离所述第二信号连接引脚的2个所述第二对位检测引脚与所述第一对位检测引脚电连接，靠近所述第二信号连接引脚的2个所述第二对位检测引脚上没有对位检测结果信号的反馈，则确定所述多个第一信号连接引脚与所述多个第二信号连接引脚对位准确；
    其中，位于所述第二信号连接引脚的同一侧的2个所述第二对位检测引脚均与所述第一对位检测引脚电连接，靠近所述第二信号连接引脚的2个所述第二对位检测引脚之一反馈对位检测结果信号，则确定所述多个第一信号连接引脚与所述多个第二信号连接引脚对位不准确。
  19. 根据权利要求17或18所述的对准检测方法，其中，所述对位检测结果信号为电信号。
  20. 根据权利要求19所述的对准检测方法，其中，所述电信号为电流。
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