WO2017202098A1 - 电路板结构、绑定测试方法及显示装置 - Google Patents

电路板结构、绑定测试方法及显示装置 Download PDF

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Publication number
WO2017202098A1
WO2017202098A1 PCT/CN2017/075531 CN2017075531W WO2017202098A1 WO 2017202098 A1 WO2017202098 A1 WO 2017202098A1 CN 2017075531 W CN2017075531 W CN 2017075531W WO 2017202098 A1 WO2017202098 A1 WO 2017202098A1
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Prior art keywords
circuit board
electrodes
binding
electrode
board structure
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PCT/CN2017/075531
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English (en)
French (fr)
Inventor
李琨
马韬
吕凤珍
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/558,412 priority Critical patent/US10616997B2/en
Publication of WO2017202098A1 publication Critical patent/WO2017202098A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/70—Testing of connections between components and printed circuit boards
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H05K1/028—Bending or folding regions of flexible printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/118—Printed elements for providing electric connections to or between printed circuits specially for flexible printed circuits, e.g. using folded portions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/041—Stacked PCBs, i.e. having neither an empty space nor mounted components in between
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09936—Marks, inscriptions, etc. for information
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display
    • H05K2201/10136—Liquid Crystal display [LCD]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/166—Alignment or registration; Control of registration

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a circuit board structure, a binding test method, and a display device.
  • TFT LCD Thin Film Transistor Liquid Crystal Display
  • Bonding is mainly about Panel and FPC (flexible circuit board), or FPC and PCB ( Printed circuit boards) are commonly used in TFT-LCD module factories by ACF (isotropic conductive film) combined and electrically connected according to a certain workflow.
  • ACF isotropic conductive film
  • the main object of the present disclosure is to provide a technical solution that can detect a binding state between circuit boards and improve work efficiency.
  • a circuit board structure includes a first circuit board, a second circuit board, and a test circuit; the first circuit board includes a first binding area, the second circuit board includes a second binding area, and the second binding a zone matching the first binding zone; the test circuit for testing the first circuit board and the second circuit board Alignment case, and includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes, the plurality of first electrodes and the plurality of second electrodes being insulated from each other in the first circuit a plurality of third electrodes disposed on the second circuit board; wherein a group consisting of one of the plurality of first electrodes and one of the plurality of second electrodes One of the plurality of third electrodes is matched such that the test circuit can be turned on when energized.
  • the first binding area includes a plurality of first connecting pieces
  • the second binding area includes a plurality of second connecting pieces
  • the number of the first connecting pieces and the second connecting pieces Equivalent and arranged in the same manner, each of the plurality of first connecting pieces is connected to the plurality of second connections when the first binding area and the second binding area are successfully matched
  • the corresponding second connecting pieces in the sheet are attached to each other.
  • the number of the plurality of first electrodes, the number of the plurality of second electrodes, and the number of the plurality of third electrodes are both 2.
  • the plurality of first electrodes and the plurality of second electrodes are both located on two sides of the first binding area, and the plurality of third electrodes are located on both sides of the second binding area .
  • the plurality of second electrodes are located on opposite sides of the plurality of first electrodes.
  • the plurality of first electrodes and the plurality of second electrodes are strip conductors.
  • each of the plurality of third electrodes is a U-shaped conductor.
  • the test circuit further includes a first test point connected to each of the plurality of first electrodes, and a second test point connected to each of the plurality of second electrodes.
  • the first electrode and the second electrode are separated from each other and The ones respectively matching the plurality of third electrodes are electrically conductively connected.
  • the first circuit board further includes a plurality of first alignment regions
  • the second circuit board further includes a plurality of second alignment regions on the first circuit board and the second circuit board In the successfully bound state, the plurality of first alignment regions and the plurality of second alignment regions can be completely aligned.
  • the plurality of first electrodes and the plurality of second electrodes are located between the plurality of first alignment regions and the first binding region, and the plurality of third electrodes are located at the Between the plurality of second alignment regions and the second binding region.
  • the first circuit board is a printed circuit board
  • the second circuit board is a flexible circuit board
  • the first circuit board and the second circuit board are both printed circuit boards, or the a circuit The board and the second circuit board are both flexible circuit boards.
  • a first aligning area and a second aligning area matching the first aligning area are respectively disposed on the first circuit board and the second circuit board.
  • a display device including the above-described circuit board structure.
  • a binding test method is provided, the method being applied to the circuit board structure of claim 1, the method comprising: pairing one of the plurality of first electrodes a group consisting of one of the plurality of second electrodes is energized; and determining whether the magnitude of the current flowing is within a predetermined current range.
  • the current flowing through is zero or significantly smaller than the predetermined current, determining that the binding of the circuit board structure is unsuccessful; if the current flowing in the predetermined current range is determined, determining the binding of the circuit board structure Success.
  • the test circuit further includes a first test point connected to each of the plurality of first electrodes and a second test point connected to each of the plurality of second electrodes, wherein The first test point and the second test point energize a group consisting of one of the plurality of first electrodes and one of the plurality of second electrodes.
  • the circuit board structure and the display device of the present disclosure solve the problem that the related microscopic observation method cannot observe the binding state between the non-transparent PCB board and the FPC because the power-on test method is adopted.
  • the problem, and the accuracy of this test method is higher, and the binding detection efficiency in the module production process of the thin film transistor liquid crystal display can be improved.
  • FIG. 1 is a schematic structural view of a first circuit board according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural view of a second circuit board according to an embodiment of the present disclosure
  • FIG. 3 is a cross-sectional structural view of the first circuit board and the second circuit board taken along the line A-A of FIG. 2 after the merging and pressing before the aligning according to the embodiment of the present disclosure;
  • FIG. 4 is an assembled view of a display device after board bonding is completed, according to an embodiment of the present disclosure
  • FIG. 5 is a flowchart of a binding test method in accordance with an embodiment of the present disclosure.
  • a circuit board structure includes a first circuit board, a second circuit board, and a test circuit.
  • the test circuit is used to test the alignment of the first circuit board and the second circuit board.
  • the test circuit includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes.
  • the plurality of first electrodes and the plurality of second electrodes are disposed on the first circuit board in insulation from each other, and the plurality of third electrodes are disposed on the second circuit board.
  • the first circuit board includes a first binding area
  • the second circuit board includes a second binding area, wherein the first binding area is matched with the second binding area, and the group consists of a first electrode and a second electrode Matching with a third electrode allows the test circuit to be turned on when energized.
  • the binding area between the two boards to be bound needs to be completely docked to be successful in binding the two boards.
  • the operator when detecting the binding state between two transparent boards, the operator directly observes using a microscope. In this way, the operator can directly judge whether there is a misalignment between the binding areas of the two boards by visually. If there is a misalignment, it means that the binding fails. If there is no misalignment, the binding is successful.
  • a special test circuit is added on the circuit board to judge whether the binding between the two boards is successful.
  • a first electrode and a second electrode which are insulated from each other (that is, in an off state) are disposed on the first circuit board, and a third electrode is disposed on the second circuit board. Since the first electrode and the second electrode and the third electrode are completely matched in a state in which the first circuit board and the second circuit board are successfully bonded (ie, there is no misalignment), in the power-on state, the current passes through the three Electrodes form a conductive path.
  • the voltage used in the test is set to the standard value, since the resistance of the three electrodes after contact depends on the alignment of the three, if the alignment is accurate, the current through the three electrodes is within a predetermined current range. of. However, if there is a misalignment, no current will pass, or the current will be significantly less than the predetermined current. Therefore, using this to add to the circuit board The way the circuit is tested can accurately determine whether the two boards are successfully aligned (ie, the binding is successful).
  • the first binding area includes a plurality of first connecting pieces
  • the second binding area includes a plurality of second connecting pieces
  • the number of the first connecting pieces is equal to the number of the second connecting pieces and is arranged The same way.
  • the connecting piece in order to form a circuit board structure, in two binding areas respectively set on two circuit boards that need to be bound, the connecting piece is used for transmitting data, that is, the first connecting piece and the second connecting piece are Data interaction is required. Therefore, the first connecting piece and the second connecting piece need to be matched and matched, so that the binding is successful.
  • the success of the binding is mainly reflected in the good position between the two, and because of the characteristics of the binding process, as long as the first connecting piece and the second connecting piece are not misaligned, the fitting will basically not cause problems.
  • first connecting piece, the second connecting piece, the first electrode, the second electrode, and the third electrode may all be made of metal, such as Cu.
  • the number of the first electrodes, the number of the second electrodes, and the number of the third electrodes are both 2, and the plurality of first electrodes and the plurality of second electrodes are both located in the first binding.
  • a plurality of third electrodes are located on both sides of the second binding zone. That is, one first electrode and one second electrode may be used as the first group, and the other first electrode and the other second electrode may be used as the second group.
  • the first group is disposed on the left side of the first binding area, and the second group is disposed on the right side of the first binding area, and the first The positional relationship of the first electrode and the second electrode in the group is opposite to the positional relationship of the first electrode and the second electrode in the second group.
  • the first electrode is located on the left side of the second electrode, and in the second group, the first electrode is located on the right side of the second electrode; or in the first group, the first electrode is located on the right side of the second electrode
  • the first electrode is located on the left side of the second electrode.
  • one third electrode is disposed on the left side of the second binding area, and the other third electrode is disposed on the right side of the second binding area.
  • the binding success depends mainly on whether or not a misalignment occurs, such a design
  • the accuracy of detecting misalignment can be better improved, and the binding state can be more easily obtained.
  • test area in the area of the binding area, and the number of test areas may be three or more, or only one.
  • the embodiments of the present disclosure are not limited.
  • the first electrode and the second electrode are designed as strip conductors. Accordingly, the third electrode is designed as a U-shaped conductor.
  • the first electrode and the second electrode the third electrode may have a plurality of design shapes, and the embodiment of the present disclosure does not limit the present, as long as the first electrode and the second electrode are When the insulation state is broken and the third electrode is in an integrated design state, a conduction loop can be formed when the three electrodes are in the bonded state.
  • the test circuit may further include a first test point connected to the first electrode and a second test point connected to the second electrode. These two test points are designed to meet the testability requirements. For example, the test probe is directly contacted with two test points, and if the test current can flow in and out from the two test points, respectively, it can be determined that the first electrode and the second electrode are in a connected conduction state with the third electrode.
  • the first electrode and the second electrode and the third electrode may be completely new designs, or may be improved in related designs.
  • the main reason is that in the current circuit board structure design, there are sometimes dummy connecting pieces inside and outside the binding area of the circuit board that do not need to transmit data (the shape and material of the first connecting piece and The second tab has the same shape and material). In this case, it is only necessary to improve the shape of these dummy connecting pieces.
  • the two dummy connecting pieces on the first circuit board are respectively used as the first electrode and the second electrode, and the bottom of the dummy connecting piece on the second circuit board is connected to form a third electrode which is approximately U-shaped. .
  • the shape of the two test points may be a circle, a semicircle, a rectangle, or a triangle, and the embodiment of the present disclosure is not limited thereto.
  • the two circuit boards in the process of binding the first circuit board and the second circuit board, in order to help the first circuit board and the second circuit board to be combined, may also be separately Set the corresponding flag (Mark). That is, the first circuit board may further include a first alignment area, and the second circuit board may further include a second alignment area, the second alignment area matching the first alignment area. In a state in which the first circuit board and the second circuit board are successfully bound, the first alignment area and the second alignment area can be aligned with each other.
  • the first electrode and the second electrode may be located between the first alignment area and the first binding area, and the third electrode may be located in the second alignment area and the second binding Area between.
  • FIG. 1 is a schematic structural view of a first circuit board according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural view of a second circuit board according to an embodiment of the present disclosure
  • FIG. 3 is a first circuit board and a second according to an embodiment of the present disclosure.
  • the first circuit board may be a printed circuit board (PCB) and the second circuit board may be a flexible circuit board (FPC). Since the PCB is non-transparent and the FPC is transparent or translucent, the above board structure is well suited for PCB and FPC matching. It should be understood that although the embodiments of the present disclosure are described with the first circuit board as the PCB and the second circuit board as the FPC, the embodiments of the present disclosure are also fully applicable between two non-transparent circuit boards or two. A test of the binding state between transparent boards, such as the test of the binding state between two PCBs, or the test of the binding state between two FPCs.
  • a binding area (ie, a first binding area) 11 is respectively designed on a first circuit board (such as a PCB) 1, two first electrodes 12, two second electrodes 13, and two The alignment area (ie, the first alignment area) 14, the two first test points 15 and the two second test points 16, wherein the binding area 11 is in the middle, the two first electrodes 12 and the two second electrodes 13
  • the electrodes on both sides of the first binding region 11 are stripped in sequence, and the two first alignment regions 14 are located on both sides of the two second electrodes 13.
  • the second binding region 21 is located in the middle, and the two third electrodes 22 are arranged on both sides of the second binding region 21 and are two U-shaped electrodes.
  • the first circuit board 1 and the second circuit board 2 are first aligned by using the first alignment area and the second alignment area, and then pressed.
  • the first electrode 12 and the second electrode 13 and the third electrode 22 are subjected to a power-on test using test points (ie, the first test point 15 and the second test point 16).
  • the pressing process does not cause a defect, so that no misalignment means that the second circuit board 1 and the second circuit board 2 are successfully bound.
  • the state when the first circuit board 1 and the second circuit board 2 are successfully bonded can be seen from the cross-sectional structure shown in FIG. 2.
  • the first circuit board 1 such as The first connecting piece 17 of the PCB
  • the second connecting piece 24 of the second circuit board 2 such as FPC
  • the embodiment of the present disclosure further provides a display device 30 including the circuit board structure of the embodiment of the present disclosure.
  • the specific configuration of the display device 30 will not be described in detail based on the description of the above-described circuit board structure.
  • FIG. 4 is an assembled view of the display device 30 after the board binding is completed according to an embodiment of the present disclosure.
  • the first circuit board 1 and the second circuit board 2 in the display device 30 of the embodiment of the present disclosure may be a non-transparent printed circuit board PCB and a transparent flexible circuit board FPC, or two non-transparent circuit boards. Or two transparent boards.
  • FIG. 5 is a flowchart of a binding test method in accordance with an embodiment of the present disclosure.
  • the binding test method described in the embodiment of the present disclosure shown in FIG. 5 is applied to the above-described circuit board structure of the present disclosure.
  • the binding test method includes steps S1-S2.
  • S1 energizing a group consisting of one of the plurality of first electrodes and one of the plurality of second electrodes.
  • S2 It is judged whether the magnitude of the current flowing is within a predetermined current range. If the current flowing through is zero or significantly smaller than the predetermined current, it is judged that the binding of the circuit board structure is unsuccessful; if the current flowing is within a predetermined current range, it is judged that the binding of the circuit board structure is successful.
  • the embodiment of the present disclosure adopts a method of performing power-on testing on two boards that are bound together, and solves the problem that the related microscope observation method cannot observe the binding state between the non-transparent PCB board and the transparent FPC. Improves the detection efficiency of the test accuracy and the binding state between the boards.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
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Abstract

一种电路板结构、绑定测试方法及显示装置。该电路板结构包括第一电路板（1）、第二电路板（2）以及测试电路。测试电路用于测试第一电路板（1）和第二电路板（2）的对位情况，并且包括第一电极（12）、第二电极（13）和第三电极（22），第一电极（12）与第二电极（13）相互绝缘地设置在第一电路板（1）上，第三电极（22）设置在第二电路板（2）上。第一电路板（1）包括第一绑定区（11），第二电路板（2）包括第二绑定区（21），第一绑定区（11）用于与第二绑定区（21）相匹配，由一个第一电极（12）和一个第二电极（13）组成的组与一个第三电极（22）相匹配使得测试电路在通电情况下能够导通。

Description

电路板结构、绑定测试方法及显示装置
相关申请的交叉引用
本申请主张在2016年5月24日在中国提交的中国专利申请号No.201620505253.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其是涉及一种电路板结构、绑定测试方法及显示装置。
背景技术
在薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display(TFT LCD))模组工厂的生产中，Bonding(绑定)主要是将Panel(面板)和FPC(柔性电路板)，或将FPC和PCB(印刷电路板)通过ACF(异方性导电胶膜)按照一定的工作流程组合到一起并使其电导通，是TFT-LCD模组工厂普遍采用的工艺。
但是，对绑定状态的确认主要是通过显微镜进行观察。这种方法较为繁琐且作业效率较低，导致产能较低。目前，由于面板的基板是透明的，所以柔性电路板与面板之间的绑定状态是可以通过显微镜进行观察的。但对于非透明的印刷电路板，如何检测柔性电路板与印刷电路板之间的绑定状态成为亟待解决的技术问题。
发明内容
本公开的主要目的在于提供一种可以检测电路板之间的绑定状态且提高作业效率的技术方案。
为了达到上述目的，根据本公开的一个方面，提供了一种电路板结构。该电路板结构包括第一电路板、第二电路板和测试电路；所述第一电路板包括第一绑定区，所述第二电路板包括第二绑定区，所述第二绑定区与所述第一绑定区相匹配；所述测试电路用于测试所述第一电路板和所述第二电路板 的对位情况，并且包括多个第一电极、多个第二电极和多个第三电极，所述多个第一电极与所述多个第二电极相互绝缘地设置在所述第一电路板上，所述多个第三电极设置在所述第二电路板上；其中，由所述多个第一电极中的一个电极和所述多个第二电极中的一个电极组成的组与所述多个第三电极中的一个第三电极相匹配，使得所述测试电路在通电情况下能够导通。
可选地，所述第一绑定区包括多个第一连接片，所述第二绑定区包括多个第二连接片，所述第一连接片与所述第二连接片的个数相等且排列方式相同，在所述第一绑定区与所述第二绑定区成功匹配时，所述多个第一连接片中的每个第一连接片与所述多个第二连接片中对应的第二连接片彼此贴合。
可选地，所述多个第一电极的个数、所述多个第二电极的个数和所述多个第三电极的个数均为2。
可选地，所述多个第一电极和所述多个第二电极均位于所述第一绑定区的两侧，所述多个第三电极位于所述第二绑定区的两侧。
可选地，所述多个第二电极位于所述多个第一电极两侧。
可选地，所述多个第一电极和所述多个第二电极为条状导体。
可选地，所述多个第三电极中的每个为U字形导体。
可选地，所述测试电路还包括与所述多个第一电极中的每个连接的第一测试点，和与所述多个第二电极中的每个连接的第二测试点。
可选地，在由所述多个第一电极中的一个第一电极和所述多个第二电极中的一个第二电极组成的组中，所述第一电极和第二电极相互分离并且分别与所述多个第三电极中相匹配的所述一个可导电地连接。
可选地，所述第一电路板还包括多个第一对位区，所述第二电路板还包括多个第二对位区，在所述第一电路板与所述第二电路板成功绑定的状态下，所述多个第一对位区与所述多个第二对位区能够完全对合。
可选地，所述多个第一电极和所述多个第二电极位于所述多个第一对位区与所述第一绑定区之间，所述多个第三电极位于所述多个第二对位区与所述第二绑定区之间。
可选地，所述第一电路板为印刷电路板，所述第二电路板为柔性电路板，或者所述第一电路板和所述第二电路板均为印刷电路板，或者所述第一电路 板和所述第二电路板均为柔性电路板。
可选地，在所述第一电路板和所述第二电路板上分别设置第一对位区和与所述第一对位区相匹配的第二对位区。
根据本公开的另一个方面，提供了一种显示装置，该显示装置包括上述电路板结构。
根据本公开的再一个方面，提供了一种绑定测试方法，所述方法应用于权利要求1所述的电路板结构，所述方法包括：对由所述多个第一电极中的一个和所述多个第二电极中的一个组成的组通电；以及判断流过的电流的大小是否在预定电流范围内。
可选地，如果流过的电流为零或者明显小于预定电流，则判断所述电路板结构的绑定不成功；如果流过的电流在预定电流范围内，则判断所述电路板结构的绑定成功。
可选地，所述测试电路还包括与所述多个第一电极中的每个连接的第一测试点和与所述多个第二电极中的每个连接的第二测试点，其中通过所述第一测试点和所述第二测试点对由所述多个第一电极中的一个和所述多个第二电极中的一个组成的组通电。
与相关技术相比，本公开所述的电路板结构及显示装置，由于采用了通电测试的方式，因此解决了相关的显微镜观察方法无法观察到非透明PCB板与FPC之间的绑定状态的问题，而且这种测试方式的精度更高，同时可以提高薄膜晶体管液晶显示器的模组生产过程中的绑定检测效率。
附图说明
图1是根据本公开实施例的第一电路板的结构示意图；
图2是根据本公开实施例的第二电路板的结构示意图；
图3是根据本公开实施例的第一电路板和第二电路板在对合后、压合前沿图2的线A-A截取的剖面结构示意图；
图4是根据本公开实施例的在完成电路板绑定后的显示装置的组装示意图；以及
图5是根据本公开实施例的绑定测试方法的流程图。
具体实施方式
下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开的实施例，本领域的普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
为了达到上述目的，根据本公开的一个方面，提供了一种电路板结构。该电路板结构包括第一电路板、第二电路板和测试电路。该测试电路用于测试第一电路板和第二电路板的对位情况。该测试电路包括多个第一电极、多个第二电极和多个第三电极。多个第一电极与多个第二电极相互绝缘地设置在第一电路板上，多个第三电极设置在第二电路板上。第一电路板包括第一绑定区，第二电路板包括第二绑定区，其中第一绑定区与第二绑定区相匹配，由一个第一电极和一个第二电极组成的组与一个第三电极相匹配，使得测试电路在通电情况下能够导通。
相关的电路板结构中，待绑定的两个电路板之间的绑定区需要完全对接才算是两个电路板绑定成功。当前，当对两个透明的电路板之间的绑定状态进行检测时，由操作者直接使用显微镜进行观察。这样操作者直接通过视觉就可以判断出两个电路板之间的绑定区是否有错位现象发生。如果有错位则意味着绑定失败，如果没有错位则代表绑定成功。但是，缺少与非透明的电路板的绑定状态相对应的检测方式。
针对这种情况，在本公开提供的电路板结构中，在电路板上增加专门的测试电路来判断两个电路板之间是否绑定成功。在第一电路板上设置相互绝缘(也即处于断开状态)的第一电极和第二电极，在第二电路板上设置第三电极。由于第一电极和第二电极与第三电极在第一电路板和第二电路板绑定成功的状态下是完全匹配的(即不存在错位)，所以在通电状态下，电流会通过这三个电极而形成导电通路。如果测试采用的电压设定为标准值，则由于三个电极接触后的电阻大小取决于三者的对位情况，所以如果对位精确，则通过三个电极的电流大小是在预定电流范围内的。但如果存在错位，则不会有电流通过，或者电流明显小于预定电流。因此，采用这种在电路板上增设 测试电路的方式，可以精准地判断两种电路板是否对位成功(即绑定成功)。
作为可选实施方式，第一绑定区包括多个第一连接片，第二绑定区包括多个第二连接片，第一连接片的个数与第二连接片的个数相等且排列方式相同。在第一绑定区与第二绑定区绑定成功时，第一连接片与对应的第二连接片彼此贴合。
也就是说，为了构成电路板结构，在需要绑定的两个电路板上分别设置的两个绑定区中，连接片是用于传输数据的，即第一连接片与第二连接片之间需要进行数据交互。因此，第一连接片与第二连接片需要进行对应匹配设计，这样才便于绑定成功。绑定成功主要体现在二者之间不错位，而由于绑定工艺的特点，所以只要第一连接片和第二连接片不发生错位，贴合就基本不会发生问题。
需要说明的是，在实际应用中，第一连接片、第二连接片、第一电极、第二电极以及第三电极均可以采用金属制成，例如Cu。
在本公开的实施例中，第一电极的个数、第二电极的个数和第三电极的个数均为2，且多个第一电极和多个第二电极均位于第一绑定区的两侧，多个第三电极位于第二绑定区的两侧。也就是说，一个第一电极和一个第二电极可以作为第一组，将另一个第一电极和另一个第二电极可以作为第二组。例如，在实际应用过程中，在第一电路板上，将第一组设置在第一绑定区的左侧，并且可以将第二组设置在第一绑定区的右侧，并且第一组中的第一电极和第二电极的位置关系与第二组中的第一电极和第二电极的位置关系是相反的。例如，第一组中，第一电极位于第二电极的左侧，第二组中，第一电极位于第二电极的右侧；或者第一组中，第一电极位于第二电极的右侧，第二组中，第一电极位于第二电极的左侧。对应地，在第二电路板上，将一个第三电极设置在第二绑定区的左侧，将另一个第三电极设置在第二绑定区的右侧。
由于将由第一电极和第二电极构成的两个组以及相匹配的两个第三电极分别设置在两个电路板的两端位置，且绑定成功主要取决于是否发生错位，所以这样的设计可以更好地提高检测错位的精度，从而更便于获得绑定状态。
当然，这只是一种可选的设计方式，在实际应用中，为了提高检测精度， 还可以在绑定区的区域内设计类似的测试区，而且测试区的个数也可以是3个以上，或者也可以只是1个。对此，本公开实施例并不作出限定。
作为本公开的实施例的一个可选设计方式，第一电极和第二电极设计为条状导体。相应地，第三电极设计为U字形导体。当然，在实际应用中，第一电极和第二电极，第三电极的设计形状可以有很多种，本公开实施例对此并不作出任何限定，只要保证第一电极和第二电极之间为断开绝缘状态，第三电极为一体设计状态，就可以在三个电极处于绑定贴合状态时形成导通回路。
进一步地，测试电路还可以包括与第一电极连接的第一测试点，和与第二电极连接的第二测试点。这两个测试点的设计可以很好地满足测试的方便性要求。例如，用测试探针直接接触两个测试点，测试电流如果能够分别从两个测试点流进和流出，即可确定第一电极和第二电极与第三电极之间处于连接导通状态。
在实际应用中，第一电极和第二电极以及第三电极可以是完全新增加的设计，也可以是对相关的设计进行改进。针对后者，主要原因是在目前的电路板结构设计中，在电路板的绑定区内部或外部有时会存在一些并不需要传输数据的假连接片(其形状和材料与第一连接片和第二连接片的形状和材料相同)。在这种情况下，只需要对这些假连接片的形状进行改进设计即可。例如，将第一电路板上的两条假连接片分别做第一电极和第二电极，将第二电路板上的假连接片的底部形成连接状态，可得到大概呈U字形的第三电极。
在实际应用中，两个测试点的形状可以是圆形，半圆形，矩形，还可以是三角形，对此本公开的实施例不作出限定。
在本公开的实施例中，在对第一电路板和第二电路板进行绑定的过程中，为了帮助第一电路板和第二电路板进行对合，还可以在两个电路板上分别设置对应标志(Mark)。也就是说，第一电路板还可以包括第一对位区，第二电路板还可以包括第二对位区，第二对位区与第一对位区相匹配。在第一电路板与第二电路板绑定成功的状态下，第一对位区与第二对位区能够彼此对合。
作为本公开实施例的一个可选设计方式，第一电极与第二电极可以位于第一对位区与第一绑定区之间，第三电极可以位于第二对位区与第二绑定区 之间。
当然，在实际应用中，完全可以根据产品需求进行同等效果的改进设计。对此，本公开的实施例不做限定。
为便于理解，请参考图1至图3。图1是根据本公开实施例的第一电路板的结构示意图，图2是根据本公开实施例的第二电路板的结构示意图，图3是根据本公开实施例的第一电路板和第二电路板在对合后、压合前沿图2的线A-A截取的剖面结构示意图。
在本公开的实施例中，第一电路板可以为印刷电路板(PCB)，第二电路板可以为柔性电路板(FPC)。由于PCB是非透明的，FPC是透明或半透明的，因此上述电路板结构非常适合于由PCB和FPC匹配构成。应该理解，尽管本公开的实施例是以第一电路板为PCB、第二电路板为FPC为实施例描述的，但是本公开的实施例也完全适用于两个非透明的电路板之间或两个透明的电路板之间绑定状态的测试，例如两块PCB之间绑定状态的测试，或者两块FPC之间绑定状态的测试。
在图1和图2中，在第一电路板(如PCB)1上分别设计绑定区(即第一绑定区)11，两个第一电极12、两个第二电极13、两个对位区(即第一对位区)14、两个第一测试点15和两个第二测试点16，其中绑定区11位于中间，两个第一电极12及两个第二电极13依次分列第一绑定区11两侧且为条状的电极，两个第一对位区14位于两个第二电极13两侧。在第二电路板(如FPC)2上分别设计绑定区(即第二绑定区)21，两个第三电极22以及两个对位区(即两个第二对位区)23，其中第二绑定区21位于中间，两个第三电极22分列第二绑定区21两侧且为两个U形的电极。在对绑定状态进行检测的过程中，先利用第一对位区和第二对位区将第一电路板1与第二电路板2进行对合，再进行压合。此时利用测试点(即，第一测试点15和第二测试点16)对第一电极12和第二电极13以及第三电极22进行通电测试。如果导通，则代表第一绑定区中的所有第一连接片和第二绑定区中的所有第二连接片没有发生错位现象。通常压合过程不会产生不良，因此没有发生错位即表示第二电路板1与第二电路板2绑定成功。第一电路板1与第二电路板2绑定成功时的状态能够从图2所示的剖面结构中看出。在图3中，第一电路板1(如 PCB)的第一连接片17与第二电路板2(如FPC)的第二连接片24在绑定成功状态下是完全一一对应的，不存在任何错位现象。
在上述电路板结构的基础上，本公开实施例还提供了一种显示装置30，该显示装置30包括本公开的实施例的电路板结构。基于上述电路板结构的描述，不再对该显示装置30的具体构造进行详细说明。为便于理解，请参考图4，图4是根据本公开实施例的在完成电路板绑定后的显示装置30的组装示意图。应该理解，本公开的实施例的显示装置30中的第一电路板1和第二电路板2可以是非透明的印刷电路板PCB和透明的柔性电路板FPC，或者是两个非透明的电路板或两个透明的电路板。在本公开的实施例中，当将非透明的PCB和透明的FPC用作本公开的上述实施例的电路板结构时，对PCB和FPC之间的绑定状态进行测试的效率将大大提高，自然也就提高了将PCB、FPC、液晶面板3以及背光源4组装成液晶显示模组的组装效率，以得到绑定完好的显示装置。
图5是根据本公开实施例的绑定测试方法的流程图。图5所示的本公开的实施例所述的绑定测试方法应用于本公开上述的电路板结构。参考图5，该绑定测试方法包括步骤S1-S2。
S1：对由所述多个第一电极中的一个和所述多个第二电极中的一个组成的组通电。
S2：判断流过的电流的大小是否在预定电流范围内。如果流过的电流为零或者明显小于预定电流，则判断所述电路板结构的绑定不成功；如果流过的电流在预定电流范围内，则判断所述电路板结构的绑定成功。
本公开的实施例采用了对绑定在一起的两个电路板进行通电测试的方式，解决了相关的显微镜观察方法无法观察到非透明PCB板与透明的FPC之间的绑定状态的问题，提高了测试精度和电路板之间的绑定状态的检测效率。
以上是本公开的可选实施方式。应当指出，对于本领域的普通技术人员来说，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为包含在本公开的保护范围之内。

Claims (17)

  1. 一种电路板结构，包括：
    第一电路板，包括第一绑定区；
    第二电路板，包括第二绑定区，所述第二绑定区与所述第一绑定区相匹配；
    测试电路，用于测试所述第一电路板和所述第二电路板的对位情况并且包括多个第一电极、多个第二电极和多个第三电极，所述多个第一电极与所述多个第二电极相互绝缘地设置在所述第一电路板上，所述多个第三电极设置在所述第二电路板上，
    其中，由所述多个第一电极中的一个电极和所述多个第二电极中的一个电极组成的组与所述多个第三电极中的一个第三电极相匹配，使得所述测试电路在通电情况下能够导通。
  2. 根据权利要求1所述的电路板结构，其中，所述第一绑定区包括多个第一连接片，所述第二绑定区包括多个第二连接片，所述第一连接片与所述第二连接片的个数相等且排列方式相同，在所述第一绑定区与所述第二绑定区成功匹配时，所述多个第一连接片中的每个第一连接片与所述多个第二连接片中对应的第二连接片彼此贴合。
  3. 根据权利要求1或2所述的电路板结构，其中，所述多个第一电极的个数、所述多个第二电极的个数和所述多个第三电极的个数均为2。
  4. 根据权利要求3所述的电路板结构，其中，所述多个第一电极和所述多个第二电极均位于所述第一绑定区的两侧，所述多个第三电极位于所述第二绑定区的两侧。
  5. 根据权利要求4所述的电路板结构，其中，所述多个第二电极位于所述多个第一电极两侧。
  6. 根据权利要求1至5中任一项所述的电路板结构，其中，所述多个第一电极和所述多个第二电极为条状导体。
  7. 根据权利要求6所述的电路板结构，其中，所述多个第三电极中的每个为U字形导体。
  8. 根据权利要求6或7所述的电路板结构，其中，所述测试电路还包括与所述多个第一电极中的每个连接的第一测试点，和与所述多个第二电极中的每个连接的第二测试点。
  9. 根据权利要求6至8中任一项所述的电路板结构，其中，在由所述多个第一电极中的一个第一电极和所述多个第二电极中的一个第二电极组成的组中，所述第一电极和第二电极相互分离并且分别与所述多个第三电极中相匹配的所述一个可导电地连接。
  10. 根据权利要求1至9中任一项所述的电路板结构，其中，所述第一电路板还包括多个第一对位区，所述第二电路板还包括多个第二对位区，在所述第一电路板与所述第二电路板成功绑定的状态下，所述多个第一对位区与所述多个第二对位区能够完全对合。
  11. 根据权利要求10所述的电路板结构，其中，所述多个第一电极和所述多个第二电极位于所述多个第一对位区与所述第一绑定区之间，所述多个第三电极位于所述多个第二对位区与所述第二绑定区之间。
  12. 根据权利要求1至11中任一项所述的电路板结构，其中，所述第一电路板为印刷电路板，所述第二电路板为柔性电路板，或者
    所述第一电路板和所述第二电路板均为印刷电路板，或者
    所述第一电路板和所述第二电路板均为柔性电路板。
  13. 根据权利要求1至12中任一项所述的电路板结构，其中，在所述第一电路板和所述第二电路板上分别设置第一对位区和与所述第一对位区相匹配的第二对位区。
  14. 一种显示装置，包括根据权利要求1至13中任一项所述的电路板结构。
  15. 一种绑定测试方法，所述方法应用于权利要求1所述的电路板结构，所述方法包括：
    对由所述多个第一电极中的一个和所述多个第二电极中的一个组成的组通电；以及
    判断流过的电流的大小是否在预定电流范围内。
  16. 根据权利要求15所述的绑定测试方法，其中，如果流过的电流为零 或者明显小于预定电流，则判断所述电路板结构的绑定不成功；如果流过的电流在预定电流范围内，则判断所述电路板结构的绑定成功。
  17. 根据权利要求15所述的绑定测试方法，其中，所述测试电路还包括与所述多个第一电极中的每个连接的第一测试点和与所述多个第二电极中的每个连接的第二测试点，其中通过所述第一测试点和所述第二测试点对由所述多个第一电极中的一个和所述多个第二电极中的一个组成的组通电。
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