WO2019080577A1 - 静电保护电路、阵列基板及显示装置 - Google Patents

静电保护电路、阵列基板及显示装置

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Publication number
WO2019080577A1
WO2019080577A1 PCT/CN2018/098275 CN2018098275W WO2019080577A1 WO 2019080577 A1 WO2019080577 A1 WO 2019080577A1 CN 2018098275 W CN2018098275 W CN 2018098275W WO 2019080577 A1 WO2019080577 A1 WO 2019080577A1
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WIPO (PCT)
Prior art keywords
transistor
signal line
pole
array substrate
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/098275
Other languages
English (en)
French (fr)
Chinese (zh)
Inventor
龙春平
乔勇
吴新银
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to JP2019563387A priority Critical patent/JP7278965B2/ja
Priority to EP18865335.6A priority patent/EP3703125B1/en
Priority to US16/340,186 priority patent/US11495594B2/en
Publication of WO2019080577A1 publication Critical patent/WO2019080577A1/zh
Anticipated expiration legal-status Critical
Priority to US17/897,302 priority patent/US12100703B2/en
Priority to US18/783,487 priority patent/US20240379655A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/921—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H10D89/813—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements specially adapted to provide an electrical current path other than the field-effect induced current path
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements

Definitions

  • the present disclosure relates to an electrostatic protection circuit, an array substrate, and a display device.
  • the signal lines disposed on the array substrate of the display device become denser and denser, and the spacing between adjacent signal lines is also smaller and smaller, so that the adjacent signal lines are also more Defects such as leakage or short circuit caused by static electricity are prone to occur.
  • an electrostatic protection device connected to the signal line is disposed on the array substrate.
  • the electrostatic protection device in the related art generally includes a plurality of transistors and at least one electrostatic protection wire such as a common electrode wire or a short-circuit ring or the like. Each transistor can be respectively connected to a signal line and the static protection line to discharge static electricity generated on the signal line to the static protection line in time.
  • the electrostatic protection device in the related art needs to additionally arrange an electrostatic protection line on the array substrate, which results in a large space occupied by the electrostatic protection device, which is disadvantageous for the realization of the narrow bezel display panel.
  • the present disclosure provides an electrostatic protection circuit, an array substrate, and a display device.
  • the technical solutions are as follows:
  • an electrostatic protection circuit including: at least one first transistor and at least one second transistor; a gate and a first pole of the first transistor are connected to a first signal line, a second pole of the first transistor is connected to the second signal line; a gate and a first pole of the second transistor are connected to the second signal line, and a second pole of the second transistor is opposite to the first The signal line is connected; wherein the first signal line and the second signal line are any two adjacent signal lines on the array substrate.
  • the first transistor and the second transistor are thin film transistors; a gate of the first transistor is disposed in the same layer as the first signal line; a gate of the second transistor is The second signal line is set in the same layer.
  • the first transistor and the second transistor are thin film transistors; the first and second poles of the first transistor are disposed in the same layer as the first signal line; and the second transistor is The first pole and the second pole are disposed in the same layer as the second signal line.
  • the first transistor is a thin film transistor;
  • the first signal line includes a first wire and a second wire disposed in different layers, and a lead portion of the first wire passes through a via hole disposed in the lead region a lead portion of the second wire is connected;
  • a gate of the first transistor is formed by a lead portion of the first wire, and a first electrode of the first transistor is formed by a lead portion of the second wire
  • the second pole of the first transistor is formed by a lead portion of the second signal line.
  • the second transistor is a thin film transistor;
  • the second signal line includes a third wire and a fourth wire disposed in different layers, and a lead portion of the third wire passes through a via hole disposed in the lead region a lead portion of the fourth wire is connected;
  • a gate of the second transistor is formed by a lead portion of the third wire, and a first electrode of the second transistor is formed by a lead portion of the fourth wire
  • the second pole of the second transistor is formed by a lead portion of the first signal line.
  • the width to length ratio of the channel of each transistor is less than or equal to a quarter.
  • the orthographic projection of the channel of each transistor on the array substrate is a meandering serpentine shape.
  • an orthographic projection of a channel of the first transistor on the array substrate is located in an orthographic projection of the first signal line in the array substrate; a channel of the second transistor is in the array An orthographic projection on the substrate is located within the orthographic projection of the second signal line within the array substrate.
  • an orthographic projection of the first pole of the first transistor on the array substrate is located in an orthographic projection of the first signal line in the array substrate; a first pole of the second transistor is in the An orthographic projection on the array substrate is located in the orthographic projection of the second signal line in the array substrate.
  • an orthographic projection of at least one of the first pole and the second pole of each transistor near the end of the channel on the array substrate is triangular or trapezoidal, and a tip end of the triangle faces the channel,
  • the upper base of the trapezoid is adjacent to the channel with respect to the lower base.
  • the orthographic projection of the end of the transistor adjacent to the first pole on the array substrate is triangular or trapezoidal, the tip end of the triangle faces the first pole, and the upper base of the trapezoid is opposite to the bottom Adjacent to the first pole; and/or an orthographic projection of an end of each transistor near the second pole on the array substrate is triangular or trapezoidal, the tip of the triangle facing the second pole, the trapezoid
  • the upper base is adjacent to the second pole with respect to the lower base.
  • a method of fabricating an electrostatic protection circuit comprising:
  • the signal line is any two adjacent signal lines on the array substrate.
  • the first transistor and the second transistor are thin film transistors; a gate of the first transistor and the first signal line are formed by one patterning process; a gate of the second transistor is The second signal line is formed by one patterning process.
  • the first transistor and the second transistor are both thin film transistors; the first and second poles of the first transistor and the first signal line are formed by one patterning process; the second The first and second poles of the transistor and the second signal line are formed by one patterning process.
  • the first transistor is a thin film transistor;
  • the first signal line includes a first wire and a second wire formed on different layers, and a lead portion of the first wire passes through a via formed in the lead region a lead portion of the second wire is connected;
  • a gate of the first transistor is formed by a lead portion of the first wire, and a first electrode of the first transistor is formed by a lead portion of the second wire
  • the second pole of the first transistor is formed by a lead portion of the second signal line.
  • an array substrate comprising: the electrostatic protection circuit of the above aspect.
  • the array substrate is provided with a plurality of signal lines, and the electrostatic protection circuit is disposed between each two adjacent ones of the plurality of signal lines.
  • a display device comprising: the array substrate of the above aspect.
  • FIG. 1 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram of an electrostatic protection circuit according to an embodiment of the present disclosure
  • FIG. 3 is an equivalent circuit diagram of another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a flow chart of a method for manufacturing an electrostatic protection circuit according to an embodiment of the present disclosure.
  • the transistors employed in the embodiments of the present disclosure may all be thin film transistors, and the transistors employed in the embodiments of the present disclosure are mainly switching transistors according to the functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiments of the present disclosure, the source may be referred to as a first pole and the drain as a second pole. Alternatively, the source may be referred to as a second pole and the drain as a first pole. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • Embodiments of the present disclosure provide an electrostatic protection circuit that can be applied to an array substrate.
  • the electrostatic protection circuit can include at least one first transistor and at least one second transistor.
  • FIG. 1 is a schematic structural diagram of an electrostatic protection circuit according to an embodiment of the present disclosure.
  • 2 is an equivalent circuit diagram of an electrostatic protection circuit according to an embodiment of the present disclosure.
  • the first protection transistor M1 and a second transistor M2 may be included in the electrostatic protection circuit.
  • FIG. 3 is an equivalent circuit diagram of another electrostatic protection circuit according to an embodiment of the present disclosure. As shown in FIG. 3, the first protection transistor M1 and the two second transistors M2 may be included in the electrostatic protection circuit.
  • the gate 11 and the first pole 12 of the first transistor M1 are connected to the first signal line P1, and the second pole 13 of the first transistor M1 is connected to the second signal line P2.
  • the gate 21 and the first pole 22 of the second transistor M2 are connected to the second signal line P2, and the second pole 23 of the second transistor M2 is connected to the first signal line P1.
  • the first signal line P1 and the second signal line P2 may be any two adjacent signal lines on the array substrate.
  • the at least one first transistor M1 is turned on, and the first signal line P1 is connected to the second signal line P2, so that the static electricity generated on the first signal line P1 can be released.
  • the second signal line P2 Up to the second signal line P2.
  • the at least one second transistor M2 is turned on, and the second signal line P2 is connected to the first signal line P1, so that the second signal line P2 can be generated.
  • the static electricity is discharged to the first signal line P1. Thereby, it is possible to release the static electricity accumulated on the signal line to the adjacent signal line, thereby reducing the probability that the static electricity causes a defect such as a short circuit of the signal line.
  • the electrostatic protection circuit when the first protection transistor M1 and the second transistor M2 are included in the electrostatic protection circuit, the electrostatic protection circuit has a simple structure and a small occupied area.
  • the plurality of first transistors M1 and the plurality of second transistors M2 when one of the first transistors or a certain second transistor fails, the other transistors can also ensure that the electrostatic protection circuit works normally. Therefore, the reliability of the electrostatic protection circuit can be effectively improved.
  • the number of the first transistor and the second transistor in the electrostatic protection circuit can be flexibly selected according to the application requirements, which is not limited in the embodiment of the present disclosure.
  • the electrostatic protection circuit includes: at least one first transistor and at least one second transistor, the gate and the first pole of the first transistor are connected to the first signal line, and the first transistor is The two poles are connected to the second signal line.
  • the gate and the first pole of the second transistor are connected to the second signal line, and the second pole of the second transistor is connected to the first signal line. Therefore, when static electricity is generated on any one of the first signal line and the second signal line, the transistor connected to the static generating signal line can discharge the static electricity to the other signal line, thereby realizing effective static electricity. Release, thereby reducing the probability that static electricity will cause defects such as short circuits on the signal line.
  • the electrostatic protection circuit does not need to be additionally wired on the array substrate, and takes up less space, which is beneficial to the realization of the narrow bezel display panel.
  • the first transistor M1 and the second transistor M2 may both be thin film transistors.
  • the gate 11 of the first transistor M1 may be disposed in the same layer as the first signal line P1.
  • the gate 21 of the second transistor M2 can also be disposed in the same layer as the second signal line P2.
  • first pole 12 and the second pole 13 of the first transistor M1 may be disposed in the same layer as the first signal line P1.
  • the first pole 22 and the second pole 23 of the second transistor M2 may also be disposed in the same layer as the second signal line P2.
  • the gate 11 and the first pole 12 of the first transistor M1 are both part of the first signal line P1
  • the gate 21 and the first pole 22 of the second transistor M2 are both A portion of the second signal line P2. This can avoid extra space occupied by each transistor and improve the space utilization of the array substrate.
  • the electrostatic protection circuit provided by the embodiment of the present disclosure may be disposed in a non-display area of the array substrate.
  • it may be disposed in a lead region (also referred to as a fan-out region) of the array substrate, and the lead region is provided with lead portions of the respective signal lines.
  • the first signal line P1 may include a first wire P11 and a second wire P12 disposed in different layers.
  • the lead portion of the first wire P11 is connected to the lead portion of the second wire P12 through a via hole 14 provided in the lead portion.
  • a conductive layer 15 may be formed in the via hole 14.
  • the lead portion of the second wire P12 is connected to the conductive layer 15.
  • the conductive layer 15 is connected to the first wire P11, thereby implementing the second wire P12.
  • the conductive layer 15 may be made of indium tin oxide (ITO).
  • the gate 11 of the first transistor M1 may be formed by a lead portion of the first wire P11, and the first electrode 12 of the first transistor M1 may be formed by a lead portion of the second wire P12, and the second electrode 13 of the first transistor M1 It may be constituted by a lead portion of the second signal line P2.
  • the second signal line P2 may also include a third wire P21 and a fourth wire P22 disposed in different layers.
  • the lead portion of the third wire P21 is connected to the lead portion of the fourth wire P22 through a via hole 24 provided in the lead portion.
  • a conductive layer 25 (for example, an ITO layer) is formed in the via hole 24, and a lead portion of the fourth wire P22 is connected to the conductive layer 25, and the conductive layer 25 is connected to the third wire P21, thereby achieving the An effective connection of the four wires P22 to the third wire P21.
  • the gate 21 of the second transistor M2 may be formed by the lead portion of the third wire P21, the first electrode 22 of the second transistor M2 may be formed by the lead portion of the fourth wire P22, and the second electrode 23 of the second transistor may be It is composed of a lead portion of the first signal line P1.
  • the first wire P11 of the first signal line P1 and the third wire P21 of the second signal line P2 may be disposed in the same layer, and the second wire P12 of the first signal line P1 and the second wire
  • the fourth wire P22 of the signal line P2 may be disposed in the same layer.
  • the second electrode 13 of the first transistor M1 may be formed by the lead portion of the fourth wire P22
  • the second electrode 23 of the second transistor M2 may be formed by the lead portion of the second wire P12. .
  • the second wire P12 may be located on a side of the first wire P11 away from the array substrate, and the fourth wire P22 is also located on the third wire P21. Keep away from the side of the array substrate. If the transistors in the electrostatic protection circuit are transistors of a top gate structure, the second wire P12 may be located on a side of the first wire P11 adjacent to the array substrate, and the fourth wire P22 is also located on a side of the third wire P21 adjacent to the array substrate.
  • the relative positional relationship of the two segments of the wires in each of the signal lines can be adaptively adjusted according to the specific structure of the transistor, which is not limited in the embodiment of the present disclosure.
  • each of the wires in each of the signal lines may include a lead portion located in the lead region and a wire portion extending toward the peripheral region.
  • the first wire P11 of the first signal line P1 may include a lead portion P111 located in the lead region, and a wire portion extending to a peripheral region (eg, a crimp region, also referred to as a PAD region).
  • the second wire P12 may include a lead portion P121 located in the lead portion, and a wire portion P122 extending toward the peripheral region.
  • the third wire P21 of the second signal line P2 may include a lead portion P211 and a wire portion P212
  • the fourth wire P22 may include a lead portion P221 and a wire portion P222.
  • one of the wires of each of the signal lines may include a lead portion located in the lead region and a wire portion extending toward the peripheral region.
  • the other wire may include only the lead portion located in the lead region.
  • the first wire P11 of the first signal line P1 may include only the lead portion located in the lead region, and the second wire P12 may include the lead portion P121 located in the lead region, and A wire portion P122 in which the peripheral region extends.
  • the third wire P21 of the second signal line P2 may include only the lead portion, and the fourth wire P22 may include the lead portion P221 and the wire portion P222.
  • the first wire P11 of the first signal line P1 may include a lead portion P111 located in the lead region, and a wire portion P112 extending to the peripheral region; and the second wire P12 may include only The lead portion located in the lead area.
  • the third wire P21 of the second signal line P2 may include the lead portion P211 and the wire portion P212, and the fourth wire P22 includes only the lead portion.
  • the width to length ratio of the channel of each transistor may be less than or equal to a quarter.
  • the aspect ratio of the channel may refer to the ratio of the width of the channel to the length of the channel, and the leakage current of the transistor is proportional to the width to length ratio of the transistor channel, that is, the larger the aspect ratio of the channel, the transistor The leakage current is greater.
  • the leakage current of each transistor in the electrostatic protection circuit can be effectively reduced, that is, the output of each transistor is reduced to the phase.
  • the current of the adjacent signal line can effectively improve the electrostatic protection capability of the electrostatic protection circuit.
  • the orthographic projection of the channel of each transistor on the array substrate may be a curved serpentine shape. Therefore, when the channel width is constant, the length of the channel can be effectively increased, thereby effectively reducing the aspect ratio of the channel and reducing the leakage current of the transistor.
  • a top view of the channel of each transistor is shown in FIG. As can be seen from FIG. 1, the channel 16 of the first transistor M1 and the channel 26 of the second transistor M2 each have a meandering serpentine shape.
  • the orthographic projection of the channel 16 of the first transistor M1 on the array substrate can be located within the orthographic projection of the first signal line P1 within the array substrate.
  • the orthographic projection of the channel 26 of the second transistor M2 on the array substrate may also be located in the orthographic projection of the second signal line P2 within the array substrate.
  • the orthographic projection of the first pole 12 of the first transistor M1 on the array substrate may be located in the orthographic projection of the first signal line P1 in the array substrate.
  • the orthographic projection of the first pole 22 of the second transistor M2 on the array substrate may also be located in the orthographic projection of the second signal line P2 in the array substrate.
  • the transistor in the electrostatic protection circuit can be prevented from occupying too much space, effectively improving the space utilization ratio of the array substrate, and facilitating the narrow frame.
  • an orthographic projection of at least one of the first pole and the second pole of each transistor near the end of the channel on the array substrate may be triangular or trapezoidal, and the tip of the triangle Facing the channel, the upper base of the trapezoid is adjacent to the channel with respect to the lower base.
  • FIG. 7 is a schematic structural diagram of still another electrostatic protection circuit according to an embodiment of the present disclosure.
  • the orthographic projections of the first pole and the second pole of each transistor near the channel on the array substrate are all triangular, that is, the first pole and the second pole of each transistor are close to one end of the channel. They are all tip-shaped, so the leakage current when each transistor is turned on is small.
  • the orthographic projection of the channel of each transistor near the first pole on the array substrate may be triangular or trapezoidal, and the tip end of the triangle faces the first pole, and the upper base of the trapezoid is close to the bottom.
  • the first pole the orthographic projection of the channel of each transistor near the second pole on the array substrate may also be triangular or trapezoidal, and the tip end of the triangle faces the second pole, and the upper base of the trapezoid is close to the lower bottom.
  • the second pole thereby, the contact area of the transistor channel with the first pole and the contact area of the channel with the second pole can be further reduced, thereby further reducing the leakage current when the transistor is turned on.
  • the orthographic projection of the end of each transistor near the first pole on the array substrate, and the orthographic projection of the end near the second pole on the array substrate are triangular, thus each When the transistor is turned on, the leakage current is small, and the electrostatic protection circuit has a strong electrostatic protection capability.
  • the embodiments of the present disclosure provide an electrostatic protection circuit including at least one first transistor and at least one second transistor disposed between two adjacent signal lines, the first transistor capable of The static electricity generated by the first signal line is released to the second signal line, and the second transistor is capable of releasing the static electricity generated by the second signal line to the first signal line, thereby effectively avoiding defects such as short circuit caused by static electricity, and
  • the electrostatic protection circuit does not need to be additionally wired on the array substrate, and takes up less space, which is beneficial to the realization of the narrow bezel display panel.
  • FIG. 9 is a flowchart of a method of manufacturing an electrostatic protection circuit according to an embodiment of the present disclosure.
  • the method can be used to manufacture the electrostatic protection circuit provided by the above embodiments.
  • the method can include the following work process:
  • step 101 a substrate is provided.
  • the base substrate may be a transparent glass substrate.
  • step 102 at least one first transistor and at least one second transistor are formed on the base substrate.
  • the gate and the first pole of the first transistor are connected to the first signal line, and the second pole of the first transistor is connected to the second signal line.
  • the gate and the first pole of the second transistor are connected to the second signal line, and the second pole of the second transistor is connected to the first signal line.
  • the first signal line and the second signal line may be any two adjacent signal lines on the array substrate.
  • the first transistor and the second transistor in the electrostatic protection circuit may be thin film transistors.
  • the gate of the first transistor may be formed by the one-time patterning process with the first signal line.
  • the gate of the second transistor may be formed by the one-time patterning process with the second signal line.
  • the gates of the respective first transistors can be formed by one patterning process.
  • the first pole and the second pole of the first transistor may be formed by a patterning process with the first signal line.
  • the first and second poles of the second transistor may be formed by the one patterning process with the second signal line.
  • the first pole and the second pole of each transistor can be formed by one patterning process.
  • a metal thin film may be first formed on the substrate by magnetron sputtering or evaporation. The metal film can then be patterned using a photolithography process to form the gates of the individual transistors and the individual signal lines.
  • the lithography process may include steps of photoresist coating, exposure, development, etching, and photoresist stripping.
  • the material of the metal thin film may be a film layer formed of a low-resistance metal material, and may be, for example, molybdenum (Mo), aluminum (Al), aluminum-nickel alloy, chromium (Cr) or copper (Cu), titanium (Ti).
  • Mo molybdenum
  • Al aluminum
  • Al-nickel alloy chromium
  • Cu copper
  • Ti titanium
  • the first signal line may include a first wire and a second wire formed on different layers, and a lead portion of the first wire may be connected to a lead portion of the second wire through a via formed in the lead region.
  • a gate of the first transistor may be formed by a lead portion of the first wire
  • a first pole of the first transistor may be formed by a lead portion of the second wire
  • a second pole of the first transistor may be formed by the second signal line The lead portion is formed.
  • the second signal line may also include a third wire and a fourth wire disposed in different layers, and the lead portion of the third wire may pass through a via hole disposed in the lead region The lead portions of the fourth wire are connected.
  • a gate of the second transistor is formed by a lead portion of the third wire, a first electrode of the second transistor is formed by a lead portion of the fourth wire, and a second electrode of the second transistor is formed by a lead portion of the first signal line .
  • the materials forming the first and second poles of each transistor may be similar to the material forming the gate, and the manufacturing process of forming the first and second poles of each transistor may also be combined with forming the gate. The manufacturing process is similar and will not be described here.
  • An embodiment of the present disclosure provides an array substrate, which may include an electrostatic protection circuit as shown in any of FIGS. 1 to 8.
  • a plurality of signal lines may be disposed on the array substrate.
  • an electrostatic protection circuit can be disposed between every two adjacent signal lines of the plurality of signal lines. If a signal line is adjacent to two signal lines respectively, two transistors may be disposed in a region covered by the signal line, and the two transistors are respectively connected to an adjacent signal line.
  • a second transistor M2 and a first transistor M1 are disposed in a region covered by the second signal line P2.
  • the second transistor M2 is for connecting the first signal line P1 on the left side of the second signal line P2
  • the first transistor M1 is for connecting the signal line on the right side of the second signal line P2.
  • the gate connected to the electrostatically generated signal line can be turned on, and the static generated signal line is adjacent to the adjacent one.
  • the signal lines are connected to discharge static electricity to the adjacent signal lines. If the static electricity is discharged from the signal line that generates static electricity, the transistor whose gate is connected to the adjacent signal line can also be driven to turn on, thereby releasing the static electricity to another signal line until a certain signal line is released. The static electricity can no longer drive the transistor to turn on. Thereby, the effective release of static electricity on each signal line can be realized, and the probability that the signal line is leaky or short-circuited due to static electricity is reduced.
  • the signal lines on the array substrate may include any one of signal lines such as a gate line, a data line, a common electrode line, a clock signal line of the gate driving circuit, a test line of the array substrate, or a repair line.
  • the adjacent signal lines may be the same type of signal lines, or may be different types of signal lines, which are not limited by the embodiments of the present disclosure.
  • the embodiment of the present disclosure further provides a display device, which may include an array substrate, which may include an electrostatic protection circuit as shown in any of FIGS. 1 to 8.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like, or any product or component having a display function.

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Liquid Crystal (AREA)
PCT/CN2018/098275 2017-10-23 2018-08-02 静电保护电路、阵列基板及显示装置 Ceased WO2019080577A1 (zh)

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JP2019563387A JP7278965B2 (ja) 2017-10-23 2018-08-02 静電気保護回路及びその製造方法、アレイ基板、表示装置
EP18865335.6A EP3703125B1 (en) 2017-10-23 2018-08-02 Electrostatic protection circuit, array substrate, and display device
US16/340,186 US11495594B2 (en) 2017-10-23 2018-08-02 Electrostatic protection circuit and manufacturing method thereof, array substrate and display device
US17/897,302 US12100703B2 (en) 2017-10-23 2022-08-29 Electrostatic protection circuit and manufacturing method thereof, array substrate and display device
US18/783,487 US20240379655A1 (en) 2017-10-23 2024-07-25 Electrostatic protection circuit and manufacturing method thereof, array substrate and display device

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CN109698192B (zh) 2021-01-22
US12100703B2 (en) 2024-09-24
EP3703125A1 (en) 2020-09-02
US20210398970A1 (en) 2021-12-23
CN109698192A (zh) 2019-04-30
US11495594B2 (en) 2022-11-08
EP3703125B1 (en) 2023-11-22
US20240379655A1 (en) 2024-11-14
US20240072039A1 (en) 2024-02-29
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