WO2019061886A1 - 一种显示面板及其制作方法 - Google Patents

一种显示面板及其制作方法 Download PDF

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Publication number
WO2019061886A1
WO2019061886A1 PCT/CN2017/117972 CN2017117972W WO2019061886A1 WO 2019061886 A1 WO2019061886 A1 WO 2019061886A1 CN 2017117972 W CN2017117972 W CN 2017117972W WO 2019061886 A1 WO2019061886 A1 WO 2019061886A1
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Prior art keywords
layer
insulating layer
gate
interlayer insulating
display panel
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English (en)
French (fr)
Inventor
胡重粮
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/748,803 priority Critical patent/US20190393289A1/en
Publication of WO2019061886A1 publication Critical patent/WO2019061886A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the invention belongs to the technical field of display, and in particular relates to a display panel and a manufacturing method thereof.
  • AMOLED is a shorthand for English Active-matrix organic light emitting diode.
  • the full name of Chinese is active matrix organic light emitting diode or active matrix organic light emitting diode. Because active matrix organic light emitting diode (AMOLED) panel has a fast response speed, With high contrast and wide viewing angle, more and more applications are applied to terminals with display devices such as mobile terminals (such as mobile phones and tablet computers), televisions, car terminals, and personal computers. Display technology.
  • a buffer layer is generally formed on a substrate, and then a driving TFT, a gate insulating layer, an interlayer insulating layer are formed on the buffer layer by a deposition, a yellow light, an etching process, and then between the layers.
  • a flat layer, an anode, a pixel defining layer, and a photoresist spacer are sequentially formed on the insulating layer.
  • the present invention provides a method for fabricating a display panel.
  • the specific technical solutions are as follows:
  • a manufacturing method of a display panel comprising the following steps:
  • forming an active layer on the buffer layer is to deposit an amorphous silicon layer on the buffer layer, and performing molecular laser retreating treatment on the amorphous silicon layer, so that the amorphous silicon layer is crystallized and converted into polysilicon.
  • the layer is patterned by a yellow light or etching process to form a polysilicon layer, and then a source-drain contact region is formed on both ends of the polysilicon segment by a deposition, yellowing, or etching process.
  • the illuminating functional layer sequentially forms an anode, a second contact hole, a pixel defining layer and a photoresist spacer on the flat layer, and the anode is electrically connected to the source drain through the second contact hole.
  • the second interlayer insulating layer is an organic film layer
  • the material of the organic film layer is an organic material or an organic glue.
  • the distance between the source drain and the first gate is 0.15-0.5 ⁇ m, and the first gate and the second gate are parallel to each other, and the distance between them is 0.001-0.01 in the vertical direction. Mm.
  • the first gate insulating layer has a thickness of 0.1-0.15 ⁇ m
  • the second gate insulating layer has a thickness of 0.1-0.15 ⁇ m.
  • the first gate insulating layer has a thickness of 0.13 ⁇ m
  • the second gate insulating layer has a thickness of 0.12 ⁇ m.
  • the first interlayer insulating layer has a thickness of 0.4-0.6 ⁇ m
  • the second interlayer insulating layer has a thickness of 1.4-1.6 ⁇ m.
  • the first interlayer insulating layer has a thickness of 0.5 ⁇ m
  • the second interlayer insulating layer has a thickness of 1.5 ⁇ m.
  • the material of the first gate and the second gate is a combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the buffer layer is silicon nitride, silicon oxide or a combination of the two; the material of the first interlayer insulating layer is silicon oxide, silicon nitride or a combination of the two.
  • the material of the anode is an indium tin oxide/silver/silver oxide tin composite material.
  • the invention also provides a display panel, the display panel comprising:
  • a buffer layer disposed on the substrate
  • An active layer disposed on the buffer layer
  • a first gate insulating layer disposed on the buffer layer and covering the active layer
  • a first gate disposed on the first gate insulating layer, the first gate being directly above the active layer;
  • a second gate insulating layer disposed on the first gate insulating layer and covering the first gate
  • a second gate disposed on the second gate insulating layer, the second gate being located directly above the first gate
  • first interlayer insulating layer disposed on the second gate insulating layer and covering the second gate
  • a flat layer disposed on the first interlayer insulating layer and covering the source and drain electrodes and the second interlayer insulating layer;
  • the active layer includes a polysilicon segment and a source and drain contact region across the polysilicon segment.
  • the display area corresponds to a region of the removed second interlayer insulating layer directly above the active layer, corresponding to the blank area described above.
  • the second interlayer insulating layer is an organic film layer
  • the material of the organic film layer is an organic material or an organic glue.
  • the distance between the source drain and the first gate is 0.15-0.5 ⁇ m, and the first gate and the second gate are parallel to each other, and the distance between them is 0.001-0.01 in the vertical direction. Mm.
  • the first gate insulating layer has a thickness of 0.1-0.15 ⁇ m
  • the second gate insulating layer has a thickness of 0.1-0.15 ⁇ m.
  • the first gate insulating layer has a thickness of 0.13 ⁇ m
  • the second gate insulating layer has a thickness of 0.12 ⁇ m.
  • the first interlayer insulating layer has a thickness of 0.4-0.6 ⁇ m
  • the second interlayer insulating layer has a thickness of 1.4-1.6 ⁇ m.
  • the first interlayer insulating layer has a thickness of 0.5 ⁇ m
  • the second interlayer insulating layer has a thickness of 1.5 ⁇ m.
  • the light emitting functional layer is an anode, a second contact hole, a pixel defining layer and a photoresist spacer disposed on the flat layer, and the anode is electrically connected to the source drain through the second contact hole.
  • the invention provides a method for preparing a display panel.
  • a second interlayer insulating layer is deposited on the first interlayer insulating layer, and the second interlayer insulating layer is an organic film layer, which can serve as a buffering effect.
  • the display panel of the present invention has two gates, respectively a first gate and a second gate, and the two gates respectively function to control different pixel switches; but the above-mentioned increased organic film
  • the layer and the two gates improve the toughness and display effect of the display panel, the hole depth of the first contact hole is also increased. For this reason, the present invention forms the corresponding organic film layer region of the first contact hole in the step S8.
  • the second interlayer insulating layer is removed by the yellow light and etching process, so that the hole depth of the first contact hole is lowered, and then the deposition of the source and drain electrodes is prevented from being too long to cause breakage, because the source and drain electrodes
  • the metal itself is formed, and penetrates from the first gate insulating layer to the first interlayer insulating layer, and has a certain length to be easily broken, thereby reducing the hole depth of the first contact hole and reducing the formation of the source and drain electrodes. Difficulty.
  • FIG. 1 is a schematic cross-sectional view of a display panel manufactured by the present invention:
  • 10 is a substrate, 20 is a buffer layer, 30 is a first gate insulating layer, 40 is a second gate insulating layer, 50 is a first interlayer insulating layer, 60 is a second interlayer insulating layer, and 70 is a flat layer.
  • 80 is a pixel defining layer, 90 is an anode, 110 is a photoresist spacer, 301 is a source-drain contact region, 302 is a polysilicon segment, 304 is a first contact hole, 305 is a source drain, and 41 is a first gate.
  • 51 is a second gate
  • 91 is a second contact hole
  • 140 is a blank area.
  • FIG. 2 is a schematic view showing the second interlayer insulating layer corresponding to the upper side of the active layer by yellow light and etching.
  • FIG. 3 is a flow chart showing the manufacture of the display panel of the present invention.
  • FIG. 4 is a schematic cross-sectional view of a display panel without removing the second interlayer insulating layer corresponding to the active layer by yellow light and etching.
  • Figure 5 is an enlarged cross-sectional view showing a portion of the first contact hole of the panel of Figure 4;
  • FIG. 6 is a schematic view showing the first contact hole formed by yellow light and etching directly on the second interlayer insulating layer.
  • FIG. 1 is a schematic structural view of a display panel obtained by a manufacturing method according to a first embodiment of the present invention
  • FIG. 2 is a schematic view of removing a second interlayer insulating layer corresponding to an active layer by a yellow etching method.
  • FIG. 3 is a flowchart of a method for manufacturing a display panel according to a first embodiment of the present invention. The manufacturing method of the present invention comprises the following steps:
  • a substrate 10 is provided on which a buffer layer 20 is deposited.
  • An active layer (not shown) is formed on the buffer layer 20.
  • the active layer includes a polysilicon segment 301 and a source and drain contact region 302, and the source and drain contact regions 302 are located at both ends of the polysilicon segment 301.
  • S3 depositing a first gate insulating layer 30 on the active layer.
  • the first gate insulating layer 30 covers the active layer formed on the buffer layer 20 .
  • the first gate insulating layer 30 is in contact with the buffer layer 20 except for a region covering the active layer.
  • S4 depositing a first metal layer (not shown) on the first gate insulating layer 30, and patterning the first metal layer to form a first gate 41, the first gate 41 Located directly above the active layer, the plane in which the first gate 41 is located is substantially parallel to the plane in which the active layer is located, and is spaced apart from each other by a certain distance in the vertical direction.
  • S5 depositing a second gate insulating layer 40 on the first gate electrode 41, the second gate insulating layer 40 covering the first gate electrode 41.
  • the second gate insulating layer 40 is in contact with the first gate insulating layer except for a region covering the first gate electrode 41.
  • S6 depositing a second metal layer on the second gate insulating layer 40, and patterning the second metal layer to form a second gate 51.
  • the second gate is located directly above the first gate and is spaced apart from the first gate by a distance in a vertical direction.
  • S7 depositing a first interlayer insulating layer 50 on the second gate 51, the first interlayer insulating layer 50 covering the second gate 51.
  • the first interlayer insulating layer 50 is in contact with the second gate insulating layer except for a region covering the second gate.
  • a blank region 140 on the first interlayer insulating layer 50 forms a source and drain 305, and the source and drain electrodes 305 are electrically connected to the active layer through the first contact hole 304.
  • the source and drain electrodes 305 are electrically connected to the source and drain contact regions 302 of the active layer.
  • the illuminating function layer sequentially forms an anode 70, a second contact hole 91, a pixel defining layer 80, and a photoresist spacer 110 on the flat layer 70.
  • the anode 90 is electrically connected to the source and drain electrodes 305 through the second contact hole 91. .
  • two gates are formed, which are a first gate and a second gate, respectively, and the two gates respectively function to control different pixel switches.
  • the second interlayer insulating layer 60 is an organic film layer, and the material of the organic film layer is an organic material or an organic glue. It can act as a buffer and bond the upper and lower layers.
  • a second interlayer insulating layer is deposited on the first interlayer insulating layer, and the second interlayer insulating layer is an organic film layer, which functions as a buffering function and bonds the upper and lower layers.
  • the above-mentioned increased organic film layer and the two gate electrodes increase the toughness and display effect of the display panel, but also increase the hole depth of the first contact hole. For this reason, the present invention will form the first contact hole by the step S8.
  • the organic film layer region corresponding to the blank region 140 is removed by a yellow light or etching process, so that the hole depth of the first contact hole is lowered, and then the deposition of the source and drain electrodes is prevented from being too long to cause breakage, because the source
  • the drain itself is formed of a metal, and penetrates from the first gate insulating layer to the first interlayer insulating layer, and has a certain length to be easily broken, thereby reducing the hole depth of the first contact hole and also reducing the formation of the source and drain electrodes. The difficulty of the process. .
  • the active layer is formed on the buffer layer 20 in the S2, wherein an amorphous silicon layer is deposited on the buffer layer 20, and the amorphous silicon layer is subjected to molecular laser annealing treatment, so that the amorphous silicon layer is crystallized.
  • the polysilicon layer is patterned by a yellow light or etching process to form a polysilicon segment 302, and then a source/drain contact region 301 is formed on both ends of the polysilicon segment by a deposition, yellowing, or etching process.
  • the polysilicon section 302, the source and drain contact regions 301, the first gate 41 and the second gate 51, and the source and drain electrodes 305 constitute a driving TFT.
  • the distance between the source and drain electrodes 305 and the first gate electrode 41 is 0.15-0.5 ⁇ m, and the first gate electrode 41 and the second gate electrode 51 are parallel to each other, and are mutually perpendicular in the vertical direction.
  • the separation distance is 0.001-0.01 ⁇ m.
  • the first gate insulating layer 30 has a thickness of 0.1-0.15 ⁇ m
  • the second gate insulating layer 40 has a thickness of 0.1-0.15 ⁇ m.
  • the first gate insulating layer 30 has a thickness of 0.13 ⁇ m
  • the second gate insulating layer 40 has a thickness of 0.12 ⁇ m.
  • the first interlayer insulating layer 50 has a thickness of 0.4 to 0.6 ⁇ m
  • the second interlayer insulating layer 60 has a thickness of 1.4 to 1.6 ⁇ m.
  • the first interlayer insulating layer 50 has a thickness of 0.5 ⁇ m
  • the second interlayer insulating layer 60 has a thickness of 1.5 ⁇ m.
  • the material of the first gate electrode 41 and the second gate electrode 51 is a combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the buffer layer 20 is silicon nitride, silicon oxide or a combination of the two; the material of the first interlayer insulating layer 50 is silicon oxide, silicon nitride or a combination of the two.
  • the material of the anode 80 is an indium tin oxide/silver/silver oxide tin composite.
  • the present invention also provides a display panel.
  • the display panel includes:
  • the substrate 10 is provided on the buffer layer 20 on the substrate 10.
  • the material of the buffer layer 20 is silicon nitride, silicon oxide or a combination of the two.
  • the active layer is not shown in the drawing, and the active layer includes a polysilicon section 302, a channel region, and a source and drain contact region 301, and the source and drain contact regions 301 are located at both ends of the polysilicon segment 302.
  • a first gate insulating layer 30 is disposed on the buffer layer 20 and covers the active layer.
  • the material of the first gate insulating layer 30 may be a combination of one or more of molybdenum, titanium, aluminum, and copper.
  • a first gate electrode 41 is disposed on the first gate insulating layer 30, and a second gate insulating layer 40 is disposed on a portion of the first gate insulating layer 30 and covering the first gate electrode 41.
  • the second gate insulating layer 40 is in contact with the first gate insulating layer 30 except for a region covering the first gate electrode 41.
  • the material of the second gate insulating layer 40 is a combination of one or more of molybdenum, titanium, aluminum, and copper, and may be the same as or different from the material of the first gate insulating layer 30.
  • a second gate 51 is further disposed on the second gate insulating layer 40, and a portion of the second gate insulating layer 40 and covering the second gate 51 is provided with a first interlayer insulating layer 50. .
  • the first interlayer insulating layer 50 is in contact with the second gate insulating layer 40 except for a region covering the second gate 51.
  • the material of the first layer of the insulating layer 50 may be silicon oxide, silicon nitride or a combination of the two.
  • a source and a drain 305 are disposed on the first interlayer insulating layer 50.
  • the source and drain electrodes 305 are disposed between the source and drain contact regions 301 in the first contact hole 304, and the source and drain electrodes 305 pass through the first contact hole.
  • 304 is electrically connected to the source and drain electrodes 301 of the active layer.
  • the source and drain electrodes 305 penetrate from the first gate insulating layer to the first interlayer insulating layer.
  • the polysilicon section 302, the source/drain contact region 301, the first gate electrode 41 and the second gate electrode 51, and the source and drain electrodes 305 described above constitute a driving TFT.
  • a second interlayer insulating layer 60 is disposed on the non-display region on the first interlayer insulating layer 50 but not in the horizontal direction from the active layer. That is, the second interlayer insulating layer 60 is provided outside the blank region 140 (display region).
  • the second interlayer insulating layer 60 is an organic film layer, and the material of the organic film layer is an organic material or an organic glue, which can serve as a buffering function and bond the upper and lower layers.
  • a flat layer 70 is disposed on the first interlayer insulating layer 50 and overlying the source and drain electrodes 305 and the second interlayer insulating layer 60, and a light emitting functional layer disposed on the flat layer 70 (not shown) show).
  • the light emitting function layer is an anode 90, a second contact hole 91, a pixel defining layer 80 and a photoresist spacer 110 disposed on the flat layer 70, and the anode 90 passes through the second contact hole 91.
  • the source drain 305 is electrically connected.
  • the material of the anode 80 is an indium tin oxide/silver/silver oxide tin composite material
  • the flat layer 70 is a transparent resin material.
  • the distance between the source and drain electrodes 305 and the first gate electrode 41 is 0.15-0.5 ⁇ m, and the first gate electrode 41 and the second gate electrode 51 are parallel to each other, and are mutually perpendicular in the vertical direction.
  • the separation distance is 0.001-0.01 ⁇ m.
  • the first gate insulating layer 30 has a thickness of 0.1-0.15 ⁇ m
  • the second gate insulating layer 40 has a thickness of 0.1-0.15 ⁇ m.
  • the first gate insulating layer 30 has a thickness of 0.13 ⁇ m
  • the second gate insulating layer 40 has a thickness of 0.12 ⁇ m.
  • the first interlayer insulating layer 50 has a thickness of 0.4-0.6 ⁇ m
  • the second interlayer insulating layer 60 has a thickness of 1.4-1.6 ⁇ m.
  • the first interlayer insulating layer 50 has a thickness of 0.5 ⁇ m
  • the second interlayer insulating layer 60 has a thickness of 1.5 ⁇ m.
  • the TFT driving of the display panel of the present invention is provided with two gates, which are respectively a first gate and a second gate, and the two gates respectively function to control different pixel switches.
  • the first interlayer insulating layer of the display panel of the present invention is provided with a second interlayer insulating layer, and the second interlayer insulating layer may be an organic film layer, which can serve as a buffering function and bond the upper and lower layers.
  • the second interlayer insulating layer may be an organic film layer, which can serve as a buffering function and bond the upper and lower layers.
  • the present invention combines the corresponding organic film layer region of the first contact hole. The yellow hole and the etching process are removed, so that the hole depth of the first contact hole is lowered, and then the source and the drain are deposited to avoid the problem of being too long to be easily broken, and the hole depth of the first contact hole is lowered and reduced.
  • the process difficulty of forming the source and drain electrodes is improved, and the yield of the display panel is improved.
  • FIG. 4 is a schematic cross-sectional view of a display panel in which the second interlayer insulating layer corresponding to the active layer is removed by yellow light and etching. It can be seen that the depth of the first contact hole of FIG. 4 is deeper than the depth of the first contact hole of FIG. 5 is a cross-sectional enlarged view of a portion of the first contact hole of FIG. 1.
  • the thickness of the second interlayer insulating layer 60 is 1.5 ⁇ m
  • the thickness of the first interlayer insulating layer 50 is 0.5 ⁇ m
  • the thickness of the second gate insulating layer 40 is 0.12 ⁇ m
  • the thickness of the first gate insulating layer 30 is 0.13 ⁇ m.
  • the photomask film 130 is placed over the second interlayer insulating layer 60, and the first contact hole 304 is patterned to be irradiated by the light 120.
  • a first contact hole 304 is formed on the second interlayer insulating layer by etching.
  • the depth of the first contact hole 304 is the thickness of the fourth interlayer insulating layer 60, the first interlayer insulating layer 50, the second gate insulating layer 40, and the first gate insulating layer 30 is about 2.3 ⁇ m. .
  • the second interlayer insulating layer 60 passes through the yellow light and etching process corresponding to the region indicated by the blank region 140 above the active layer.
  • the thickness of the first contact hole is increased by the thickness of the first interlayer insulating layer 50, the second gate insulating layer 40, and the first gate insulating layer 30 by about 0.6 ⁇ m, which is relative to FIG.
  • the method reduces the depth of the first contact hole by 1.5 ⁇ m, about 65%, which greatly reduces the process difficulty, and at the same time, the depth of the first contact hole 304 is lowered, and the source and the drain of the deposited metal film are not easily broken. The problem has greatly improved the yield of the display panel.
  • the manufacturing method adopted by the invention ensures the toughness and display effect requirements of the display panel, reduces the process difficulty of forming the source and the drain, and ensures the yield rate.

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Abstract

一种显示面板的制作方法，在有源层上通过沉积、黄光、蚀刻制程制备两个栅极，在第一层间绝缘层（50）上沉积第二层间绝缘层（60），第二层间绝缘层（60）为有机膜层，可以起到缓冲作用和粘结上下层的作用，也增加第一接触孔（304）的孔深，在形成第一接触孔（304）的对应第二层间绝缘层（60）能通过黄光、蚀刻制程去掉，从而使第一接触孔（304）的孔深降低了，然后沉积形成源漏极（305）就避免了过长而导致易断裂的问题，将第一接触孔（304）的孔深降低同时也降低了形成源漏极（305）的工艺难度。本方案还提供一种显示面板。

Description

一种显示面板及其制作方法
本发明要求2017年9月30日递交的发明名称为“一种显示面板及其制作方法”的申请号2017109140612的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明属于显示技术领域，具体涉及一种显示面板及其制作方法。
背景技术
AMOLED是英文Active-matrix organic light emitting diode的简写，中文全称是有源矩阵有机发光二极体或主动矩阵有机发光二极体，由于有源矩阵有机发光二极管(AMOLED)面板具有反应速度较快、对比度高、视角较广等特点，因而越来越多的应用在便携式终端(例如，手机、平板电脑等)、电视机、车载终端、个人电脑等具有显示设备的终端上,被称为下一代显示技术。
目前在制备AMOLED的显示面板的工艺一般为在基板上形成缓冲层，然后依次在缓冲层上通过沉积、黄光、蚀刻制程形成驱动TFT和栅极绝缘层、层间绝缘层，然后在层间绝缘层上依次形成平坦层、阳极、像素定义层和光阻间隙物。本发明在现有工艺基础之上提供一种改进的工艺制程，提高良品率。
发明内容
为了提供一种改进的工艺制程和提高良品率的解决方案，本发明提供一种显示面板的制作方法，具体技术方案如下：
一种显示面板的制作方法,所述制造方法包括如下步骤:
S1：提供一基板,在该基板上沉积形成缓冲层；
S2：在缓冲层上形成有源层；
S3：在所述缓冲层上沉积形成第一栅极绝缘层，所述第一栅极绝缘层覆盖所述有源层；
S4：在所述第一栅极绝缘层上沉积并图案化第一金属层，形成第一栅极， 所述第一栅极位于有源层上方；
S5：在第一栅极上沉积第二栅极绝缘层，所述第二栅极绝缘层覆盖所述第一栅极；
S6：在所述第二栅极绝缘层上沉积并图案化第二金属层，形成第二栅极，所述第二栅极位于第一栅极上方；
S7：在所述第二栅极上沉积第一层间绝缘层，所述第一层间绝缘层覆盖所述第二栅极；
S8：在所述第一层间绝缘层上沉积第二层间绝缘层，然后通过黄光、蚀刻制程把对应于有源层上方的第二层间绝缘层蚀刻掉形成空白区，只保留空白区以外的第二层间绝缘层；
S9：在所述第一栅极绝缘层、第二栅极绝缘层和第一层间绝缘层上与所述有源层的两端对应的位置形成第一接触孔；
在所述第一层间绝缘层上的空白区形成源漏极，所述源漏极通过第一接触孔与有源层电连接；
S10：在所述第一层间绝缘层上并覆盖源漏极和第二层间绝缘层上形成平坦层；以及在所述平坦层上形成发光功能层。
优选的，所述S2步骤中在缓冲层上形成有源层是在缓冲层上沉积非晶硅层，并对非晶硅层进行分子激光退回处理，使得该非晶硅层结晶、转变为多晶硅层，并通过黄光、蚀刻制程对多晶硅层进行图案化处理，形成多晶硅段，接着通过沉积、黄光、蚀刻制程在多晶硅段两端形成源漏极接触区。
优选的，所述发光功能层在所述平坦层上依次形成的阳极、第二接触孔、像素定义层和光阻间隙物，所述阳极通过第二接触孔电连接源漏极。
优选的，所述第二层间绝缘层为有机膜层，所述有机膜层的材料为有机材料或者有机胶。
优选的，所述源漏极与第一栅极之间相互间隔的距离为0.15-0.5μm，所述第一栅极和第二栅极相互平行，在垂直方向上相互间隔距离为0.001-0.01μm。
优选的，所述第一栅极绝缘层的厚度为0.1-0.15μm，第二栅极绝缘层的厚度为0.1-0.15μm。
优选的，所述第一栅极绝缘层的厚度为0.13μm，第二栅极绝缘层的厚度为0.12μm。
优选的，所述第一层间绝缘层的厚度为0.4-0.6μm，第二层间绝缘层的厚度为1.4-1.6μm。
优选的，所述第一层间绝缘层的厚度为0.5μm，第二层间绝缘层的厚度为1.5μm。
优选的，所述第一栅极和第二栅极的材料为钼、钛、铝、铜中的一种或多种的组合。
优选的，所述缓冲层的材料为氮化硅、氧化硅或者两者的组合；所述第一层间绝缘层的材料为氧化硅、氮化硅或者两者的组合。
优选的，所述阳极的材料为氧化铟锡/银/氧化银锡复合材料。
本发明还提供一种显示面板，所述显示面板包括：
基板；
设于所述基板上的缓冲层；
设于所述缓冲层上的有源层；
设于所述缓冲层上并包覆所述有源层的第一栅极绝缘层；
设于所述第一栅极绝缘层上的第一栅极，所述第一栅极位于有源层正上方；
设于第一栅极绝缘层上并包覆所述第一栅极的第二栅极绝缘层；
设于第二栅极绝缘层上的第二栅极，所述第二栅极位于第一栅极正上方；
设于第二栅极绝缘层上并包覆所述第二栅极的第一层间绝缘层；
设于第一层间绝缘层上的源漏极；
在所述第一层间绝缘层上与有源层不重合的非显示区域上设置有第二层间绝缘层；
设于所述第一层间绝缘层上并包覆源漏极和第二层间绝缘层上的平坦层；
以及设于所述平坦层上的发光功能层。
所述有源层包括多晶硅段和多晶硅段两端的源漏极接触区。
所述显示区域对应于有源层正上方的去掉的第二层间绝缘层的区域，与上面所述的空白区对应。
优选的，所述第二层间绝缘层为有机膜层，所述有机膜层的材料为有机材料或者有机胶。
优选的，所述源漏极与第一栅极之间相互间隔的距离为0.15-0.5μm，所述第一栅极和第二栅极相互平行，在垂直方向上相互间隔距离为0.001-0.01μm。
优选的，所述第一栅极绝缘层的厚度为0.1-0.15μm，第二栅极绝缘层的厚度为0.1-0.15μm。
优选的，所述第一栅极绝缘层的厚度为0.13μm，第二栅极绝缘层的厚度为0.12μm。
优选的，所述第一层间绝缘层的厚度为0.4-0.6μm，第二层间绝缘层的厚度为1.4-1.6μm。
优选的，所述第一层间绝缘层的厚度为0.5μm，第二层间绝缘层的厚度为1.5μm。
优选的，所述发光功能层为设于所述平坦层上的阳极、第二接触孔、像素定义层和光阻间隙物，所述阳极通过第二接触孔电连接源漏极。
本发明的有益效果：本发明提供制备显示面板的方法在S8步骤中在第一层间绝缘层上沉积第二层间绝缘层，第二层间绝缘层为有机膜层，可以起到缓冲作用和粘结上下层的作用；本发明显示面板具有两个栅极，分别为第一栅极和第二栅极，两个栅极分别起到控制不同像素开关的作用；但上述增加的有机膜层和两个栅极虽然提高了显示面板的韧性和显示效果，但同时也增加第一接触孔的孔深，为此本发明通过在S8步骤中将形成第一接触孔的对应有机膜层区域(第二层间绝缘层)通过黄光、蚀刻制程去掉，从而使第一接触孔的孔深降低了，然后沉积形成源漏极就避免了过长而导致易断裂的问题，因为源漏极本身是金属形成的，而且从第一栅极绝缘层贯穿到第一层间绝缘层，具有一定的长度易断裂，因此将第一接触孔的孔深降低同时也降低了形成源漏极的工艺难度。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施 例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1本发明制造的显示面板的剖面示意图：
其中10为基板，20为缓冲层，30为第一栅极绝缘层，40为第二栅极绝缘层，50为第一层间绝缘层，60为第二层间绝缘层，70为平坦层，80为像素定义层，90为阳极，110为光阻间隙物，301为源漏极接触区，302为多晶硅段，304为第一接触孔，305为源漏极，41为第一栅极，51为第二栅极，91为第二接触孔，140为空白区。
图2为本发明先通过黄光、蚀刻去掉有源层对应上方的第二层间绝缘层的示意图。
图3为本发明显示面板的制造流程图。
图4为没有通过黄光、蚀刻去掉有源层对应上方的第二层间绝缘层的显示面板的剖面示意图。
图5为图4显示面板的第一接触孔部分剖面放大图。
图6为直接在第二层间绝缘层上通过黄光、蚀刻形成第一接触孔的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例
请参阅图1-图3，图1为本发明第一实施例制造方法得到的显示面板的结构示意图，图2为通过黄光蚀刻法去掉有源层对应上方的第二层间绝缘层的示意图，图3为本发明第一实施例提供一种显示面板的制造方法的流程图。本发明制造方法包括如下步骤:
S1：提供一基板10,在该基板10上沉积形成缓冲层20。
S2：在缓冲层20上形成有源层(图中未标识)。所述有源层包括多晶硅段301和源漏极接触区302，所述源漏极接触区302位于多晶硅段301的两端。
S3：在所述有源层上沉积形成第一栅极绝缘层30。所述第一栅极绝缘层30包覆所述形成于缓冲层20上的有源层。所述第一栅极绝缘层30除覆盖所述有源层以外的区域与缓冲层20相接触。
S4：在所述第一栅极绝缘层30上沉积形成第一金属层(图中未标识))，对第一金属层进行图案化以形成第一栅极41，所述第一栅极41位于有源层正上方，第一栅极41所在的平面与有源层所在的平面大致平行，且在垂直方向上相互间隔一定距离。
S5：在第一栅极41上沉积第二栅极绝缘层40，所述第二栅极绝缘层40包覆所述第一栅极41。所述第二栅极绝缘层40除覆盖所述第一栅极41以外的区域与第一栅极绝缘层相接触。
S6：在所述第二栅极绝缘层40上沉积形成第二金属层，对第二金属层进行图案化形成第二栅极51。所述第二栅极位于第一栅极的正上方，与第一栅极在垂直方向上相互间隔一定距离。
S7：在所述第二栅极51上沉积形成第一层间绝缘层50，所述第一层间绝缘层50包覆所述第二栅极51。所述第一层间绝缘层50除覆盖所述第二栅极以外的区域与第二栅极绝缘层相接触。
S8：在所述第一层间绝缘层50上沉积形成第二层间绝缘层60。然后通过黄光、蚀刻制程把对应于有源层上方的第二层间绝缘层区域去掉，形成空白区140，只保留空白区140以外的第二层间绝缘层60。
S9：在所述第一栅极绝缘层30、第二栅极绝缘层40和第一层间绝缘层50上与所述有源层的两端对应的位置形成第一接触孔304；
在所述第一层间绝缘层50上的空白区140形成源漏极305，所述源漏极305通过第一接触孔304与有源层电连接。所述源漏极305电连接于有源层的源漏极接触区302。
S10：在所述第一层间绝缘层50上并覆盖源漏极305和第二层间绝缘层60上形成平坦层70；以及在所述平坦层70上形成发光功能层(图中未示出)。所述发光功能层在所述平坦层70上依次形成的阳极70、第二接触孔91、像素 定义层80和光阻间隙物110，所述阳极90通过第二接触孔91电连接源漏极305。
在上述S4和S6步骤中形成两个栅极，分别为第一栅极和第二栅极，两个栅极分别起到控制不同像素开关的作用。
进一步的实施例，第二层间绝缘层60为有机膜层，所述有机膜层的材料为有机材料或者有机胶。可以起到缓冲作用和粘结上下层的作用。
在上述S8步骤中在第一层间绝缘层上沉积第二层间绝缘层，第二层间绝缘层为有机膜层，可以起到缓冲作用和粘结上下层的作用。但上述增加的有机膜层和两个栅极虽然提高了显示面板的韧性和显示效果，但同时也增加第一接触孔的孔深，为此本发明通过在S8步骤中将形成第一接触孔的对应空白区140的有机膜层区域通过黄光、蚀刻制程去掉，从而使第一接触孔的孔深降低了，然后沉积形成源漏极就避免了过长而导致易断裂的问题，因为源漏极本身是金属形成的，而且从第一栅极绝缘层贯穿到第一层间绝缘层，具有一定的长度易断裂，因此将第一接触孔的孔深降低同时也降低了形成源漏极的工艺难度。。
进一步的实施例，所述S2中在缓冲层20上形成有源层是在缓冲层20上沉积非晶硅层，并对非晶硅层进行分子激光退火处理，使得该非晶硅层结晶转变为多晶硅层，并通过黄光、蚀刻制程对多晶硅层进行图案化处理，形成多晶硅段302，接着通过沉积、黄光、蚀刻制程在多晶硅段两端形成源漏极接触区301。
所述多晶硅段302、源漏极接触区301、第一栅极41和第二栅极51和源漏极305构成驱动TFT。
进一步的实施例，所述源漏极305与第一栅极41之间相互间隔的距离为0.15-0.5μm，所述第一栅极41和第二栅极51相互平行，在垂直方向上相互间隔距离为0.001-0.01μm。
进一步的实施例，所述第一栅极绝缘层30的厚度为0.1-0.15μm，第二栅极绝缘层40的厚度为0.1-0.15μm。
进一步的实施例，所述第一栅极绝缘层30的厚度为0.13μm，第二栅极绝缘层40的厚度为0.12μm。
进一步的实施例，所述第一层间绝缘层50的厚度为0.4-0.6μm，第二层 间绝缘层60的厚度为1.4-1.6μm。
进一步的实施例，所述第一层间绝缘层50的厚度为0.5μm，第二层间绝缘层60的厚度为1.5μm。
进一步的实施例，所述第一栅极41和第二栅极51的材料为钼、钛、铝、铜中的一种或多种的组合。
进一步的实施例，所述缓冲层20的材料为氮化硅、氧化硅或者两者的组合；所述第一层间绝缘层50的材料为氧化硅、氮化硅或者两者的组合。
进一步的实施例，所述阳极80的材料为氧化铟锡/银/氧化银锡复合材料。
请再次参看图1，本发明还提供一种显示面板。所述显示面板包括：
基板10，设于所述基板10上的缓冲层20。所述缓冲层20的材料为氮化硅、氧化硅或者两者的组合。设于所述缓冲层20上的有源层。所述有源层在图中未示出，所述有源层包括多晶硅段302、沟道区和源漏极接触区301，所述源漏极接触区301位于多晶硅段302的两端。
设于所述缓冲层20上并包覆所述有源层的第一栅极绝缘层30。所述第一栅极绝缘层30的材料可以为钼、钛、铝、铜中的一种或多种的组合。
在所述第一栅极绝缘层30上设有第一栅极41，在第一栅极绝缘层30上并包覆所述第一栅极41的部分设有第二栅极绝缘层40。所述第二栅极绝缘层40除覆盖所述第一栅极41以外的区域与第一栅极绝缘层30相接触。第二栅极绝缘层40的材料为钼、钛、铝、铜中的一种或多种的组合，可以与第一栅极绝缘层30的材料相同或者不相同。
在所述第二栅极绝缘层40上还设置有第二栅极51，在第二栅极绝缘层40上并包覆所述第二栅极51的部分设有第一层间绝缘层50。所述第一层间绝缘层50除覆盖所述第二栅极51以外的区域与第二栅极绝缘层40相接触。第一层将绝缘层50的材料可以为氧化硅、氮化硅或者两者的组合。
在第一层间绝缘层50上设有源漏极305，所述源漏极305与源漏极接触区301之间设于第一接触孔304，所述源漏极305通过第一接触孔304与有源层的源漏极301电连接。源漏极305从第一栅极绝缘层贯穿到第一层间绝缘层。
上面所述多晶硅段302、源漏极接触区301、第一栅极41和第二栅极51和源漏极305构成驱动TFT。
在所述第一层间绝缘层50上但在水平方向上与有源层不重合的非显示区域上设置有第二层间绝缘层60。即在空白区140(显示区域)以外设有第二层间绝缘层60。所述第二层间绝缘层60为有机膜层，有机膜层的材料为有机材料或者有机胶，可以起到缓冲作用和粘结上下层的作用。
在所述第一层间绝缘层50上并包覆源漏极305和第二层间绝缘层60上设有平坦层70，以及设于所述平坦层70上的发光功能层(图中未示出)。
进一步的实施例中，所述发光功能层为设于所述平坦层70上的阳极90、第二接触孔91、像素定义层80和光阻间隙物110，所述阳极90通过第二接触孔91电连接源漏极305。所述阳极80的材料为氧化铟锡/银/氧化银锡复合材料，所述平坦层70为透明树脂材料。
进一步的实施例，所述源漏极305与第一栅极41之间相互间隔的距离为0.15-0.5μm，所述第一栅极41和第二栅极51相互平行，在垂直方向上相互间隔距离为0.001-0.01μm。
进一步的实施例，所述第一栅极绝缘层30的厚度为0.1-0.15μm，第二栅极绝缘层40的厚度为0.1-0.15μm。
进一步的实施例，所述第一栅极绝缘层30的厚度为0.13μm，第二栅极绝缘层40的厚度为0.12μm。
进一步的实施例，所述第一层间绝缘层50的厚度为0.4-0.6μm，第二层间绝缘层60的厚度为1.4-1.6μm。
进一步的实施例，所述第一层间绝缘层50的厚度为0.5μm，第二层间绝缘层60的厚度为1.5μm。
本发明显示面板的TFT驱动设有两个栅极，分别为第一栅极和第二栅极，两个栅极分别起到控制不同像素开关的作用。
本发明显示面板的第一层间绝缘层上设有第二层间绝缘层，第二层间绝缘层可以为有机膜层，可以起到缓冲作用和粘结上下层的作用。但上述增加的有机膜层和两个栅极虽然提高了显示面板的韧性和显示效果，但同时也增加第一接触孔的孔深，为此本发明将第一接触孔的对应有机膜层区域通过黄光、蚀刻制程去掉，从而使第一接触孔的孔深降低了，然后沉积形成源漏极就避免了过长而导致易断裂的问题，将第一接触孔的孔深降低同时也降低了形成源漏极的 工艺难度，提高显示面板的良品率。
对比实施例
为了便于理解本发明，在本实施例中还提供本发明的对比实施例用以说明本发明技术方案的发明构思和创新。如图4所述，图4是为没有通过黄光、蚀刻去掉有源层对应上方的第二层间绝缘层的显示面板的剖面示意图。可以看到，图4的第一接触孔的深度比图1的第一接触孔的深度要深。结合图5，图5是图1中的第一接触孔部分剖面放大图。其中第二层间绝缘层60的厚度为1.5μm，第一层间绝缘层50的厚度为0.5μm，第二栅极绝缘层40的厚度为0.12μm，第一栅极绝缘层30的厚度为0.13μm。
如果采用图6的方法进行黄光、蚀刻，如图6所示，将光罩膜130置于第二层间绝缘层60的上方，图案化形成第一接触孔304，通过光线120照射后，再通过蚀刻在第二层间绝缘层上形成第一接触孔304。此时第一接触孔304的深度为第二层间绝缘层60、第一层间绝缘层50、第二栅极绝缘层40、第一栅极绝缘层30四层厚度相加约为2.3μm。
但是如果采用本发明实施例的方法进行黄光、蚀刻，如图2所示，在第二层间绝缘层60对应于有源层的上方即空白区140所示的区域通过黄光、蚀刻制程去掉，此时第一接触孔的深度为第一层间绝缘层50、第二栅极绝缘层40、第一栅极绝缘层30三层厚度相加约为0.6μm，这相对于图6的方法将第一接触孔的深度减小了1.5μm，约65％，大大降低了工艺难度，同时由于降低了第一接触孔304的深度，在进行沉积金属薄膜形成源漏极时不容易发生断裂问题，大大提高了显示面板的良品率。
因此，本发明采用的制造方法即保证了显示面板的韧性和显示效果要求，又降低了形成源漏极的工艺难度，保证了良品率。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种显示面板的制作方法，其中，所述制造方法包括如下步骤:
    S1：提供一基板,在该基板上沉积形成缓冲层；
    S2：在缓冲层上形成有源层；
    S3：在所述缓冲层上沉积第一栅极绝缘层，所述第一栅极绝缘层覆盖所述有源层；
    S4：在所述第一栅极绝缘层上沉积并图案化第一金属层，形成第一栅极，所述第一栅极位于有源层正上方；
    S5：在第一栅极上沉积第二栅极绝缘层，所述第二栅极绝缘层覆盖所述第一栅极；
    S6：在所述第二栅极绝缘层上沉积并图案化第二金属层，形成第二栅极，所述第二栅极位于第一栅极正上方；
    S7：在所述第二栅极上沉积第一层间绝缘层，所述第一层间绝缘层覆盖所述第二栅极；
    S8：在所述第一层间绝缘层上沉积第二层间绝缘层，然后通过黄光、蚀刻制程把对应于有源层上方的第二层间绝缘层蚀刻掉形成空白区，只保留空白区以外的第二层间绝缘层；
    S9：在所述第一栅极绝缘层、第二栅极绝缘层和第一层间绝缘层上与所述有源层的两端对应的位置形成第一接触孔；
    在所述第一层间绝缘层上的空白区形成源漏极，所述源漏极通过第一接触孔与有源层电连接；
    S10：在所述第一层间绝缘层上并覆盖源漏极和第二层间绝缘层上形成平坦层；以及在所述平坦层上形成发光功能层。
  2. 如权利要求1所述的制造方法，其中，所述S2步骤中在缓冲层上形成有源层是在缓冲层上沉积非晶硅层，并对非晶硅层进行分子激光退火处理，使得该非晶硅层结晶、转变为多晶硅层，并通过黄光、蚀刻制程对多晶硅层进行图案化处理，形成多晶硅段，接着通过沉积、黄光、蚀刻制程在多晶硅段两端 形成源漏极接触区。
  3. 如权利要求1所述的制造方法，其中，所述第二层间绝缘层为有机膜层，所述有机膜层的材料为有机材料或者有机胶。
  4. 如权利要求1所述的制造方法，其中，所述第一栅极和第二栅极的材料为钼、钛、铝、铜中的一种或多种的组合。
  5. 一种显示面板，其中，所述显示面板包括：
    基板；
    设于所述基板上的缓冲层；
    设于所述缓冲层上的有源层；
    设于所述缓冲层上并包覆所述有源层的第一栅极绝缘层；
    设于所述第一栅极绝缘层上的第一栅极，所述第一栅极位于有源层正上方；
    设于第一栅极绝缘层上并包覆所述第一栅极的第二栅极绝缘层；
    设于第二栅极绝缘层上的第二栅极，所述第二栅极位于第一栅极正上方；
    设于第二栅极绝缘层上并包覆所述第二栅极的第一层间绝缘层；
    设于第一层间绝缘层上的源漏极；
    在所述第一层间绝缘层上与有源层不重合的非显示区域上设置有第二层间绝缘层；
    设于所述第一层间绝缘层上并覆盖源漏极和第二层间绝缘层上的平坦层；
    以及设于所述平坦层上的发光功能层。
  6. 如权利要求5所述的显示面板，其中，所述第二层间绝缘层为有机膜层，所述有机膜层的材料为有机材料或者有机胶。
  7. 如权利要求5所述的显示面板，其中，所述源漏极与第一栅极之间相互间隔的距离为0.15-0.5μm，所述第一栅极和第二栅极在相互平行，在垂直 方向上相互间隔距离为0.001-0.01μm。
  8. 如权利要求5所述的显示面板，其中，所述第一栅极绝缘层的厚度为0.1-0.15μm，第二栅极绝缘层的厚度为0.1-0.15μm。
  9. 如权利要求5所述的显示面板，其中，所述第一层间绝缘层的厚度为0.4-0.6μm，第二层间绝缘层的厚度为1.4-1.6μm。
  10. 如权利要求5所述的显示面板，其中，所述发光功能层为设于所述平坦层上的阳极、第二接触孔、像素定义层和光阻间隙物，所述阳极通过第二接触孔电连接源漏极。
PCT/CN2017/117972 2017-09-30 2017-12-22 一种显示面板及其制作方法 Ceased WO2019061886A1 (zh)

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108962946B (zh) * 2018-06-29 2020-06-16 武汉华星光电半导体显示技术有限公司 显示面板及其制造方法
CN109065583B (zh) * 2018-08-06 2020-10-16 武汉华星光电半导体显示技术有限公司 柔性显示面板的制造方法及柔性显示面板
CN109065616B (zh) 2018-08-06 2022-01-04 武汉华星光电半导体显示技术有限公司 柔性显示面板及制造方法
CN109285872A (zh) * 2018-10-18 2019-01-29 武汉华星光电半导体显示技术有限公司 有机自发光二极管显示面板及其制作方法
KR102620972B1 (ko) * 2018-10-23 2024-01-05 삼성디스플레이 주식회사 디스플레이 장치
CN109638021B (zh) * 2018-12-11 2020-09-08 深圳市华星光电技术有限公司 柔性tft基板的制作方法及柔性oled面板的制作方法
CN109638054B (zh) * 2018-12-18 2020-11-24 武汉华星光电半导体显示技术有限公司 显示面板及制作方法
CN110391255B (zh) * 2019-07-23 2021-04-02 武汉华星光电半导体显示技术有限公司 一种tft阵列基板、其制备方法及其显示面板
CN110534530A (zh) * 2019-08-15 2019-12-03 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN110649068A (zh) * 2019-09-02 2020-01-03 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制备方法
CN110690226B (zh) * 2019-09-03 2021-06-01 武汉华星光电半导体显示技术有限公司 阵列基板和显示面板
CN111769142B (zh) * 2020-06-23 2022-07-12 武汉华星光电半导体显示技术有限公司 一种显示面板及其制备方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050179829A1 (en) * 2002-04-15 2005-08-18 Samsung Sdi Co., Ltd. Flat panel display with black matrix and method of fabricating thereof
CN1851901A (zh) * 2006-04-28 2006-10-25 友达光电股份有限公司 有机发光二极管面板的制作方法
US20090009440A1 (en) * 2001-11-29 2009-01-08 Genshiro Kawachi Display device including an organic el device
CN104966718A (zh) * 2015-05-04 2015-10-07 深圳市华星光电技术有限公司 Amoled背板的制作方法及其结构
CN106158882A (zh) * 2016-09-27 2016-11-23 厦门天马微电子有限公司 一种显示装置、显示面板、阵列基板及其制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4662647B2 (ja) * 2001-03-30 2011-03-30 シャープ株式会社 表示装置及びその製造方法
JP2005072144A (ja) * 2003-08-21 2005-03-17 Seiko Epson Corp 薄膜半導体装置及びその製造方法、電気光学装置、並びに電子機器
US7582904B2 (en) * 2004-11-26 2009-09-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device and method for manufacturing thereof, and television device
CN101387799B (zh) * 2007-09-13 2011-04-13 北京京东方光电科技有限公司 液晶显示器基板、液晶显示器及制造方法
US8748892B2 (en) * 2009-10-09 2014-06-10 Lg Display Co., Ltd. Thin film transistor and method for fabricating the same
TWI549289B (zh) * 2014-02-26 2016-09-11 友達光電股份有限公司 有機發光顯示面板及其製作方法
KR102364387B1 (ko) * 2014-07-04 2022-02-18 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102223900B1 (ko) * 2014-07-10 2021-03-05 엘지디스플레이 주식회사 유기 발광 다이오드 표시 장치 및 이의 제조 방법
CN104538429B (zh) * 2014-12-26 2019-07-02 深圳市华星光电技术有限公司 Amoled背板的制作方法及其结构
CN104867961B (zh) * 2015-04-24 2020-06-30 京东方科技集团股份有限公司 阵列基板、其制造方法及显示装置
KR102456061B1 (ko) * 2015-10-08 2022-10-18 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102500161B1 (ko) * 2016-01-15 2023-02-16 삼성디스플레이 주식회사 유기 발광 표시 장치
CN106024838B (zh) * 2016-06-21 2019-04-30 武汉华星光电技术有限公司 基于混合tft结构的显示元件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090009440A1 (en) * 2001-11-29 2009-01-08 Genshiro Kawachi Display device including an organic el device
US20050179829A1 (en) * 2002-04-15 2005-08-18 Samsung Sdi Co., Ltd. Flat panel display with black matrix and method of fabricating thereof
CN1851901A (zh) * 2006-04-28 2006-10-25 友达光电股份有限公司 有机发光二极管面板的制作方法
CN104966718A (zh) * 2015-05-04 2015-10-07 深圳市华星光电技术有限公司 Amoled背板的制作方法及其结构
CN106158882A (zh) * 2016-09-27 2016-11-23 厦门天马微电子有限公司 一种显示装置、显示面板、阵列基板及其制作方法

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