WO2019041921A1 - 可折叠阵列基板及其制备方法、显示装置 - Google Patents
可折叠阵列基板及其制备方法、显示装置 Download PDFInfo
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- WO2019041921A1 WO2019041921A1 PCT/CN2018/088958 CN2018088958W WO2019041921A1 WO 2019041921 A1 WO2019041921 A1 WO 2019041921A1 CN 2018088958 W CN2018088958 W CN 2018088958W WO 2019041921 A1 WO2019041921 A1 WO 2019041921A1
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/326—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor the printed circuit having integral resilient or deformable parts, e.g. tabs or parts of flexible circuits
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to the field of foldable display technologies, and in particular to a foldable array substrate, a method of fabricating the same, and a display device.
- Flexible foldable displays such as OLED displays, offer users a new visual experience. However, after repeated bending of such a display, it is easy to cause a device failure phenomenon, thereby affecting the display.
- the current solution is to perform wire change processing between pixel units, that is, to use a wire with better bending resistance to improve the bending resistance of the device.
- this scheme is not suitable for flexible displays with high pixel density (high PPI).
- the embodiments of the present invention provide a foldable array substrate, a preparation method thereof, and a display device, which can improve the bending resistance of the foldable array substrate by reducing the stress.
- the foldable array substrate includes a base substrate, a gate metal layer disposed on one side of the base substrate, a source/drain metal layer disposed on an opposite side of a side of the gate metal layer on which the base substrate is located, and a setting An insulating layer between the gate metal layer and the source/drain metal layer, the gate metal layer includes a gate line, the source/drain metal layer includes a data line, and the gate line and the data line are disposed at intersection
- the foldable array substrate being provided with a hole, the hole not being disposed in the pixel unit, the hole being from the substrate of the insulating layer
- the opposite side of the side on which the substrate is located extends toward the base substrate.
- the foldable array substrate includes a predetermined puncturing area between two rows of pixel units adjacent to each other and/or between two columns of pixel units adjacent to each other, the holes being disposed in the The preset punching area.
- the predetermined perforated area has a width in the range of 2 microns to 10 microns.
- the apertures include at least a first type of apertures that do not intersect the metal of each metal layer of the foldable array substrate.
- the first type of aperture extends from the opposite side of the side of the insulating substrate from the side of the substrate to the substrate.
- the foldable array substrate further includes a buffer layer disposed on the one side of the base substrate and in contact with the base substrate, the first type of holes from the insulating layer The opposite side of the side on which the base substrate is located extends toward the base substrate to the buffer layer.
- the hole further includes a second type of hole extending from an opposite side of the side of the insulating substrate on the side of the substrate to a metal trace in the gate metal layer .
- the foldable array substrate further includes at least two rows of pixel units adjacent to each other, and between the two rows of pixel units, the holes include a first hole extending along a length of the gate line groove.
- the foldable array substrate further includes a buffer layer disposed on the one side of the base substrate and in contact with the base substrate, the first hole from the insulating layer The opposite side of the side on which the base substrate is located extends to the buffer layer.
- the aperture further includes a plurality of apertures extending along a length of the data line.
- the plurality of holes extend from opposite sides of the side of the insulating substrate to the buffer layer.
- the foldable array substrate further includes at least two columns of pixel units adjacent to each other, and between the two columns of pixel units, the holes include a second hole extending along a length of the data line groove.
- the second hole trench includes a portion extending from an opposite side of a side of the insulating substrate on which the substrate substrate is located to a portion of the buffer layer and a portion extending to the gate line.
- the foldable array substrate further includes a capacitor layer between the gate metal layer and the source/drain metal layer, the insulating layer including the capacitor layer and the source/drain metal a first insulating layer between the layers and a second insulating layer disposed between the capacitor layer and the gate metal layer.
- the material of the insulating layer comprises an inorganic silicon material.
- the inorganic silicon material comprises at least one of silicon oxide and silicon nitride.
- Another aspect of the present invention provides an OLED display device including the above-described foldable array substrate.
- Still another aspect of the present invention provides a method of fabricating a foldable array substrate, comprising: forming an active layer pattern, a gate metal layer pattern, and an insulating layer on one side of a base substrate, wherein the gate metal layer pattern includes a gate a hole extending from a side opposite to a side of the base substrate of the insulating layer toward a direction of the base substrate, wherein the hole is not formed in the pixel unit and does not intersect the pixel unit.
- the forming a hole extending from a side opposite to a side of the underlying substrate of the insulating layer toward the substrate includes: at least one pair of two rows of pixel cells adjacent to each other A first hole extending along a length direction of the gate line is formed therebetween.
- forming a source/drain metal layer pattern after forming a hole extending from a side opposite to a side of the substrate of the insulating layer toward the substrate includes a data line, and the hole extending from a side opposite to a side of the insulating substrate on which the substrate substrate is located further includes at least one pair adjacent to each other A second hole extending along the length direction of the data line is formed between the two columns of pixel units.
- the foldable array substrate and the OLED display device provided by the embodiments of the present invention effectively improve the stress concentration phenomenon by punching holes outside the pixel unit of the foldable array substrate, thereby improving the bending resistance of the device.
- FIG. 1a is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
- FIG. 1b is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
- FIG. 2 is a cross-sectional view of the array substrate of FIG. 1a taken along the A-A direction.
- FIG. 3 is a cross-sectional view of the array substrate of FIG. 1a taken along line B-B.
- FIG. 4 is a flow chart of preparing an array substrate according to an embodiment of the present invention.
- FIG. 5 is a flow chart of preparing an array substrate according to an embodiment of the present invention.
- the array substrate includes a base substrate 100, a gate metal layer disposed on one side of the base substrate 100, and a source/drain metal layer disposed on the opposite side of the side of the base substrate 100 of the gate metal layer. And an insulating layer disposed between the gate metal layer and the source/drain metal layer.
- the gate metal layer includes a gate line 101
- the source/drain metal layer includes a data line 103
- the gate line 101 and the data line 103 are disposed to intersect to define a plurality of pixel units on the base substrate 100.
- the array substrate is provided with holes extending from the opposite side of the side on which the base substrate 100 of the insulating layer is located toward the side of the base substrate 100 (not shown). Those skilled in the art will recognize that the holes do not intersect the pixel elements.
- the present invention can effectively alleviate the stress in the array substrate and improve the bending resistance.
- the insulating layer of the foldable array substrate may be, for example, an inorganic insulating material.
- the inorganic insulating material may be an inorganic silicon material, and specifically, may be silicon nitride or silicon oxide.
- the array substrate is liable to cause device failure due to stress concentration of the film layer of the array substrate when bent.
- the stress occurring in the insulating layer can be effectively dispersed, and the bending resistance of the device can be improved.
- the holes extend from the opposite side of the side where the base substrate of the insulating layer is located toward the base substrate, but do not intersect the area defined by the respective pixel units. That is to say, these holes need to avoid the pixel unit of the array substrate to avoid affecting the display effect.
- the substrate of the embodiment of the present invention may be, for example, a flexible substrate in order to obtain a foldable array substrate.
- the holes can be distributed in an array.
- a plurality of holes are disposed around one pixel unit to separate the pixel unit from its adjacent pixel unit, so that the pixel unit forms an "island" structure, improving the stress dispersion effect.
- a plurality of holes may be disposed around several pixel units to separate the pixel units from the periphery to improve the stress dispersion effect.
- the sizes of the holes may be different from each other depending on the size and resolution of the screen.
- the holes may range in size from 2 um to 20 um.
- the larger the size of a single hole the better the stress dispersion effect, and the less difficult the process to prepare a smaller number of holes.
- the size of the pores can be further limited to between 5 um and 10 um, so that the stress can be better reduced, the performance of the array substrate can be improved, and the process difficulty of punching is not excessively increased.
- the shape of the cross section perpendicular to the axis of each hole may be different, for example, the shape of the cross section may be square, elliptical, circular or polygonal.
- the shape of the cross section of the hole may include at least two of a square, a circle, an ellipse, and a polygon.
- Different stress dispersion effects can be obtained by providing holes of different shapes in the array substrate. That is, the stress dispersion property can be further improved by the cooperation between the holes having different shapes.
- the holes may also be structures whose dimensions vary along their axial direction.
- the cross section of the circular hole may be a structure whose diameter gradually becomes smaller in a direction from the opposite side of the side of the base substrate on which the circular hole is located toward the side where the base substrate is located.
- the axial direction of the holes may extend in a direction at an angle to a direction perpendicular to the array substrate, for example, the angle may be 5 to 10 . Therefore, the metal traces of the metal layers of the array substrate can be effectively avoided, and the holes are further extended toward the array substrate to improve the performance of the array substrate.
- the two rows of pixel units adjacent to each other of the array substrate may include a predetermined puncturing area, and the holes may be disposed in the predetermined puncturing area. That is to say, when designing an array substrate (especially an array substrate with a high PPI), it is possible to artificially leave a certain area between two adjacent rows of pixels, which can be used for punching to better eliminate the array. The stress of the substrate. Generally, for a high PPI array substrate, if the preset punching area is not reserved, the punching difficulty is very large due to the limitation of the punching process. Therefore, the circuit of the pixel unit can be designed to be more compact without reducing the size of the pixel unit, so that the preset punched area can be reserved without affecting the display effect.
- the orthographic projection of the predetermined punctured area on the array substrate may not coincide with the metal trace and the TFT switch.
- the width of the predetermined perforated area (the size in the column direction) may be in the range of 2 um to 10 um, thereby ensuring the circuit safety of the pixel unit on the one hand and ensuring the punching on the other hand. Going smoothly.
- the size of the hole to be punched is large, the internal stress of the array substrate can be significantly reduced, and the bending resistance of the array substrate can be improved.
- a preset puncturing area may be reserved between adjacent two columns of pixel units of the array substrate.
- the width of the predetermined punched area (the size in the row direction) may be in the range of 2 um to 10 um, so that the array substrate has the effect as described above after punching.
- the pre-punched area is preferably a metal-free area, so that the bending resistance of the array substrate can be effectively improved without affecting the electrical performance of the array substrate.
- the apertures can include a first type of aperture.
- the first type of holes do not intersect the metal traces of the gate metal layer and the metals of the other metal layers in the array substrate.
- the first type of holes can avoid the metal present in each metal layer to extend toward the substrate substrate to the greatest extent.
- the first type of holes can extend to the vicinity of the array substrate.
- the first type of holes may also be inclined holes.
- the array substrate further includes a buffer layer 110 disposed on the one side of the base substrate 100 and in contact with the base substrate 100.
- the first type of holes are insulated from the substrate.
- the opposite side of the side of the base substrate 100 of the layer 113 extends toward the base substrate 100 to the buffer layer 110.
- a dry etching method or a wet etching method may be employed.
- a dry etching method or a wet etching method may also etch a portion of the buffer layer 110.
- the holes may further include a second type of holes extending from the opposite side of the side of the insulating substrate 113 on which the base substrate 100 is located toward the base substrate 100 to the gate line 101.
- the second type of holes may also extend from the opposite side of the side of the base layer 100 of the insulating layer 113 toward the substrate substrate 100 to the traces of the other metal layers (the source and drain metal layers are formed after the formation of the insulating layer, and thus Other layers at the location may not include source/drain metal layers, such as metals in the capacitive layer of the array substrate of the OLED display device.
- a metal layer exists between the insulating layer and the substrate, it may be in the process of punching. Will encounter the traces of these metal layers.
- punching by dry or wet etching if the traces of these metal layers are encountered, for example, the etching operation can be stopped to prevent the normal operation of the array substrate from being affected by etching off the gate lines or other metal traces.
- the depth of such holes is relatively small, macroscopically, these shallower holes also increase the total number of holes, thereby improving the stress dispersion effect.
- the array substrate includes at least two rows of pixel cells adjacent to each other.
- the aperture includes a first aperture 10 extending along the length of the gate line 101 (the puncturing location may be, for example, a grid-like hatching as shown in FIG. 1a) The range defined by the rectangle).
- the puncturing location may be, for example, a grid-like hatching as shown in FIG. 1a
- the range defined by the rectangle For example, in the preparation process, holes may be drilled in a row between two adjacent rows of pixel units, and then the source and drain metal layers will raise the first hole 10 when the sputtering source leaks the metal layer.
- the source/drain metal layers sputtered on the array substrate are substantially the same, and after the sputtering source drains the metal layer, the first holes 10 arranged along the length direction of the gate line 101 still exist, but only the first The inner wall and the bottom of the hole 10 are raised a little.
- the source/drain metal layer is etched to form the data line 103, a space is formed at a position where the longitudinally arranged data lines 103 intersect the first hole 10 described above.
- the length of each of the first holes 10 may be substantially equal to the length of the gate lines 101, and the width may be slightly smaller than the distance between adjacent two rows of pixel units.
- two rows of pixel units can be effectively separated to block the stress propagation path, thereby effectively reducing Small and discrete array substrate stress.
- a whole row of holes is formed between any two adjacent rows of pixel units on the array substrate, thereby blocking the transfer of stress between rows and rows, and improving the mechanical properties of the array substrate.
- the first hole 10 may be from the base substrate of the insulating layer 113.
- the opposite side of the side on which the 100 is located extends to the buffer layer 110.
- the depth of the holes in the lateral direction along the longitudinal direction of the gate line 101 may be between 700 nm and 800 nm.
- the depth of the hole groove may vary depending on the process conditions, and may also vary with the thickness of some film layers, which is not limited by the present invention.
- the aperture further includes a plurality of apertures 20 extending along the length of the data line.
- the holes are disposed between two adjacent columns of pixel cells. It should be noted that, since the gate line 101 is under the holed insulating layer 113, in order to prevent the hole to be struck from intersecting the gate line 101, the hole (discontinuous) is punched at the gate line 101. the way.
- the holes may be a plurality of spaced apart holes, or may be a plurality of continuous holes distributed between the two gate lines 101 and along the length direction of the data line 103.
- a plurality of holes distributed along the length direction of the data line 103 may be opposite from the side of the base substrate 100 of the insulating layer 113. The side extends to the buffer layer 110.
- the holes spaced apart along the length direction of the data line 103 and the first holes 10 spaced along the length direction of the gate line 101 cooperate with each other to reduce and disperse the stress during the bending of the array substrate as a whole. Avoid device failure.
- the array substrate includes at least two columns of pixel cells adjacent to each other, between the two columns of pixel cells, the holes including a second aperture 20 extending along the length of the data line 103.
- the holes can be drilled in a row between any two columns of pixel units of the array substrate.
- the second holes 20 intersect with the first holes 10 to form a mesh structure, thereby effectively preventing the stress from being transmitted in the lateral or longitudinal direction (up and down direction in FIGS. 1a and 1b) when the array substrate is bent, thereby improving The bending resistance of the array substrate.
- the punching layer (insulating layer) is located above the gate metal layer and the gate lines 101 are arranged in the lateral direction, when the holes are aligned in the longitudinal direction of the data line 103, The two-hole groove 20 inevitably crosses the gate line 101.
- the second hole 20 may include a portion extending from the opposite side of the side of the base substrate 100 of the insulating layer 113 to the buffer layer 110 and a portion extending to the gate line 101. That is, the depth of the second hole grooves 20 in the direction perpendicular to the base substrate 100 is not completely the same.
- the second hole 20 includes: a portion extending to the gate line 101, the depth of the portion being a distance from the gate line 101 to the opposite side of the side of the insulating substrate 113 on which the base substrate 100 is located; and extending to the buffer layer 110 Part (in the case where a buffer layer is provided on the surface of the base substrate).
- the dry etching method can selectively etch only the non-metal material, so that the second hole 20 having different depths can be obtained at one time, simplifying Punching process.
- the array substrate further includes a capacitor layer 109 between the gate metal layer and the source/drain metal layer, and the insulating layer includes a capacitor layer 109 disposed between the capacitor layer 109 and the source/drain metal layer.
- the insulating layer 113 (the first insulating layer 113) and the second insulating layer 112 disposed between the capacitor layer and the gate metal layer.
- a buffer layer 110, an active layer, and a third insulating layer 111 disposed between the active layer and the gate metal layer 101 are sequentially included.
- the first insulating layer 113 disposed between the capacitor layer 109 and the source/drain metal layer 103 may serve as a hole initiating layer. That is, each of the types of holes in the above embodiment may be a structure extending from the opposite side of the side of the base substrate 100 of the first insulating layer 113 toward the base substrate 100.
- the structure of the array substrate of this embodiment is a top gate structure, but the solution of the present invention is not limited to the top gate structure, and the array substrate may also be a bottom gate structure.
- each of the insulating layers may be an inorganic insulating layer, wherein the material of the inorganic insulating layer may include a silicon material, such as an inorganic silicon material. Further, the inorganic silicon material may include at least one of silicon oxide and silicon nitride. Generally, silicon materials are used as the insulating material, and stress is easily generated or accumulated in each film layer of the array substrate. The holes of the embodiments of the present invention can effectively disperse and reduce the stress in the film layer, thereby improving the performance of the array substrate. .
- the array substrate of the present invention can be applied to various foldable display devices, but the present invention does not limit the application of the above array substrate.
- Another aspect of the present invention provides a display device including the above array substrate, such as an OLED display device.
- the OLED display device by punching holes outside the pixel unit of the array substrate, the phenomenon of stress concentration is effectively improved, thereby improving the bending resistance of the device.
- Still another aspect of the present invention provides a method of preparing the above array substrate.
- the method may include the following steps:
- S100 forming an active layer pattern, a gate metal layer pattern, and an insulating layer on one side of the base substrate, wherein the gate metal layer pattern includes a gate line;
- both the active layer pattern and the gate metal layer pattern in this step can be prepared by photolithography.
- a buffer layer is first deposited on a substrate, then an active layer is deposited over the buffer layer, and an active layer pattern is formed by photolithography.
- a gate metal layer is deposited on the active layer, and gate lines and gates connected to the gate lines are formed by photolithography.
- an insulating layer may also be deposited on the gate metal layer, for example, the material of the insulating layer may be an inorganic material (for example, may be an inorganic silicon material including at least one of silicon oxide and silicon nitride).
- a capacitor layer may be further deposited over the insulating layer, and a capacitor layer pattern is formed by a photolithographic masking method.
- an insulating layer is deposited over the capacitor layer pattern, and as described above, the material of the insulating layer may be an inorganic material (for example, may be an inorganic silicon material including at least one of silicon oxide and silicon nitride).
- punching is performed from the insulating layer farthest from the substrate substrate toward the substrate substrate.
- Punching can be done by dry or wet etching.
- the punching position avoids the pixel unit of the array substrate, as many holes as possible can be punched to minimize the stress between the film layers of the array substrate.
- the above holes may include two types of holes, one of which is a hole extending from the opposite side of the side of the substrate on which the insulating layer farthest from the substrate substrate is located to the substrate substrate (the holes cannot be hit) On the base substrate, so as not to affect the display effect, and the other is to extend from the opposite side of the side of the base substrate of the insulating layer farthest from the substrate substrate to the metal layer of the array substrate below the insulating layer. hole.
- holes are perforated by dry etching or wet etching to form a hole structure.
- the hole structure can effectively avoid the transfer of stress between the inner film layers and improve the mechanical properties of the array substrate.
- the method of puncturing the entire line may specifically be, but is not limited to, the following methods:
- the exposed area of the mask pattern may be elongated, thereby including on the mask pattern a plurality of strips corresponding to the positions to be punched on the insulating layer. It can be understood that the strips are respectively located between adjacent rows of pixel units on the array substrate;
- the predetermined puncturing area is etched by dry etching or wet etching until the buffer layer is exposed (in the case where a buffer layer is deposited on the surface of the array substrate), at this time, on the array substrate, adjacent two rows of pixel units A first hole extending in the length direction of the gate line is formed therebetween.
- the second hole can effectively avoid the transfer of stress between the inner film layers and improve the mechanical properties of the array substrate.
- the method of puncturing the entire row is similar to the method of puncturing the entire row described above, and will not be described here. However, it should be noted that when the entire column is punched, since the hole will intersect the gate line, the hole is stopped when the gate line is to be etched. For example, etching can be continued at a position where there is no gate metal (gate line) until the second hole reaches the buffer layer.
- the method when preparing the array substrate, after the above steps, the method further includes the following steps:
- S300 depositing a source/drain metal layer on the opposite side of the side of the underlying substrate of the insulating layer, and forming a source/drain metal layer pattern by mask exposure.
- the pores may be shielded to prevent leakage of the metal layer in the deposition source.
- the metal material enters and blocks the holes.
- the source/drain metal layer may be directly deposited after S200, that is, the first hole groove is not required to be shielded, thereby simplifying the punching process.
- the second holes formed by the entire row of holes since the second holes may intersect the gate lines, after S200, for example, the second holes may be shielded to avoid leakage of the metal layer in the deposition source.
- the metal material enters the second hole and contacts the gate line to cause a short circuit.
- the above description of the punching method does not mean that only the corresponding hole can be used in the above manner, and only a punching method is provided.
- the foldable array substrate of the present invention, the preparation method thereof and the display device can effectively alleviate the stress in the array substrate by punching holes outside the pixel unit of the array substrate, thereby effectively improving the stress concentration phenomenon, thereby improving the resistance of the device. Bending performance.
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Abstract
Description
Claims (20)
- 一种可折叠阵列基板,其中,包括衬底基板、设置于所述衬底基板的一侧的栅金属层、设置于所述栅金属层的所述衬底基板所在侧的相反侧的源漏金属层以及设置于所述栅金属层和所述源漏金属层之间的绝缘层,所述栅金属层包括栅线,所述源漏金属层包括数据线,并且所述栅线和所述数据线交叉设置,以在所述衬底基板上限定多个像素单元,所述可折叠阵列基板设置有孔,所述孔不设置在所述像素单元内,所述孔从所述绝缘层的所述衬底基板所在侧的相反侧朝向所述衬底基板延伸。
- 根据权利要求1所述的可折叠阵列基板,其中,所述可折叠阵列基板在彼此相邻的两行像素单元之间和/或在彼此相邻的两列像素单元之间包括预设打孔区,所述孔设置于所述预设打孔区内。
- 根据权利要求2所述的可折叠阵列基板,其中,所述预设打孔区的宽度在2微米至10微米的范围内。
- 根据权利要求1至3中任一项所述的可折叠阵列基板,其中,所述孔至少包括第一类孔,所述第一类孔与所述可折叠阵列基板的各金属层的金属均不相交。
- 根据权利要求4所述的可折叠阵列基板,其中,所述第一类孔从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述衬底基板。
- 根据权利要求4所述的可折叠阵列基板,其中,所述可折叠阵列基板还包括设置于所述衬底基板的所述一侧且与所述衬底基板接触的缓冲层,所述第一类孔从所述绝缘层的所述衬底基板所在侧的相反侧朝向所述衬底基板延伸至所述缓冲层。
- 根据权利要求1至3中任一项所述的可折叠阵列基板,其中,所述孔还包括第二类孔,所述第二类孔从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述栅金属层中的金属走线。
- 根据权利要求1至7中任一项所述的可折叠阵列基板,其中,所述可折叠阵列基板还包括彼此相邻的至少两行像素单元,在该两行像素单元之间,所述孔包括沿所述栅线的长度方向延伸的第一孔槽。
- 根据权利要求8所述的可折叠阵列基板,其中,所述可折叠阵列基板还包括设置于所述衬底基板的所述一侧且与所述衬底基板接触的缓冲层,所述第一孔槽从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述缓冲层。
- 根据权利要求9所述的可折叠阵列基板,其中,所述孔还包括沿所述数据线的长度方向延伸的多个孔。
- 根据权利要求10所述的可折叠阵列基板,其中,所述多个孔从所述绝缘 层的所述衬底基板所在侧的相反侧延伸至所述缓冲层。
- 根据权利要求1至7中任一项所述的可折叠阵列基板,其中,所述可折叠阵列基板还包括彼此相邻的至少两列像素单元,在该两列像素单元之间,所述孔包括沿所述数据线的长度方向延伸的第二孔槽。
- 根据权利要求12所述的可折叠阵列基板,其中,所述第二孔槽包括从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述缓冲层的部分和延伸至所述栅线的部分。
- 根据权利要求1-13中任一项所述的可折叠阵列基板,其中,所述可折叠阵列基板还包括位于所述栅金属层和所述源漏金属层之间的电容层,所述绝缘层包括设置在所述电容层与所述源漏金属层之间的第一绝缘层以及设置于所述电容层与所述栅金属层之间的第二绝缘层。
- 根据权利要求1至14中的任一项所述的可折叠阵列基板,其中,所述绝缘层的材料包括无机硅材料。
- 根据权利要求15所述的可折叠阵列基板,其中,所述无机硅材料包括氧化硅和氮化硅的至少一种。
- 一种包括如权利要求1-16中任一项所述的可折叠阵列基板的OLED显示装置。
- 一种可折叠阵列基板的制备方法,其中,包括:在衬底基板的一侧形成有源层图案、栅金属层图案和绝缘层,其中所述栅金属层图案包括栅线;从所述绝缘层的所述衬底基板所在侧的相反侧形成朝向所述衬底基板的方向延伸的孔,其中所述孔不形成在像素单元内且与所述像素单元不相交。
- 根据权利要求18所述的可折叠阵列基板的制备方法,其中,所述从所述绝缘层的所述衬底基板所在侧的相反侧形成朝向所述衬底基板的方向延伸的孔包括:在彼此相邻的至少一对两行像素单元之间形成沿所述栅线的长度方向延伸的第一孔槽。
- 根据权利要求19所述的可折叠阵列基板的制备方法,其中,在所述从所述绝缘层的所述衬底基板所在侧的相反侧形成朝向所述衬底基板的方向延伸的孔之后还包括形成源漏金属层图案,其中所述源漏金属层图案包括数据线,所述从所述绝缘层的所述衬底基板所在侧的相反侧形成朝向所述衬底基板的方向延伸的孔还包括:在彼此相邻的至少一对两列像素单元之间形成沿所述数据线的长度方向延伸的第二孔槽。
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EP18851732.0A EP3598496A4 (en) | 2017-08-31 | 2018-05-30 | FOLDABLE ARRAY SUBSTRATE, PRODUCTION METHOD THEREFOR, AND DISPLAY DEVICE |
KR1020197028660A KR102356258B1 (ko) | 2017-08-31 | 2018-05-30 | 폴더블 어레이 기판과 그 제조 방법, 및 표시 장치 |
US16/410,271 US11121332B2 (en) | 2017-08-31 | 2019-05-13 | Foldable array substrate, preparation method thereof and display device |
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- 2017-08-31 CN CN201710773088.4A patent/CN109427818B/zh active Active
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- 2018-05-30 EP EP18851732.0A patent/EP3598496A4/en active Pending
- 2018-05-30 KR KR1020197028660A patent/KR102356258B1/ko active IP Right Grant
- 2018-05-30 JP JP2019555617A patent/JP6876147B2/ja active Active
- 2018-05-30 WO PCT/CN2018/088958 patent/WO2019041921A1/zh unknown
- 2018-07-12 TW TW107124025A patent/TWI677121B/zh active
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2019
- 2019-05-13 US US16/410,271 patent/US11121332B2/en active Active
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Also Published As
Publication number | Publication date |
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KR20190118656A (ko) | 2019-10-18 |
CN109427818A (zh) | 2019-03-05 |
KR102356258B1 (ko) | 2022-01-28 |
JP2020517109A (ja) | 2020-06-11 |
EP3598496A4 (en) | 2020-06-03 |
EP3598496A1 (en) | 2020-01-22 |
US20190267558A1 (en) | 2019-08-29 |
TWI677121B (zh) | 2019-11-11 |
CN109427818B (zh) | 2019-11-01 |
TW201914073A (zh) | 2019-04-01 |
JP6876147B2 (ja) | 2021-05-26 |
US11121332B2 (en) | 2021-09-14 |
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