WO2019041921A1 - 可折叠阵列基板及其制备方法、显示装置 - Google Patents

可折叠阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2019041921A1
WO2019041921A1 PCT/CN2018/088958 CN2018088958W WO2019041921A1 WO 2019041921 A1 WO2019041921 A1 WO 2019041921A1 CN 2018088958 W CN2018088958 W CN 2018088958W WO 2019041921 A1 WO2019041921 A1 WO 2019041921A1
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Prior art keywords
substrate
array substrate
hole
metal layer
foldable array
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PCT/CN2018/088958
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English (en)
French (fr)
Inventor
王刚
张露
韩珍珍
胡思明
朱晖
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昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to JP2019555617A priority Critical patent/JP6876147B2/ja
Priority to EP18851732.0A priority patent/EP3598496A4/en
Priority to KR1020197028660A priority patent/KR102356258B1/ko
Publication of WO2019041921A1 publication Critical patent/WO2019041921A1/zh
Priority to US16/410,271 priority patent/US11121332B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H05K1/028—Bending or folding regions of flexible printed circuits
    • H05K1/0281—Reinforcement details thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/118—Printed elements for providing electric connections to or between printed circuits specially for flexible printed circuits, e.g. using folded portions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • H05K3/326—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor the printed circuit having integral resilient or deformable parts, e.g. tabs or parts of flexible circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of foldable display technologies, and in particular to a foldable array substrate, a method of fabricating the same, and a display device.
  • Flexible foldable displays such as OLED displays, offer users a new visual experience. However, after repeated bending of such a display, it is easy to cause a device failure phenomenon, thereby affecting the display.
  • the current solution is to perform wire change processing between pixel units, that is, to use a wire with better bending resistance to improve the bending resistance of the device.
  • this scheme is not suitable for flexible displays with high pixel density (high PPI).
  • the embodiments of the present invention provide a foldable array substrate, a preparation method thereof, and a display device, which can improve the bending resistance of the foldable array substrate by reducing the stress.
  • the foldable array substrate includes a base substrate, a gate metal layer disposed on one side of the base substrate, a source/drain metal layer disposed on an opposite side of a side of the gate metal layer on which the base substrate is located, and a setting An insulating layer between the gate metal layer and the source/drain metal layer, the gate metal layer includes a gate line, the source/drain metal layer includes a data line, and the gate line and the data line are disposed at intersection
  • the foldable array substrate being provided with a hole, the hole not being disposed in the pixel unit, the hole being from the substrate of the insulating layer
  • the opposite side of the side on which the substrate is located extends toward the base substrate.
  • the foldable array substrate includes a predetermined puncturing area between two rows of pixel units adjacent to each other and/or between two columns of pixel units adjacent to each other, the holes being disposed in the The preset punching area.
  • the predetermined perforated area has a width in the range of 2 microns to 10 microns.
  • the apertures include at least a first type of apertures that do not intersect the metal of each metal layer of the foldable array substrate.
  • the first type of aperture extends from the opposite side of the side of the insulating substrate from the side of the substrate to the substrate.
  • the foldable array substrate further includes a buffer layer disposed on the one side of the base substrate and in contact with the base substrate, the first type of holes from the insulating layer The opposite side of the side on which the base substrate is located extends toward the base substrate to the buffer layer.
  • the hole further includes a second type of hole extending from an opposite side of the side of the insulating substrate on the side of the substrate to a metal trace in the gate metal layer .
  • the foldable array substrate further includes at least two rows of pixel units adjacent to each other, and between the two rows of pixel units, the holes include a first hole extending along a length of the gate line groove.
  • the foldable array substrate further includes a buffer layer disposed on the one side of the base substrate and in contact with the base substrate, the first hole from the insulating layer The opposite side of the side on which the base substrate is located extends to the buffer layer.
  • the aperture further includes a plurality of apertures extending along a length of the data line.
  • the plurality of holes extend from opposite sides of the side of the insulating substrate to the buffer layer.
  • the foldable array substrate further includes at least two columns of pixel units adjacent to each other, and between the two columns of pixel units, the holes include a second hole extending along a length of the data line groove.
  • the second hole trench includes a portion extending from an opposite side of a side of the insulating substrate on which the substrate substrate is located to a portion of the buffer layer and a portion extending to the gate line.
  • the foldable array substrate further includes a capacitor layer between the gate metal layer and the source/drain metal layer, the insulating layer including the capacitor layer and the source/drain metal a first insulating layer between the layers and a second insulating layer disposed between the capacitor layer and the gate metal layer.
  • the material of the insulating layer comprises an inorganic silicon material.
  • the inorganic silicon material comprises at least one of silicon oxide and silicon nitride.
  • Another aspect of the present invention provides an OLED display device including the above-described foldable array substrate.
  • Still another aspect of the present invention provides a method of fabricating a foldable array substrate, comprising: forming an active layer pattern, a gate metal layer pattern, and an insulating layer on one side of a base substrate, wherein the gate metal layer pattern includes a gate a hole extending from a side opposite to a side of the base substrate of the insulating layer toward a direction of the base substrate, wherein the hole is not formed in the pixel unit and does not intersect the pixel unit.
  • the forming a hole extending from a side opposite to a side of the underlying substrate of the insulating layer toward the substrate includes: at least one pair of two rows of pixel cells adjacent to each other A first hole extending along a length direction of the gate line is formed therebetween.
  • forming a source/drain metal layer pattern after forming a hole extending from a side opposite to a side of the substrate of the insulating layer toward the substrate includes a data line, and the hole extending from a side opposite to a side of the insulating substrate on which the substrate substrate is located further includes at least one pair adjacent to each other A second hole extending along the length direction of the data line is formed between the two columns of pixel units.
  • the foldable array substrate and the OLED display device provided by the embodiments of the present invention effectively improve the stress concentration phenomenon by punching holes outside the pixel unit of the foldable array substrate, thereby improving the bending resistance of the device.
  • FIG. 1a is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 1b is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the array substrate of FIG. 1a taken along the A-A direction.
  • FIG. 3 is a cross-sectional view of the array substrate of FIG. 1a taken along line B-B.
  • FIG. 4 is a flow chart of preparing an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a flow chart of preparing an array substrate according to an embodiment of the present invention.
  • the array substrate includes a base substrate 100, a gate metal layer disposed on one side of the base substrate 100, and a source/drain metal layer disposed on the opposite side of the side of the base substrate 100 of the gate metal layer. And an insulating layer disposed between the gate metal layer and the source/drain metal layer.
  • the gate metal layer includes a gate line 101
  • the source/drain metal layer includes a data line 103
  • the gate line 101 and the data line 103 are disposed to intersect to define a plurality of pixel units on the base substrate 100.
  • the array substrate is provided with holes extending from the opposite side of the side on which the base substrate 100 of the insulating layer is located toward the side of the base substrate 100 (not shown). Those skilled in the art will recognize that the holes do not intersect the pixel elements.
  • the present invention can effectively alleviate the stress in the array substrate and improve the bending resistance.
  • the insulating layer of the foldable array substrate may be, for example, an inorganic insulating material.
  • the inorganic insulating material may be an inorganic silicon material, and specifically, may be silicon nitride or silicon oxide.
  • the array substrate is liable to cause device failure due to stress concentration of the film layer of the array substrate when bent.
  • the stress occurring in the insulating layer can be effectively dispersed, and the bending resistance of the device can be improved.
  • the holes extend from the opposite side of the side where the base substrate of the insulating layer is located toward the base substrate, but do not intersect the area defined by the respective pixel units. That is to say, these holes need to avoid the pixel unit of the array substrate to avoid affecting the display effect.
  • the substrate of the embodiment of the present invention may be, for example, a flexible substrate in order to obtain a foldable array substrate.
  • the holes can be distributed in an array.
  • a plurality of holes are disposed around one pixel unit to separate the pixel unit from its adjacent pixel unit, so that the pixel unit forms an "island" structure, improving the stress dispersion effect.
  • a plurality of holes may be disposed around several pixel units to separate the pixel units from the periphery to improve the stress dispersion effect.
  • the sizes of the holes may be different from each other depending on the size and resolution of the screen.
  • the holes may range in size from 2 um to 20 um.
  • the larger the size of a single hole the better the stress dispersion effect, and the less difficult the process to prepare a smaller number of holes.
  • the size of the pores can be further limited to between 5 um and 10 um, so that the stress can be better reduced, the performance of the array substrate can be improved, and the process difficulty of punching is not excessively increased.
  • the shape of the cross section perpendicular to the axis of each hole may be different, for example, the shape of the cross section may be square, elliptical, circular or polygonal.
  • the shape of the cross section of the hole may include at least two of a square, a circle, an ellipse, and a polygon.
  • Different stress dispersion effects can be obtained by providing holes of different shapes in the array substrate. That is, the stress dispersion property can be further improved by the cooperation between the holes having different shapes.
  • the holes may also be structures whose dimensions vary along their axial direction.
  • the cross section of the circular hole may be a structure whose diameter gradually becomes smaller in a direction from the opposite side of the side of the base substrate on which the circular hole is located toward the side where the base substrate is located.
  • the axial direction of the holes may extend in a direction at an angle to a direction perpendicular to the array substrate, for example, the angle may be 5 to 10 . Therefore, the metal traces of the metal layers of the array substrate can be effectively avoided, and the holes are further extended toward the array substrate to improve the performance of the array substrate.
  • the two rows of pixel units adjacent to each other of the array substrate may include a predetermined puncturing area, and the holes may be disposed in the predetermined puncturing area. That is to say, when designing an array substrate (especially an array substrate with a high PPI), it is possible to artificially leave a certain area between two adjacent rows of pixels, which can be used for punching to better eliminate the array. The stress of the substrate. Generally, for a high PPI array substrate, if the preset punching area is not reserved, the punching difficulty is very large due to the limitation of the punching process. Therefore, the circuit of the pixel unit can be designed to be more compact without reducing the size of the pixel unit, so that the preset punched area can be reserved without affecting the display effect.
  • the orthographic projection of the predetermined punctured area on the array substrate may not coincide with the metal trace and the TFT switch.
  • the width of the predetermined perforated area (the size in the column direction) may be in the range of 2 um to 10 um, thereby ensuring the circuit safety of the pixel unit on the one hand and ensuring the punching on the other hand. Going smoothly.
  • the size of the hole to be punched is large, the internal stress of the array substrate can be significantly reduced, and the bending resistance of the array substrate can be improved.
  • a preset puncturing area may be reserved between adjacent two columns of pixel units of the array substrate.
  • the width of the predetermined punched area (the size in the row direction) may be in the range of 2 um to 10 um, so that the array substrate has the effect as described above after punching.
  • the pre-punched area is preferably a metal-free area, so that the bending resistance of the array substrate can be effectively improved without affecting the electrical performance of the array substrate.
  • the apertures can include a first type of aperture.
  • the first type of holes do not intersect the metal traces of the gate metal layer and the metals of the other metal layers in the array substrate.
  • the first type of holes can avoid the metal present in each metal layer to extend toward the substrate substrate to the greatest extent.
  • the first type of holes can extend to the vicinity of the array substrate.
  • the first type of holes may also be inclined holes.
  • the array substrate further includes a buffer layer 110 disposed on the one side of the base substrate 100 and in contact with the base substrate 100.
  • the first type of holes are insulated from the substrate.
  • the opposite side of the side of the base substrate 100 of the layer 113 extends toward the base substrate 100 to the buffer layer 110.
  • a dry etching method or a wet etching method may be employed.
  • a dry etching method or a wet etching method may also etch a portion of the buffer layer 110.
  • the holes may further include a second type of holes extending from the opposite side of the side of the insulating substrate 113 on which the base substrate 100 is located toward the base substrate 100 to the gate line 101.
  • the second type of holes may also extend from the opposite side of the side of the base layer 100 of the insulating layer 113 toward the substrate substrate 100 to the traces of the other metal layers (the source and drain metal layers are formed after the formation of the insulating layer, and thus Other layers at the location may not include source/drain metal layers, such as metals in the capacitive layer of the array substrate of the OLED display device.
  • a metal layer exists between the insulating layer and the substrate, it may be in the process of punching. Will encounter the traces of these metal layers.
  • punching by dry or wet etching if the traces of these metal layers are encountered, for example, the etching operation can be stopped to prevent the normal operation of the array substrate from being affected by etching off the gate lines or other metal traces.
  • the depth of such holes is relatively small, macroscopically, these shallower holes also increase the total number of holes, thereby improving the stress dispersion effect.
  • the array substrate includes at least two rows of pixel cells adjacent to each other.
  • the aperture includes a first aperture 10 extending along the length of the gate line 101 (the puncturing location may be, for example, a grid-like hatching as shown in FIG. 1a) The range defined by the rectangle).
  • the puncturing location may be, for example, a grid-like hatching as shown in FIG. 1a
  • the range defined by the rectangle For example, in the preparation process, holes may be drilled in a row between two adjacent rows of pixel units, and then the source and drain metal layers will raise the first hole 10 when the sputtering source leaks the metal layer.
  • the source/drain metal layers sputtered on the array substrate are substantially the same, and after the sputtering source drains the metal layer, the first holes 10 arranged along the length direction of the gate line 101 still exist, but only the first The inner wall and the bottom of the hole 10 are raised a little.
  • the source/drain metal layer is etched to form the data line 103, a space is formed at a position where the longitudinally arranged data lines 103 intersect the first hole 10 described above.
  • the length of each of the first holes 10 may be substantially equal to the length of the gate lines 101, and the width may be slightly smaller than the distance between adjacent two rows of pixel units.
  • two rows of pixel units can be effectively separated to block the stress propagation path, thereby effectively reducing Small and discrete array substrate stress.
  • a whole row of holes is formed between any two adjacent rows of pixel units on the array substrate, thereby blocking the transfer of stress between rows and rows, and improving the mechanical properties of the array substrate.
  • the first hole 10 may be from the base substrate of the insulating layer 113.
  • the opposite side of the side on which the 100 is located extends to the buffer layer 110.
  • the depth of the holes in the lateral direction along the longitudinal direction of the gate line 101 may be between 700 nm and 800 nm.
  • the depth of the hole groove may vary depending on the process conditions, and may also vary with the thickness of some film layers, which is not limited by the present invention.
  • the aperture further includes a plurality of apertures 20 extending along the length of the data line.
  • the holes are disposed between two adjacent columns of pixel cells. It should be noted that, since the gate line 101 is under the holed insulating layer 113, in order to prevent the hole to be struck from intersecting the gate line 101, the hole (discontinuous) is punched at the gate line 101. the way.
  • the holes may be a plurality of spaced apart holes, or may be a plurality of continuous holes distributed between the two gate lines 101 and along the length direction of the data line 103.
  • a plurality of holes distributed along the length direction of the data line 103 may be opposite from the side of the base substrate 100 of the insulating layer 113. The side extends to the buffer layer 110.
  • the holes spaced apart along the length direction of the data line 103 and the first holes 10 spaced along the length direction of the gate line 101 cooperate with each other to reduce and disperse the stress during the bending of the array substrate as a whole. Avoid device failure.
  • the array substrate includes at least two columns of pixel cells adjacent to each other, between the two columns of pixel cells, the holes including a second aperture 20 extending along the length of the data line 103.
  • the holes can be drilled in a row between any two columns of pixel units of the array substrate.
  • the second holes 20 intersect with the first holes 10 to form a mesh structure, thereby effectively preventing the stress from being transmitted in the lateral or longitudinal direction (up and down direction in FIGS. 1a and 1b) when the array substrate is bent, thereby improving The bending resistance of the array substrate.
  • the punching layer (insulating layer) is located above the gate metal layer and the gate lines 101 are arranged in the lateral direction, when the holes are aligned in the longitudinal direction of the data line 103, The two-hole groove 20 inevitably crosses the gate line 101.
  • the second hole 20 may include a portion extending from the opposite side of the side of the base substrate 100 of the insulating layer 113 to the buffer layer 110 and a portion extending to the gate line 101. That is, the depth of the second hole grooves 20 in the direction perpendicular to the base substrate 100 is not completely the same.
  • the second hole 20 includes: a portion extending to the gate line 101, the depth of the portion being a distance from the gate line 101 to the opposite side of the side of the insulating substrate 113 on which the base substrate 100 is located; and extending to the buffer layer 110 Part (in the case where a buffer layer is provided on the surface of the base substrate).
  • the dry etching method can selectively etch only the non-metal material, so that the second hole 20 having different depths can be obtained at one time, simplifying Punching process.
  • the array substrate further includes a capacitor layer 109 between the gate metal layer and the source/drain metal layer, and the insulating layer includes a capacitor layer 109 disposed between the capacitor layer 109 and the source/drain metal layer.
  • the insulating layer 113 (the first insulating layer 113) and the second insulating layer 112 disposed between the capacitor layer and the gate metal layer.
  • a buffer layer 110, an active layer, and a third insulating layer 111 disposed between the active layer and the gate metal layer 101 are sequentially included.
  • the first insulating layer 113 disposed between the capacitor layer 109 and the source/drain metal layer 103 may serve as a hole initiating layer. That is, each of the types of holes in the above embodiment may be a structure extending from the opposite side of the side of the base substrate 100 of the first insulating layer 113 toward the base substrate 100.
  • the structure of the array substrate of this embodiment is a top gate structure, but the solution of the present invention is not limited to the top gate structure, and the array substrate may also be a bottom gate structure.
  • each of the insulating layers may be an inorganic insulating layer, wherein the material of the inorganic insulating layer may include a silicon material, such as an inorganic silicon material. Further, the inorganic silicon material may include at least one of silicon oxide and silicon nitride. Generally, silicon materials are used as the insulating material, and stress is easily generated or accumulated in each film layer of the array substrate. The holes of the embodiments of the present invention can effectively disperse and reduce the stress in the film layer, thereby improving the performance of the array substrate. .
  • the array substrate of the present invention can be applied to various foldable display devices, but the present invention does not limit the application of the above array substrate.
  • Another aspect of the present invention provides a display device including the above array substrate, such as an OLED display device.
  • the OLED display device by punching holes outside the pixel unit of the array substrate, the phenomenon of stress concentration is effectively improved, thereby improving the bending resistance of the device.
  • Still another aspect of the present invention provides a method of preparing the above array substrate.
  • the method may include the following steps:
  • S100 forming an active layer pattern, a gate metal layer pattern, and an insulating layer on one side of the base substrate, wherein the gate metal layer pattern includes a gate line;
  • both the active layer pattern and the gate metal layer pattern in this step can be prepared by photolithography.
  • a buffer layer is first deposited on a substrate, then an active layer is deposited over the buffer layer, and an active layer pattern is formed by photolithography.
  • a gate metal layer is deposited on the active layer, and gate lines and gates connected to the gate lines are formed by photolithography.
  • an insulating layer may also be deposited on the gate metal layer, for example, the material of the insulating layer may be an inorganic material (for example, may be an inorganic silicon material including at least one of silicon oxide and silicon nitride).
  • a capacitor layer may be further deposited over the insulating layer, and a capacitor layer pattern is formed by a photolithographic masking method.
  • an insulating layer is deposited over the capacitor layer pattern, and as described above, the material of the insulating layer may be an inorganic material (for example, may be an inorganic silicon material including at least one of silicon oxide and silicon nitride).
  • punching is performed from the insulating layer farthest from the substrate substrate toward the substrate substrate.
  • Punching can be done by dry or wet etching.
  • the punching position avoids the pixel unit of the array substrate, as many holes as possible can be punched to minimize the stress between the film layers of the array substrate.
  • the above holes may include two types of holes, one of which is a hole extending from the opposite side of the side of the substrate on which the insulating layer farthest from the substrate substrate is located to the substrate substrate (the holes cannot be hit) On the base substrate, so as not to affect the display effect, and the other is to extend from the opposite side of the side of the base substrate of the insulating layer farthest from the substrate substrate to the metal layer of the array substrate below the insulating layer. hole.
  • holes are perforated by dry etching or wet etching to form a hole structure.
  • the hole structure can effectively avoid the transfer of stress between the inner film layers and improve the mechanical properties of the array substrate.
  • the method of puncturing the entire line may specifically be, but is not limited to, the following methods:
  • the exposed area of the mask pattern may be elongated, thereby including on the mask pattern a plurality of strips corresponding to the positions to be punched on the insulating layer. It can be understood that the strips are respectively located between adjacent rows of pixel units on the array substrate;
  • the predetermined puncturing area is etched by dry etching or wet etching until the buffer layer is exposed (in the case where a buffer layer is deposited on the surface of the array substrate), at this time, on the array substrate, adjacent two rows of pixel units A first hole extending in the length direction of the gate line is formed therebetween.
  • the second hole can effectively avoid the transfer of stress between the inner film layers and improve the mechanical properties of the array substrate.
  • the method of puncturing the entire row is similar to the method of puncturing the entire row described above, and will not be described here. However, it should be noted that when the entire column is punched, since the hole will intersect the gate line, the hole is stopped when the gate line is to be etched. For example, etching can be continued at a position where there is no gate metal (gate line) until the second hole reaches the buffer layer.
  • the method when preparing the array substrate, after the above steps, the method further includes the following steps:
  • S300 depositing a source/drain metal layer on the opposite side of the side of the underlying substrate of the insulating layer, and forming a source/drain metal layer pattern by mask exposure.
  • the pores may be shielded to prevent leakage of the metal layer in the deposition source.
  • the metal material enters and blocks the holes.
  • the source/drain metal layer may be directly deposited after S200, that is, the first hole groove is not required to be shielded, thereby simplifying the punching process.
  • the second holes formed by the entire row of holes since the second holes may intersect the gate lines, after S200, for example, the second holes may be shielded to avoid leakage of the metal layer in the deposition source.
  • the metal material enters the second hole and contacts the gate line to cause a short circuit.
  • the above description of the punching method does not mean that only the corresponding hole can be used in the above manner, and only a punching method is provided.
  • the foldable array substrate of the present invention, the preparation method thereof and the display device can effectively alleviate the stress in the array substrate by punching holes outside the pixel unit of the array substrate, thereby effectively improving the stress concentration phenomenon, thereby improving the resistance of the device. Bending performance.

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Abstract

本发明提供可折叠阵列基板及其制备方法、显示装置。该可折叠阵列基板包括衬底基板、设置于衬底基板的一侧的栅金属层、设置于栅金属层的衬底基板所在侧的相反侧的源漏金属层以及设置于栅金属层和源漏金属层之间的绝缘层，栅金属层包括栅线，源漏金属层包括数据线，并且栅线和数据线交叉设置，以在衬底基板上限定多个像素单元，可折叠阵列基板设置有孔，孔不设置在像素单元内，孔从绝缘层的衬底基板所在侧的相反侧朝向衬底基板延伸。采用本发明的可折叠阵列基板、显示装置和该可折叠阵列基板的制备方法，可以通过减小可折叠阵列基板的应力，提高其抗弯折性能。

Description

可折叠阵列基板及其制备方法、显示装置
本发明要求2017年8月31日递交的中国专利申请No.CN 201710773088.4的优先权，通过引用将其全部内容并入本文。
技术领域
本发明涉及可折叠显示器技术领域，具体地，涉及可折叠阵列基板及其制备方法、显示装置。
发明背景
柔性可折叠显示器，例如OLED显示器，可以为用户带来全新的视觉体验。但这种显示器在多次弯折后，容易产生器件失效的现象，从而影响显示。
目前的解决方法是在像素单元之间进行换线处理，即采用抗弯性能更好的走线，提高器件的抗弯折能力。然而，这种方案并不适用于像素密度较高(高PPI)的柔性显示器。
因此，亟待提出一种应用更广的能够提高例如高PPI器件的抗弯折能力的技术。
发明内容
有鉴于此，本发明实施例提供了可折叠阵列基板及其制备方法、显示装置，其可以通过降小可折叠阵列基板的应力，提高其抗弯折性能。
本发明的一个方面提供一种可折叠阵列基板。该可折叠阵列基板包括衬底基板、设置于所述衬底基板的一侧的栅金属层、设置于所述栅金属层的所述衬底基板所在侧的相反侧的源漏金属层以及设置于所述栅金属层和所述源漏金属层之间的绝缘层，所述栅金属层包括栅线，所述源漏金属层包括数据线，并且所述栅线和所述数据线交叉设置，以在所述衬底基板上限定多个像素单元，所述可折叠阵列基板设置有孔，所述孔不设置在所述像素单元内，所述孔从所述绝缘层的所述衬底基板所在侧的相反侧朝向所述衬底基板延伸。
在一个实施例中，所述可折叠阵列基板在彼此相邻的两行像素单元之间和/或在彼此相邻的两列像素单元之间包括预设打孔区，所述孔设置于所述预设打孔区内。
在一个实施例中，所述预设打孔区的宽度在2微米至10微米的范围内。
在一个实施例中，所述孔至少包括第一类孔，所述第一类孔与所述可折叠阵列基板的各金属层的金属均不相交。
在一个实施例中，所述第一类孔从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述衬底基板。
在一个实施例中，所述可折叠阵列基板还包括设置于所述衬底基板的所述一侧且与所述衬底基板接触的缓冲层，所述第一类孔从所述绝缘层的所述衬底基板所在侧的相反侧朝向所述衬底基板延伸至所述缓冲层。
在一个实施例中，所述孔还包括第二类孔，所述第二类孔从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述栅金属层中的金属走线。
在一个实施例中，所述可折叠阵列基板还包括彼此相邻的至少两行像素单元，在该两行像素单元之间，所述孔包括沿所述栅线的长度方向延伸的第一孔槽。
在一个实施例中，所述可折叠阵列基板还包括设置于所述衬底基板的所述一侧且与所述衬底基板接触的缓冲层，所述第一孔槽从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述缓冲层。
在一个实施例中，所述孔还包括沿所述数据线的长度方向延伸的多个孔。
在一个实施例中，所述多个孔从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述缓冲层。
在一个实施例中，所述可折叠阵列基板还包括彼此相邻的至少两列像素单元，在该两列像素单元之间，所述孔包括沿所述数据线的长度方向延伸的第二孔槽。
在一个实施例中，所述第二孔槽包括从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述缓冲层的部分和延伸至所述栅线的部分。
在一个实施例中，所述可折叠阵列基板还包括位于所述栅金属层和所述源漏金属层之间的电容层，所述绝缘层包括设置在所述电容层与所述源漏金属层之间的第一绝缘层以及设置于所述电容层与所述栅金属层之间的第二绝缘层。
在一个实施例中，所述绝缘层的材料包括无机硅材料。
在一个实施例中，所述无机硅材料包括氧化硅和氮化硅的至少一种。
本发明的另一个方面提供了一种包括上述可折叠阵列基板的OLED显示装置。
本发明的再一个方面提供了一种可折叠阵列基板的制备方法，包括：在衬底基板的一侧形成有源层图案、栅金属层图案和绝缘层，其中所述栅金属层图案包括栅线；从所述绝缘层的所述衬底基板所在侧的相反侧形成朝向所述衬底基板的方向延伸的孔，其中所述孔不形成在像素单元内且与所述像素单元不相交。
在一个实施例中，所述从所述绝缘层的所述衬底基板所在侧的相反侧形成朝向所述衬底基板的方向延伸的孔包括：在彼此相邻的至少一对两行像素单元之间形成沿所述栅线的长度方向延伸的第一孔槽。
在一个实施例中，在所述从所述绝缘层的所述衬底基板所在侧的相反侧形成朝向所述衬底基板的方向延伸的孔之后还包括形成源漏金属层图案，其中所述源 漏金属层图案包括数据线，所述从所述绝缘层的所述衬底基板所在侧的相反侧形成朝向所述衬底基板的方向延伸的孔还包括：在彼此相邻的至少一对两列像素单元之间形成沿所述数据线的长度方向延伸的第二孔槽。
本发明实施例提供的可折叠阵列基板和OLED显示装置，通过在该可折叠阵列基板的像素单元之外打孔，有效地改善了应力集中现象，从而提高了器件的抗弯折性能。
附图简要说明
图1a所示为本发明一实施例提供的一种阵列基板的结构示意图。
图1b所示为本发明一实施例提供的一种阵列基板的结构示意图。
图2所示为图1a的阵列基板的沿A-A方向的剖视示意图。
图3所示为图1a的阵列基板的沿B-B方向的剖视示意图。
图4为本发明实施例的阵列基板的制备流程图。
图5为本发明实施例的阵列基板的制备流程图。
实施本发明的方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的一个方面提供一种可折叠阵列基板(以下简称阵列基板)。参见图1a至图3，该阵列基板包括衬底基板100、设置于衬底基板100的一侧的栅金属层、设置于栅金属层的衬底基板100所在侧的相反侧的源漏金属层以及设置于栅金属层和源漏金属层之间的绝缘层。其中栅金属层包括栅线101，源漏金属层包括数据线103，并且栅线101和数据线103交叉设置，以在衬底基板100上限定多个像素单元。除了多个像素单元以外，阵列基板还设置有孔，孔从绝缘层的衬底基板100所在侧的相反侧向衬底基板100所在侧延伸(图中未示意)。本领域技术人员可知这些孔与像素单元不相交。本发明通过在阵列基板的绝缘层设置孔，可以有效地缓解阵列基板内的应力，提高抗弯折能力。
需要说明的是，该可折叠阵列基板的绝缘层例如可以是无机绝缘材料。例如，无机绝缘材料可以为无机硅材料，具体地，可以为氮化硅或氧化硅等。通常情况下，例如，当以无机硅材料作为绝缘层时，阵列基板在弯折时容易因阵列基板的膜层发生应力集中而导致器件失效。通过在阵列基板的绝缘层设置孔，可以有效地分散发生在绝缘层的应力，提高器件的抗弯折性能。此外，这些孔从绝缘层的 衬底基板所在侧的相反侧朝向衬底基板延伸，但不与由各个像素单元限定的区域相交。也就是说，这些孔需要避开阵列基板的像素单元，避免影响显示效果。此外，本领域技术人员可知，为了获得可折叠阵列基板，本发明实施例的衬底基板例如可以为柔性基板。
为了使应力更好地分散，可以在避开阵列基板像素单元的前提下设置尽可能多的孔。例如，这些孔可以呈阵列分布。例如多个孔围绕一个像素单元设置，以将该像素单元与其相邻像素单元隔开，使该像素单元形成“孤岛”结构，改善应力分散效果。同样，例如，多个孔也可以围绕几个像素单元设置，以将这几个像素单元与周边隔开，改善应力分散效果。通过使多个孔围绕几个像素单元设置，可以在确保应力分散效果的同时，简化打孔工艺，从而降低打孔成本。
需要了解的是，根据屏体尺寸和分辨率的不同，孔的尺寸可以彼此不同。例如，这些孔的尺寸可以在2um至20um之间。通常情况下，单个孔的尺寸越大，其应力分散效果越好，并且制备数量较少且尺寸较大的孔的工艺难度也相对较小。然而，在一定的面积下，相对于数量少且尺寸大的孔的情况而言，数量多且尺寸小的孔的情况具有更好的应力分散效果。因此，可以进一步将孔的尺寸限定在5um至10um之间，从而可以更好地减小应力，改善阵列基板性能，并且不会过多地增加打孔的工艺难度。
同样，各个孔的垂直于轴线的截面的形状可以各不相同，例如，该截面的形状可以为方形、椭圆形、圆形或多边形。例如，孔的该截面的形状可以同时包括方形、圆形、椭圆形和多边形的至少两种。通过在阵列基板内设置不同形状的孔，可以获得不同的应力分散效果。即可以通过具有不同形状的孔之间的配合，进一步改善应力分散性能。另外，孔还可以为尺寸沿其轴向变化的结构。例如，对于圆形孔而言，在从圆形孔的衬底基板所在侧的相反侧朝向衬底基板所在侧的方向上，圆形孔的截面可以为直径逐渐变小的结构。此外，这些孔的轴向方向可以沿与垂直于阵列基板的方向呈一定角度的方向延伸，例如，该角度可以为5°至10°。从而可以有效地避开阵列基板的各金属层的金属走线，使孔进一步朝向阵列基板方向延伸，改善阵列基板的性能。
在一个实施例中，阵列基板的彼此相邻的两行像素单元之间可以包括预设打孔区，上述孔可以设置于预设打孔区内。也就是说，在设计阵列基板(特别是具有高PPI的阵列基板)时，可以人为的在相邻两行像素之间留出一定区域，该区域可以用于打孔，以更好的消除阵列基板的应力。通常情况下，对于高PPI的阵列基板而言，如果没有预留该预设打孔区，则由于打孔工艺的限制，打孔难度会非常大。因此，可以在不减小像素单元尺寸的情况下，将像素单元的电路设计得更紧凑，从而能够预留出预设打孔区，且不影响显示效果。例如，该预设打孔区域在阵列基板上的正投影可以不与金属走线和TFT开关重合。例如，该预设打孔 区的宽度(在列方向上的尺寸)可以在2um至10um的范围内，从而一方面可以确保打孔操作时像素单元的电路安全，另一方面可以确保打孔的顺利进行。并且，由于所打的孔的尺寸较大，因此可以明显减小阵列基板的内应力，改善阵列基板的抗弯折性。同样，阵列基板的相邻两列像素单元之间也可以预留预设打孔区。例如，该预设打孔区的宽度(在行方向上的尺寸)可以在2um至10um的范围内，从而在打孔后使阵列基板具有如上所述的效果。预设打孔区域优选为没有金属的区域，这样可以在不影响阵列基板的电学性能的前提下，有效地提高阵列基板抗弯折性。
在一个实施例中，例如，孔可以包括第一类孔。第一类孔与位于栅金属层的金属走线以及阵列基板中的其它金属层的金属均不相交。例如，第一类孔可以避开各金属层中存在的金属，从而最大程度地朝向衬底基板方向延伸。例如，第一类孔可以延伸至阵列基板附近。如上所述，在一些情况下，为了避开金属层的金属，第一类孔也可以为倾斜孔。通过设置第一类孔，可以有效地减小和分散阵列基板中的应力，改善阵列基板的性能。
继续参见图1a、图1b和图2，在一个实施例中，阵列基板还包括设置于衬底基板100的该一侧且与该衬底基板100接触的缓冲层110，第一类孔从绝缘层113的衬底基板100所在侧的相反侧朝向衬底基板100延伸至缓冲层110。在打孔过程中，可以采用干刻法或湿刻法，例如，采用干刻法或湿刻法也会蚀刻掉一部分缓冲层110。
在一个实施例中，例如，孔还可以包括第二类孔，第二类孔从绝缘层113的衬底基板100所在侧的相反侧朝向衬底基板100延伸至栅线101。或者，第二类孔也可以从绝缘层113的衬底基板100所在侧的相反侧朝向衬底基板100延伸至其它金属层的走线(源漏金属层在绝缘层形成之后才形成，故而此处的其它层可以不包括源漏金属层)，例如OLED显示装置的阵列基板的电容层中的金属。在从绝缘层的衬底基板所在侧的相反侧打孔时，会主动避开阵列基板的像素单元，但由于在绝缘层与衬底基板之间存在金属层，因此，在打孔过程中可能会遇到这些金属层的走线。通过干刻法或湿刻法打孔时，如果遇到这些金属层的走线，例如，可以停止蚀刻操作，以防由于蚀刻掉栅线或其它金属走线而影响阵列基板的正常工作。尽管这类孔的深度相对小，但从宏观上看，这些深度较浅的孔也使孔的总数增加，进而改善应力分散效果。
在一个实施例中，阵列基板上包括彼此相邻的至少两行像素单元。继续参见图1a，在该两行像素单元之间，孔包括沿栅线101的长度方向延伸的第一孔槽10(打孔位置例如可以是如图1a中的以网格状阴影线表示的长方形所限定的范围)。例如，在制备过程中，可以在相邻两行像素单元之间整行地打孔，之后在溅射源漏金属层时，这些源漏金属层会把第一孔槽10垫高一些。也就是说，阵列基 板上溅射而成的源漏金属层大致相同，且在溅射源漏金属层后，沿栅线101的长度方向排布的第一孔槽10依然存在，只是第一孔槽10的内壁和底部垫高了一些。在蚀刻源漏金属层以形成数据线103时，在纵向排列的数据线103与上述第一孔槽10交叉的位置处会形成悬空。例如，以该方式制备的阵列基板，每个第一孔槽10的长度可以与栅线101的长度大致相等，宽度可以略小于相邻的两行像素单元之间的距离。通过沿栅线101的长度方向整行打孔，并形成沿栅线的长度方向延伸的第一孔槽10，可以有效地隔开两行像素单元，阻断应力传播路径，从而可以有效地减小和分散阵列基板的应力。优选地，在阵列基板上的任意两行相邻像素单元之间均进行整行打孔，从而阻断应力在行与行之间的传递，改善阵列基板的力学性能。
在该实施例中，如上所述，在阵列基板包括设置于衬底基板100且与该衬底基板100接触的缓冲层110的情况下，第一孔槽10可以从绝缘层113的衬底基板100所在侧的相反侧延伸至缓冲层110。例如，沿栅线101的长度方向的横向(图1a和图1b中的左右方向)孔的深度可以在700nm至800nm之间。但孔槽的深度会随着工艺条件的改变而变化，也可以随着某些膜层厚度的变化而变化，本发明对此不作限制。
参见图1a，在一个实施例中，孔还包括沿数据线的长度方向延伸的多个孔20。例如，这些孔设置在相邻两列像素单元之间。需要说明的是，由于栅线101在被打孔的绝缘层113之下，因此为了避免所打的孔与栅线101相交，可以采用在栅线101处断开(不连续)地打孔的方式。如上所述，孔可以为多个间隔开的孔，也可以是在两个栅线101之间且沿数据线103的长度方向分布的多个连续的孔。
在阵列基板设置有缓冲层110且该缓冲层110直接接触阵列基板的一个表面的情况下，沿数据线103的长度方向分布的多个孔可以从绝缘层113的衬底基板100所在侧的相反侧延伸至缓冲层110。这些沿着数据线103的长度方向间隔分布的孔与沿沿栅线101的长度方向间隔分布的第一孔槽10彼此配合，可以从整体上减小和分散阵列基板弯折过程中的应力，避免器件失效。
继续参见图1b，在一个实施例中，阵列基板包括彼此相邻的至少两列像素单元，在该两列像素单元之间，孔包括沿数据线103的长度方向延伸的第二孔槽20。优选地，可以在阵列基板的任意两列像素单元之间都整列地打孔。这些第二孔槽20与第一孔槽10相交，构成网状结构，进而可以有效地阻止阵列基板被弯折时应力沿横向或纵向(图1a和图1b中的上下方向)的传递，提高阵列基板的抗弯折性。
需要说明的是，在该实施例中，由于打孔层(绝缘层)位于栅金属层的上方，并且栅线101沿横向排列，因此在沿数据线103的长度方向整列地打孔时，第二孔槽20不可避免地会与栅线101交叉。从而，第二孔槽20可以包括从绝缘层113 的衬底基板100所在侧的相反侧延伸至缓冲层110的部分和延伸至栅线101的部分。也就是说，第二孔槽20在垂直于衬底基板100的方向上的深度不完全相同。具体地，第二孔槽20包括：延伸至栅线101的部分，该部分的深度为从栅线101到绝缘层113的衬底基板100所在侧的相反侧的距离；以及延伸至缓冲层110的部分(在衬底基板的表面设置有缓冲层的情况下)。当采用同一种干刻法进行第二孔槽20的打孔操作时，例如，该干刻法可以选择性地仅蚀刻非金属材料，从而可以一次得到具有不同深度的第二孔槽20，简化打孔工艺。
继续参见图1a至图3，在一个实施例中，阵列基板还包括位于栅金属层和源漏金属层之间的电容层109，绝缘层包括设置在电容层109与源漏金属层之间的绝缘层113(第一绝缘层113)以及设置于电容层与栅金属层之间的第二绝缘层112。进一步地，在阵列基板的一个表面例如还依次包括缓冲层110、有源层、设置于有源层与栅金属层101之间的第三绝缘层111。在此情况下，设置在电容层109与源漏金属层103之间的第一绝缘层113可以作为打孔起始层。也就是说，上述实施例中各种类型的孔都可以是从第一绝缘层113的衬底基板100所在侧的相反侧朝向衬底基板100延伸的结构。
需要说明的是，该实施例的阵列基板的结构为顶栅结构，但本发明的方案不限于顶栅结构，阵列基板也可以是底栅结构。
在一个实施例中，各个绝缘层都可以为无机绝缘层，其中，无机绝缘层的材料可以包括硅材料，例如无机硅材料。进一步地，无机硅材料可以包括氧化硅和氮化硅中的至少一种。通常来说，采用硅材料作为绝缘材料，阵列基板的各膜层内容易产生或聚集应力，本发明的实施例的孔可以有效地分散和减小膜层内的应力，进而提高阵列基板的性能。
以上实施例可以彼此组合，且具有相应的效果。
本发明的阵列基板可以应用于各种可折叠的显示器件，但本发明对上述阵列基板的应用不做限制。
本发明的另一个方面提供了一种包括上述阵列基板的显示装置，例如OLED显示装置。根据该OLED显示装置，通过在阵列基板的像素单元外部打孔，有效地改善了应力集中的现象，从而提高了器件的抗弯折性能。
本发明的再一个方面提供了一种制备上述阵列基板的方法。参见图4，该方法可以包括如下步骤：
S100：在衬底基板的一侧形成有源层图案、栅金属层图案和绝缘层，其中栅金属层图案包括栅线；和
S200：从绝缘层的衬底基板所在侧的相反侧且在像素单元外部形成朝向衬底基板延伸的孔，其中孔与像素单元不相交。
在S100中，具体地，该步骤中的有源层图案和栅金属层图案都可以采用光刻 法制备。例如，首先在衬底基板上沉积一层缓冲层，随后在缓冲层之上沉积有源层，并通过光刻法形成有源层图案。随后，在有源层上沉积栅金属层，并通过光刻法形成栅线和与栅线连接的栅极。随后，还可以在栅金属层上沉积绝缘层，例如该绝缘层的材料可以为无机材料(例如，可以是包括氧化硅和氮化硅中的至少一种的无机硅材料)。随后，可以进一步在该绝缘层之上沉积电容层，并通过光刻掩膜法形成电容层图案。同样，在该电容层图案之上沉积绝缘层，如上所述，该绝缘层的材料可以为无机材料(例如，可以是包括氧化硅和氮化硅中的至少一种的无机硅材料)。
在S200中，例如，在存在多个绝缘层的情况下，从距离衬底基板最远的绝缘层开始向靠近衬底基板的方向打孔。打孔可以采用干刻法或湿刻法。例如，在打孔位置避开阵列基板的像素单元的情况下，可以尽可能多地打孔，用以最大程度地减小阵列基板的膜层之间的应力。通常情况下，以上孔可以包含两类孔，其中，一类是从距离衬底基板最远的绝缘层的衬底基板所在侧的相反侧延伸至衬底基板附近的孔(这些孔不能打到衬底基板上，以免影响显示效果)，另一类是从距离衬底基板最远的绝缘层的衬底基板所在侧的相反侧延伸至阵列基板的在该绝缘层下方的金属层走线的孔。
另外，也可以选择整行打孔。即在相邻两行像素单元之间，通过干刻法或湿刻法整行地打孔，以形成孔槽结构。该孔槽结构可以有效地避免应力在内膜层之间的传递，改善阵列基板的力学性能。
整行打孔的方法具体可以是但不限于如下方法：
设计掩膜版图案，其中，掩膜版图案包括与绝缘层上的待打孔位置对应的曝光区域，例如，掩膜版图案的曝光区域可以呈长条形，从而使得掩膜版图案上包括与绝缘层上的待打孔位置对应的多个长条，可以理解，这些长条恰好分别位于阵列基板上的相邻两行像素单元之间；
在绝缘层上涂覆光刻胶、进行曝光处理并去除预设打孔区域的光刻胶；以及
通过干刻法或湿刻法对预设打孔区进行蚀刻，直到露出缓冲层(在阵列基板的表面沉积有缓冲层的情况下)，此时，在阵列基板上，相邻两行像素单元之间形成了沿栅线的长度方向延伸的第一孔槽。
此外，也可以选择整列打孔。即在相邻两列像素单元之间，通过干刻法或湿刻法整列地打孔，以形成第二孔槽。该第二孔槽可以有效地避免应力在内膜层之间的传递，改善阵列基板的力学性能。整列打孔的方法与上述整行打孔的方法类似，在此不做赘述。但需要注意，整列打孔时，由于孔会与栅线相交，所以在即将蚀刻到栅线位置时，停止打孔。例如，可以在没有栅金属(栅线)的位置继续蚀刻，直到第二孔槽到达缓冲层为止。
参见图5，在制备阵列基板时，通常在上述步骤之后，还包括如下步骤：
S300：在绝缘层的衬底基板所在侧的相反侧沉积源漏金属层，并通过掩膜曝光形成源漏金属层图案。
需要说明的是，对于常规的孔结构(即前面所述的第一类孔和第二类孔)，例如可以在通过S200形成孔后，对这些孔进行遮挡保护，避免在沉积源漏金属层时，金属材料进入并堵住这些孔。对于通过整行打孔的方式形成的第一孔槽，例如，可以在S200之后，直接沉积源漏金属层，即不需要对第一孔槽进行遮挡，从而简化打孔工艺难度。对于整列打孔形成的第二孔槽，由于这些第二孔槽可能会与栅线相交，所以在S200之后，例如，可以对这些第二孔槽进行遮挡保护，从而避免在沉积源漏金属层时，金属材料进入第二孔槽与栅线接触而发生短路的情况。当然，上述对打孔方式的说明并不意味着只能采取以上方式打相应的孔，仅仅是提供了一种打孔方法。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换等，均应包含在本发明的保护范围之内。
工业实用性
本发明的可折叠阵列基板及其制备方法、显示装置通过在阵列基板的像素单元之外打孔，有效地缓解了阵列基板内的应力，有效地改善了应力集中现象，从而提高了器件的抗弯折性能。

Claims (20)

  1. 一种可折叠阵列基板，其中，包括衬底基板、设置于所述衬底基板的一侧的栅金属层、设置于所述栅金属层的所述衬底基板所在侧的相反侧的源漏金属层以及设置于所述栅金属层和所述源漏金属层之间的绝缘层，
    所述栅金属层包括栅线，所述源漏金属层包括数据线，并且所述栅线和所述数据线交叉设置，以在所述衬底基板上限定多个像素单元，
    所述可折叠阵列基板设置有孔，所述孔不设置在所述像素单元内，所述孔从所述绝缘层的所述衬底基板所在侧的相反侧朝向所述衬底基板延伸。
  2. 根据权利要求1所述的可折叠阵列基板，其中，所述可折叠阵列基板在彼此相邻的两行像素单元之间和/或在彼此相邻的两列像素单元之间包括预设打孔区，所述孔设置于所述预设打孔区内。
  3. 根据权利要求2所述的可折叠阵列基板，其中，所述预设打孔区的宽度在2微米至10微米的范围内。
  4. 根据权利要求1至3中任一项所述的可折叠阵列基板，其中，所述孔至少包括第一类孔，所述第一类孔与所述可折叠阵列基板的各金属层的金属均不相交。
  5. 根据权利要求4所述的可折叠阵列基板，其中，所述第一类孔从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述衬底基板。
  6. 根据权利要求4所述的可折叠阵列基板，其中，所述可折叠阵列基板还包括设置于所述衬底基板的所述一侧且与所述衬底基板接触的缓冲层，所述第一类孔从所述绝缘层的所述衬底基板所在侧的相反侧朝向所述衬底基板延伸至所述缓冲层。
  7. 根据权利要求1至3中任一项所述的可折叠阵列基板，其中，所述孔还包括第二类孔，所述第二类孔从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述栅金属层中的金属走线。
  8. 根据权利要求1至7中任一项所述的可折叠阵列基板，其中，所述可折叠阵列基板还包括彼此相邻的至少两行像素单元，在该两行像素单元之间，所述孔包括沿所述栅线的长度方向延伸的第一孔槽。
  9. 根据权利要求8所述的可折叠阵列基板，其中，所述可折叠阵列基板还包括设置于所述衬底基板的所述一侧且与所述衬底基板接触的缓冲层，所述第一孔槽从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述缓冲层。
  10. 根据权利要求9所述的可折叠阵列基板，其中，所述孔还包括沿所述数据线的长度方向延伸的多个孔。
  11. 根据权利要求10所述的可折叠阵列基板，其中，所述多个孔从所述绝缘 层的所述衬底基板所在侧的相反侧延伸至所述缓冲层。
  12. 根据权利要求1至7中任一项所述的可折叠阵列基板，其中，所述可折叠阵列基板还包括彼此相邻的至少两列像素单元，在该两列像素单元之间，所述孔包括沿所述数据线的长度方向延伸的第二孔槽。
  13. 根据权利要求12所述的可折叠阵列基板，其中，所述第二孔槽包括从所述绝缘层的所述衬底基板所在侧的相反侧延伸至所述缓冲层的部分和延伸至所述栅线的部分。
  14. 根据权利要求1-13中任一项所述的可折叠阵列基板，其中，所述可折叠阵列基板还包括位于所述栅金属层和所述源漏金属层之间的电容层，
    所述绝缘层包括设置在所述电容层与所述源漏金属层之间的第一绝缘层以及设置于所述电容层与所述栅金属层之间的第二绝缘层。
  15. 根据权利要求1至14中的任一项所述的可折叠阵列基板，其中，所述绝缘层的材料包括无机硅材料。
  16. 根据权利要求15所述的可折叠阵列基板，其中，所述无机硅材料包括氧化硅和氮化硅的至少一种。
  17. 一种包括如权利要求1-16中任一项所述的可折叠阵列基板的OLED显示装置。
  18. 一种可折叠阵列基板的制备方法，其中，包括：
    在衬底基板的一侧形成有源层图案、栅金属层图案和绝缘层，其中所述栅金属层图案包括栅线；
    从所述绝缘层的所述衬底基板所在侧的相反侧形成朝向所述衬底基板的方向延伸的孔，其中所述孔不形成在像素单元内且与所述像素单元不相交。
  19. 根据权利要求18所述的可折叠阵列基板的制备方法，其中，所述从所述绝缘层的所述衬底基板所在侧的相反侧形成朝向所述衬底基板的方向延伸的孔包括：
    在彼此相邻的至少一对两行像素单元之间形成沿所述栅线的长度方向延伸的第一孔槽。
  20. 根据权利要求19所述的可折叠阵列基板的制备方法，其中，在所述从所述绝缘层的所述衬底基板所在侧的相反侧形成朝向所述衬底基板的方向延伸的孔之后还包括形成源漏金属层图案，其中所述源漏金属层图案包括数据线，
    所述从所述绝缘层的所述衬底基板所在侧的相反侧形成朝向所述衬底基板的方向延伸的孔还包括：
    在彼此相邻的至少一对两列像素单元之间形成沿所述数据线的长度方向延伸的第二孔槽。
PCT/CN2018/088958 2017-08-31 2018-05-30 可折叠阵列基板及其制备方法、显示装置 WO2019041921A1 (zh)

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