WO2019019395A1 - 一种碳化硅开关器件及制作方法 - Google Patents

一种碳化硅开关器件及制作方法 Download PDF

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WO2019019395A1
WO2019019395A1 PCT/CN2017/104856 CN2017104856W WO2019019395A1 WO 2019019395 A1 WO2019019395 A1 WO 2019019395A1 CN 2017104856 W CN2017104856 W CN 2017104856W WO 2019019395 A1 WO2019019395 A1 WO 2019019395A1
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region
silicon carbide
pwell
conductivity type
doping concentration
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PCT/CN2017/104856
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English (en)
French (fr)
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黄润华
柏松
陶永洪
汪玲
刘奥
李士颜
刘昊
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中国电子科技集团公司第五十五研究所
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Priority to RU2020102072A priority Critical patent/RU2740124C1/ru
Priority to KR1020207001442A priority patent/KR102285500B1/ko
Priority to EP17918868.5A priority patent/EP3637474B1/en
Publication of WO2019019395A1 publication Critical patent/WO2019019395A1/zh

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Definitions

  • the invention belongs to the technical field of semiconductor devices, and in particular relates to a silicon carbide switching device and a manufacturing method thereof.
  • Silicon carbide (SiC) materials have large forbidden band width, high breakdown electric field, high saturation drift velocity and high thermal conductivity. The superior properties of these materials make them ideal materials for high power, high frequency, high temperature and radiation resistant devices. Silicon carbide Schottky diodes have a series of advantages such as high breakdown voltage, high current density, and high operating frequency, so the development prospects are very broad.
  • silicon carbide MOSFET devices are limited by the oxidation level, and the channel mobility is low, which in turn causes the channel resistance to be excessively large in the entire on-resistance.
  • silicon carbide MOSFET devices typically use shorter channels, while short channels typically cause the device's preset voltage to go low, while the device's blocking performance is degraded, and the device's channel length fluctuates. The redundancy is reduced, which affects the productivity of the device.
  • due to the different material properties of silicon carbide its oxidation technology is slow to improve.
  • the channel resistance is the most important factor plaguing device performance for a long time. Therefore, it is necessary to develop a new silicon carbide MOSFET structure to reduce the trench. The proportion of the track resistance.
  • the present invention provides a silicon carbide switching device and a manufacturing method thereof, which reduce the proportion of channel resistance in the on-resistance of the device.
  • the technical solution adopted by the present invention is: a silicon carbide switching device comprising a substrate, the first conductive type drift layer is formed over the substrate, and the second conductive type is formed by ion implantation. a hetero-Pwell region, a first conductivity type N+ region formed by ion implantation, and a second conductivity type doped P+ region formed by ion implantation; the first conductivity type drift layer is sequentially a first conductivity type secondary epitaxial channel region and a second Epitaxial N+ region; a second conductivity type formed by lateral ion implantation on the surface of the device is laterally implanted into the Pwell region; a laterally implanted Pwell region is an oxide gate dielectric layer; a gate dielectric layer is a gate electrode; and a gate electrode is isolated Medium; an ohmic contact drain electrode is disposed under the substrate, and an ohmic contact region is disposed on a side of the device laterally implanted into the Pwell region
  • a manufacturing method of a silicon carbide switching device comprises the following steps:
  • An ohmic contact drain electrode is formed by a metallization process on the back side of the substrate, and an ohmic contact region is formed by high temperature annealing on the side of the upper surface of the device laterally implanted into the Pwell region.
  • the present invention can effectively reduce the proportion of the channel resistance in the on-resistance of the device, and complete the switching of the device through two mechanisms.
  • the sidewall channel of the secondary epitaxial channel region is very short, as long as the shutdown process Producing a sufficiently high voltage drop can turn off the epitaxial drift layer current path without considering the channel punch-through under high voltage, which has a great advantage over the traditional silicon carbide MOSFET; at the same time, the device uses a wider epitaxial drift layer current path. Keeping the preset voltage positive in the case is a big advantage compared to conventional silicon carbide JFETs.
  • Figure 1 is a schematic diagram of epitaxial growth
  • Figure 2 is a schematic view of the injection of the Pwell region
  • Figure 3 is a schematic view of the injection of the N+ region
  • Figure 4 is a schematic view of the injection of the P+ region
  • Figure 5 is a schematic diagram of secondary epitaxial growth
  • FIG. 6 is a schematic diagram of etching of a secondary epitaxial layer
  • Figure 7 is a schematic view of lateral ion implantation of a MOS channel region
  • Figure 8 is a schematic diagram of gate dielectric growth
  • Figure 9 is a schematic view showing the fabrication of a gate electrode
  • Figure 10 is a schematic view showing the growth of an isolation medium
  • Figure 11 is a schematic view of dielectric hole etching
  • Figure 12 is a schematic illustration of ohmic contact metallization.
  • the silicon carbide switching device and the manufacturing method thereof according to the present invention comprise the following process steps:
  • the first conductive type substrate 1 is a silicon carbide or silicon crystal, for example, a 4H, 6H, 3C crystal structure having a doping concentration of 1E19 cm-3 or more.
  • the drift layer 2 is a silicon carbide film, for example, a 4H, 6H, 3C crystal structure having a doping concentration of between 1E14 cm-3 and 1.5E16 cm-3.
  • the doping impurity is a nitrogen atom
  • the doping impurity is aluminum.
  • a second conductive type doped region P+ region 10 is formed on the doped Pwell region 3 by ion implantation, and the P+ region 10 is connected to the N+ region 4 and the doped Pwell region 3;
  • the first conductivity type secondary epitaxial channel region 5 and the secondary epitaxial N + region 6 are formed by epitaxial growth on the surface of the device;
  • the thickness of the secondary epitaxial channel region 5 is less than 2 microns.
  • the top structure processing of the device is completed by two epitaxial growth of the second epitaxial channel region 5 and the second epitaxial N+ region 6, wherein the doping concentration of the second epitaxial channel region 5 is lower than the doping concentration of the laterally implanted Pwell region 7,
  • the secondary epitaxial N+ region 6 has a higher doping concentration, which is much higher than the concentration of the laterally implanted Pwell region 7.
  • the doping concentration of the N+ region 4 is much higher than that of the laterally implanted Pwell region 7, and the secondary epitaxial channel region 5 is doped.
  • the concentration is higher than that of the drift layer 2, such a structure that the channel length on the sidewalls of the secondary epitaxial channel region 5 is completely dependent on the epitaxial growth thickness.
  • the laterally implanted Pwell region 7 employs lateral ion implantation with an angle between the implant and the wafer surface of between 85 and 0 degrees. This method enables the formation of a channel on the sidewall and ensures a second type of doping on the sidewall.
  • the area has a sufficient width.
  • the oxide layer gate dielectric layer 8 is formed by high temperature oxidation on the laterally implanted Pwell region 7, and the gate dielectric layer is grown to a thickness of between 0.005 um and 1 um;
  • the isolation medium 11 is grown on the surface of the device
  • the dielectric hole is opened by etching
  • an ohmic contact drain electrode 13 is formed on the back surface of the substrate 1 by a metallization process, and an ohmic contact region 12 is formed by high temperature annealing on the side of the upper surface of the device which is laterally implanted into the Pwell region 7.
  • the gate electrode 9 When the gate electrode 9 is applied with a forward voltage, a portion of the semiconductor sidewall surface intersecting the secondary epitaxial channel region 5 and the laterally implanted Pwell region 7 is inverted to form a conductive channel, and the switching device is turned on; when the voltage applied to the gate electrode 9 is gradually applied When decreasing, the channel resistance increases rapidly, which causes a current to flow through the channel to generate a larger voltage drop. Since the N+ region 4, the P+ region 10 and the doped Pwell region 3 are connected, the potentials of the three regions are the same, and thus the generated voltage is generated.
  • the drop will cause the potential of the epitaxial drift layer 2 to be higher than that of the doped Pwell region 3, and thus the width of the depletion region of the doped Pwell region 3 in the epitaxial drift layer 2 increases, and as the voltage gradually decreases, the doped Pwell region 3
  • the depletion region in the epitaxial drift layer 2 is getting larger and larger, and the current path in the epitaxial drift layer 2 is finally completely turned off.
  • the sidewall channel of the secondary epitaxial channel region 5 can be very short, only To generate a sufficiently high voltage drop during the turn-off process, the epitaxial drift layer 2 current path can be turned off without considering the channel punch-through under high voltage, which has a great advantage over the conventional silicon carbide MOSFET.
  • the device can maintain a preset voltage with a positive value in the case of a wide epitaxial drift layer 2 current path, which has a great advantage compared with the conventional silicon carbide JFET, and the device is a normally-off device.

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Abstract

本发明公开了一种碳化硅开关器件及制作方法，降低沟道电阻在器件导通电阻中所占比例。本发明通过两次外延生长完成器件顶部结构加工，二次外延沟道区掺杂浓度低于侧向注入Pwell区的掺杂浓度，二次外延N+区掺杂浓度远高于侧向注入Pwell区的浓度，N+区的掺杂浓度远高于侧向注入Pwell区，这种结构使得二次外延沟道区侧壁上的沟道长度取决于外延生长厚度。本发明采用两种机制完成器件的开关，二次外延沟道区的侧壁沟道非常短，在关断过程中产生足够高的压降就可以将外延漂移层电流通路关断，不用考虑高压下的沟道穿通，与传统碳化硅MOSFET相比有较大优势，同时采用较宽外延漂移层电流通路，保持预置电压为正值，与传统碳化硅JFET相比有很大的优势。

Description

一种碳化硅开关器件及制作方法 技术领域
本发明属于半导体器件技术领域，尤其涉及一种碳化硅开关器件及制作方法。
背景技术
碳化硅(SiC)材料禁带宽度大、击穿电场高、饱和漂移速度和热导率大，这些材料优越性能使其成为制作高功率、高频、耐高温、抗辐射器件的理想材料。碳化硅肖特基二极管具有击穿电压高、电流密度大、工作频率高等一系列优点，因此发展前景非常广泛。
目前碳化硅MOSFET器件受氧化水平的限制，沟道迁移率偏低，进而造成沟道电阻在整个导通电阻中的比例过大。为了实现较好的导通能力，碳化硅MOSFET器件通常采用较短的沟道，而短沟道通常会导致器件的预置电压变低，同时器件的阻断性能下降，器件对沟道长度波动的冗余减小，影响器件的可生产性。同时碳化硅由于其材料性质的不同，其氧化技术提升速度缓慢，沟道电阻在很长时间内都是困扰器件性能的最主要原因，因此需要开发一种新的碳化硅MOSFET结构来减小沟道电阻所占比例。
发明内容
发明目的：针对以上问题，本发明提出一种碳化硅开关器件及制作方法，降低沟道电阻在器件导通电阻中所占比例。
技术方案：为实现本发明的目的，本发明所采用的技术方案是：一种碳化硅开关器件，包括衬底，衬底上方包括第一导电类型漂移层、离子注入形成的第二导电类型掺杂Pwell区、离子注入形成的第一导电类型N+区和离子注入形成的第二导电类型掺杂P+区；第一导电类型漂移层上方依次为第一导电类型二次外延沟道区和二次外延N+区；在器件表面通过侧向离子注入形成的第二导电类型侧向注入Pwell区；侧向注入Pwell区上方为氧化层栅介质层；栅介质层上方为栅电极；栅电极上方为隔离介质；衬底下方设置欧姆接触漏电极，器件上方侧向注入Pwell区一侧设置欧姆接触区。
一种碳化硅开关器件的制作方法，具体包括以下步骤：
(1)在第一导电类型衬底上外延生长第一导电类型漂移层；
(2)在漂移层上通过离子注入形成第二导电类型掺杂Pwell区；
(3)在掺杂Pwell区上通过离子注入形成第一导电类型N+区；
(4)在掺杂Pwell区上通过离子注入形成第二导电类型掺杂区P+区，P+区与N+区和掺杂Pwell区均相连；
(5)在器件表面外延生长顺序形成第一导电类型二次外延沟道区和二次外延N+区；
(6)在二次外延沟道区和二次外延N+区通过刻蚀工艺形成碳化硅台阶；
(7)在器件表面通过侧向离子注入形成第二导电类型侧向注入Pwell区；
(8)在侧向注入Pwell区上通过高温氧化形成氧化层栅介质层；
(9)在器件表面一侧通过生长制作栅电极；
(10)在器件表面生长隔离介质；
(11)在隔离介质和栅介质层上通过刻蚀开介质孔；
(12)在衬底背面通过金属化工艺制作欧姆接触漏电极，并在器件上表面侧向注入Pwell区一侧通过高温退火形成欧姆接触区。
有益效果：本发明可以有效降低沟道电阻在器件导通电阻中所占比例，并通过两种机制完成器件的开关，二次外延沟道区的侧壁沟道非常短，只要在关断过程中产生足够高的压降就可以将外延漂移层电流通路关断而不用考虑高压下的沟道穿通，与传统的碳化硅MOSFET有较大优势；同时器件采用较宽的外延漂移层电流通路的情况下保持预置电压为正值，与传统的碳化硅JFET相比具有很大的优势。
附图说明
图1是外延生长示意图；
图2是Pwell区注入示意图；
图3是N+区注入示意图；
图4是P+区注入示意图；
图5是二次外延生长示意图；
图6是二次外延层刻蚀示意图；
图7是MOS沟道区侧向离子注入示意图；
图8是栅介质生长示意图；
图9是栅电极制作示意图；
图10是隔离介质生长示意图；
图11是介质孔刻蚀示意图；
图12是欧姆接触金属化示意图。
具体实施方式
下面结合附图和实施例对本发明的技术方案作进一步的说明。
本发明所述的碳化硅开关器件及制作方法，包括如下工艺步骤：
(1)如图1所示，在第一导电类型衬底1上通过外延生长第一导电类型漂移层2；
第一导电类型衬底1为碳化硅或硅晶体，例如4H、6H、3C晶体结构，其掺杂浓度在1E19cm-3以上。
(2)如图2所示，在漂移层2上通过离子注入形成第二导电类型掺杂Pwell区3；
漂移层2为碳化硅薄膜，例如4H、6H、3C晶体结构，其掺杂浓度在1E14cm-3到1.5E16cm-3之间。当第一导电类型为N型掺杂时，掺杂杂质为氮原子，当第一导电类型为P型掺杂时，掺杂杂质为铝。
(3)如图3所示，在掺杂Pwell区3上通过离子注入形成第一导电类型N+区4；
(4)如图4所示，在掺杂Pwell区3上通过离子注入形成第二导电类型掺杂区P+区10，P+区10与N+区4和掺杂Pwell区3相连；
(5)如图5所示，在器件表面通过外延生长顺序形成第一导电类型二次外延沟道区5和二次外延N+区6；
二次外延沟道区5的厚度小于2微米。通过二次外延沟道区5和二次外延N+区6两次外延生长完成器件顶部结构加工，其中，二次外延沟道区5掺杂浓度低于侧向注入Pwell区7的掺杂浓度，二次外延N+区6掺杂浓度较高，远高于侧向注入Pwell区7的浓度，N+区4的掺杂浓度远高于侧向注入Pwell区7，二次外延沟道区5掺杂浓度高于漂移层2，这样的结构使得二次外延沟道区5侧壁上的沟道长度完全取决于外延生长厚度。
(6)如图6所示，通过刻蚀工艺形成碳化硅台阶；
(7)如图7所示，在器件表面侧向离子注入形成第二导电类型侧向注入Pwell区7；
侧向注入Pwell区7采用侧向离子注入，注入方向与晶圆表面夹角在85到0度之间，采用这一方法能够在侧壁上形成沟道并且保证侧壁上第二类型掺杂区具有足够的宽度。
(8)如图8所示，在侧向注入Pwell区7上通过高温氧化形成氧化层栅介质层8，栅介质层生长厚度在0.005um到1um之间；
(9)如图9所示，再在栅介质层8上通过生长制作栅电极9；
(10)如图10所示，在器件表面生长隔离介质11；
(11)如图11所示，通过刻蚀开介质孔；
(12)如图12所示，在衬底1背面通过金属化工艺制作欧姆接触漏电极13，并在器件上表面侧向注入Pwell区7一侧通过高温退火形成欧姆接触区12。
当栅电极9加正向电压，二次外延沟道区5和侧向注入Pwell区7相交的部分半导体侧壁表面反型形成导电沟道，开关器件导通；当栅电极9所加电压逐渐降低时，沟道电阻快速增大，进而造成电流流经沟道产生更大的压降，由于N+区4、P+区10和掺杂Pwell区3相连，三个区域电位相同，因此产生的压降将导致外延漂移层2的电位高于掺杂Pwell区3，进而掺杂Pwell区3在外延漂移层2中的耗尽区宽度增大，随着电压的逐渐降低，掺杂Pwell区3在外延漂移层2中的耗尽区越来越大，最终将外延漂移层2中的电流通路彻底关断。
通过以上两种机制完成器件的开关，二次外延沟道区5的侧壁沟道可以非常短，只 要在关断过程中产生足够高的压降就可以将外延漂移层2电流通路关断而不用考虑高压下的沟道穿通，与传统的碳化硅MOSFET有较大优势。同时器件可以采用较宽的外延漂移层2电流通路的情况下保持预置电压为正值，与传统的碳化硅JFET相比具有很大的优势，器件为常关器件。

Claims (9)

  1. 一种碳化硅开关器件，其特征在于：包括衬底，衬底上方包括第一导电类型漂移层、离子注入形成的第二导电类型掺杂Pwell区、离子注入形成的第一导电类型N+区和离子注入形成的第二导电类型掺杂P+区；
    第一导电类型漂移层上方依次为第一导电类型二次外延沟道区和二次外延N+区；在器件表面通过侧向离子注入形成的第二导电类型侧向注入Pwell区；
    侧向注入Pwell区上方为氧化层栅介质层；栅介质层上方为栅电极；栅电极上方为隔离介质；
    衬底下方设置欧姆接触漏电极，器件上方侧向注入Pwell区一侧设置欧姆接触区。
  2. 根据权利要求1所述的碳化硅开关器件，其特征在于：第二导电类型掺杂Pwell区注入深度小于第一导电类型漂移层注入深度，第一导电类型N+区和第二导电类型掺杂P+区输入深度小于第二导电类型掺杂Pwell区。
  3. 根据权利要求1所述的碳化硅开关器件，其特征在于：二次外延N+区的掺杂浓度高于侧向注入Pwell区的掺杂浓度，N+区的掺杂浓度高于侧向注入Pwell区的掺杂浓度。
  4. 根据权利要求1所述的碳化硅开关器件，其特征在于：侧向注入Pwell区的掺杂浓度高于二次外延沟道区的掺杂浓度。
  5. 根据权利要求1所述的碳化硅开关器件，其特征在于：二次外延沟道区的掺杂浓度高于漂移层的掺杂浓度。
  6. 根据权利要求1所述的碳化硅开关器件，其特征在于：二次外延沟道区的厚度小于2微米。
  7. 根据权利要求1所述的碳化硅开关器件，其特征在于：栅介质层的生长厚度为0.005-1um。
  8. 一种碳化硅开关器件的制作方法，其特征在于：具体包括以下步骤：
    (1)在第一导电类型衬底上外延生长第一导电类型漂移层；
    (2)在漂移层上通过离子注入形成第二导电类型掺杂Pwell区；
    (3)在掺杂Pwell区上通过离子注入形成第一导电类型N+区；
    (4)在掺杂Pwell区上通过离子注入形成第二导电类型掺杂区P+区，P+区与N+区和掺杂Pwell区均相连；
    (5)在器件表面外延生长顺序形成第一导电类型二次外延沟道区和二次外延N+区；
    (6)在二次外延沟道区和二次外延N+区通过刻蚀工艺形成碳化硅台阶；
    (7)在器件表面通过侧向离子注入形成第二导电类型侧向注入Pwell区；
    (8)在侧向注入Pwell区上通过高温氧化形成氧化层栅介质层；
    (9)在器件表面一侧通过生长制作栅电极；
    (10)在器件表面生长隔离介质；
    (11)在隔离介质和栅介质层上通过刻蚀开介质孔；
    (12)在衬底背面通过金属化工艺制作欧姆接触漏电极，并在器件上表面侧向注入Pwell区一侧通过高温退火形成欧姆接触区。
  9. 根据权利要求8所述的碳化硅开关器件的制作方法，其特征在于：所述步骤(7)中注入方向与器件表面夹角为85-0度。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020139992A1 (en) * 2001-03-30 2002-10-03 Rajesh Kumar Silicon carbide semiconductor device and method of fabricating the same
CN104319292A (zh) * 2014-11-06 2015-01-28 株洲南车时代电气股份有限公司 一种新型碳化硅mosfet及其制造方法
CN104979395A (zh) * 2014-04-03 2015-10-14 财团法人工业技术研究院 半导体结构
CN106847879A (zh) * 2017-01-19 2017-06-13 北京世纪金光半导体有限公司 一种斜面沟道的SiC MOSFET器件及制备方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2046455C1 (ru) * 1992-04-13 1995-10-20 Минский научно-исследовательский приборостроительный институт Способ включения полевого транзистора с управляющим p-n-переходом
RU2054752C1 (ru) * 1993-02-25 1996-02-20 Александр Алексеевич Красин Комплементарный ключ
US5907169A (en) * 1997-04-18 1999-05-25 Megamos Corporation Self-aligned and process-adjusted high density power transistor with gate sidewalls provided with punch through prevention and reduced JFET resistance
JP5017768B2 (ja) * 2004-05-31 2012-09-05 富士電機株式会社 炭化珪素半導体素子
US7314799B2 (en) * 2005-12-05 2008-01-01 Semisouth Laboratories, Inc. Self-aligned trench field effect transistors with regrown gates and bipolar junction transistors with regrown base contact regions and methods of making
EP2674966B1 (en) * 2006-06-29 2019-10-23 Cree, Inc. Silicon carbide switching devices including P-type channels
WO2009050871A1 (ja) * 2007-10-15 2009-04-23 Panasonic Corporation 半導体装置およびその製造方法
US8610130B2 (en) * 2009-10-30 2013-12-17 Cree, Inc. Monolithic high voltage switching devices
JP6182921B2 (ja) * 2013-03-21 2017-08-23 富士電機株式会社 Ｍｏｓ型半導体装置
JP6067133B2 (ja) * 2013-10-17 2017-01-25 三菱電機株式会社 炭化珪素半導体装置
CN106409915A (zh) * 2016-11-25 2017-02-15 东莞市联洲知识产权运营管理有限公司 一种垂直双扩散金属氧化物半导体场效应晶体管

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020139992A1 (en) * 2001-03-30 2002-10-03 Rajesh Kumar Silicon carbide semiconductor device and method of fabricating the same
CN104979395A (zh) * 2014-04-03 2015-10-14 财团法人工业技术研究院 半导体结构
CN104319292A (zh) * 2014-11-06 2015-01-28 株洲南车时代电气股份有限公司 一种新型碳化硅mosfet及其制造方法
CN106847879A (zh) * 2017-01-19 2017-06-13 北京世纪金光半导体有限公司 一种斜面沟道的SiC MOSFET器件及制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3637474A4 *

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