CN107681001A - 一种碳化硅开关器件及制作方法 - Google Patents

一种碳化硅开关器件及制作方法 Download PDF

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CN107681001A
CN107681001A CN201710605642.8A CN201710605642A CN107681001A CN 107681001 A CN107681001 A CN 107681001A CN 201710605642 A CN201710605642 A CN 201710605642A CN 107681001 A CN107681001 A CN 107681001A
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conduction type
pwell
silicon carbide
doping
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CN107681001B (zh
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黄润华
柏松
陶永洪
汪玲
刘奥
李士颜
刘昊
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CETC 55 Research Institute
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Priority to PCT/CN2017/104856 priority patent/WO2019019395A1/zh
Priority to RU2020102072A priority patent/RU2740124C1/ru
Priority to EP17918868.5A priority patent/EP3637474B1/en
Priority to KR1020207001442A priority patent/KR102285500B1/ko
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Abstract

本发明公开了一种碳化硅开关器件及制作方法，降低沟道电阻在器件导通电阻中所占比例。本发明通过两次外延生长完成器件顶部结构加工，二次外延沟道区掺杂浓度低于侧向注入Pwell区的掺杂浓度，二次外延N+区掺杂浓度远高于侧向注入Pwell区的浓度，N+区的掺杂浓度远高于侧向注入Pwell区，这种结构使得二次外延沟道区侧壁上的沟道长度取决于外延生长厚度。本发明采用两种机制完成器件的开关，二次外延沟道区的侧壁沟道非常短，在关断过程中产生足够高的压降就可以将外延漂移层电流通路关断，不用考虑高压下的沟道穿通，与传统碳化硅MOSFET相比有较大优势，同时采用较宽外延漂移层电流通路，保持预置电压为正值，与传统碳化硅JFET相比有很大的优势。

Description

一种碳化硅开关器件及制作方法
技术领域
本发明属于半导体器件技术领域，尤其涉及一种碳化硅开关器件及制作方法。
背景技术
碳化硅(SiC)材料禁带宽度大、击穿电场高、饱和漂移速度和热导率大，这些材料优越性能使其成为制作高功率、高频、耐高温、抗辐射器件的理想材料。碳化硅肖特基二极管具有击穿电压高、电流密度大、工作频率高等一系列优点，因此发展前景非常广泛。
目前碳化硅MOSFET器件受氧化水平的限制，沟道迁移率偏低，进而造成沟道电阻在整个导通电阻中的比例过大。为了实现较好的导通能力，碳化硅MOSFET器件通常采用较短的沟道，而短沟道通常会导致器件的预置电压变低，同时器件的阻断性能下降，器件对沟道长度波动的冗余减小，影响器件的可生产性。同时碳化硅由于其材料性质的不同，其氧化技术提升速度缓慢，沟道电阻在很长时间内都是困扰器件性能的最主要原因，因此需要开发一种新的碳化硅MOSFET结构来减小沟道电阻所占比例。
发明内容
发明目的：针对以上问题，本发明提出一种碳化硅开关器件及制作方法，降低沟道电阻在器件导通电阻中所占比例。
技术方案：为实现本发明的目的，本发明所采用的技术方案是：一种碳化硅开关器件，包括衬底，衬底上方包括第一导电类型漂移层、离子注入形成的第二导电类型掺杂Pwell区、离子注入形成的第一导电类型N+区和离子注入形成的第二导电类型掺杂P+区；第一导电类型漂移层上方依次为第一导电类型二次外延沟道区和二次外延N+区；在器件表面通过侧向离子注入形成的第二导电类型侧向注入Pwell区；侧向注入Pwell区上方为氧化层栅介质层；栅介质层上方为栅电极；栅电极上方为隔离介质；衬底下方设置欧姆接触漏电极，器件上方侧向注入Pwell区一侧设置欧姆接触区。
一种碳化硅开关器件的制作方法，具体包括以下步骤：
(1)在第一导电类型衬底上外延生长第一导电类型漂移层；
(2)在漂移层上通过离子注入形成第二导电类型掺杂Pwell区；
(3)在掺杂Pwell区上通过离子注入形成第一导电类型N+区；
(4)在掺杂Pwell区上通过离子注入形成第二导电类型掺杂区P+区，P+区与N+区和掺杂Pwell区均相连；
(5)在器件表面外延生长顺序形成第一导电类型二次外延沟道区和二次外延N+区；
(6)在二次外延沟道区和二次外延N+区通过刻蚀工艺形成碳化硅台阶；
(7)在器件表面通过侧向离子注入形成第二导电类型侧向注入Pwell区；
(8)在侧向注入Pwell区上通过高温氧化形成氧化层栅介质层；
(9)在器件表面一侧通过生长制作栅电极；
(10)在器件表面生长隔离介质；
(11)在隔离介质和栅介质层上通过刻蚀开介质孔；
(12)在衬底背面通过金属化工艺制作欧姆接触漏电极，并在器件上表面侧向注入Pwell区一侧通过高温退火形成欧姆接触区。
有益效果：本发明可以有效降低沟道电阻在器件导通电阻中所占比例，并通过两种机制完成器件的开关，二次外延沟道区的侧壁沟道非常短，只要在关断过程中产生足够高的压降就可以将外延漂移层电流通路关断而不用考虑高压下的沟道穿通，与传统的碳化硅MOSFET有较大优势；同时器件采用较宽的外延漂移层电流通路的情况下保持预置电压为正值，与传统的碳化硅JFET相比具有很大的优势。
附图说明
图1是外延生长示意图；
图2是Pwell区注入示意图；
图3是N+区注入示意图；
图4是P+区注入示意图；
图5是二次外延生长示意图；
图6是二次外延层刻蚀示意图；
图7是MOS沟道区侧向离子注入示意图；
图8是栅介质生长示意图；
图9是栅电极制作示意图；
图10是隔离介质生长示意图；
图11是介质孔刻蚀示意图；
图12是欧姆接触金属化示意图。
具体实施方式
下面结合附图和实施例对本发明的技术方案作进一步的说明。
本发明所述的碳化硅开关器件及制作方法，包括如下工艺步骤：
(1)如图1所示，在第一导电类型衬底1上通过外延生长第一导电类型漂移层2；
第一导电类型衬底1为碳化硅或硅晶体，例如4H、6H、3C晶体结构，其掺杂浓度在1E19cm-3以上。
(2)如图2所示，在漂移层2上通过离子注入形成第二导电类型掺杂Pwell区3；
漂移层2为碳化硅薄膜，例如4H、6H、3C晶体结构，其掺杂浓度在1E14cm-3到1.5E16cm-3之间。当第一导电类型为N型掺杂时，掺杂杂质为氮原子，当第一导电类型为P型掺杂时，掺杂杂质为铝。
(3)如图3所示，在掺杂Pwell区3上通过离子注入形成第一导电类型N+区4；
(4)如图4所示，在掺杂Pwell区3上通过离子注入形成第二导电类型掺杂区P+区10，P+区10与N+区4和掺杂Pwell区3相连；
(5)如图5所示，在器件表面通过外延生长顺序形成第一导电类型二次外延沟道区5和二次外延N+区6；
二次外延沟道区5的厚度小于2微米。通过二次外延沟道区5和二次外延N+区6两次外延生长完成器件顶部结构加工，其中，二次外延沟道区5掺杂浓度低于侧向注入Pwell区7的掺杂浓度，二次外延N+区6掺杂浓度较高，远高于侧向注入Pwell区7的浓度，N+区4的掺杂浓度远高于侧向注入Pwell区7，二次外延沟道区5掺杂浓度高于漂移层2，这样的结构使得二次外延沟道区5侧壁上的沟道长度完全取决于外延生长厚度。
(6)如图6所示，通过刻蚀工艺形成碳化硅台阶；
(7)如图7所示，在器件表面侧向离子注入形成第二导电类型侧向注入Pwell区7；
侧向注入Pwell区7采用侧向离子注入，注入方向与晶圆表面夹角在85到0度之间，采用这一方法能够在侧壁上形成沟道并且保证侧壁上第二类型掺杂区具有足够的宽度。
(8)如图8所示，在侧向注入Pwell区7上通过高温氧化形成氧化层栅介质层8，栅介质层生长厚度在0.005um到1um之间；
(9)如图9所示，再在栅介质层8上通过生长制作栅电极9；
(10)如图10所示，在器件表面生长隔离介质11；
(11)如图11所示，通过刻蚀开介质孔；
(12)如图12所示，在衬底1背面通过金属化工艺制作欧姆接触漏电极13，并在器件上表面侧向注入Pwell区7一侧通过高温退火形成欧姆接触区12。
当栅电极9加正向电压，二次外延沟道区5和侧向注入Pwell区7相交的部分半导体侧壁表面反型形成导电沟道，开关器件导通；当栅电极9所加电压逐渐降低时，沟道电阻快速增大，进而造成电流流经沟道产生更大的压降，由于N+区4、P+区10和掺杂Pwell区3相连，三个区域电位相同，因此产生的压降将导致外延漂移层2的电位高于掺杂Pwell区3，进而掺杂Pwell区3在外延漂移层2中的耗尽区宽度增大，随着电压的逐渐降低，掺杂Pwell区3在外延漂移层2中的耗尽区越来越大，最终将外延漂移层2中的电流通路彻底关断。
通过以上两种机制完成器件的开关，二次外延沟道区5的侧壁沟道可以非常短，只要在关断过程中产生足够高的压降就可以将外延漂移层2电流通路关断而不用考虑高压下的沟道穿通，与传统的碳化硅MOSFET有较大优势。同时器件可以采用较宽的外延漂移层2电流通路的情况下保持预置电压为正值，与传统的碳化硅JFET相比具有很大的优势，器件为常关器件。

Claims (9)

1.一种碳化硅开关器件，其特征在于：包括衬底，衬底上方包括第一导电类型漂移层、离子注入形成的第二导电类型掺杂Pwell区、离子注入形成的第一导电类型N+区和离子注入形成的第二导电类型掺杂P+区；
第一导电类型漂移层上方依次为第一导电类型二次外延沟道区和二次外延N+区；在器件表面通过侧向离子注入形成的第二导电类型侧向注入Pwell区；
侧向注入Pwell区上方为氧化层栅介质层；栅介质层上方为栅电极；栅电极上方为隔离介质；
衬底下方设置欧姆接触漏电极，器件上方侧向注入Pwell区一侧设置欧姆接触区。
2.根据权利要求1所述的碳化硅开关器件，其特征在于：第二导电类型掺杂Pwell区注入深度小于第一导电类型漂移层注入深度，第一导电类型N+区和第二导电类型掺杂P+区输入深度小于第二导电类型掺杂Pwell区。
3.根据权利要求1所述的碳化硅开关器件，其特征在于：二次外延N+区的掺杂浓度高于侧向注入Pwell区的掺杂浓度，N+区的掺杂浓度高于侧向注入Pwell区的掺杂浓度。
4.根据权利要求1所述的碳化硅开关器件，其特征在于：侧向注入Pwell区的掺杂浓度高于二次外延沟道区的掺杂浓度。
5.根据权利要求1所述的碳化硅开关器件，其特征在于：二次外延沟道区的掺杂浓度高于漂移层的掺杂浓度。
6.根据权利要求1所述的碳化硅开关器件，其特征在于：二次外延沟道区的厚度小于2微米。
7.根据权利要求1所述的碳化硅开关器件，其特征在于：栅介质层的生长厚度为0.005-1um。
8.一种碳化硅开关器件的制作方法，其特征在于：具体包括以下步骤：
(1)在第一导电类型衬底上外延生长第一导电类型漂移层；
(2)在漂移层上通过离子注入形成第二导电类型掺杂Pwell区；
(3)在掺杂Pwell区上通过离子注入形成第一导电类型N+区；
(4)在掺杂Pwell区上通过离子注入形成第二导电类型掺杂区P+区，P+区与N+区和掺杂Pwell区均相连；
(5)在器件表面外延生长顺序形成第一导电类型二次外延沟道区和二次外延N+区；
(6)在二次外延沟道区和二次外延N+区通过刻蚀工艺形成碳化硅台阶；
(7)在器件表面通过侧向离子注入形成第二导电类型侧向注入Pwell区；
(8)在侧向注入Pwell区上通过高温氧化形成氧化层栅介质层；
(9)在器件表面一侧通过生长制作栅电极；
(10)在器件表面生长隔离介质；
(11)在隔离介质和栅介质层上通过刻蚀开介质孔；
(12)在衬底背面通过金属化工艺制作欧姆接触漏电极，并在器件上表面侧向注入Pwell区一侧通过高温退火形成欧姆接触区。
9.根据权利要求8所述的碳化硅开关器件的制作方法，其特征在于：所述步骤(7)中注入方向与器件表面夹角为85-0度。
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