WO2019015291A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2019015291A1
WO2019015291A1 PCT/CN2018/074131 CN2018074131W WO2019015291A1 WO 2019015291 A1 WO2019015291 A1 WO 2019015291A1 CN 2018074131 W CN2018074131 W CN 2018074131W WO 2019015291 A1 WO2019015291 A1 WO 2019015291A1
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Prior art keywords
signal line
groove
insulating layer
substrate
array substrate
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Application number
PCT/CN2018/074131
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English (en)
French (fr)
Inventor
张国林
程久阳
邹佳洪
肖文豪
李俊良
马一鸿
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/082,709 priority Critical patent/US10935857B2/en
Priority to EP18759018.7A priority patent/EP3657241B1/en
Publication of WO2019015291A1 publication Critical patent/WO2019015291A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • At least one embodiment of the present disclosure is directed to an array substrate, a method of fabricating the same, and a display device.
  • the market-leading thin film transistor liquid crystal display in the flat panel display market is a display that needs to rely on a backlight for display.
  • the main structure of the display includes an array substrate, a liquid crystal, and a color filter substrate, wherein the array substrate can determine the resolution, viewing angle, and the like of the thin film transistor liquid crystal display.
  • At least one embodiment of the present disclosure provides an array substrate including: a substrate substrate; a first signal line extending along a first direction on the substrate substrate; and a second signal line extending along the second direction at the first
  • the signal line is away from the side of the substrate substrate and insulated from the first signal line, and the first direction and the second direction intersect each other, wherein a side of the first signal line facing the second signal line is provided with a groove, and the groove is located At the intersection between the first signal line and the second signal line, at the intersection, the orthographic projection of the second signal line on the substrate substrate completely falls into the orthographic projection of the groove in the substrate.
  • the first signal line further includes a first portion and a second portion on both sides of the groove, the first portion includes a first connection portion connected to the groove, and the second portion includes And a second connecting portion connected to the groove, wherein the largest dimension of the groove is larger than the size of at least one of the first connecting portion and the second connecting portion.
  • the method further includes: a first insulating layer between the first signal line and the second signal line.
  • the method further includes: a second insulating layer between the first signal line and the second signal line, wherein the second insulating layer is orthographically projected on the substrate
  • the orthographic projections of the grooves on the substrate are completely coincident, and the thickness of the second insulating layer is the same as the depth of the grooves in a direction perpendicular to the substrate to compensate for the first signal line or the first insulating layer away from the substrate The difference in height of the surface relative to the substrate due to the grooves.
  • the second insulating layer is located between the first insulating layer and the first signal line or between the first insulating layer and the second signal line.
  • the ratio of the depth of the groove to the thickness of the portion of the first signal line not including the groove is not more than 1:2 in a direction perpendicular to the substrate.
  • one of the first signal line and the second signal line is a scan line, and the other is a data line.
  • At least one embodiment of the present disclosure provides a method of fabricating an array substrate, comprising: forming a first signal line extending along a first direction on a substrate; forming a groove on a side of the first signal line away from the substrate Forming a second signal line extending along the second direction on the first signal line, the second signal line and the first signal line are insulated from each other, the first direction and the second direction intersect each other, wherein the groove is located at the first signal line At the intersection with the second signal line, at the intersection, the orthographic projection of the second signal line on the substrate substrate completely falls within the orthographic projection of the groove in the substrate.
  • forming the recess includes: forming a first insulating layer on the first signal line; and etching the first insulating layer at the intersection to form a via hole Exposing the first signal line; etching the exposed first signal line to form a groove.
  • the method before the forming the second signal line, the method further includes: filling the recess and the via with an insulating material, wherein the recess is filled with an insulating material to form a second insulating layer.
  • the surface of the second insulating layer is flush with the surface of the first signal line, and the via hole is filled with an insulating material to make the thickness of the first insulating layer uniform.
  • forming the recess includes: forming a photoresist pattern on the first signal line; and etching the first signal line by using the photoresist pattern as a mask A groove is formed.
  • the first signal line and the groove are patterned by the same mask and formed by a halftone mask process.
  • the method before the forming the second signal line, the method further includes: filling the recess with an insulating material to form a second insulating layer, the surface of the second insulating layer and the first signal line The surface is flush; a first insulating layer is formed on the first signal line and the second insulating layer.
  • the method before the forming the second signal line, the method further includes: forming a first insulating layer on the first signal line, where the first insulating layer is located at a position of the groove to form a depressed portion Filling the recess with an insulating material to form a second insulating layer, the surface of the second insulating layer being flush with the surface of the first insulating layer.
  • the first signal line further includes a first portion and a second portion on both sides of the groove, and the first portion includes a first connection portion connected to the groove,
  • the second portion includes a second connection portion connected to the groove, wherein forming the first signal line includes: patterning the first signal line such that the first signal line in the second direction is at a position where the groove is to be formed Greater than the size of at least one of the first connecting portion and the second connecting portion.
  • the ratio of the depth of the groove to the thickness of the portion of the first signal line not including the groove is not more than 1: in a direction perpendicular to the substrate. 2.
  • At least one embodiment of the present disclosure provides a display device including any of the array substrates provided in the above embodiments.
  • 1 is a partial schematic view of an array substrate
  • FIG. 2 is a partial schematic view of an array substrate according to an embodiment of the present disclosure
  • 3A is a partial plan view showing a groove and a first signal line in the vicinity thereof according to an example of an embodiment of the present disclosure
  • 3B is a partial plan view showing a groove and a first signal line in the vicinity thereof according to another example of an embodiment of the present disclosure
  • FIG. 4A is a partial cross-sectional view of an array substrate according to an example of an embodiment of the present disclosure
  • 4B is a partial cross-sectional view of an array substrate according to another example of an embodiment of the present disclosure.
  • FIG. 5 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure.
  • the array substrate includes a gate line 11 on the substrate substrate 10, and a data line 12 on the side of the gate line 11 away from the substrate substrate 10, and the data line 12
  • An insulating layer (not shown in FIG. 1) is provided between the gate lines 11 to insulate the two from each other.
  • the gate line 11 and the data line 12 cross each other to define a pixel unit in which the pixel electrode 13 is disposed.
  • the array substrate further includes a thin film transistor including a gate, a source 15 and a drain 14, the gate line 11 is connected to the gate to control opening or closing of the thin film transistor, the data line 12 is connected to the source 15, and the pixel electrode 13 is The drain electrodes 14 are connected, and the data line 12 inputs a voltage signal required for displaying a picture to the pixel electrode 13 through the thin film transistor to realize display of the display panel including the array substrate.
  • the inventors of the present disclosure found that in the process of fabricating the array substrate, due to the instability of the device and the influence of the environment, the array substrate is prone to defects, thereby affecting the quality of the thin film transistor liquid crystal display.
  • a common disadvantage is the short circuit (ie, Data Gate Short, DGS) phenomenon at the intersection between the data line and the gate line. So far, the way to reduce the chances of DGS is mainly relying on environmental improvement, but it can not prevent DGS from the source.
  • Embodiments of the present disclosure provide an array substrate, a method of fabricating the same, and a display device.
  • the array substrate includes: a substrate substrate; a first signal line extending along the first direction on the substrate; a second signal line extending along the second direction, the second signal line being located at the first signal line away from the substrate
  • One side and the first signal line are insulated from each other, the first direction and the second direction intersect each other, wherein a side of the first signal line facing the second signal line is provided with a groove, and the groove is located at the first signal line and the first At the intersection between the two signal lines, at the intersection, the orthographic projection of the second signal line on the substrate substrate completely falls within the orthographic projection of the groove in the substrate.
  • the array substrate provided by the embodiment of the present disclosure reduces the thickness of the first signal line at the intersection of the first signal line and the second signal line, that is, the first signal line at the intersection of the first signal line and the second signal line Providing a groove to increase a distance between the first signal line and the second signal line at the intersection, thereby increasing an insulation layer at a junction of the first signal line and the second signal line without increasing the thickness of the array substrate.
  • the thickness of the device effectively reduces the risk of short circuit between the first signal line and the second signal line, improves the yield of the product, reduces the cost, and does not affect the performance of the array substrate.
  • FIG. 2 is a partial schematic view of an array substrate according to an embodiment of the present disclosure.
  • the array substrate includes: a substrate substrate 100; and is disposed on the substrate substrate 100.
  • a first signal line 110 extending in a first direction, that is, an X direction
  • a second signal line 120 extending in a second direction, that is, a Y direction.
  • the second signal line 120 is located at a distance of the first signal line 110 away from the substrate 100.
  • the side and the first signal line 110 are insulated from each other, and the first direction and the second direction intersect each other.
  • the present embodiment is described by taking the X direction and the Y direction perpendicular to each other as an example, but is not limited thereto.
  • a groove 111 is disposed on a side of the first signal line 110 facing the second signal line 120. As shown in FIG. 2, the groove 111 is located at an intersection between the first signal line 110 and the second signal line 120. At the intersection, the orthographic projection of the second signal line 120 on the base substrate 100 completely falls within the orthographic projection of the recess 111 in the base substrate 100.
  • the array substrate provided in this embodiment is provided with a groove at a junction of the first signal line and the second signal line by thinning the first signal line, that is, a groove is formed on the first signal line at the intersection of the first signal line and the second signal line, Increasing the distance between the first signal line and the second signal line at the intersection, thereby increasing the thickness of the insulating layer at the intersection of the first signal line and the second signal line without increasing the thickness of the array substrate, which is effective.
  • the risk of short circuit between the first signal line and the second signal line is reduced, the yield of the product is improved, the cost is reduced, and the performance of the array substrate is not affected.
  • the orthographic projection of the second signal line 120 on the substrate substrate 100 completely falls into the groove 111.
  • the orthographic projection of the substrate substrate 100 includes: at the intersection, the second signal line 120 is The orthographic projection on the base substrate 100 completely coincides with the orthographic projection of the groove 111 on the base substrate 100, or the orthographic projection of the second signal line 120 on the substrate substrate 100 is only the positive of the groove 111 on the substrate substrate 100. Part of the projection.
  • the first direction and the second direction are interchangeable, which is not limited in this embodiment.
  • the groove 111 may be disposed on the first signal line 110 at the intersection of the first signal line 110 and the second signal line 120, in the embodiment, the first signal line 110 and the second signal line 120.
  • the groove 111 is provided on the first signal line 110 at all intersections as an example, but is not limited thereto.
  • one of the first signal line 110 and the second signal line 120 is a scan line, and the other is a data line, that is, the first signal line 110 is a scan line, and the second signal line 120 is a data line; or the first signal line 110 is a data line, and the second signal line 120 is a scan line.
  • This embodiment does not limit this.
  • the first signal line 110 and the second signal line 120 in the array substrate cross each other to define a pixel unit in which the pixel electrode 160 is disposed.
  • the array substrate further includes a thin film transistor including a gate, a source 151 and a drain 152.
  • the first signal line 110 is connected to the gate to control opening or closing of the thin film transistor, and the second signal line 120 is connected to the source 151.
  • the pixel electrode 160 is connected to the drain electrode 152, and the second signal line 120 inputs a voltage signal required for displaying a picture to the pixel electrode 160 through the thin film transistor to realize display of the display panel including the array substrate.
  • the first signal line 110 is a scan line
  • the second signal line 120 is a data line as an example.
  • the material of the base substrate 100 may be made of one or more materials of glass, polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, and the embodiment includes Not limited to this.
  • the material of the first signal line 110 and the second signal line 120 may include one or more of materials such as copper, silver, aluminum, molybdenum, titanium, platinum, gold, chromium, etc., which is not limited in this embodiment.
  • the materials of the first signal line 110 and the second signal line 120 may further include one or more combinations of the group consisting of indium tin oxide, indium zinc oxide, zinc oxide, indium oxide, and indium gallium oxide.
  • FIG. 3A is a partial plan view showing a groove and a first signal line in the vicinity thereof according to an example of an embodiment of the present disclosure.
  • the first signal line 110 further includes a groove 111.
  • the maximum size of the groove 111 is larger than the size of the first connecting portion 113 and/or the second connecting portion 114.
  • the maximum size of the groove 111 is larger than the size of the first connecting portion 113 and the second connecting portion 114; in the Y direction, the first connection When the size of the portion 113 and the second connecting portion 114 are different, the maximum size of the groove 111 is larger than the size of at least one of the first connecting portion 113 and the second connecting portion 114.
  • FIG. 2 is a schematic view of the embodiment, wherein the first connecting portion and the second connecting portion are portions directly connected to the groove, and in the second direction, the size of the first connecting portion may be smaller than In addition to the size of the first connecting portion, the second connecting portion may be smaller in size than the second portion except the second connecting portion.
  • the embodiment is not limited thereto.
  • the size of the first connecting portion may be equal to the size of the first portion except the first connecting portion
  • the size of the second connecting portion may be equal to the second portion except the second connecting portion.
  • the size, that is, in the second direction, the entire first signal line except the groove has the same size and is smaller than the size of the groove.
  • the first signal line 110 located at the position of the groove 111 is d perpendicular to the thickness of the base substrate 100, the resistivity is ⁇ , and the length in the X direction is L2, along the Y direction.
  • the dimension of the first connecting portion 113 and the second connecting portion 114 directly connected to the two sides of the groove 111 in the Y direction is L0, and L1>L0.
  • the thickness d of the first signal line 110 at the position where the groove 111 is located is reduced, L1 is increased, so that the first signal line 110 and the second signal line 120 in FIG. 2 can be made by adjusting the value of d*L1.
  • the resistance of the first signal line 110 at the junction remains substantially unchanged with respect to the array substrate shown in FIG. It should be noted that the present example is described by taking a rectangular shape of a groove (ie, an orthographic projection on a base substrate) as a regular rectangle, but is not limited thereto.
  • FIG. 3B is a partial plan view showing a groove and a first signal line in the vicinity thereof according to another example of an embodiment of the present disclosure.
  • the groove in this example is The planar pattern (ie, the orthographic projection on the base substrate) is not a regular rectangle, that is, the edge of the groove 111 extending in the X direction in this example may not be a straight line, may be a curved type as shown in FIG. 3B, or may be The present invention does not limit this, as long as the maximum size of the groove 111 is larger than the size of the first connecting portion 113 and/or the second connecting portion 114 in the second direction to ensure the first signal line 110 and the second signal.
  • the resistance of the first signal line 110 at the intersection of the lines 120 may remain substantially unchanged with respect to the array substrate shown in FIG.
  • FIG. 4A is a partial cross-sectional view of an array substrate according to an example of an embodiment of the present disclosure.
  • the array substrate further includes a first insulating layer between the first signal line 110 and the second signal line 120. 130 is to insulate the first signal line 110 from the second signal line 120 from each other to prevent a short circuit (ie, Data Gate Short, DGS).
  • a short circuit ie, Data Gate Short, DGS.
  • the material of the first insulating layer 130 may include an inorganic material such as a metal oxide, a metal sulfide, or a metal nitride. This embodiment is not limited thereto.
  • the material of the first insulating layer 130 may further include polyimide. A combination of one or more of polyamide, polycarbonate, epoxy resin, and the like.
  • the array substrate provided in this example further includes a second insulating layer 140 between the first signal line 110 and the second signal line 120, and the second insulating layer 140 in the example is located at the first The insulating layer 130 is between the first signal line 110.
  • the orthographic projection of the second insulating layer 140 on the substrate substrate 100 completely coincides with the orthographic projection of the groove 111 on the substrate substrate 100, in a direction perpendicular to the substrate substrate 100, that is, the Z direction, the second insulating layer 140
  • the thickness is the same as the depth of the groove 111 to compensate for the difference in thickness of the first signal line 110 generated by the groove 111, that is, the second insulating layer 140 in this example is used to fill the groove 111 to compensate the first signal line 110 away from the lining
  • the surface of the base substrate 100 is different in height from the substrate 100 due to the grooves 111. With respect to the array substrate provided in FIG.
  • the thickness of the second insulating layer in the array substrate provided by the present example is the thickness of the insulating layer added at the intersection of the first signal line and the second signal line, and thus the array substrate is not increased.
  • the second insulating layer in the present example serves to effectively reduce the risk of short circuit between the first signal line and the second signal line, thereby improving the yield of the product and reducing the cost.
  • the second insulating layer 140 may be made of the same material as the first insulating layer 130, or a material different from the first insulating layer 130, which is not limited in this embodiment.
  • FIG. 4B is a partial cross-sectional view of an array substrate according to another example of an embodiment of the present disclosure.
  • the second insulating layer 140 in the present example is located on the first insulating layer 130 .
  • the first insulating layer 130 is directly located on the side of the first signal line 110 away from the substrate 100, since the first signal line 110 is provided with the recess 111, the first insulating layer located on the recess 111
  • the recess 130 is also formed in exactly the same shape and size as the recess 111, and the second insulating layer 140 on the side of the first insulating layer 130 away from the base substrate 100 may be used to fill the recess in the first insulating layer 130. In order to eliminate the difference in height of the surface of the first insulating layer 130 away from the substrate 100 relative to the substrate 100.
  • the thickness of the second insulating layer in the present example is the thickness of the insulating layer at the intersection of the first signal line and the second signal line, and the second insulating layer is effective without increasing the thickness of the array substrate.
  • the effect of the risk of short circuit between the first signal line and the second signal line is reduced, thereby improving the yield of the product and reducing the cost.
  • the ratio of the depth of the groove 111 to the thickness of the portion of the first signal line 110 not including the groove 111 is not more than 1:2, that is, The ratio of the thickness of the first signal line 110 at the position where the groove 111 is located to the thickness of the portion of the first signal line 110 not including the groove 111 is greater than 1:2 to prevent the first signal line 110 at the position where the groove 111 is located from occurring. fracture.
  • FIG. 5 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure. As shown in FIG. 5, the method includes the following steps.
  • S203 forming a second signal line extending along the second direction on the first signal line, the second signal line and the first signal line are insulated from each other, the first direction and the second direction intersect each other, and the groove is located at the first signal line At the intersection between the second signal lines, at the intersection, the orthographic projection of the second signal line on the substrate substrate completely falls within the orthographic projection of the groove in the substrate.
  • the orthographic projection of the second signal line on the substrate substrate completely falls into the groove in the orthographic projection of the substrate substrate including: at the intersection, the second signal line is on the substrate substrate.
  • the orthographic projection and the groove exactly coincide with the orthographic projection of the substrate, or the orthographic projection of the second signal line on the substrate is only a portion of the groove in the orthographic projection of the substrate.
  • a metal layer is formed on the base substrate, a photoresist pattern is formed on the metal layer, and the metal layer is patterned by using the photoresist pattern as a mask to form a first signal line. For example, wet etching may be employed. The metal layer forms a first signal line.
  • the first signal line and the groove may be patterned by using different masks, that is, after the metal layer is patterned by using the photoresist pattern as a mask to form the first signal line, the photoresist is stripped and then followed.
  • the step of forming a groove may be used.
  • a groove may be formed on the first signal line at at least one intersection between the first signal line and the second signal line, in this embodiment at all intersections between the first signal line and the second signal line
  • the groove is formed on the first signal line as an example, but is not limited thereto.
  • one of the first signal line and the second signal line is a scan line, and the other is a data line, that is, the first signal line is a scan line, the second signal line is a data line; or the first signal line is a data line,
  • the second signal line is a scan line, which is not limited in this embodiment.
  • the embodiment provides a method of forming an array substrate, wherein forming the recess includes forming a first insulating layer on the first signal line, that is, forming a first insulating layer on a side of the first signal line away from the substrate. Locating and etching a first insulating layer at the junction to form a via to expose the first signal line.
  • the first insulating layer at the intersection may be dry etched to expose the first portion at the intersection. a signal line; etching the exposed first signal line to form a recess, for example, the first signal line may be wet-etched with the etched first insulating layer as a mask to make the intersection
  • the first signal line forms a groove.
  • the first etching of the first insulating layer can be prevented by wet etching the first signal line.
  • the method further includes: filling the recess and the via hole with an insulating material.
  • the recess is filled with an insulating material to form a second insulating layer, and the surface of the second insulating layer is flush with the surface of the first signal line, that is, the thickness and recess of the second insulating layer in a direction perpendicular to the substrate.
  • the depths of the grooves are the same to compensate for the difference in height of the surface of the first signal line away from the substrate substrate due to the groove relative to the substrate.
  • the via of the first insulating layer filling the via of the first insulating layer with an insulating material to make the thickness of the first insulating layer uniform, that is, making the surface of the insulating material filled in the via be flush with the surface of the first insulating layer, and the via hole in this example
  • the insulating material can be regarded as a part of the first insulating layer, and the portion and the first insulating layer etched in the previous step constitute a complete first insulating layer.
  • the second insulating layer in this example is formed between the first signal line and the first insulating layer, as shown in FIG. 4A.
  • the filling of the insulating material into the recess and the via may include: forming a layer of insulating material on the first insulating layer, filling the recess and the via hole with the insulating material layer, and then patterning and etching the insulating material layer and then etching
  • the insulating material layer other than the filling portion is peeled off so that the surface of the insulating material filled in the via hole is flush with the surface of the first insulating layer, and the embodiment includes but is not limited thereto.
  • the method for fabricating the array substrate forms a concave portion by thinning the thickness of the first signal line at the intersection thereof with the second signal line, that is, at the intersection of the first signal line and the second signal line. a groove to increase a distance between the first signal line and the second signal line at the intersection, thereby increasing the thickness of the insulating layer at the intersection of the first signal line and the second signal line without increasing the thickness of the array substrate.
  • the utility model can effectively reduce the risk of short circuit between the first signal line and the second signal line, improve the yield of the product, reduce the cost, and does not affect the performance of the array substrate.
  • the thickness of the second insulating layer formed in the method for fabricating the array substrate provided by the above example is the thickness of the insulating layer increased at the intersection of the first signal line and the second signal line, and therefore, without increasing the thickness of the array substrate,
  • the second insulating layer in this example serves to effectively reduce the risk of short circuit between the first signal line and the second signal line.
  • the material of the first insulating layer may include an inorganic material such as a metal oxide, a metal sulfide, or a metal nitride. This embodiment is not limited thereto.
  • the material of the first insulating layer may further include polyimide and polyamide. A combination of one or more of polycarbonate, epoxy resin, and the like.
  • the second insulating layer in this example may be selected from the same material as the first insulating layer; or the second insulating layer may also be made of a material different from the first insulating layer, in which case the first insulating layer is composed of two materials. Composition.
  • the forming a recess includes: forming a photoresist pattern on the first signal line, for example, applying a photoresist on the first signal line, and performing photolithography
  • the glue is subjected to a patterning process such as exposure, development, or the like to form a photoresist pattern, which is the same as the pattern of the first insulating layer after the positioning and etching in the previous example; using the photoresist pattern as a mask, engraving
  • the first signal line is etched to form a recess, for example, the photoresist pattern exposes a first signal line at the intersection, and the exposed first signal line is wet etched to form a desired recess.
  • the method further comprises: filling the recess with an insulating material to form a second insulating layer, the surface of the second insulating layer being flush with the surface of the first signal line, that is, perpendicular to the substrate In the direction of the substrate, the thickness of the second insulating layer is the same as the depth of the groove to compensate for the height difference of the surface of the first signal line away from the substrate substrate due to the groove relative to the substrate; forming on the first signal line
  • the first insulating layer, the second insulating layer in this example is formed between the first signal line and the first insulating layer, as shown in FIG. 4A.
  • the second insulating layer in this example may be selected from the same material as the first insulating layer, or a material different from the first insulating layer.
  • the method further includes: forming a first insulating layer on the first signal line, where the first insulating layer is located at a position of the groove to form a recess, that is, directly at the first signal Forming a first insulating layer on the line, and forming a recess in the first insulating layer at the position of the recess; filling the recess with an insulating material to form a second insulating layer, the surface of the second insulating layer and the first insulating layer The surface is flush, that is, the second insulating layer is located on a side of the first insulating layer away from the substrate to compensate for the difference in height of the surface of the first insulating layer away from the substrate due to the groove, in this example
  • the second insulating layer is formed between the first insulating layer and the second signal line, as shown in FIG. 4B.
  • the second insulating layer formed by using any of the above method steps can effectively reduce the risk of short circuit between the first signal line and the second signal line without increasing the thickness of the array substrate, thereby improving the effect.
  • the yield of the product reduces the cost.
  • the first signal line and the groove may also be patterned using the same mask and formed using a halftone mask process.
  • a metal layer is formed on a base substrate, a photoresist layer is formed on the metal layer, and then the photoresist layer is patterned using a halftone mask process to form a photoresist layer having different thicknesses.
  • the thickness H1 of the photoresist layer directly above the position where the first signal line (excluding the groove) is to be formed is larger than the thickness H2 of the photoresist layer directly above the position where the groove is to be formed, and the thickness H2 is larger than The thickness H3 of the photoresist layer directly above the position where the first signal line is not formed.
  • the photoresist layer having different thicknesses is processed by an ashing process and patterned to form a first signal line having grooves to reduce the one-step mask process, and the embodiment includes but is not limited thereto.
  • the steps of forming the first insulating layer and the second signal line after this are the same as those provided in the above examples, and are not described herein again.
  • the first signal line when the first signal line is formed, the first signal line is patterned and patterned so that the maximum size of the first signal line of the position of the subsequent recess to be etched is
  • the dimension of the second direction is slightly larger than the size of a portion of the first signal line connected to both sides of the groove, that is, the first signal line further includes a first portion and a second portion on both sides of the groove, and the first portion includes a connection with the groove a first connecting portion, the second portion includes a second connecting portion connected to the groove, wherein a maximum dimension of the first signal line at a position of the subsequent groove to be formed is greater than the first connecting portion and/or the second in the second direction The size of the connection.
  • the thickness of the first signal line at the position where the groove is located decreases in a direction perpendicular to the substrate substrate, the size in the second direction is increased, and thus the first signal line of the position where the groove is located is adjusted.
  • the value of the thickness and the dimension in the second direction may cause the resistance of the first signal line at the intersection of the first signal line and the second signal line in the present embodiment to remain substantially unchanged with respect to the array substrate shown in FIG.
  • the shape of the orthographic projection of the groove on the substrate may be a regular shape such as a rectangle or an irregular shape, which is not limited in this embodiment.
  • the ratio of the depth of the groove to the thickness of the portion of the first signal line not including the groove does not exceed 1:2, that is, the thickness of the first signal line at the position where the groove is located
  • the ratio of the thickness of the portion not including the groove of the first signal line is greater than 1:2 to prevent the first signal line at the position where the groove is located from being broken.
  • Another embodiment of the present disclosure provides a display device, including any of the array substrates provided by the above embodiments, wherein the display device using the array substrate reduces the thickness of the first signal line at the intersection with the second signal line. That is, a groove is disposed on the first signal line at the intersection of the first signal line and the second signal line to increase the distance between the first signal line and the second signal line at the intersection, thereby not increasing the thickness of the array substrate.
  • the risk of short circuit between the first signal line and the second signal line is effectively reduced, the yield of the product is improved, and the yield is lowered. The cost does not affect the performance of the array substrate.
  • the display device may be a display device such as a liquid crystal display device, an organic light-emitting diode (OLED) display device, and a television, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, and a navigation device including the display device.
  • a display device such as a liquid crystal display device, an organic light-emitting diode (OLED) display device, and a television, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, and a navigation device including the display device.
  • OLED organic light-emitting diode
  • the present embodiment is not limited thereto, such as a product or a component having a display function.

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Abstract

一种阵列基板及其制作方法、显示装置。该阵列基板包括：衬底基板(100)；沿第一方向延伸的第一信号线(110)，位于衬底基板(100)上；沿第二方向延伸的第二信号线(120)，位于第一信号线(110)远离衬底基板(100)的一侧且与第一信号线(110)彼此绝缘，第一方向与第二方向彼此交叉，其中，第一信号线(110)面向第二信号线(120)的一侧设置有凹槽(111)，凹槽(111)位于第一信号线(110)与第二信号线(120)之间的交汇处，在交汇处，第二信号线(120)在衬底基板(100)上的正投影完全落入凹槽(111)在衬底基板(100)的正投影内。该阵列基板通过减薄第一信号线(110)在其与第二信号线(120)交汇处的厚度以增加第一信号线(110)与第二信号线(120)交汇处的绝缘层的厚度，从而有效降低了第一信号线(110)与第二信号线(120)之间发生短路的风险。

Description

阵列基板及其制作方法、显示装置
相关申请的交叉引用
本申请要求于2017年7月21日递交的中国专利申请第201710601282.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一个实施例涉及一种阵列基板及其制作方法、显示装置。
背景技术
目前，平板显示器市场中的占据主导市场地位的薄膜晶体管液晶显示器是一种需要依靠背光来显示的显示器。显示器的主要结构包括阵列基板、液晶以及彩膜基板，其中的阵列基板可以对薄膜晶体管液晶显示器的分辨率、视角等起到决定作用。
发明内容
本公开的至少一实施例提供一种阵列基板，包括：衬底基板；沿第一方向延伸的第一信号线，位于衬底基板上；沿第二方向延伸的第二信号线，位于第一信号线远离衬底基板的一侧且与第一信号线彼此绝缘，第一方向与第二方向彼此交叉，其中，第一信号线面向第二信号线的一侧设置有凹槽，凹槽位于第一信号线与第二信号线之间的交汇处，在交汇处，第二信号线在衬底基板上的正投影完全落入凹槽在衬底基板的正投影内。
例如，在本公开一实施例提供的阵列基板中，第一信号线还包括位于凹槽两侧的第一部分与第二部分，第一部分包括与凹槽连接的第一连接部，第二部分包括与凹槽连接的第二连接部，沿第二方向，凹槽的最大尺寸大于第一连接部和第二连接部的至少之一的尺寸。
例如，在本公开一实施例提供的阵列基板中，还包括：第一绝缘层，位于第一信号线与第二信号线之间。
例如，在本公开一实施例提供的阵列基板中，还包括：第二绝缘层，位于第一信号线与第二信号线之间，其中，第二绝缘层在衬底基板上的正投影与凹 槽在衬底基板上的正投影完全重合，沿垂直于衬底基板的方向，第二绝缘层的厚度与凹槽的深度相同以补偿第一信号线或第一绝缘层远离衬底基板的表面由于凹槽产生的相对于衬底基板的高度差。
例如，在本公开一实施例提供的阵列基板中，第二绝缘层位于第一绝缘层与第一信号线之间或者第一绝缘层与第二信号线之间。
例如，在本公开一实施例提供的阵列基板中，沿垂直于衬底基板的方向，凹槽的深度与第一信号线不包括凹槽的部分的厚度之比不超过1:2。
例如，在本公开一实施例提供的阵列基板中，第一信号线和第二信号线之一为扫描线，另一条为数据线。
本公开的至少一实施例提供一种阵列基板的制作方法，包括：在衬底基板上形成沿第一方向延伸的第一信号线；在第一信号线远离衬底基板的一侧形成凹槽；在第一信号线上形成沿第二方向延伸的第二信号线，第二信号线与第一信号线彼此绝缘，第一方向与第二方向彼此交叉，其中，凹槽位于第一信号线与第二信号线之间的交汇处，在交汇处，第二信号线在衬底基板上的正投影完全落入凹槽在衬底基板的正投影内。
例如，在本公开一实施例提供的阵列基板的制作方法中，形成凹槽包括：在第一信号线上形成第一绝缘层；对位于交汇处的第一绝缘层进行刻蚀形成过孔以暴露出第一信号线；对暴露出的第一信号线进行刻蚀以形成凹槽。
例如，在本公开一实施例提供的阵列基板的制作方法中，形成第二信号线之前还包括：对凹槽以及过孔填充绝缘材料，其中，对凹槽填充绝缘材料以形成第二绝缘层，第二绝缘层的表面与第一信号线的表面平齐，对过孔填充绝缘材料以使第一绝缘层的厚度均匀。
例如，在本公开一实施例提供的阵列基板的制作方法中，形成凹槽包括：在第一信号线上形成光刻胶图案；以光刻胶图案为掩模，刻蚀第一信号线以形成凹槽。
例如，在本公开一实施例提供的阵列基板的制作方法中，第一信号线与凹槽采用同一个掩模板图案化，并采用半色调掩模工艺形成。
例如，在本公开一实施例提供的阵列基板的制作方法中，形成第二信号线之前还包括：对凹槽填充绝缘材料以形成第二绝缘层，第二绝缘层的表面与第一信号线的表面平齐；在第一信号线以及第二绝缘层上形成第一绝缘层。
例如，在本公开一实施例提供的阵列基板的制作方法中，形成第二信号线 之前还包括：在第一信号线上形成第一绝缘层，第一绝缘层位于凹槽的位置形成凹陷部；对凹陷部填充绝缘材料以形成第二绝缘层，第二绝缘层的表面与第一绝缘层的表面平齐。
例如，在本公开一实施例提供的阵列基板的制作方法中，第一信号线还包括位于凹槽两侧的第一部分与第二部分，第一部分包括与凹槽连接的第一连接部，第二部分包括与凹槽连接的第二连接部，其中，形成第一信号线包括：对第一信号线图案化以使沿第二方向，待形成凹槽所在位置的第一信号线的最大尺寸大于第一连接部和第二连接部的至少之一的尺寸。
例如，在本公开一实施例提供的阵列基板的制作方法中，沿垂直于衬底基板的方向上，凹槽的深度与第一信号线不包括凹槽的部分的厚度之比不超过1:2。
本公开的至少一实施例提供一种显示装置，包括上述实施例提供的任一阵列基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种阵列基板的局部示意图；
图2为本公开一实施例提供的阵列基板的局部示意图；
图3A为本公开一实施例的一示例提供的凹槽及其附近第一信号线的局部平面示意图；
图3B为本公开一实施例的另一示例提供的凹槽及其附近第一信号线的局部平面示意图；
图4A为本公开一实施例的一示例提供的阵列基板的局部剖视图；
图4B为本公开一实施例的另一示例提供的阵列基板的局部剖视图；
图5为本公开一实施例提供的一种阵列基板的制作方法的示意性流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所 描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种阵列基板的局部示意图，如图1所示，阵列基板包括位于衬底基板10上的栅线11，位于栅线11远离衬底基板10一侧的数据线12，数据线12与栅线11之间设置有绝缘层(图1中未示出)以使两者彼此绝缘。
栅线11与数据线12彼此交叉以限定像素单元，像素单元中设置有像素电极13。阵列基板还包括薄膜晶体管，薄膜晶体管包括栅极、源极15以及漏极14，栅线11与栅极相连以控制薄膜晶体管的打开或者关闭，数据线12与源极15相连，像素电极13与漏极14相连，数据线12通过薄膜晶体管对像素电极13输入显示画面所需的电压信号以实现包括该阵列基板的显示面板的显示。
在研究中，本公开的发明人发现：在制作阵列基板的过程中，由于设备的不稳定以及环境的影响，阵列基板很容易出现瑕疵，从而影响着薄膜晶体管液晶显示器的品质。一种常见的不良是数据线与栅线之间的交汇处发生短路(即Data Gate Short，DGS)现象。到目前为止，降低发生DGS的几率的方法主要是依靠环境的改善，但是却不能从源头阻止DGS的产生。
本公开的实施例提供一种阵列基板及其制作方法、显示装置。该阵列基板包括：衬底基板；位于衬底基板上的沿第一方向延伸的第一信号线；沿第二方向延伸的第二信号线，第二信号线位于第一信号线远离衬底基板的一侧且与第一信号线彼此绝缘，第一方向与第二方向彼此交叉，其中，第一信号线面向第二信号线的一侧设置有凹槽，凹槽位于第一信号线与第二信号线之间的交汇处，在交汇处，第二信号线在衬底基板上的正投影完全落入凹槽在衬底基板的正投影内。本公开的实施例提供的阵列基板通过减薄第一信号线与第二信号线交汇处的第一信号线的厚度，即在第一信号线与第二信号线交汇处的第一信号 线上设置凹槽，以增加位于交汇处的第一信号线与第二信号线之间的距离，从而在不增加阵列基板厚度的基础上，增加第一信号线与第二信号线交汇处的绝缘层的厚度，既有效降低了第一信号线与第二信号线之间发生短路的风险，提高了产品的良率，降低了成本，又不影响阵列基板的性能。
下面结合附图对本公开实施例提供的阵列基板及其制作方法、显示装置进行描述。
本公开一实施例提供一种阵列基板，图2为本公开一实施例提供的阵列基板的局部示意图，如图2所示，该阵列基板包括：衬底基板100；位于衬底基板100上的沿第一方向，即X方向延伸的第一信号线110以及沿第二方向，即Y方向延伸的第二信号线120，第二信号线120位于第一信号线110远离衬底基板100的一侧且与第一信号线110彼此绝缘，这里的第一方向与第二方向彼此交叉，本实施例以X方向与Y方向彼此垂直为例进行描述，但不限于此。本实施例中第一信号线110面向第二信号线120的一侧设置有凹槽111，如图2所示，凹槽111位于第一信号线110与第二信号线120之间的交汇处，在交汇处，第二信号线120在衬底基板100上的正投影完全落入凹槽111在衬底基板100的正投影内。本实施例提供的阵列基板通过减薄第一信号线在其与第二信号线交汇处的厚度，即在第一信号线与第二信号线交汇处的第一信号线上设置凹槽，以增加位于交汇处的第一信号线与第二信号线之间的距离，从而在不增加阵列基板厚度的基础上，增加第一信号线与第二信号线交汇处的绝缘层的厚度，既有效降低了第一信号线与第二信号线之间发生短路的风险，提高了产品的良率，降低了成本，又不影响阵列基板的性能。
需要说明的是，在交汇处，第二信号线120在衬底基板100上的正投影完全落入凹槽111在衬底基板100的正投影内包括：在交汇处，第二信号线120在衬底基板100上的正投影与凹槽111在衬底基板100的正投影完全重合，或者第二信号线120在衬底基板100上的正投影仅为凹槽111在衬底基板100的正投影中的一部分。另外，第一方向与第二方向可以互换，本实施例对此不作限制。
例如，可以在第一信号线110与第二信号线120之间的至少一个交汇处的第一信号线110上设置凹槽111，本实施例以在第一信号线110与第二信号线120之间的全部交汇处的第一信号线110上设置凹槽111为例进行描述，但不限于此。
例如，第一信号线110和第二信号线120之一为扫描线，另一条为数据线，即，第一信号线110为扫描线，第二信号线120为数据线；或者第一信号线110为数据线，第二信号线120为扫描线，本实施例对此不作限制。
例如，如图2所示，阵列基板中的第一信号线110与第二信号线120彼此交叉以限定像素单元，像素单元中设置有像素电极160。阵列基板还包括薄膜晶体管，薄膜晶体管包括栅极、源极151以及漏极152，第一信号线110与栅极相连以控制薄膜晶体管的打开或者关闭，第二信号线120与源极151相连，像素电极160与漏极152相连，第二信号线120通过薄膜晶体管对像素电极160输入显示画面所需的电压信号以实现包括该阵列基板的显示面板的显示。这里以第一信号线110为扫描线，第二信号线120为数据线为例进行描述。
例如，衬底基板100的材料可以由玻璃、聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜中的一种或多种材料制成，本实施例包括但不限于此。
例如，第一信号线110和第二信号线120的材料可以包括铜、银、铝、钼、钛、铂、金、铬等材料中的一种或几种，本实施例对此不作限制，例如，第一信号线110和第二信号线120的材料还可以包括由氧化铟锡、氧化铟锌、氧化锌、氧化铟和氧化铟镓构成的组中的一种或多种组合。
例如，图3A为本公开一实施例的一示例提供的凹槽及其附近第一信号线的局部平面示意图，如图2和图3A所示，第一信号线110还包括位于凹槽111的两侧的第一部分112与第二部分115，第一部分112包括与凹槽111连接的第一连接部113，第二部分115包括与凹槽111连接的第二连接部114。沿第二方向，即Y方向，凹槽111的最大尺寸大于第一连接部113和/或第二连接部114的尺寸。例如，沿Y方向，第一连接部113和第二连接部114的尺寸相同时，凹槽111的最大尺寸大于第一连接部113和第二连接部114的尺寸；沿Y方向，第一连接部113和第二连接部114的尺寸不相同时，凹槽111的最大尺寸大于第一连接部113和第二连接部114的至少之一的尺寸。
需要说明的是，图2为本实施例的示意性视图，其中的第一连接部和第二连接部为与凹槽直接连接的部分，并且沿第二方向，第一连接部的尺寸可以小于第一部分除第一连接部的尺寸，第二连接部的尺寸可以小于第二部分除第二连接部的尺寸。本实施例不限于此，例如，沿第二方向，第一连接部的尺寸也可以等于第一部分除第一连接部的尺寸，第二连接部的尺寸可以等于第二部分除第二连接部的尺寸，即沿第二方向，整条第一信号线除凹槽以外的其他部分 的尺寸相同，且均小于凹槽的尺寸。
例如，如图3A所示，假设位于凹槽111所在位置的第一信号线110沿垂直于衬底基板100的厚度为d，电阻率为ρ，沿X方向的长度为L2，沿Y方向的长度为L1，则凹槽111所在位置的第一信号线110的电阻为R＝(ρ*L2)/(d*L1)。凹槽111两侧与其直接相连的第一连接部113与第二连接部114沿Y方向的尺寸为L0，并且L1>L0。虽然位于凹槽111所在位置的第一信号线110的厚度d减小了，但是L1增大了，因此通过调节d*L1的数值可以使图2中第一信号线110与第二信号线120交汇处的第一信号线110的电阻相对于图1示出的阵列基板基本保持不变。需要说明是的，本示例以凹槽的平面图形(即在衬底基板上的正投影)为规则的矩形为例进行描述，但不限于此。
例如，图3B为本公开一实施例的另一示例提供的凹槽及其附近第一信号线的局部平面示意图，如图3B所示，与图3A不同的是，本示例中的凹槽的平面图形(即在衬底基板上的正投影)不是规则的矩形，即本示例中凹槽111沿X方向延伸的边可以不是直线型，可以是如图3B所示的曲线型，也可以是折线型等，本示例对此不作限制，只要沿第二方向，凹槽111的最大尺寸大于第一连接部113和/或第二连接部114的尺寸以保证第一信号线110与第二信号线120交汇处的第一信号线110的电阻相对于图1示出的阵列基板基本保持不变即可。
例如，图4A为本公开一实施例的一示例提供的阵列基板的局部剖视图，如图4A所示，阵列基板还包括位于第一信号线110与第二信号线120之间的第一绝缘层130以使第一信号线110与第二信号线120彼此绝缘，防止发生短路(即Data Gate Short，DGS)。
例如，第一绝缘层130的材料可以包括金属氧化物、金属硫化物或金属氮化物等无机材料，本实施对此不作限制，例如，第一绝缘层130的材料还可以包括聚酰亚胺、聚酰胺、聚碳酸酯、环氧树脂等中的一种或几种的组合等。
例如，如图4A所示，本示例提供的阵列基板还包括位于第一信号线110与第二信号线120之间的第二绝缘层140，且本示例中的第二绝缘层140位于第一绝缘层130与第一信号线110之间。第二绝缘层140在衬底基板100上的正投影与凹槽111在衬底基板100上的正投影完全重合，沿垂直于衬底基板100的方向，即Z方向，第二绝缘层140的厚度与凹槽111的深度相同以补偿第一信号线110中由凹槽111产生的厚度差，即本示例中的第二绝缘层140用于填 充凹槽111以补偿第一信号线110远离衬底基板100的表面由于凹槽111产生的相对于衬底基板100的高度差。相对于图1提供的阵列基板，本示例提供的阵列基板中的第二绝缘层的厚度即为第一信号线与第二信号线的交汇处增加的绝缘层的厚度，因此在不增加阵列基板厚度的基础上，本示例中的第二绝缘层起到了有效降低第一信号线与第二信号线之间发生短路风险的作用，因而提高了产品的良率，降低了成本。
例如，第二绝缘层140可以选用与第一绝缘层130相同的材料，也可以选用与第一绝缘层130不同的材料，本实施例对此不作限制。
例如，图4B为本公开一实施例的另一示例提供的阵列基板的局部剖视图，如图4B所示，与图4A不同的是，本示例中的第二绝缘层140位于第一绝缘层130与第二信号线120之间以补偿第一绝缘层130远离衬底基板100的表面由于凹槽111产生的相对于衬底基板100的高度差。即，当第一绝缘层130直接位于第一信号线110远离衬底基板100的一侧时，由于第一信号线110上设置有凹槽111，因此，位于凹槽111上的第一绝缘层130也会产生与凹槽111形状及尺寸完全相同的凹陷部，而位于第一绝缘层130远离衬底基板100一侧的第二绝缘层140可以用于填充第一绝缘层130中的凹陷部，以消除第一绝缘层130远离衬底基板100的表面相对于衬底基板100的高度差。因此，本示例中的第二绝缘层的厚度即为第一信号线与第二信号线的交汇处增加的绝缘层的厚度，在不增加阵列基板厚度的基础上，第二绝缘层起到了有效降低第一信号线与第二信号线之间发生短路风险的作用，因而提高了产品的良率，降低了成本。
例如，如图4A和4B所示，沿垂直于衬底基板100的方向，凹槽111的深度与第一信号线110不包括凹槽111的部分的厚度之比不超过1:2，即，位于凹槽111所在位置的第一信号线110的厚度与第一信号线110不包括凹槽111的部分的厚度之比大于1:2以防止位于凹槽111所在位置的第一信号线110发生断裂。
本公开另一实施例提供一种阵列基板的制作方法，图5为本公开一实施例提供的一种阵列基板的制作方法的示意性流程图，如图5所示，制作方法包括如下步骤。
S201：在衬底基板上形成沿第一方向延伸的第一信号线。
S202：在第一信号线远离衬底基板的一侧形成凹槽。
S203：在第一信号线上形成沿第二方向延伸的第二信号线，第二信号线与第一信号线彼此绝缘，第一方向与第二方向彼此交叉，凹槽位于第一信号线与第二信号线之间的交汇处，在交汇处，第二信号线在衬底基板上的正投影完全落入凹槽在衬底基板的正投影内。
需要说明的是，在交汇处，第二信号线在衬底基板上的正投影完全落入凹槽在衬底基板的正投影内包括：在交汇处，第二信号线在衬底基板上的正投影与凹槽在衬底基板的正投影完全重合，或者第二信号线在衬底基板上的正投影仅为凹槽在衬底基板的正投影中的一部分。
例如，在衬底基板上形成金属层，在金属层上形成光刻胶图案，以光刻胶图案为掩模对金属层进行图案化以形成第一信号线，例如，可以采用湿法刻蚀金属层以形成第一信号线。
例如，第一信号线与凹槽可以采用不同的掩模板图案化，即，以光刻胶图案为掩模对金属层进行图案化形成第一信号线后，剥离光刻胶，然后再进行后续形成凹槽的步骤。
例如，可以在第一信号线与第二信号线之间的至少一个交汇处的第一信号线上形成凹槽，本实施例以在第一信号线与第二信号线之间的全部交汇处的第一信号线上形成凹槽为例进行描述，但不限于此。
例如，第一信号线和第二信号线之一为扫描线，另一条为数据线，即，第一信号线为扫描线，第二信号线为数据线；或者第一信号线为数据线，第二信号线为扫描线，本实施例对此不作限制。
例如，本实施例提供阵列基板的制作方法的一示例中形成凹槽包括：在第一信号线上形成第一绝缘层，即在第一信号线远离衬底基板的一侧形成第一绝缘层；对位于交汇处的第一绝缘层进行定位刻蚀形成过孔以暴露出第一信号线，例如，可以对位于交汇处的第一绝缘层采用干法刻蚀以暴露出位于交汇处的第一信号线；对暴露出的第一信号线进行刻蚀以形成凹槽，例如，可以以被刻蚀后的第一绝缘层为掩模对第一信号线进行湿刻以使位于交汇处的第一信号线形成凹槽。这里对第一绝缘层采用干法刻蚀后，对第一信号线采用湿法刻蚀可以防止对第一绝缘层的二次刻蚀。
例如，本示例中形成第二信号线之前还包括：对凹槽以及过孔填充绝缘材料。这里对凹槽填充绝缘材料以形成第二绝缘层，第二绝缘层的表面与第一信号线的表面平齐，即，沿垂直于衬底基板的方向上，第二绝缘层的厚度与凹槽 的深度相同以补偿第一信号线远离衬底基板的表面由于凹槽产生的相对于衬底基板的高度差。并且对第一绝缘层的过孔填充绝缘材料以使第一绝缘层的厚度均匀，即，使过孔中填充的绝缘材料的表面与第一绝缘层的表面平齐，且本示例中过孔填充绝缘材料后，该绝缘材料可以看作第一绝缘层的一部分，该部分与上一步骤刻蚀后的第一绝缘层构成完整的第一绝缘层。本示例中的第二绝缘层形成于第一信号线与第一绝缘层之间，即如图4A所示。
例如，对凹槽以及过孔进行定点填充绝缘材料可以包括：在第一绝缘层上形成绝缘材料层，绝缘材料层填充了凹槽以及过孔，然后对绝缘材料层进行图案化后刻蚀并剥离掉填充部分以外的绝缘材料层以使过孔中填充的绝缘材料的表面与第一绝缘层的表面平齐，本实施例包括但不限于此。
本实施例提供的阵列基板的制作方法通过减薄第一信号线在其与第二信号线交汇处的厚度，即在第一信号线与第二信号线交汇处的第一信号线上形成凹槽，以增加位于交汇处的第一信号线与第二信号线之间的距离，从而在不增加阵列基板厚度的基础上，增加第一信号线与第二信号线交汇处的绝缘层的厚度，既有效降低了第一信号线与第二信号线之间发生短路的风险，提高了产品的良率，降低了成本，又不影响阵列基板的性能。
上述示例提供的阵列基板的制作方法中形成的第二绝缘层的厚度即为第一信号线与第二信号线的交汇处增加的绝缘层的厚度，因此在不增加阵列基板厚度的基础上，本示例中的第二绝缘层起到了有效降低第一信号线与第二信号线之间发生短路风险的作用。
例如，第一绝缘层的材料可以包括金属氧化物、金属硫化物或金属氮化物等无机材料，本实施对此不作限制，例如，第一绝缘层的材料还可以包括聚酰亚胺、聚酰胺、聚碳酸酯、环氧树脂等中的一种或几种的组合等。
例如，本示例中的第二绝缘层可以选用与第一绝缘层相同的材料；或者第二绝缘层还可以选用与第一绝缘层不相同的材料，此时的第一绝缘层由两种材料构成。
例如，本实施例提供阵列基板的制作方法的另一示例中形成凹槽包括：在第一信号线上形成光刻胶图案，例如，在第一信号线上涂敷光刻胶，对光刻胶进行曝光、显影等图案化工艺以形成光刻胶图案，该光刻胶图案与上一示例中的定位刻蚀后的第一绝缘层的图案相同；以光刻胶图案为掩模，刻蚀第一信号线以形成凹槽，例如，光刻胶图案暴露出位于交汇处的第一信号线，对暴露的 第一信号线进行湿法刻蚀以形成所需的凹槽。
例如，本示例中形成第二信号线之前还包括：对凹槽填充绝缘材料以形成第二绝缘层，第二绝缘层的表面与第一信号线的表面平齐，即，沿垂直于衬底基板的方向上，第二绝缘层的厚度与凹槽的深度相同以补偿第一信号线远离衬底基板的表面由于凹槽产生的相对于衬底基板的高度差；在第一信号线上形成第一绝缘层，本示例中的第二绝缘层形成于第一信号线与第一绝缘层之间，即如图4A所示。
例如，本示例中的第二绝缘层可以选用与第一绝缘层相同的材料，也可以选用与第一绝缘层不同的材料。
例如，本示例的另一示例中形成第二信号线之前还包括：在第一信号线上形成第一绝缘层，第一绝缘层位于凹槽的位置形成凹陷部，即，直接在第一信号线上形成第一绝缘层，在位于凹槽的位置上的第一绝缘层会出现凹陷部；对凹陷部填充绝缘材料以形成第二绝缘层，第二绝缘层的表面与第一绝缘层的表面平齐，即第二绝缘层位于第一绝缘层远离衬底基板的一侧以补偿第一绝缘层远离衬底基板的表面由于凹槽产生的相对于衬底基板的高度差，本示例中的第二绝缘层形成于第一绝缘层与第二信号线之间，即如图4B所示。
无论采用上述哪种方法步骤形成的第二绝缘层，都可以在不增加阵列基板厚度的基础上，起到有效降低第一信号线与第二信号线之间发生短路风险的作用，因而提高了产品的良率，降低了成本。
例如，第一信号线与凹槽还可以采用同一个掩模板图案化，并采用半色调掩模工艺形成。例如，在衬底基板上形成金属层，在金属层上形成光刻胶层，然后利用半色调掩模工艺对光刻胶层图案化以形成具有不同厚度的光刻胶层。
例如，位于待形成第一信号线(不包括凹槽)的位置的正上方的光刻胶层的厚度H1大于待形成凹槽的位置的正上方的光刻胶层的厚度H2，厚度H2大于不形成第一信号线的位置的正上方的光刻胶层的厚度H3。利用灰化工艺处理具有不同厚度的光刻胶层并图案化形成具有凹槽的第一信号线以减少一步掩模板工艺，本实施例包括但不限于此。在此之后形成第一绝缘层以及第二信号线的步骤与上述示例提供的步骤相同，在此不再赘述。
例如，本实施例提供的阵列基板的制作方法中在形成第一信号线时，对第一信号线进行定位图案化，以使后续待刻蚀凹槽的位置的第一信号线的最大尺寸沿第二方向的尺寸略大于凹槽两侧与其相连的部分第一信号线的尺寸，即第 一信号线还包括位于凹槽的两侧的第一部分与第二部分，第一部分包括与凹槽连接的第一连接部，第二部分包括与凹槽连接的第二连接部，沿第二方向，后续待形成凹槽的位置的第一信号线的最大尺寸大于第一连接部和/或第二连接部的尺寸。因此，虽然位于凹槽所在位置的第一信号线沿垂直于衬底基板方向的厚度减小了，但是沿第二方向的尺寸增大了，因此通过调节凹槽所在位置的第一信号线的厚度与沿第二方向的尺寸的数值可以使本实施中的第一信号线与第二信号线交汇处的第一信号线的电阻相对于图1示出的阵列基板基本保持不变。
例如，凹槽在衬底基板上的正投影的形状可以是矩形等规则形状，也可是非规则的形状，本实施例对此不作限制。
例如，沿垂直于衬底基板的方向，凹槽的深度与第一信号线不包括凹槽的部分的厚度之比不超过1:2，即，位于凹槽所在位置的第一信号线的厚度与第一信号线不包括凹槽的部分的厚度之比大于1:2以防止位于凹槽所在位置的第一信号线发生断裂。
本公开另一实施例提供一种显示装置，包括上述实施例提供的任一种阵列基板，采用该阵列基板的显示装置通过减薄第一信号线在其与第二信号线交汇处的厚度，即在第一信号线与第二信号线交汇处的第一信号线上设置凹槽，以增加位于交汇处的第一信号线与第二信号线之间的距离，从而在不增加阵列基板厚度的基础上，增加第一信号线与第二信号线交汇处的绝缘层的厚度，既有效降低了第一信号线与第二信号线之间发生短路的风险，提高了产品的良率，降低了成本，又不影响阵列基板的性能。
例如，该显示装置可以为液晶显示装置、有机发光二极管(Organic Light-Emitting Diode，OLED)显示装置等显示器件以及包括该显示装置的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件，本实施例不限于此。
有以下几点需要说明：
(1)除非另作定义，本公开实施例以及附图中，同一标号代表同一含义。
(2)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件 “上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种阵列基板，包括：
    衬底基板；
    沿第一方向延伸的第一信号线，位于所述衬底基板上；
    沿第二方向延伸的第二信号线，位于所述第一信号线远离所述衬底基板的一侧且与所述第一信号线彼此绝缘，所述第一方向与所述第二方向彼此交叉，
    其中，所述第一信号线面向所述第二信号线的一侧设置有凹槽，所述凹槽位于所述第一信号线与所述第二信号线之间的交汇处，在所述交汇处，所述第二信号线在所述衬底基板上的正投影完全落入所述凹槽在所述衬底基板的正投影内。
  2. 根据权利要求1所述的阵列基板，其中，所述第一信号线还包括位于所述凹槽两侧的第一部分与第二部分，所述第一部分包括与所述凹槽连接的第一连接部，所述第二部分包括与所述凹槽连接的第二连接部，沿所述第二方向，所述凹槽的最大尺寸大于所述第一连接部和所述第二连接部的至少之一的尺寸。
  3. 根据权利要求1或2所述的阵列基板，还包括：
    第一绝缘层，位于所述第一信号线与所述第二信号线之间。
  4. 根据权利要求3所述的阵列基板，还包括：
    第二绝缘层，位于所述第一信号线与所述第二信号线之间，
    其中，所述第二绝缘层在所述衬底基板上的正投影与所述凹槽在所述衬底基板上的正投影完全重合，沿垂直于所述衬底基板的方向，所述第二绝缘层的厚度与所述凹槽的深度相同以补偿所述第一信号线或所述第一绝缘层远离所述衬底基板的表面由于所述凹槽产生的相对于所述衬底基板的高度差。
  5. 根据权利要求4所述的阵列基板，其中，所述第二绝缘层位于所述第一绝缘层与所述第一信号线之间或者所述第一绝缘层与所述第二信号线之间。
  6. 根据权利要求1-5任一项所述的阵列基板，其中，沿垂直于所述衬底基板的方向，所述凹槽的深度与所述第一信号线不包括所述凹槽的部分的厚度之比不超过1:2。
  7. 根据权利要求1-5任一项所述的阵列基板，其中，所述第一信号线和所述第二信号线之一为扫描线，另一条为数据线。
  8. 一种显示装置，包括权利要求1-7任一项所述的阵列基板。
  9. 一种阵列基板的制作方法，包括：
    在衬底基板上形成沿第一方向延伸的第一信号线；
    在所述第一信号线远离所述衬底基板的一侧形成凹槽；
    在所述第一信号线上形成沿第二方向延伸的第二信号线，所述第二信号线与所述第一信号线彼此绝缘，所述第一方向与所述第二方向彼此交叉，
    其中，所述凹槽位于所述第一信号线与所述第二信号线之间的交汇处，在所述交汇处，所述第二信号线在所述衬底基板上的正投影完全落入所述凹槽在所述衬底基板的正投影内。
  10. 根据权利要求9所述的阵列基板的制作方法，其中，形成所述凹槽包括：
    在所述第一信号线上形成第一绝缘层；
    对位于所述交汇处的所述第一绝缘层进行刻蚀形成过孔以暴露出所述第一信号线；
    对暴露出的所述第一信号线进行刻蚀以形成所述凹槽。
  11. 根据权利要求10所述的阵列基板的制作方法，其中，形成所述第二信号线之前还包括：
    对所述凹槽以及所述过孔填充绝缘材料，其中，对所述凹槽填充所述绝缘材料以形成第二绝缘层，所述第二绝缘层的表面与所述第一信号线的表面平齐，对所述过孔填充所述绝缘材料以使所述第一绝缘层的厚度均匀。
  12. 根据权利要求9所述的阵列基板的制作方法，其中，形成所述凹槽包括：
    在所述第一信号线上形成光刻胶图案；
    以所述光刻胶图案为掩模，刻蚀所述第一信号线以形成所述凹槽。
  13. 根据权利要求9所述的阵列基板的制作方法，其中，所述第一信号线与所述凹槽采用同一个掩模板图案化，并采用半色调掩模工艺形成。
  14. 根据权利要求12或13所述的阵列基板的制作方法，其中，形成所述第二信号线之前还包括：
    对所述凹槽填充绝缘材料以形成第二绝缘层，所述第二绝缘层的表面与所述第一信号线的表面平齐；
    在所述第一信号线以及所述第二绝缘层上形成第一绝缘层。
  15. 根据权利要求12或13所述的阵列基板的制作方法，其中，形成所述第二信号线之前还包括：
    在所述第一信号线上形成第一绝缘层，所述第一绝缘层位于所述凹槽的位置形成凹陷部；
    对所述凹陷部填充绝缘材料以形成第二绝缘层，所述第二绝缘层的表面与所述第一绝缘层的表面平齐。
  16. 根据权利要求10或12或13所述的阵列基板的制作方法，其中，所述第一信号线还包括位于所述凹槽两侧的第一部分与第二部分，所述第一部分包括与所述凹槽连接的第一连接部，所述第二部分包括与所述凹槽连接的第二连接部，其中，形成所述第一信号线包括：
    对所述第一信号线图案化以使沿所述第二方向，待形成所述凹槽所在位置的第一信号线的最大尺寸大于所述第一连接部和所述第二连接部的至少之一的尺寸。
  17. 根据权利要求9-16任一项所述的阵列基板的制作方法，其中，沿垂直于所述衬底基板的方向上，所述凹槽的深度与所述第一信号线不包括所述凹槽的部分的厚度之比不超过1:2。
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