WO2018232907A1 - 一种阵列基板及其制作方法和液晶显示面板 - Google Patents

一种阵列基板及其制作方法和液晶显示面板 Download PDF

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Publication number
WO2018232907A1
WO2018232907A1 PCT/CN2017/097319 CN2017097319W WO2018232907A1 WO 2018232907 A1 WO2018232907 A1 WO 2018232907A1 CN 2017097319 W CN2017097319 W CN 2017097319W WO 2018232907 A1 WO2018232907 A1 WO 2018232907A1
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Prior art keywords
layer
pixel electrode
ito
metal layer
array substrate
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PCT/CN2017/097319
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English (en)
French (fr)
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邓竹明
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/571,049 priority Critical patent/US20180364527A1/en
Publication of WO2018232907A1 publication Critical patent/WO2018232907A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a liquid crystal display panel.
  • An object of the present invention is to provide an array substrate, a method of fabricating the same, and a liquid crystal display panel, which can effectively improve the transmittance.
  • the invention provides a method for fabricating an array substrate, and the method for fabricating the array substrate comprises the following steps:
  • An active layer is disposed on the insulating layer to form an active layer pattern
  • the ITO layer being electrically connected to the drain of the second metal layer
  • Performing deposition of the pixel electrode layer forms a pixel electrode pattern such that the pixel electrode pattern is electrically connected to the ITO layer through the via hole.
  • the step of performing deposition of the pixel electrode layer to form a pixel electrode pattern includes:
  • the pixel electrode pattern is then formed using a yellow light and an etching process such that adjacent pixel electrode patterns are spaced apart.
  • the step of forming a via hole at a corresponding position of the drain by etching includes:
  • the passivation layer at the corresponding position of the drain is etched to form the via hole.
  • the pixel electrode patterns of the pixel electrode layer collectively form a four-domain structure of a fishbone shape.
  • the ITO electrode of the ITO layer has a continuous surface structure.
  • the invention also provides an array substrate, the array substrate comprising:
  • the first metal layer is disposed on the surface of the substrate; the first metal layer includes a gate of the thin film transistor;
  • An insulating layer, the insulating layer is disposed on the first metal layer;
  • An active layer the active layer being disposed on the insulating layer
  • the second metal layer is disposed on the active layer;
  • the second metal layer includes a source of the thin film transistor, a drain of the thin film transistor;
  • ITO layer An ITO layer, the ITO layer is entirely laid on the second metal layer;
  • a passivation layer disposed on the ITO layer for isolating the ITO layer and the pixel electrode layer;
  • the pixel electrode layer is disposed on the passivation layer; the pixel electrode layer includes a pixel electrode;
  • the ITO layer is electrically connected to the pixel electrode layer, and the ITO layer is electrically connected to the second metal layer.
  • the passivation layer at the corresponding position of the drain is provided with a through hole so that the pixel electrode is electrically connected to the ITO layer through the through hole.
  • adjacent pixel electrodes of the pixel electrode layer are spaced apart; and pixel electrodes of the pixel electrode layer collectively form a four-domain structure of a fishbone shape.
  • the ITO electrode of the ITO layer is a continuous and continuous planar structure.
  • the present invention also provides a liquid crystal display panel, comprising an array substrate, a color filter substrate, and a liquid crystal cell disposed between the array substrate and the color filter substrate;
  • the array substrate includes:
  • the first metal layer is disposed on the surface of the substrate; the first metal layer includes a gate of the thin film transistor;
  • An insulating layer, the insulating layer is disposed on the first metal layer;
  • An active layer the active layer being disposed on the insulating layer
  • the second metal layer is disposed on the active layer;
  • the second metal layer includes a source of the thin film transistor, a drain of the thin film transistor;
  • ITO layer An ITO layer, the ITO layer is entirely laid on the second metal layer;
  • a passivation layer disposed on the ITO layer for isolating the ITO layer and the pixel electrode layer;
  • the pixel electrode layer is disposed on the passivation layer; the pixel electrode layer includes a pixel electrode;
  • the ITO layer is electrically connected to the pixel electrode layer, and the ITO layer is electrically connected to the second metal layer.
  • the passivation layer at the corresponding position of the drain is provided with a through hole so that the pixel electrode is electrically connected to the ITO layer through the through hole.
  • adjacent pixel electrodes of the pixel electrode layer are spaced apart; and pixel electrodes of the pixel electrode layer collectively form a four-domain structure of a fishbone shape.
  • the ITO electrode of the ITO layer is a continuous and continuous planar structure.
  • the present invention provides a through-hole through the passivation layer at the corresponding position of the drain of the second metal layer by laying a full-surface ITO layer on the second metal layer, so that the pixel electrode of the pixel electrode layer
  • the ITO layer is electrically connected to the ITO layer through the through hole, and the ITO layer is electrically connected to the second metal layer. That is, the present invention adds an ITO layer under the pixel electrode in the conventional PSVA pixel to form a novel PSVA pixel. Since the ITO layer is laid over the entire surface, the trench portion can also form an electric field with the upper substrate ITO, causing the liquid crystal to tilt and contribute. The transmission rate of this part. Therefore, the present invention can effectively improve the penetration rate and optimize the performance.
  • FIG. 1 is a schematic flowchart showing the implementation of a method for fabricating an array substrate according to Embodiment 1 of the present invention
  • FIG. 2 is a schematic structural diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 3 is a schematic structural diagram of a pixel electrode of a pixel electrode layer according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of an ITO electrode of an ITO layer according to an embodiment of the present invention.
  • the passivation layer at the corresponding position of the drain of the second metal layer is provided with a through hole so that the pixel electrode of the pixel electrode layer
  • the ITO layer is electrically connected to the ITO layer through the through hole
  • the ITO layer is electrically connected to the second metal layer. That is, the present invention adds an ITO layer under the pixel electrode in the conventional PSVA (polymer stable vertical alignment) pixel to form a novel PSVA pixel. Since the ITO layer is laid over the entire surface, the groove portion can also form with the upper substrate ITO. The electric field tilts the liquid crystal and contributes to the transmittance of this portion. Therefore, the present invention can effectively improve the penetration rate and optimize the performance.
  • PSVA polymer stable vertical alignment
  • FIG. 1 is a schematic flowchart of an implementation process of a method for fabricating an array substrate according to Embodiment 1 of the present invention.
  • the implementation flow of the method for fabricating the array substrate is described in detail below, which mainly includes the following steps:
  • step S101 a substrate is provided.
  • the substrate may be a glass substrate.
  • step S102 a first metal layer is disposed on the surface of the substrate to form a gate electrode layer pattern.
  • a first metal layer is deposited on the surface of the substrate, and then a pattern of the first metal layer is formed using a yellow light and an etch process, wherein the pattern of the first metal layer includes a gate electrode of the transistor.
  • step S103 an insulating layer is disposed on the first metal layer.
  • step S104 an active layer is disposed on the insulating layer to form an active layer pattern.
  • step S105 a second metal layer is disposed on the active layer to form a source drain layer pattern.
  • the pattern of the second metal layer includes: a source of the thin film transistor and a thin film transistor The drain.
  • step S106 the entire layer of ITO is laid (Indium Tin An Oxide, tin-doped indium oxide layer, the ITO layer being electrically connected to a drain of the second metal layer.
  • the ITO electrode of the ITO layer is a continuous and continuous planar structure.
  • step S107 a passivation layer is provided on the ITO layer to form a passivation layer pattern.
  • step S108 a via hole is formed at the corresponding position of the drain by etching.
  • the passivation layer at the corresponding position of the drain is etched to form the via hole.
  • step S109 deposition of the pixel electrode layer is performed to form a pixel electrode pattern such that the pixel electrode pattern is electrically connected to the ITO layer through the via hole.
  • the pixel electrode pattern is then formed using a yellow light and an etching process such that adjacent pixel electrode patterns are spaced apart.
  • the pixel electrode patterns of the pixel electrode layer collectively form a four-domain structure of a fishbone shape.
  • the passivation layer at the corresponding position of the drain of the second metal layer is provided with a through-pass.
  • a hole such that a pixel electrode of the pixel electrode layer is electrically connected to the ITO layer through the through hole, and the ITO layer is electrically connected to the second metal layer. That is, the present invention adds an ITO layer under the pixel electrode in the conventional PSVA pixel to form a novel PSVA pixel. Since the ITO layer is laid over the entire surface, the trench portion can also form an electric field with the upper substrate ITO, causing the liquid crystal to tilt and contribute. The transmission rate of this part. Therefore, the present invention can effectively improve the penetration rate and optimize the performance.
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. For the convenience of description, only parts related to the embodiment of the present invention are shown.
  • the array substrate includes a substrate 100, a first metal layer 101, an insulating layer 102, an active layer 103, a second metal layer 104, an ITO layer 105, a passivation layer 106, and a pixel electrode. Layer 107.
  • the first metal layer 101 is disposed on the surface of the substrate 100; the first metal layer 101 includes a gate of the thin film transistor; the insulating layer 102 is disposed on the first metal layer 101; The active layer 103 is disposed on the insulating layer 102; the second metal layer 104 is disposed on the active layer 103; the second metal layer 104 includes a source of the thin film transistor and a drain of the thin film transistor; The ITO layer 105 is entirely disposed on the second metal layer 104; the passivation layer 106 is disposed on the ITO layer 105 for isolating the ITO layer 105 and the pixel electrode layer 107; An electrode layer 107 is disposed on the passivation layer 106; the pixel electrode layer 107 includes a pixel electrode.
  • the ITO layer 105 is electrically connected to the pixel electrode layer 107, and the ITO layer is electrically connected to the second metal layer 104, and the potential is the same.
  • the passivation layer 106 at the corresponding position of the drain is provided with a through hole so that the pixel electrode is electrically connected to the ITO layer through the through hole.
  • adjacent pixel electrodes of the pixel electrode layer are spaced apart; and pixel electrodes of the pixel electrode layer collectively form a four-domain structure of a fishbone shape.
  • the ITO electrode of the ITO layer is a continuous and continuous planar structure.
  • the first metal layer 101 is deposited on the surface of the substrate 100, and then the pattern of the first metal layer 101 is formed by using a yellow light and an etching process, wherein the pattern of the first metal layer 101 includes the gate of the thin film transistor. pole.
  • the pattern of the second metal layer 104 is formed by using a yellow light and an etching process, wherein the pattern of the second metal layer 104 includes the source of the thin film transistor.
  • the drain of the thin film transistor is the pattern of the second metal layer 104 in the embodiment of the present invention.
  • the pattern of the pixel electrode layer 107 is formed by using a yellow light and an etching process, wherein the pattern of the pixel electrode layer 107 includes a pixel electrode. .
  • the pixel electrode layer 107 is made of ITO (Indium Tin). Oxide, tin-doped indium oxide) or indium zinc oxide IZO or the like; the insulating layer 102 may be made of G-Sinx material; however, it is understood that it is not limited to the above materials, and is in the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
  • the passivation layer at the corresponding position of the drain of the second metal layer is provided with a through hole
  • the pixel electrode of the pixel electrode layer is electrically connected to the ITO layer through the through hole
  • the ITO layer is electrically connected to the second metal layer. That is, the present invention adds an ITO layer under the pixel electrode in the conventional PSVA pixel to form a novel PSVA pixel. Since the ITO layer is laid over the entire surface, the trench portion can also form an electric field with the upper substrate ITO, causing the liquid crystal to tilt and contribute. The transmission rate of this part. Therefore, the present invention can effectively improve the penetration rate and optimize the performance.
  • the embodiment of the invention further provides a liquid crystal display panel.
  • the liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal cell disposed between the array substrate and the color filter substrate.
  • the array substrate includes a substrate 100, a first metal layer 101, an insulating layer 102, an active layer 103, a second metal layer 104, an ITO layer 105, a passivation layer 106, and a pixel electrode. Layer 107.
  • the first metal layer 101 is disposed on the surface of the substrate 100; the first metal layer 101 includes a gate of the thin film transistor; the insulating layer 102 is disposed on the first metal layer 101; The active layer 103 is disposed on the insulating layer 102; the second metal layer 104 is disposed on the active layer 103; the second metal layer 104 includes a source of the thin film transistor and a drain of the thin film transistor; The ITO layer 105 is entirely disposed on the second metal layer 104; the passivation layer 106 is disposed on the ITO layer 105 for isolating the ITO layer 105 and the pixel electrode layer 107; An electrode layer 107 is disposed on the passivation layer 106; the pixel electrode layer 107 includes a pixel electrode.
  • the ITO layer 105 is electrically connected to the pixel electrode layer 107 , and the ITO layer is electrically connected to the second metal layer 104 .
  • the passivation layer 106 at the corresponding position of the drain is provided with a through hole so that the pixel electrode is electrically connected to the ITO layer through the through hole.
  • adjacent pixel electrodes of the pixel electrode layer are spaced apart; and pixel electrodes of the pixel electrode layer collectively form a four-domain structure of a fishbone shape.
  • the ITO electrode of the ITO layer is a continuous and continuous planar structure.
  • the entire ITO layer is laid on the second metal layer, and the passivation layer at the corresponding position of the drain of the second metal layer is provided with a through hole, so that the pixel electrode layer
  • the pixel electrode is electrically connected to the ITO layer through the through hole, and the ITO layer is electrically connected to the second metal layer. That is, the present invention adds an ITO layer under the pixel electrode in the conventional PSVA pixel to form a novel PSVA pixel. Since the ITO layer is laid over the entire surface, the trench portion can also form an electric field with the upper substrate ITO, causing the liquid crystal to tilt and contribute. The transmission rate of this part. Therefore, the present invention can effectively improve the penetration rate and optimize the performance.

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Abstract

一种阵列基板及其制作方法和液晶显示面板，在第二金属层（104）上铺设整面ITO层（105），在第二金属层（104）的漏极对应位置处的钝化层（106）设置有贯穿的通孔，以使得像素电极层（107）的像素电极通过通孔与ITO层（105）电性连接，并且ITO层（105）与第二金属层（104）电性连接。能有效提高穿透率，并且能优化性能。

Description

一种阵列基板及其制作方法和液晶显示面板 技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板及其制作方法和液晶显示面板。
 背景技术
在现有技术中，对于阵列基板的像素电极层，因为在ITO（Indium Tin Oxide，掺锡氧化铟）的狭缝区域没有ITO电极，该区域无法与正上方的ITO基板形成电场，只能靠相邻ITO电极的带动，使得液晶倾斜，因此穿透率低。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种阵列基板及其制作方法和液晶显示面板，其能够有效提高穿透率。
 技术解决方案
为解决上述问题，本发明的技术方案如下：
本发明提供了一种阵列基板的制作方法，所述阵列基板的制作方法包括以下步骤：
提供一基板；
在所述基板表面上设置第一金属层，以形成栅电极层图案；
在所述第一金属层上设置绝缘层；
在所述绝缘层上设置有源层，以形成有源层图案；
在所述有源层上设置第二金属层，以形成源漏极层图案；
铺设整层ITO层，所述ITO层与所述第二金属层的漏极电性连接；
在所述ITO层上设置钝化层，以形成钝化层图案；
通过蚀刻在所述漏极对应位置处形成通孔；
进行像素电极层的沉积形成像素电极图案，以使得所述像素电极图案通过所述通孔与所述ITO层电性连接。
优选的，在所述阵列基板的制作方法中，所述进行像素电极层的沉积形成像素电极图案的步骤，包括：
溅射沉积所述像素电极层后，并接着利用黄光及蚀刻工艺形成所述像素电极图案，以使得相邻的像素电极图案间隔设置。
优选的，在所述阵列基板的制作方法中，所述通过蚀刻在所述漏极对应位置处形成通孔的步骤，包括：
蚀刻所述漏极对应位置处的所述钝化层，以形成所述通孔。
优选的，在所述阵列基板的制作方法中，所述像素电极层的像素电极图案共同形成鱼骨形状的四畴结构。
优选的，在所述阵列基板的制作方法中，所述ITO层的ITO电极为整面且连续不断的面状结构。
本发明还提供了一种阵列基板，所述阵列基板包括：
一基板；
一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层包括薄膜晶体管的栅极；
一绝缘层，所述绝缘层设置于所述第一金属层上；
一有源层，所述有源层设置于所述绝缘层上；
一第二金属层，所述第二金属层设置于所述有源层上；所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极；
一ITO层，所述ITO层整面铺设在所述第二金属层上；
一钝化层，所述钝化层设置于所述ITO层上，用于隔离所述ITO层和像素电极层；
一所述像素电极层，所述像素电极层设置于所述钝化层上；所述像素电极层包括像素电极；
其中，所述ITO层与所述像素电极层电性连接，所述ITO层与所述第二金属层电性连接。
优选的，在所述阵列基板中，所述漏极对应位置处的所述钝化层设置有贯穿的通孔，以使得所述像素电极通过所述通孔与所述ITO层电性连接。
优选的，在所述阵列基板中，所述像素电极层的相邻的像素电极间隔设置；所述像素电极层的像素电极共同形成鱼骨形状的四畴结构。
优选的，在所述阵列基板中，所述ITO层的ITO电极为整面且连续不断的面状结构。
本发明还提供了一种液晶显示面板，包括阵列基板、彩膜基板、以及设置于所述阵列基板与彩膜基板之间的液晶盒；
所述阵列基板包括：
一基板；
一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层包括薄膜晶体管的栅极；
一绝缘层，所述绝缘层设置于所述第一金属层上；
一有源层，所述有源层设置于所述绝缘层上；
一第二金属层，所述第二金属层设置于所述有源层上；所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极；
一ITO层，所述ITO层整面铺设在所述第二金属层上；
一钝化层，所述钝化层设置于所述ITO层上，用于隔离所述ITO层和像素电极层；
一所述像素电极层，所述像素电极层设置于所述钝化层上；所述像素电极层包括像素电极；
其中，所述ITO层与所述像素电极层电性连接，所述ITO层与所述第二金属层电性连接。
优选的，在所述液晶显示面板中，所述漏极对应位置处的所述钝化层设置有贯穿的通孔，以使得所述像素电极通过所述通孔与所述ITO层电性连接。
优选的，在所述液晶显示面板中，所述像素电极层的相邻的像素电极间隔设置；所述像素电极层的像素电极共同形成鱼骨形状的四畴结构。
优选的，在所述液晶显示面板中，所述ITO层的ITO电极为整面且连续不断的面状结构。
 有益效果
相对现有技术，本发明通过在第二金属层上铺设整面ITO层，在第二金属层的漏极对应位置处的钝化层设置有贯穿的通孔，以使得像素电极层的像素电极通过所述通孔与所述ITO层电性连接，并且所述ITO层与所述第二金属层电性连接。即本发明在传统的PSVA像素中的像素电极下方增加一层ITO层，形成新型PSVA像素，由于ITO层是整面铺设，因此沟槽部分也能与上基板ITO形成电场，使液晶倾斜，贡献此部分的透过率。因此，本发明能有效提高穿透率，并且能优化性能。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下。
图1 为本发明实施例一提供的阵列基板的制作方法的实现流程示意图；
图2为本发明实施例二提供的阵列基板的结构示意图；
图3为本发明实施例提供的像素电极层的像素电极的结构示意图；
图4为本发明实施例提供的ITO层的ITO电极的结构示意图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指用作实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为意指“一个或多个”，除非另外指定或从上下文清楚导向单数形式。
在本发明实施例中，通过在第二金属层上铺设整面ITO层，在第二金属层的漏极对应位置处的钝化层设置有贯穿的通孔，以使得像素电极层的像素电极通过所述通孔与所述ITO层电性连接，并且所述ITO层与所述第二金属层电性连接。即本发明在传统的PSVA(聚合物稳定垂直配向)像素中的像素电极下方增加一层ITO层，形成新型PSVA像素，由于ITO层是整面铺设，因此沟槽部分也能与上基板ITO形成电场，使液晶倾斜，贡献此部分的透过率。因此，本发明能有效提高穿透率，并且能优化性能。
实施例一
请参阅图1，为本发明实施例一提供的阵列基板的制作方法的实现流程示意图。下面详细描述所述阵列基板的制作方法的实现流程，其主要包括以下步骤：
在步骤S101中，提供一基板。
在本发明实施例中，基板可以为玻璃基板。
在步骤S102中，在所述基板表面上设置第一金属层，以形成栅电极层图案。
在本发明实施例中，在基板表面上沉积第一金属层，并接着利用黄光及蚀刻工艺形成第一金属层的图样，其中该第一金属层的图样包括晶体管的栅极电极。
在步骤S103中，在所述第一金属层上设置绝缘层。
在步骤S104中，在所述绝缘层上设置有源层，以形成有源层图案。
在步骤S105中，在所述有源层上设置第二金属层，以形成源漏极层图案。
在本发明实施例中，溅射沉积第二金属层后，并接着利用黄光及蚀刻工艺形成第二金属层的图样，所述第二金属层的图样包括：薄膜晶体管的源极和薄膜晶体管的漏极。
在步骤S106中，铺设整层ITO（Indium Tin Oxide，掺锡氧化铟）层，所述ITO层与所述第二金属层的漏极电性连接。
作为本发明一优选实施例，所述ITO层的ITO电极为整面且连续不断的面状结构。
在步骤S107中，在所述ITO层上设置钝化层，以形成钝化层图案。
在步骤S108中，通过蚀刻在所述漏极对应位置处形成通孔。
在本发明实施例中，蚀刻所述漏极对应位置处的所述钝化层，以形成所述通孔。
在步骤S109中，进行像素电极层的沉积形成像素电极图案，以使得所述像素电极图案通过所述通孔与所述ITO层电性连接。
在本发明实施例中，溅射沉积所述像素电极层后，并接着利用黄光及蚀刻工艺形成所述像素电极图案，以使得相邻的像素电极图案间隔设置。
作为本发明一优选实施例，所述像素电极层的像素电极图案共同形成鱼骨形状的四畴结构。
由上可知，本发明实施例一提供的阵列基板的制作方法，通过在第二金属层上铺设整面ITO层，在第二金属层的漏极对应位置处的钝化层设置有贯穿的通孔，以使得像素电极层的像素电极通过所述通孔与所述ITO层电性连接，并且所述ITO层与所述第二金属层电性连接。即本发明在传统的PSVA像素中的像素电极下方增加一层ITO层，形成新型PSVA像素，由于ITO层是整面铺设，因此沟槽部分也能与上基板ITO形成电场，使液晶倾斜，贡献此部分的透过率。因此，本发明能有效提高穿透率，并且能优化性能。
实施例二
请参阅图2，为本发明实施例提供的阵列基板的结构示意图。为了便于说明，仅示出了与本发明实施例相关的部分。
所述阵列基板包括：一基板100，一第一金属层101、一绝缘层102、一有源层103、一第二金属层104、一ITO层105、一钝化层106、以及一像素电极层107。其中，所述第一金属层101设置于所述基板100表面上；所述第一金属层101包括薄膜晶体管的栅极；所述绝缘层102设置于所述第一金属层101上；所述有源层103设置于所述绝缘层102上；所述第二金属层104设置于所述有源层103上；所述第二金属层104包括薄膜晶体管的源极、薄膜晶体管的漏极；所述ITO层105整面铺设在所述第二金属层104上；所述钝化层106设置于所述ITO层105上，用于隔离所述ITO层105和像素电极层107；所述像素电极层107设置于所述钝化层106上；所述像素电极层107包括像素电极。
其中，所述ITO层105与所述像素电极层107电性连接，所述ITO层与所述第二金属层104电性连接，电位相同。
优选的，所述漏极对应位置处的所述钝化层106设置有贯穿的通孔，以使得所述像素电极通过所述通孔与所述ITO层电性连接。
请参阅图3，优选的，所述像素电极层的相邻的像素电极间隔设置；所述像素电极层的像素电极共同形成鱼骨形状的四畴结构。
请参阅图4，优选的，所述ITO层的ITO电极为整面且连续不断的面状结构。
在本发明实施例中，在基板100表面上沉积第一金属层101，并接着利用黄光及蚀刻工艺形成第一金属层101的图样，其中该第一金属层101的图样包括薄膜晶体管的栅极。
在本发明实施例中，溅射沉积第二金属层104后，并接着利用黄光及蚀刻工艺形成第二金属层104的图样，其中，所述第二金属层104的图样包括薄膜晶体管的源极、薄膜晶体管的漏极。
在本发明实施例中，溅射沉积一像素电极层107后，并接着利用黄光及蚀刻工艺形成所述像素电极层107的图样，其中，所述所述像素电极层107的图样包括像素电极。
在本发明实施例中，所述像素电极层107采用ITO（Indium Tin Oxide，掺锡氧化铟）或铟锌氧化物IZO等等材料制成；所述绝缘层102可采用G-Sinx材料制成；然而，可以理解的是，并不限于上述材料，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
由上可知，本发明实施例二提供的阵列基板，通过在第二金属层上铺设整面ITO层，在第二金属层的漏极对应位置处的钝化层设置有贯穿的通孔，以使得像素电极层的像素电极通过所述通孔与所述ITO层电性连接，并且所述ITO层与所述第二金属层电性连接。即本发明在传统的PSVA像素中的像素电极下方增加一层ITO层，形成新型PSVA像素，由于ITO层是整面铺设，因此沟槽部分也能与上基板ITO形成电场，使液晶倾斜，贡献此部分的透过率。因此，本发明能有效提高穿透率，并且能优化性能。
实施例三
本发明实施例还提供了一种液晶显示面板。为了便于说明，仅示出了与本发明实施例相关的部分。所述液晶显示面板包括阵列基板、彩膜基板、以及设置于所述阵列基板与彩膜基板之间的液晶盒。
所述阵列基板包括：一基板100，一第一金属层101、一绝缘层102、一有源层103、一第二金属层104、一ITO层105、一钝化层106、以及一像素电极层107。其中，所述第一金属层101设置于所述基板100表面上；所述第一金属层101包括薄膜晶体管的栅极；所述绝缘层102设置于所述第一金属层101上；所述有源层103设置于所述绝缘层102上；所述第二金属层104设置于所述有源层103上；所述第二金属层104包括薄膜晶体管的源极、薄膜晶体管的漏极；所述ITO层105整面铺设在所述第二金属层104上；所述钝化层106设置于所述ITO层105上，用于隔离所述ITO层105和像素电极层107；所述像素电极层107设置于所述钝化层106上；所述像素电极层107包括像素电极。
其中，所述ITO层105与所述像素电极层107电性连接，所述ITO层与所述第二金属层104电性连接。
优选的，所述漏极对应位置处的所述钝化层106设置有贯穿的通孔，以使得所述像素电极通过所述通孔与所述ITO层电性连接。
优选的，所述像素电极层的相邻的像素电极间隔设置；所述像素电极层的像素电极共同形成鱼骨形状的四畴结构。
优选的，所述ITO层的ITO电极为整面且连续不断的面状结构。
综上所述，本发明实施例通过在第二金属层上铺设整面ITO层，在第二金属层的漏极对应位置处的钝化层设置有贯穿的通孔，以使得像素电极层的像素电极通过所述通孔与所述ITO层电性连接，并且所述ITO层与所述第二金属层电性连接。即本发明在传统的PSVA像素中的像素电极下方增加一层ITO层，形成新型PSVA像素，由于ITO层是整面铺设，因此沟槽部分也能与上基板ITO形成电场，使液晶倾斜，贡献此部分的透过率。因此，本发明能有效提高穿透率，并且能优化性能。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种阵列基板的制作方法，其中所述阵列基板的制作方法包括以下步骤：
    提供一基板；
    在所述基板表面上设置第一金属层，以形成栅电极层图案；
    在所述第一金属层上设置绝缘层；
    在所述绝缘层上设置有源层，以形成有源层图案；
    在所述有源层上设置第二金属层，以形成源漏极层图案；
    铺设整层ITO层，所述ITO层与所述第二金属层的漏极电性连接；
    在所述ITO层上设置钝化层，以形成钝化层图案；
    通过蚀刻在所述漏极对应位置处形成通孔；
    进行像素电极层的沉积形成像素电极图案，以使得所述像素电极图案通过所述通孔与所述ITO层电性连接。
  2. 根据权利要求1所述的阵列基板的制作方法，其中所述进行像素电极层的沉积形成像素电极图案的步骤，包括：
    溅射沉积所述像素电极层后，并接着利用黄光及蚀刻工艺形成所述像素电极图案，以使得相邻的像素电极图案间隔设置。
  3. 根据权利要求1所述的阵列基板的制作方法，其中所述通过蚀刻在所述漏极对应位置处形成通孔的步骤，包括：
    蚀刻所述漏极对应位置处的所述钝化层，以形成所述通孔。
  4. 根据权利要求1所述的阵列基板的制作方法，其中所述像素电极层的像素电极图案共同形成鱼骨形状的四畴结构。
  5. 根据权利要求1所述的阵列基板的制作方法，其中所述ITO层的ITO电极为整面且连续不断的面状结构。
  6. 一种阵列基板，其中所述阵列基板包括：
    一基板；
    一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层包括薄膜晶体管的栅极；
    一绝缘层，所述绝缘层设置于所述第一金属层上；
    一有源层，所述有源层设置于所述绝缘层上；
    一第二金属层，所述第二金属层设置于所述有源层上；所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极；
    一ITO层，所述ITO层整面铺设在所述第二金属层上；
    一钝化层，所述钝化层设置于所述ITO层上，用于隔离所述ITO层和像素电极层；
    一所述像素电极层，所述像素电极层设置于所述钝化层上；所述像素电极层包括像素电极；
    其中，所述ITO层与所述像素电极层电性连接，所述ITO层与所述第二金属层电性连接。
  7. 根据权利要求6所述的阵列基板，其中所述漏极对应位置处的所述钝化层设置有贯穿的通孔，以使得所述像素电极通过所述通孔与所述ITO层电性连接。
  8. 根据权利要求6所述的阵列基板，其中所述像素电极层的相邻的像素电极间隔设置；所述像素电极层的像素电极共同形成鱼骨形状的四畴结构。
  9. 根据权利要求6所述的阵列基板，其中所述ITO层的ITO电极为整面且连续不断的面状结构。
  10. 一种液晶显示面板，包括阵列基板、彩膜基板、以及设置于所述阵列基板与彩膜基板之间的液晶盒；其中
    所述阵列基板包括：
    一基板；
    一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层包括薄膜晶体管的栅极；
    一绝缘层，所述绝缘层设置于所述第一金属层上；
    一有源层，所述有源层设置于所述绝缘层上；
    一第二金属层，所述第二金属层设置于所述有源层上；所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极；
    一ITO层，所述ITO层整面铺设在所述第二金属层上；
    一钝化层，所述钝化层设置于所述ITO层上，用于隔离所述ITO层和像素电极层；
    一所述像素电极层，所述像素电极层设置于所述钝化层上；所述像素电极层包括像素电极；
    其中，所述ITO层与所述像素电极层电性连接，所述ITO层与所述第二金属层电性连接。
  11. 根据权利要求10所述的液晶显示面板，其中所述漏极对应位置处的所述钝化层设置有贯穿的通孔，以使得所述像素电极通过所述通孔与所述ITO层电性连接。
  12. 根据权利要求10所述的液晶显示面板，其中所述像素电极层的相邻的像素电极间隔设置；所述像素电极层的像素电极共同形成鱼骨形状的四畴结构。
  13. 根据权利要求10所述的液晶显示面板，其中所述ITO层的ITO电极为整面且连续不断的面状结构。
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CN109521596B (zh) * 2018-12-26 2020-09-01 武汉华星光电技术有限公司 阵列基板、显示面板以及显示面板的控制方法
CN110398863A (zh) * 2019-07-22 2019-11-01 深圳市华星光电半导体显示技术有限公司 显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103824866A (zh) * 2014-03-03 2014-05-28 深圳市华星光电技术有限公司 一种阵列基板及其制备方法、液晶显示面板
CN104777693A (zh) * 2015-04-28 2015-07-15 深圳市华星光电技术有限公司 高穿透率psva型液晶显示面板及其制作方法
US20150205173A1 (en) * 2011-09-23 2015-07-23 Samsung Display Co., Ltd. Display panel and method of manufacturing the display panel
CN105068325A (zh) * 2015-08-31 2015-11-18 深圳市华星光电技术有限公司 Psva型液晶显示面板
CN205247020U (zh) * 2015-12-28 2016-05-18 京东方科技集团股份有限公司 显示基板和显示装置
CN105824157A (zh) * 2015-01-28 2016-08-03 群创光电股份有限公司 液晶显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150205173A1 (en) * 2011-09-23 2015-07-23 Samsung Display Co., Ltd. Display panel and method of manufacturing the display panel
CN103824866A (zh) * 2014-03-03 2014-05-28 深圳市华星光电技术有限公司 一种阵列基板及其制备方法、液晶显示面板
CN105824157A (zh) * 2015-01-28 2016-08-03 群创光电股份有限公司 液晶显示面板
CN104777693A (zh) * 2015-04-28 2015-07-15 深圳市华星光电技术有限公司 高穿透率psva型液晶显示面板及其制作方法
CN105068325A (zh) * 2015-08-31 2015-11-18 深圳市华星光电技术有限公司 Psva型液晶显示面板
CN205247020U (zh) * 2015-12-28 2016-05-18 京东方科技集团股份有限公司 显示基板和显示装置

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