WO2018214645A1 - 一种阵列基板及其制造方法、显示装置 - Google Patents

一种阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2018214645A1
WO2018214645A1 PCT/CN2018/081094 CN2018081094W WO2018214645A1 WO 2018214645 A1 WO2018214645 A1 WO 2018214645A1 CN 2018081094 W CN2018081094 W CN 2018081094W WO 2018214645 A1 WO2018214645 A1 WO 2018214645A1
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Prior art keywords
conductive layer
layer
terminal
array substrate
terminals
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Ceased
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PCT/CN2018/081094
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English (en)
French (fr)
Inventor
张伟
李慧
石天雷
郭钟旭
方业周
张文龙
张绪
牛志军
姜瑞泽
任艳伟
刘宇
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US16/325,158 priority Critical patent/US10903249B2/en
Publication of WO2018214645A1 publication Critical patent/WO2018214645A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular, to an array substrate, a method of manufacturing the same, and a display device.
  • Electrostatic Discharge has become a technical problem of high-end liquid crystal display.
  • ESD Electrostatic Discharge
  • components such as integrated circuits (ICs) and electronic circuits in a liquid crystal module (LCM) are also susceptible to interference from electrostatic shock. Therefore, for liquid crystal devices, particularly information communication products having liquid crystal devices, antistatic impact has become a compulsory item.
  • the module process and reliability are intentionally or unintentionally experienced in ESD, for example, in the process of product lighting, due to the instantaneous high current, environmental static electricity and static electricity of the device (Panel) ) causes irreversible damage, affects product yield, and greatly increases product cost.
  • the product test terminal E Pad
  • electrostatic breakdown resulting in abnormal product display and abnormal color.
  • Embodiments of the present disclosure provide an array substrate, a method of manufacturing the same, and a display device.
  • an array substrate in a first aspect of an embodiment of the present disclosure, includes a plurality of terminals, a first conductive layer and a second conductive layer, and an insulating layer is disposed between the first conductive layer and the second conductive layer, wherein
  • a plurality of first electrode plates and a plurality of second electrode plates are respectively formed in the first conductive layer and the second conductive layer, and the first electrode plates and the second electrode plates are opposed to each other to form a capacitor structure ,
  • the terminal is disposed in the same layer as the first conductive layer or the second conductive layer, or the third conductive layer between the first conductive layer and the second conductive layer is disposed in the same layer .
  • the terminal when the terminal is disposed in the same layer as the first conductive layer or the second conductive layer, the first electrode plate or the second electrode plate and the terminal are alternately arranged, the An insulating material is filled between the terminal and the first electrode plate or the second electrode plate.
  • the array substrate further includes a fourth conductive layer, wherein a lead of the terminal is in the fourth conductive layer and is connected to the terminal through a via.
  • the terminal is disposed in the same layer as the third conductive layer between the first conductive layer and the second conductive layer, and a lead of the terminal is formed in the third conductive layer.
  • each layer above the terminal is formed with a through hole at a position corresponding to the terminal to expose the terminal.
  • an orthographic projection of the via on the substrate of the array substrate at least partially covers the terminal.
  • the array substrate includes a base substrate, a buffer layer, a TFT transistor, a flat layer, an anode metal layer, a pixel defining layer, an organic light emitting layer, and a cathode
  • the TFT transistor includes a source electrode and a drain electrode.
  • a display device in a second aspect of an embodiment of the present disclosure, includes any one of the array substrates described in the first aspect of the present disclosure.
  • a method of fabricating an array substrate includes:
  • first electrode plate and the second electrode plate constitute a capacitor structure
  • a plurality of terminals are formed in the first conductive layer or the second conductive layer, or a plurality of terminals are formed in the third conductive layer between the first conductive layer and the second conductive layer.
  • a plurality of terminals are formed in the first conductive layer or the second conductive layer, and the first electrode plate or the second electrode plate is alternately arranged with the terminal, and the terminal and the An insulating material is filled between the first electrode plate or the second electrode plate.
  • the method further includes:
  • a lead of the terminal is formed in a fourth conductive layer, and a lead of the terminal is connected to the terminal in a via manner.
  • Lead wires of the terminals are formed in the third conductive layer.
  • Figure 1 shows a schematic diagram of the structure of an associated array substrate.
  • FIG. 2 illustrates a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure.
  • FIG. 3 shows a schematic diagram of an array substrate in accordance with an embodiment of the present disclosure.
  • FIG. 4 shows a schematic diagram of an array substrate in accordance with another embodiment of the present disclosure.
  • FIG. 5 shows a schematic diagram of an array substrate in accordance with yet another embodiment of the present disclosure.
  • an array process is used to increase circuit traces on the upper and lower film layers of the terminal to form a capacitor structure, thereby protecting the terminals, avoiding electrostatic damage, improving product yield, increasing profit, and improving product test terminals. Resistance to ESD at (ET Pad).
  • a capacitor structure may be formed in any two conductive layers in the array substrate, and the terminals may be formed in the same conductive layer as the electrode plates of the capacitor structure, or may be in the conductive layer between the capacitor structures. form.
  • ESD is usually caused by environment and friction. After forming a capacitor structure, ESD preferentially discharges through the capacitor structure instead of discharging on terminals such as ET pads. Static electricity is then released to GND through the capacitor so that the product is not damaged.
  • the principle of designing on the same layer is the same. If the capacitor structure is connected to GND in the same layer design, static electricity is more likely to discharge on the capacitor without discharging on the ET pad.
  • the array substrate of the embodiment of the present disclosure may include a plurality of terminals, a first conductive layer and a second conductive layer, and the first conductive layer and the second conductive layer may include an insulating layer between the first conductive layer and the second conductive layer respectively
  • a plurality of first electrode plates and a plurality of second electrode plates constituting a capacitor structure are formed, and the first electrode plates and the second electrode plates are opposed to each other to constitute a capacitor structure.
  • the capacitor structure corresponds to at least one terminal, that is, the terminal is adjacent to the capacitor structure, and the capacitor structure can protect the terminal to avoid the influence of electrostatic discharge.
  • the terminal may be disposed in the same layer as the first conductive layer or the second conductive layer, or the terminal may be disposed in the same layer as the third conductive layer between the first conductive layer and the second conductive layer. It should be understood that, herein, the term "same layer setting" means formed from the same film layer.
  • FIG. 1 shows a schematic diagram of the structure of an associated array substrate.
  • the array substrate generally includes a base substrate 1, a buffer layer 2, a TFT transistor 5, a flat layer 6, an anode metal layer 7, a pixel defining layer 8, an organic light-emitting layer 9, and a cathode 10.
  • the TFT transistor 5 may include a source electrode 51, a drain electrode 52, a gate electrode 53, an active layer 54, and a gate insulating layer 55.
  • the array substrate can also include a gate isolation layer 56.
  • An anode and a barrier layer may be formed in the anode metal layer 7.
  • it is not limited to the above structure.
  • the conductive layer mentioned in the embodiment of the present disclosure may be any of the following layers: a layer forming the source electrode 51, a layer forming the drain electrode 52, a layer forming the gate electrode 53, an active layer 54, and an anode metal layer 7.
  • Embodiments of the present disclosure also provide a method of fabricating an array substrate, and FIG. 2 illustrates a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure. As shown in FIG. 2, the manufacturing method may include the following steps:
  • Step S201 forming a plurality of first electrode plates in the first conductive layer, for example, patterning the first conductive layer to form a first electrode plate;
  • Step S202 forming a plurality of second electrode plates respectively facing the first electrode plates in the second conductive layer, wherein the first electrode plate and the second electrode plate may constitute a capacitor structure, for example, patterning the second conductive layer to form Second electrode plate;
  • Step S203 forming a plurality of terminals in the first conductive layer or the second conductive layer, or forming a plurality of terminals in the third conductive layer between the first conductive layer and the second conductive layer, the capacitor structure corresponding to at least one terminal
  • the patterned first conductive layer, the second conductive layer, and the third conductive layer form terminals.
  • the array substrate of the present disclosure will be described in detail below by way of examples.
  • the terminal 100 is disposed in the same layer as the electrode plate 101 constituting the capacitor structure, for example, a source may be formed.
  • the terminal 100 and the electrode plate 101 are formed in the layer of the electrode 51.
  • the terminal 100 and the electrode plate 101 are alternately arranged, and an insulating material may be filled between the terminal 100 and the electrode plate 101 in order to avoid a short circuit between the terminal 100 and the electrode plate 101.
  • the electrode plate 201 faces the electrode plate 101 to constitute a capacitor structure.
  • a plurality of electrode plates 201 may be formed in the anode metal layer 7.
  • the leads of the terminal 100 are formed in other conductive layers to avoid short-circuiting of the leads of the terminal 100 and the capacitor structure.
  • the leads of the terminal 100 are disposed in the same layer as the active layer 54, and vias (not shown) are formed through the layers between the active layer 54 and the layer forming the source electrode 51, and the leads of the terminal 100 pass through the vias. Connected to the terminal 100.
  • the base substrate 1 is viewed from the bottom layer, and in each layer above the terminal 100, a through hole is formed at a position corresponding to the terminal 100, and the through hole is used to expose the terminal 100 to The external pins can be made to contact the terminal 100.
  • the orthographic projection of the through hole on the base substrate 1 at least partially covers the terminal 100.
  • the size of the through hole is not limited as long as the terminal 100 can be exposed.
  • the method of manufacturing the array substrate shown in FIG. 3 may include the following steps:
  • a buffer layer 2 is formed on the base substrate 1, a TFT transistor 5 is formed on the buffer layer 2, and a lead of the terminal 100 is formed in the active layer 54 of the TFT transistor 5 in the layer forming the source electrode 51 of the TFT transistor 5.
  • a plurality of electrode plates 101 and a plurality of terminals 100 are formed; and a shielding layer (not shown) is formed at a position above or below the TFT transistor 5; an anode and an organic layer are sequentially formed on the substrate 1 after the TFT transistor 5 is formed.
  • a plurality of electrode plates 201 opposed to the electrode plates 101 are formed in the anode metal layer 7 forming the anode.
  • FIG. 4 shows a schematic diagram of an array substrate in accordance with another embodiment of the present disclosure.
  • the array substrate shown in FIG. 4 differs from the array substrate shown in FIG. 3 in that the terminal 100 is disposed in the same layer as the electrode plate 201.
  • a plurality of electrode plates 101 may be formed in the active layer 54, a lead of the terminal 100 is formed in the anode metal layer 7, and a plurality of terminals 100 and a plurality of electrode plates are formed in the layer forming the cathode 10.
  • 101 opposite electrode plate 201 The electrode plate 101 and the opposite electrode plate 201 constitute a capacitor structure.
  • the terminal 100 and the electrode plate 201 are alternately arranged, and an insulating material is filled between the terminal 100 and the electrode plate 201 in order to avoid a short circuit between the terminal 100 and the electrode plate 201.
  • a via hole is formed through each layer between the anode metal layer 7 and the layer forming the cathode 10, and the lead of the terminal 100 is connected to the terminal 100 through the via hole.
  • a through hole is formed at a position corresponding to the terminal 100 in each of the layers above the terminal 100 as the bottom layer is viewed from the bottom layer to expose the terminal 100.
  • the orthographic projection of the through hole on the base substrate 1 at least partially covers the terminal 100, and the size of the through hole is not limited as long as the terminal 100 can be exposed.
  • the method of manufacturing the array substrate shown in FIG. 4 may include the following steps:
  • a buffer layer 2 is formed on the base substrate 1, a TFT transistor 5 is formed on the buffer layer 2, a plurality of electrode plates 101 are formed in the active layer 54 forming the TFT transistor 5, and are opposed above or below the TFT transistor 5.
  • the position forms an occlusion layer (not shown); an anode, a pixel defining layer 8, an organic light-emitting layer 9, and a cathode 10 are sequentially formed on the base substrate 1 after the TFT transistor 5 is formed.
  • Lead wires of the terminal 100 are formed in the anode metal layer 7 forming the anode, and a plurality of terminals 100 and a plurality of electrode plates 201 opposed to the electrode plates 101 are formed in the layer forming the cathode 10.
  • the terminals in the embodiments of the present disclosure may also be formed in a conductive layer between the two electrode plates of the capacitor structure.
  • FIG. 5 shows a schematic diagram of an array substrate in accordance with yet another embodiment of the present disclosure.
  • a plurality of electrode plates 101 may be formed in the active layer 54, and a plurality of terminals 100 and leads of the terminal 100 may be formed in the layer forming the gate electrode 53 in the anode metal layer.
  • a plurality of electrode plates 201 opposed to the electrode plates 101 are formed in 7, and the electrode plates 101 and the opposite electrode plates 201 constitute a capacitor structure.
  • a through hole is formed at a position corresponding to the terminal 100 to expose the terminal 100.
  • the orthographic projection of the through hole on the base substrate 1 at least partially covers the terminal 100, and the size of the through hole is not limited as long as the terminal 100 can be exposed.
  • the method of manufacturing the array substrate shown in FIG. 5 may include the following steps:
  • a buffer layer 2 is formed on the base substrate 1, a TFT transistor 5 is formed on the buffer layer 2, a plurality of electrode plates 101 are formed in the active layer 54 forming the TFT transistor 5, and a plurality of layers are formed in the layer forming the gate electrode 53.
  • a terminal 100 and a lead of the terminal 100, and a blocking layer (not shown) is formed at a position above or below the TFT transistor 5; an anode, a pixel defining layer 8 are sequentially formed on the substrate 1 after the TFT transistor 5 is formed, The organic light-emitting layer 9 and the cathode 10.
  • a plurality of electrode plates 201 are formed in the anode metal layer 7 forming the anode, and the electrode plates 201 are opposed to the electrode plates 101.
  • the two electrode plates of the capacitor structure may be formed in any two electrically conductive layers on the array substrate.

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Abstract

一种阵列基板包括多个端子（100）和至少包括第一导电层和第二导电层，第一导电层和第二导电层之间包括绝缘层，其中，第一导电层和第二导电层上分别形成有组成电容结构的多个第一电极板（101）和多个第二电极板（201），相互平行且相对的一个第一电极板（101）和一个第二电极板（201）构成一个电容结构，一个电容结构至少对应一个端子（100），端子（100）与第一导电层或与第二导电层处于同一层，或者端子（100）处于第一导电层与第二导电层之间的第三导电层。还提供一种阵列基板的制造方法和显示装置。通过在端子增加电容结构，增加产品抗ESD能力，改善从端子（100）导入引起产品损坏的不良问题，以防护端子（100），避免静电损伤。

Description

一种阵列基板及其制造方法、显示装置
本申请要求于2017年5月22日递交的中国专利申请第201710364266.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及但不限于显示技术领域，尤其涉及一种阵列基板及其制造方法、显示装置。
背景技术
随着液晶显示屏的发展和应用，静电放电(Electrostatics Discharge，简称ESD)问题越来越成为高端液晶显示屏的技术难题：一方面在器件制造过程中，由于其工艺特点，极易产生静电并造成产品损失；另一方面液晶模块(Liquid Crystal Module，简称LCM)中的集成电路(IC)等元器件及电子线路也易于受到静电冲击的干扰。因此，对于液晶器件特别是具有液晶器件的信息通讯产品，抗静电冲击已经成为必检项目。
液晶显示屏在对盒(Cell)工艺中，模组工艺和信赖性有意无意都在经历ESD，例如在产品点灯的过程中，因瞬间的大电流，环境静电和设备静电的原因对面板(Panel)造成不可逆的损坏，影响产品良率，大大增加产品成本。此外，在产品进行测试的过程中，经常会对产品测试端子(ET Pad)造成静电击穿，造成产品显示异常、色彩异常等不良。
发明内容
本公开的实施例提供一种阵列基板及其制造方法、显示装置。
在本公开的实施例的第一方面中，提供了一种阵列基板。阵列基板包括多个端子、第一导电层和第二导电层，所述第一导电层和所述第二导电 层之间包括绝缘层，其中，
所述第一导电层和所述第二导电层中分别形成有多个第一电极板和多个第二电极板，所述第一电极板和所述第二电极板彼此相对以构成电容结构，
所述端子与所述第一导电层或与所述第二导电层同层设置，或者所述端子于所述第一导电层和所述第二导电层之间的第三导电层同层设置。
可选地，所述端子与所述第一导电层或与所述第二导电层同层设置时，所述第一电极板或所述第二电极板与所述端子交替相间布置，所述端子与所述第一电极板或与所述第二电极板之间填充有绝缘材料。
可选地，所述阵列基板还包括第四导电层，其中，所述端子的引线在所述第四导电层中，并通过过孔与所述端子连接。
可选地，所述端子与所述第一导电层和所述第二导电层之间的第三导电层同层设置，所述端子的引线形成在所述第三导电层中。
可选地，所述端子之上的各个层在与所述端子对应的位置处形成有通孔，以暴露所述端子。
可选地，所述通孔在所述阵列基板的衬底基板上的正投影至少部分覆盖所述端子。
可选地，所述阵列基板包括衬底基板、缓冲层、TFT晶体管、平坦层、阳极金属层、像素限定层、有机发光层、阴极，其中，所述TFT晶体管包括源极电极、漏极电极、栅极、有源层、栅绝缘层，其中，所述第一导电层、所述第二导电层以及所述第三导电层选自以下中的任意一层：形成所述源极电极或所述漏极电极的层、形成所述栅极的层、所述有源层、所述阳极金属层、所述有机发光层、形成所述阴极的层。
在本公开的实施例的第二方面中，提供了一种显示装置。显示装置包括在本公开的第一方面中描述的任意一种阵列基板。
在本公开的实施例的第三方面中，提供了一种阵列基板的制造方法。阵列基板的制造方法包括：
在第一导电层中形成多个第一电极板；
在第二导电层中形成分别与所述第一电极板相对的多个第二电极板，其中，所述第一电极板和所述第二电极板构成电容结构；
在所述第一导电层或所述第二导电层中形成多个端子，或者在所述第一导电层和所述第二导电层之间的第三导电层中形成多个端子。
可选地，在所述第一导电层或所述第二导电层中形成多个端子，所述第一电极板或所述第二电极板与所述端子交替相间布置，所述端子与所述第一电极板或与所述第二电极板之间填充有绝缘材料。
可选地，所述方法还包括：
在第四导电层中形成所述端子的引线，所述端子的引线以过孔的方式与所述端子连接。
可选地，
在所述第一导电层和所述第二导电层之间的第三导电层中形成多个端子，还包括：
在所述第三导电层中形成所述端子的引线。
附图说明
图1示出了相关的阵列基板的结构的示意图。
图2示出了根据本公开的实施例的阵列基板的制造方法的流程图。
图3示出了根据本公开的实施例的阵列基板的示意图。
图4示出了根据本公开的另一实施例的阵列基板的示意图。
图5示出了根据本公开的又一实施例的阵列基板的示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
本发明中描绘的流程图仅仅是一个例子。在不脱离本发明精神的情况下，可以存在该流程图或其中描述的步骤的很多变型。例如，所述步骤可以以不同的顺序进行，或者可以添加、删除或者修改步骤。这些变型都被认为是所要求保护的方面的一部分。
除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，用语“包含”、“包括”、“含有”和“具有”及其语法变型旨在包括性的并且表示可以存在除所列要素之外的另外的要素。在本文中使用术语“示例”之处，特别是当其位于一组术语之后时，所述“示例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。术语“第一”、“第二”、“第三”等仅用于描述的目的，而不能理解为指示或暗示相对重要性及形成顺序。
随着液晶显示屏的发展和应用，从外挂触摸(GFF)产品到内嵌式(In Cell)产品需要增加静电放电(ESD)能力，从而减少产品损伤。在本公开的实施例中，利用阵列工艺(Array)在端子的上下膜层增加电路走线，形成电容结构，从而保护端子，避免静电损伤，提升产品的良率，增加收益，提升产品测试端子(ET Pad)处的抗ESD能力。
根据本公开的技术方案，可以在阵列基板中的任意两个导电层中形成电容结构，端子可以与电容结构的电极板在同一层导电层中形成，也可以在电容结构之间的导电层中形成。
ESD通常都是环境以及摩擦引起的，形成电容结构后，ESD优先通过该电容结构进行放电，而不是在ET pad等的端子上进行放电。静电再通过电容释放到GND上，这样产品就不会受到损坏。在同一层上设计的原理是一样的，如果在同一层设计时，因电容结构连接到GND，静电更容易在电容上放电而不在ET pad放电。
本公开实施例的阵列基板可包括多个端子、第一导电层和第二导电层，第一导电层和第二导电层之间可包括绝缘层，第一导电层和第二导电层中 分别形成有构成电容结构的多个第一电极板和多个第二电极板，第一电极板和第二电极板彼此相对以构成电容结构。该电容结构至少对应一个端子，即该端子邻近电容结构，该电容结构可以保护端子以避免静电放电的影响。端子可与第一导电层或与第二导电层同层设置，或者端子可与第一导电层与第二导电层之间的第三导电层同层设置。应理解，在本文中，术语“同层设置”表示由同一膜层形成。
图1示出了相关的阵列基板的结构的示意图。如图1所示，阵列基板一般包括：衬底基板1、缓冲层2、TFT晶体管5、平坦层6、阳极金属层7、像素限定层8、有机发光层9、阴极10。TFT晶体管5可包括源极电极51、漏极电极52、栅极53、有源层54、栅绝缘层55。阵列基板还可包括栅隔离层56。可在阳极金属层7中形成阳极和遮挡层。当然对于不同的阵列基板，不局限于上述的结构。
本公开的实施例中提到的导电层可以是以下的任意层：形成源极电极51的层、形成漏极电极52的层、形成栅极53的层、有源层54、阳极金属层7、有机发光层9、形成阴极10的层。
本公开的实施例还提供一种阵列基板的制造方法，图2示出了根据本公开的实施例的阵列基板的制造方法的流程图。如图2所示，制造方法可以包括以下步骤：
步骤S201、在第一导电层中形成多个第一电极板，例如，构图第一导电层形成第一电极板；
步骤S202、在第二导电层中形成分别与第一电极板彼此相对的多个第二电极板，其中，第一电极板和第二电极板可构成电容结构，例如，构图第二导电层形成第二电极板；
步骤S203、在第一导电层或第二导电层中形成多个端子，或者在第一导电层与第二导电层之间的第三导电层中形成多个端子，该电容结构至少对应一个端子，例如构图第一导电层、第二导电层和第三导电层形成端子。
上述制造方法的步骤不限定执行的先后顺序。
以下以实施例对本公开的阵列基板进行详细的说明。
图3示出了根据本公开的实施例的阵列基板的示意图，如图3所示，在本实施例中，端子100与构成电容结构的电极板101在同层设置，例如可在形成源极电极51的层中形成端子100和电极板101。如图3所示，端子100与电极板101交替相间布置，为了避免端子100与电极板101之间发生短路，在端子100与电极板101之间可填充有绝缘材料。
电极板201与电极板101相对，构成电容结构。例如，可在阳极金属层7中形成多个电极板201。
在本实施例中，端子100的引线在其它的导电层中形成，可以避免端子100的引线与电容结构发生短路。例如，端子100的引线与有源层54同层设置，穿过有源层54与形成源极电极51的层之间的各层形成过孔(未示出)，端子100的引线通过过孔与端子100连接。
在本实施例中，以衬底基板1为最底层向上看，在端子100之上的各个层中，在与端子100对应的位置处形成有通孔，通孔用于暴露出端子100，以使外界的引脚能接触到端子100。
在本实施例中，通孔在衬底基板1上的正投影至少部分覆盖端子100，通孔的大小不作限定，只要能暴露出端子100即可。
制造图3所示的阵列基板的方法，可包括以下步骤：
在衬底基板1上形成缓冲层2、在缓冲层2上形成TFT晶体管5，在TFT晶体管5的有源层54中形成端子100的引线，在形成TFT晶体管5的源极电极51的层中形成多个电极板101和多个端子100；并在TFT晶体管5的上方或下方相对的位置形成遮挡层(未示出)；在形成TFT晶体管5后的衬底基板1上依次形成阳极、有机发光层9和阴极10。在形成阳极的阳极金属层7中形成与电极板101相对的多个电极板201。
图4示出了根据本公开的另一实施例的阵列基板的示意图。图4所示的阵列基板与图3所示的阵列基板的区别在于，端子100与电极板201同层设置。
在本实施例中，可在有源层54中形成多个电极板101，在阳极金属层7中形成端子100的引线，在形成阴极10的层中形成多个端子100和多个与电极板101相对的电极板201。电极板101与相对的电极板201构成一个电容结构。
端子100与电极板201交替相间布置，为了避免端子100与电极板201之间发生短路，在端子100与电极板201之间填充有绝缘材料。
穿过在阳极金属层7与该形成阴极10的层之间的各层形成过孔，端子100的引线通过过孔与端子100连接。
在本实施例中，以衬底基板1为最底层向上看，在端子100之上的各个层中，在与端子100对应的位置处形成有通孔，以暴露出端子100。
通孔在衬底基板1上的正投影至少部分覆盖端子100，通孔的大小不作限定，只要能暴露出端子100即可。
制造图4所示的阵列基板的方法，可包括以下步骤：
在衬底基板1上形成缓冲层2、在缓冲层2上形成TFT晶体管5，在形成TFT晶体管5的有源层54中形成多个电极板101；并在TFT晶体管5的上方或下方相对的位置形成遮挡层(未示出)；在形成TFT晶体管5后的衬底基板1上依次形成阳极、像素限定层8、有机发光层9和阴极10。在形成阳极的阳极金属层7中形成端子100的引线，在形成阴极10的层中形成多个端子100和多个与电极板101相对的电极板201。
本公开的实施例中的端子还可形成在电容结构的两电极板之间的导电层中。
图5示出了根据本公开的又一实施例的阵列基板的示意图。如图5所示，在本实施例中，可在有源层54中形成有多个电极板101，在形成栅极53的层中形成多个端子100和端子100的引线，在阳极金属层7中形成多个与电极板101相对的电极板201，电极板101与相对的电极板201构成电容结构。
在本实施例中，以衬底基板1为最底层向上看，在端子100之上的各 个层中，在与端子100对应的位置处形成有通孔，以暴露出端子100。
通孔在衬底基板1上的正投影至少部分覆盖端子100，通孔的大小不作限定，只要能暴露出端子100即可。
制造图5所示的阵列基板的方法，可包括以下步骤：
在衬底基板1上形成缓冲层2、在缓冲层2上形成TFT晶体管5，在形成TFT晶体管5的有源层54中形成多个电极板101；在形成栅极53的层中形成多个端子100和端子100的引线，并在TFT晶体管5的上方或下方相对的位置形成遮挡层(未示出)；在形成TFT晶体管5后的衬底基板1上依次形成阳极、像素限定层8、有机发光层9和阴极10。在形成阳极的阳极金属层7中形成多个电极板201，电极板201与电极板101相对。
以上实施例仅是示例的，电容结构的两个电极板可以在阵列基板上的任意两个可导电的层中形成。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件完成，所述程序可以存储于计算机可读存储介质中，如只读存储器、磁盘或光盘等。可选地，上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地，上述实施例中的各模块/单元可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。本公开不限制于任何特定形式的硬件和软件的结合。
以上仅为本公开的优选实施例，当然，本公开还可有其他多种实施例，在不背离本公开精神及其实质的情况下，熟悉本领域的技术人员可根据本公开作出各种相应的改变和变形，但这些相应的改变和变形都应属于本公开所附的权利要求的保护范围。

Claims (12)

  1. 一种阵列基板，包括多个端子、第一导电层和第二导电层，所述第一导电层和所述第二导电层之间包括绝缘层，其中，
    所述第一导电层和所述第二导电层中分别形成有多个第一电极板和多个第二电极板，所述第一电极板和所述第二电极板彼此相对以构成电容结构
    所述端子与所述第一导电层或与所述第二导电层同层设置，或者所述端子与所述第一导电层和所述第二导电层之间的第三导电层同层设置。
  2. 如权利要求1所述的阵列基板，其中，
    所述端子与所述第一导电层或与所述第二导电层同层设置，所述第一电极板或所述第二电极板与所述端子交替相间布置，所述端子与所述第一电极板或与所述第二电极板之间填充有绝缘材料。
  3. 如权利要求2所述的阵列基板，所述阵列基板还包括第四导电层，其中，所述端子的引线形成在所述第四导电层中，并通过过孔与所述端子连接。
  4. 如权利要求1所述的阵列基板，其中，
    所述端子与所述第一导电层和所述第二导电层之间的第三导电层同层设置，所述端子的引线形成在所述第三导电层中。
  5. 如权利要求1-4任一项所述的阵列基板，其中，
    所述端子之上的各个层在与所述端子对应的位置处形成有通孔，以暴露所述端子。
  6. 如权利要求5所述的阵列基板，其中，
    所述通孔在所述阵列基板的衬底基板上的正投影至少部分覆盖所述端子。
  7. 如权利要求6所述的阵列基板，其中，所述阵列基板包括衬底基板、缓冲层、TFT晶体管、平坦层、阳极金属层、像素限定层、有机发光层、阴极，其中，所述TFT晶体管包括源极电极、漏极电极、栅极、有源 层、栅绝缘层，其中，所述第一导电层、所述第二导电层以及所述第三导电层选自以下中的任意一层：形成所述源极电极或所述漏极电极的层、形成所述栅极的层、所述有源层、所述阳极金属层、所述有机发光层、形成所述阴极的层。
  8. 一种显示装置，包括如权利要求1-7任一项所述的阵列基板。
  9. 一种阵列基板的制造方法，包括：
    在第一导电层中形成多个第一电极板；
    在第二导电层中形成分别与所述第一电极板相对的多个第二电极板，其中，所述第一电极板和所述第二电极板构成电容结构；
    在所述第一导电层或所述第二导电层中形成多个端子，或者在所述第一导电层和所述第二导电层之间的第三导电层中形成多个端子。
  10. 如权利要求9所述的制造方法，其中，
    在所述第一导电层或所述第二导电层中形成多个端子，所述第一电极板或所述第二电极板与所述端子交替相间布置，所述端子与所述第一电极板或与所述第二电极板之间填充有绝缘材料
  11. 如权利要求8所述的制造方法，所述方法还包括：
    在第四导电层中形成所述端子的引线，所述端子的引线以过孔的方式与所述端子连接。
  12. 如权利要求9所述的制造方法，其中，在所述第一导电层和所述第二导电层之间的第三导电层中形成多个端子，还包括：
    在所述第三导电层中形成所述端子的引线。
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