CN107315293A - 一种阵列基板及其制造方法、显示装置 - Google Patents
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Abstract
一种阵列基板包括多个端子和至少包括第一导电层和第二导电层,所述第一导电层和所述第二导电层之间包括绝缘层,其中,所述第一导电层和所述第二导电层上分别形成有组成电容结构的多个第一电极板和多个第二电极板,相互平行且相对的一个第一电极板和一个第二电极板构成一个电容结构,一个所述电容结构至少对应一个所述端子,所述端子与所述第一导电层或与所述第二导电层处于同一层,或者所述端子处于所述第一导电层与所述第二导电层之间的第三导电层。一种阵列基板的制造方法和显示装置。本方案通过在端子增加电容结构,增加产品抗ESD能力,改善从端子导入引起产品损坏的不良问题,以防护端子,避免静电损伤。
Description
技术领域
本发明实施例涉及但不限于显示技术领域,尤其涉及一种阵列基板及其制造方法、显示装置。
背景技术
随着液晶显示屏的发展和应用,静电放电(Electrostatics discharge,简称ESD)问题越来越成为高端液晶显示屏的技术难题:一方面在器件制造过程中,由于其工艺特点,极易产生静电并造成产品损失;另一方面LCM(Liquid Crystal Module,液晶模块)中的IC(集成电路)等元器件及电子线路也易于受到静电冲击的干扰,在液晶器件特别是信息通讯产品上抗静电冲击已经成为必检项目。
液晶显示屏在Cell(对盒)工艺,模组工艺和信赖性有意无意都在经历ESD,产品点灯的过程中,因瞬间大电流,环境静电和设备静电的原因对Panel(面板)造成不可逆的损坏,造成产品良率影响,大大增加产品成本,同时产品存在测试过程中,经常会对产品测试端子(ET Pad)造成静电击穿,造成产品异显,色彩异常等不良。
发明内容
本发明实施例提供一种阵列基板及其制造方法、显示装置,以防护端子,避免静电损伤。
一种阵列基板,包括多个端子和至少包括第一导电层和第二导电层,所述第一导电层和所述第二导电层之间包括绝缘层,其中,
所述第一导电层和所述第二导电层上分别形成有组成电容结构的多个第一电极板和多个第二电极板,相互平行且相对的一个第一电极板和一个第二电极板构成一个电容结构,一个所述电容结构至少对应一个所述端子,
所述端子与所述第一导电层或与所述第二导电层处于同一层,或者所述端子处于所述第一导电层与所述第二导电层之间的第三导电层。
可选地,所述端子与所述第一导电层或与所述第二导电层处于同一层时,所述第一电极板或所述第二电极板与所述端子交替相间布置,所述端子与所述第一电极板或与所述第二电极板之间填充有绝缘物质。
可选地,所述端子的引线形成于第四导电层上,并通过过孔与端子连接。
可选地,所述端子处于所述第一导电层与所述第二导电层之间的第三导电层时,所述端子的引线形成于所述第三导电层上。
可选地,所述端子以上的各个层在所述端子对应的位置处形成有通孔,以暴露所述端子。
可选地,所述通孔在衬底基板上的投影涵盖所述端子,或者涵盖部分所述端子。
一种显示装置,包括上述的阵列基板。
一种阵列基板的制造方法,包括:
在第一导电层上形成构成电容结构的多个第一电极板;
在第二导电层上形成分别与所述第一电极板平行且相对的多个第二电极板;
在所述第一导电层或所述第二导电层上形成多个端子,或者在所述第一导电层与所述第二导电层之间的第三导电层上形成多个端子,一个所述电容结构至少对应一个所述端子。
可选地,在所述第一导电层或所述第二导电层上形成多个端子时,所述第一电极板或所述第二电极板与所述端子交替相间布置,所述端子与所述第一电极板或与所述第二电极板之间填充有绝缘物质。
可选地,所述方法还包括:
在第四导电层上形成所述端子的引线,所述端子的引线以过孔的方式与所述端子连接。
可选地,在所述第一导电层与所述第二导电层之间的第三导电层上形成多个端子的同时,还包括:
在所述第三导电层上形成所述端子的引线。
综上,本发明实施例的一种阵列基板及其制造方法、显示装置,本方案通过在端子增加电容结构,增加产品抗ESD能力改善从端子导入引起产品损坏的不良问题,以防护端子,避免静电损伤。
附图说明
图1为相关的阵列基板的结构的示意图。
图2本发明实施例的一种阵列基板的制造方法的流程图。
图3为本发明实施例一的阵列基板的示意图。
图4为本发明实施例二的阵列基板的示意图。
图5为本发明实施例三的阵列基板的示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白,下文中将结合附图对本发明的实施例进行详细说明。需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互任意组合。
随着液晶显示屏的发展和应用,从外挂触摸(GFF)产品到内嵌式(InCell)产品需要增加ESD能力,减少产品损伤,本公开实施例中,利用Array(阵列工艺)在端子的上下膜层增加电路走线,形成电容结构,防护端子,避免静电损伤,提升产品的良率,增加收益,提升产品ET Pad处的抗ESD能力。
本公开的方案可以在阵列基板中的任意两个导电层上形成电容结构,端子可以与电容结构的电极板在同一层导电层上形成,也可以在电容结构之间的导电层上形成。
ESD通常都是环境以及摩擦引起的,形成电容结构后,ESD优先在电容上进行放电,而不是在ET pad上进行放电。静电再通过电容释放到GND上,这个样产品就不会受到损坏。在同一层上设计的道理是一样的,如果在同一层设计时,因电容结构连接在GND,静电更容易在电容上放电而不在ET pad放电。
本公开的阵列基板,包括多个端子和至少包括第一导电层和第二导电层,所述第一导电层和所述第二导电层之间包括绝缘层,所述第一导电层和所述第二导电层上分别形成有组成电容结构的多个第一电极板和多个第二电极板,相互平行且相对的一个第一电极板和一个第二电极板构成一个电容结构,一个所述电容结构至少对应一个所述端子,
所述端子与所述第一导电层或与所述第二导电层处于同一层,或者所述端子处于所述第一导电层与所述第二导电层之间的第三导电层。
如图1所示,阵列基板一般包括:衬底基板1、缓冲层2、TFT开关5、源极51、漏极52、栅极53、有源层54、栅绝缘层55、栅隔离层56、平坦层6、阳极金属层7、在阳极金属层上形成阳极和遮挡层、像素电极层8、有机发光层9、阴极10。当然对于不同的阵列基板,不局限于上述的结构。
本公开中提到的导电层可以是以下的任意层:形成源极51的层、形成漏极52的层、形成栅极53的层、有源层54、阳极金属层7、像素电极层8、有机发光层9、形成阴极10的层。
本公开还提供一种阵列基板的制造方法,如图2所示,可以包括以下步骤:
步骤S201、在第一导电层上形成构成电容结构的多个第一电极板;
步骤S202、在第二导电层上形成分别与所述第一电极板平行且相对的多个第二电极板;
步骤S203、在所述第一导电层或所述第二导电层上形成多个端子,或者在所述第一导电层与所述第二导电层之间的第三导电层上形成多个端子,一个所述电容结构至少对应一个所述端子。
上述制造方法的步骤不限定执行的先后顺序。
以下以实施例对本公开的阵列基板进行详细的说明。
实施例一
图3为本发明实施例的阵列基板的示意图,如图3所示,本实施例中,端子100与组成电容结构的电极板101在同一层形成,例如在形成源极51的层上形成端子100和电极板101。端子100与电极板101交替相间布置,为了避免端子100与电极板101之间发生短路,在端子100与电极板101之间填充有绝缘物质。
在阳极金属层7上形成电极板102,电极板102与电极板101平行且相对,构成电容结构。
本实施例中,端子100的引线在其它的导电层上形成,可以避免端子100的引线与电容结构发生短路。例如,在有源层54形成端子100的引线,在有源层54与形成源极51的层之间的各层上形成有过孔,端子100的引线通过过孔与端子100连接。
本实施例中,以衬底基板1为最底层向上看,在端子100以上的各个层中,在端子100对应的位置处形成有通孔,通孔用于暴露出端子100,使外界的引脚能接触到端子100。
通孔在衬底基板1上的投影涵盖端子100,或者涵盖部分端子100,通孔的大小不作限定,只要能暴露出端子100即可。
制作本实施例的阵列基板的方法,包括以下步骤:
在衬底基板1上形成缓冲层2、在缓冲层2上形成TFT开关5,在有源层54形成端子100的引线,在形成TFT开关5的源极51的层上形成多个电极板101和多个端子100;并在TFT开关5的上方或下方相对的位置形成遮挡层;在形成TFT开关5后的衬底基板1上依次形成阳极、有机发光层9和阴极10。在形成阳极的阳极金属层7上形成与电极板101平行的多个电极板102。
实施例二
本实施例与实施例一的区别在于,端子100与电极板102在同一层形成,如图4所示。
本实施例中,在有源层54上形成有多个电极板101,在阳极金属层7上形成端子100的引线,在像素电极层8上形成多个端子100和多个与电极板101平行且相对的电极板102,一个电极板101与一个平等且相对电极板102组成一个电容结构。
端子100与电极板102交替相间布置,为了避免端子100与电极板102之间发生短路,在端子100与电极板102之间填充有绝缘物质。
在阳极金属层7与像素电极层8之间的各层上形成有过孔,端子100的引线通过过孔与端子100连接。
本实施例中,以衬底基板1为最底层向上看,在端子100以上的各个层中,在端子100对应的位置处形成有通孔,以暴露出端子100。
通孔在衬底基板1上的投影涵盖端子100,或者涵盖部分端子100,通孔的大小不作限定,只要能暴露出端子100即可。
制作本实施例的阵列基板的方法,包括以下步骤:
在衬底基板1上形成缓冲层2、在缓冲层2上形成TFT开关5,在形成TFT开关5的有源层54上形成多个电极板101;并在TFT开关5的上方或下方相对的位置形成遮挡层;在形成TFT开关5后的衬底基板1上依次形成阳极、像素电极层8、有机发光层9和阴极10。在形成阳极的阳极金属层7上形成端子100的引线,在像素电极层8上形成多个端子100和多个与电极板101平行且相对的电极板102。
实施例三
本实施例中的端子形成在电容结构的两电极板之间的导电层上。
如图5所示,本实施例中,在有源层54上形成有多个电极板101,在形成栅极53的层上形成多个端子100和端子100的引线,在阳极金属层7上形成多个与电极板101平行且相对的电极板102,一个电极板101与一个平行且相对的电极板102组成电容结构。
本实施例中,以衬底基板1为最底层向上看,在端子100以上的各个层中,在端子100对应的位置处形成有通孔,以暴露出端子100。
通孔在衬底基板1上的投影涵盖端子100,或者涵盖部分端子100,通孔的大小不作限定,只要能暴露出端子100即可。
制作本实施例的阵列基板的方法,包括以下步骤:
在衬底基板1上形成缓冲层2、在缓冲层2上形成TFT开关5,在形成TFT开关5的有源层54上形成多个电极板101;在形成栅极53的层上形成多个端子100和端子100的引线,并在TFT开关5的上方或下方相对的位置形成遮挡层;在形成TFT开关5后的衬底基板1上依次形成阳极、像素电极层8、有机发光层9和阴极10。在形成阳极的阳极金属层7上形成多个电极板102,电极板102与电极板101平行。
以上实施例仅是示例的,电容结构的两个电极板可以在阵列基板上的任意两个可导电的层上形成。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件完成,所述程序可以存储于计算机可读存储介质中,如只读存储器、磁盘或光盘等。可选地,上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地,上述实施例中的各模块/单元可以采用硬件的形式实现,也可以采用软件功能模块的形式实现。本发明不限制于任何特定形式的硬件和软件的结合。
以上仅为本发明的优选实施例,当然,本发明还可有其他多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
Claims (11)
1.一种阵列基板,包括多个端子和至少包括第一导电层和第二导电层,所述第一导电层和所述第二导电层之间包括绝缘层,其特征在于,
所述第一导电层和所述第二导电层上分别形成有组成电容结构的多个第一电极板和多个第二电极板,相互平行且相对的一个第一电极板和一个第二电极板构成一个电容结构,一个所述电容结构至少对应一个所述端子,
所述端子与所述第一导电层或与所述第二导电层处于同一层,或者所述端子处于所述第一导电层与所述第二导电层之间的第三导电层。
2.如权利要求1所述的阵列基板,其特征在于:
所述端子与所述第一导电层或与所述第二导电层处于同一层时,所述第一电极板或所述第二电极板与所述端子交替相间布置,所述端子与所述第一电极板或与所述第二电极板之间填充有绝缘物质。
3.如权利要求2所述的阵列基板,其特征在于:
所述端子的引线形成于第四导电层上,并通过过孔与端子连接。
4.如权利要求1所述的阵列基板,其特征在于:
所述端子处于所述第一导电层与所述第二导电层之间的第三导电层时,所述端子的引线形成于所述第三导电层上。
5.如权利要求1-4任一项所述的阵列基板,其特征在于:
所述端子以上的各个层在所述端子对应的位置处形成有通孔,以暴露所述端子。
6.如权利要求5所述的阵列基板,其特征在于:
所述通孔在衬底基板上的投影涵盖所述端子,或者涵盖部分所述端子。
7.一种显示装置,包括如权利要求1-6任一项所述的阵列基板。
8.一种阵列基板的制造方法,包括:
在第一导电层上形成构成电容结构的多个第一电极板;
在第二导电层上形成分别与所述第一电极板平行且相对的多个第二电极板;
在所述第一导电层或所述第二导电层上形成多个端子,或者在所述第一导电层与所述第二导电层之间的第三导电层上形成多个端子,一个所述电容结构至少对应一个所述端子。
9.如权利要求8所述的制造方法,其特征在于:
在所述第一导电层或所述第二导电层上形成多个端子时,所述第一电极板或所述第二电极板与所述端子交替相间布置,所述端子与所述第一电极板或与所述第二电极板之间填充有绝缘物质。
10.如权利要求9所述的制造方法,其特征在于:所述方法还包括:
在第四导电层上形成所述端子的引线,所述端子的引线以过孔的方式与所述端子连接。
11.如权利要求8所述的制造方法,其特征在于:在所述第一导电层与所述第二导电层之间的第三导电层上形成多个端子的同时,还包括:
在所述第三导电层上形成所述端子的引线。
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