WO2017045367A1 - 一种阵列基板、显示面板及显示装置 - Google Patents
一种阵列基板、显示面板及显示装置 Download PDFInfo
- Publication number
- WO2017045367A1 WO2017045367A1 PCT/CN2016/074394 CN2016074394W WO2017045367A1 WO 2017045367 A1 WO2017045367 A1 WO 2017045367A1 CN 2016074394 W CN2016074394 W CN 2016074394W WO 2017045367 A1 WO2017045367 A1 WO 2017045367A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- conductive pattern
- conductive
- array substrate
- conductive line
- line segment
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 238000002161 passivation Methods 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/04—Display protection
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
Definitions
- the first conductive line segment is formed by using a transparent conductive layer.
- 4A is a schematic diagram showing a manner in which a conductive pattern of a related art is disposed on an array substrate;
- the second conductive pattern is made of a source/drain metal layer.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
Claims (12)
- 一种阵列基板,包括组成接地点保护电路的第一导电图形和第二导电图形,所述第一导电图形包括多个间隔设置的第一导电线段,相邻第一导电线段之间通过所述第二导电图形相连接,所述第一导电线段与所述第二导电图形之间设置有绝缘层,所述第一导电线段和所述第二导电图形通过贯穿所述绝缘层的过孔连接。
- 根据权利要求1所述的阵列基板,其中,所述第一导电线段采用透明导电层形成。
- 根据权利要求1所述的阵列基板,其中,所述第二导电图形采用源漏金属层或栅金属层形成。
- 根据权利要求1所述的阵列基板,其中,所述第二导电图形包括多个间隔设置的第二导电线段,所述第二导电线段对应相邻第一导电线段之间的间隙设置。
- 根据权利要求1所述的阵列基板,其中,所述第一导电线段的宽度与所述第二导电图形的宽度不同。
- 根据权利要求5所述的阵列基板,其中,所述第二导图形的宽度为所述第一导电线段宽度的一半。
- 根据权利要求1所述的阵列基板,其中,所述第一导电线段的长度大于所述第一导电线段之间间隙的长度。
- 根据权利要求1所述的阵列基板,其中,所述第二导电图形与阵列基板的衬底基板接触或与所述衬底基板间隔设置;所述第一导电图形与所述绝缘层接触,设置于所述第二导电图形远离所述衬底基板一侧。
- 根据权利要求7所述的阵列基板,其中,所述第一导电线段的长度是所述第一导电线段之间间隙的长度的两倍。
- 根据权利要求1所述的阵列基板,其中,所述绝缘层为钝化层。
- 一种显示面板,包括权利要求1-10中任意一项所述的阵列基板。
- 一种显示装置,包括权利要求1-10中任意一项所述的阵列基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/325,264 US10199400B2 (en) | 2015-09-15 | 2016-02-24 | Array substrate, display panel and display device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510587769.2 | 2015-09-15 | ||
CN201510587769.2A CN105097847B (zh) | 2015-09-15 | 2015-09-15 | 一种阵列基板、显示面板及显示装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2017045367A1 true WO2017045367A1 (zh) | 2017-03-23 |
Family
ID=54577912
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2016/074394 WO2017045367A1 (zh) | 2015-09-15 | 2016-02-24 | 一种阵列基板、显示面板及显示装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10199400B2 (zh) |
CN (1) | CN105097847B (zh) |
WO (1) | WO2017045367A1 (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105097847B (zh) * | 2015-09-15 | 2018-10-23 | 京东方科技集团股份有限公司 | 一种阵列基板、显示面板及显示装置 |
CN106405959B (zh) * | 2016-10-13 | 2019-09-27 | 武汉华星光电技术有限公司 | 一种液晶面板的静电防护结构 |
CN106653746B (zh) * | 2016-12-15 | 2019-09-06 | 武汉华星光电技术有限公司 | 一种阵列基板和显示装置 |
CN108091679B (zh) * | 2017-12-27 | 2020-09-18 | 武汉华星光电半导体显示技术有限公司 | 柔性oled显示面板弯折区的走线结构、柔性oled显示面板 |
CN109148487B (zh) * | 2018-08-30 | 2021-02-05 | 上海天马微电子有限公司 | 一种显示面板 |
CN110379347B (zh) * | 2019-07-25 | 2023-01-24 | 云谷(固安)科技有限公司 | 屏体虚设器件检测方法和装置 |
CN111857446B (zh) * | 2020-07-13 | 2021-09-24 | Tcl华星光电技术有限公司 | 掩膜板、显示面板及其制备方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6891258B1 (en) * | 2002-12-06 | 2005-05-10 | Xilinx, Inc. | Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit |
CN102376723A (zh) * | 2010-08-20 | 2012-03-14 | 三星电子株式会社 | 传感器阵列基板及其制造方法以及包括其的显示装置 |
CN202886795U (zh) * | 2012-11-14 | 2013-04-17 | 京东方科技集团股份有限公司 | 一种阵列基板的外围电路、阵列基板及显示装置 |
CN103091922A (zh) * | 2013-01-29 | 2013-05-08 | 北京京东方光电科技有限公司 | 一种阵列基板、显示面板及装置 |
CN103441119A (zh) * | 2013-07-05 | 2013-12-11 | 京东方科技集团股份有限公司 | 一种制造esd器件的方法、esd器件和显示面板 |
CN105097847A (zh) * | 2015-09-15 | 2015-11-25 | 京东方科技集团股份有限公司 | 一种阵列基板、显示面板及显示装置 |
CN204905256U (zh) * | 2015-09-15 | 2015-12-23 | 京东方科技集团股份有限公司 | 一种阵列基板、显示面板及显示装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007328922A (ja) | 2006-06-06 | 2007-12-20 | Sharp Corp | 電子機器 |
CN101231398A (zh) * | 2007-01-24 | 2008-07-30 | 胜华科技股份有限公司 | 具静电抑制措施的液晶面板 |
US8431832B2 (en) * | 2007-11-28 | 2013-04-30 | Kyocera Corporation | Circuit board, mounting structure, and method for manufacturing circuit board |
TWI471642B (zh) * | 2010-09-24 | 2015-02-01 | Wintek Corp | Touch panel structure and its touch display panel |
CN103296021B (zh) * | 2012-06-29 | 2016-12-07 | 上海天马微电子有限公司 | Tft阵列基板 |
US10033093B2 (en) * | 2013-12-27 | 2018-07-24 | Intel Corporation | mmWave antennas and transmission lines on standard substrate materials |
-
2015
- 2015-09-15 CN CN201510587769.2A patent/CN105097847B/zh active Active
-
2016
- 2016-02-24 WO PCT/CN2016/074394 patent/WO2017045367A1/zh active Application Filing
- 2016-02-24 US US15/325,264 patent/US10199400B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6891258B1 (en) * | 2002-12-06 | 2005-05-10 | Xilinx, Inc. | Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit |
CN102376723A (zh) * | 2010-08-20 | 2012-03-14 | 三星电子株式会社 | 传感器阵列基板及其制造方法以及包括其的显示装置 |
CN202886795U (zh) * | 2012-11-14 | 2013-04-17 | 京东方科技集团股份有限公司 | 一种阵列基板的外围电路、阵列基板及显示装置 |
CN103091922A (zh) * | 2013-01-29 | 2013-05-08 | 北京京东方光电科技有限公司 | 一种阵列基板、显示面板及装置 |
CN103441119A (zh) * | 2013-07-05 | 2013-12-11 | 京东方科技集团股份有限公司 | 一种制造esd器件的方法、esd器件和显示面板 |
CN105097847A (zh) * | 2015-09-15 | 2015-11-25 | 京东方科技集团股份有限公司 | 一种阵列基板、显示面板及显示装置 |
CN204905256U (zh) * | 2015-09-15 | 2015-12-23 | 京东方科技集团股份有限公司 | 一种阵列基板、显示面板及显示装置 |
Also Published As
Publication number | Publication date |
---|---|
US10199400B2 (en) | 2019-02-05 |
US20180219030A1 (en) | 2018-08-02 |
CN105097847B (zh) | 2018-10-23 |
CN105097847A (zh) | 2015-11-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2017045367A1 (zh) | 一种阵列基板、显示面板及显示装置 | |
US9046950B1 (en) | Touch display panel with electrostatic protection unit | |
US20160306212A1 (en) | Display device | |
WO2018126669A1 (zh) | 静电保护电路、阵列基板、显示面板及显示装置 | |
KR101945651B1 (ko) | 디스플레이 및 터치 제어 기능을 구비하는 패널 | |
US10921660B2 (en) | Circuit board, display panel and display device | |
WO2017156874A1 (zh) | 静电放电电路、具有静电放电电路的显示面板和静电放电方法 | |
EP3333624B1 (en) | Electrical connection structure, array substrate and display device | |
WO2016201741A1 (zh) | 走线结构及阵列基板 | |
TWI450163B (zh) | 觸控面板 | |
KR101842537B1 (ko) | 액정 표시 장치 및 액정 표시 장치의 어레이 기판 | |
US9891751B2 (en) | Touch control device and method, and method for forming touch control device | |
KR102524346B1 (ko) | 표시 장치 및 표시 장치 제조 방법 | |
US11410596B2 (en) | Display device preventing a flow of static electricity | |
CN110707065B (zh) | 阵列基板及显示面板 | |
JP6168927B2 (ja) | 表示装置 | |
WO2018214645A1 (zh) | 一种阵列基板及其制造方法、显示装置 | |
CN204905256U (zh) | 一种阵列基板、显示面板及显示装置 | |
US10757848B2 (en) | Display device and manufacturing method thereof | |
US10593706B2 (en) | Array substrate assembly, method of manufacturing array substrate assembly, display panel and display apparatus | |
US20130168147A1 (en) | Electronic device | |
KR102200800B1 (ko) | 액정표시장치 | |
US10026355B1 (en) | Display device and peripheral circuit structure thereof | |
KR101816666B1 (ko) | 전극 접속부 및 이를 포함하는 전기 소자 | |
TWI386720B (zh) | 液晶顯示面板及其製程 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 15325264 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 16845483 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 16845483 Country of ref document: EP Kind code of ref document: A1 |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 24.08.2018) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 16845483 Country of ref document: EP Kind code of ref document: A1 |