WO2020238722A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2020238722A1
WO2020238722A1 PCT/CN2020/091280 CN2020091280W WO2020238722A1 WO 2020238722 A1 WO2020238722 A1 WO 2020238722A1 CN 2020091280 W CN2020091280 W CN 2020091280W WO 2020238722 A1 WO2020238722 A1 WO 2020238722A1
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WIPO (PCT)
Prior art keywords
antistatic
electrode
resistor
display substrate
layer
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PCT/CN2020/091280
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English (en)
French (fr)
Inventor
程鸿飞
李会
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/280,896 priority Critical patent/US11662631B2/en
Publication of WO2020238722A1 publication Critical patent/WO2020238722A1/zh
Priority to US18/129,252 priority patent/US11906859B2/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • the display substrate (for example, an OLED display substrate or a liquid crystal display substrate) is generally divided into a display area and a non-display area surrounding the outer boundary of the display area.
  • a plurality of sub-pixels are arranged in the display area, and each sub-pixel includes one or more transistors.
  • multiple gate lines extending in the row direction and multiple data lines extending in the column direction are also provided in the display substrate.
  • An aspect of the present disclosure provides a display substrate, the display substrate comprising: a base; a transistor on the base, an antistatic wire, a first antistatic resistor, and a first grounding bonding pad, wherein the first The first end of the antistatic resistor is electrically connected to the first end of the antistatic wire, the second end of the first antistatic resistor is electrically connected to the first grounding binding pad, and the first antistatic resistor is electrically connected to the first end of the antistatic wire.
  • the electrostatic resistance is located on a layer different from the layer where the antistatic wire is located and the layer where the first grounding bonding pad is located, and is located on the same layer as the active layer of the transistor.
  • the display substrate further includes: a second antistatic resistor and a second grounding binding pad, and the first end of the second antistatic resistor is electrically connected to the second antistatic wire. The second end of the second antistatic resistor is electrically connected to the second binding pad.
  • the display substrate further includes: an anti-static electrode and a common electrode binding pad configured to receive a common voltage, and the orthographic projection of the anti-static electrode on the substrate is consistent with the first anti-static electrode.
  • the orthographic projection of the electrostatic resistor on the substrate overlaps, the antistatic electrode and the first antistatic resistor are insulated from each other in the thickness direction of the display substrate, and the antistatic electrode is electrically connected to the The common electrode binding pad.
  • the display substrate is divided into a display area and a non-display area surrounding the boundary of the display area, the display area includes a transistor, and the non-display area includes the antistatic wire, the The first antistatic resistor, the antistatic electrode, and a plurality of binding pads, wherein the plurality of binding pads at least include the first grounding binding pad and the common electrode binding pad .
  • the anti-static wire surrounds the boundary of the display area excluding the boundary opposite to the area where the plurality of binding pads are provided.
  • the display substrate further includes a signal line, and the anti-static wire and at least a part of the signal line are provided in the same layer.
  • the signal line includes at least one of a gate line, a data line, a ground line, and a common electrode line.
  • the transistor includes: an active layer, a gate insulating layer covering the active layer, a gate provided on the side of the gate insulating layer facing away from the substrate, and covering the gate
  • the interlayer dielectric layer, the source and drain provided on the side of the interlayer dielectric layer facing away from the substrate, the source and the drain respectively pass through the interlayer insulating layer and the gate
  • the via hole of the insulating layer is connected to the active layer.
  • the first anti-static resistor is disposed between the substrate and the gate insulating layer, and the first end of the first anti-static resistor passes through the first pass through the gate insulating layer.
  • the hole is electrically connected to the first end of the anti-static wire, and the second end of the first anti-static resistor is electrically connected to the first grounding bonding pad through a second via hole penetrating the gate insulating layer.
  • the shape of the display area is a rectangle
  • the anti-static wire is arranged along three sides of the rectangle
  • the first anti-static resistor is arranged along the remaining one side of the rectangle.
  • At least part of the projection of the first antistatic resistor on the substrate is a first square waveform
  • at least a part of the projection of the antistatic electrode on the substrate is a second square waveform, so The directions of the first square waveform and the second square waveform are different.
  • the transistor further includes a passivation layer covering the source electrode and the drain electrode, and a pixel electrode provided on the side of the passivation layer facing away from the substrate and At least one of the common electrodes on the side of the passivation layer facing away from the substrate.
  • the antistatic electrode is disposed on the passivation layer, and the antistatic electrode is electrically connected to the passivation layer and the interlayer dielectric layer through a third via hole.
  • the common electrode binding pad is disposed on the passivation layer, and the antistatic electrode is electrically connected to the passivation layer and the interlayer dielectric layer through a third via hole.
  • the anti-static electrode is provided in the same layer as at least one of the pixel electrode and the common electrode.
  • the first antistatic resistor is formed of doped polysilicon.
  • the anti-static electrode is formed of indium tin oxide.
  • Another aspect of the present disclosure provides a display device including the display substrate as described above.
  • FIG. 1 is a top perspective view of a partial structure of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view of the display substrate shown in FIG. 1 along line AA;
  • FIG. 3 is a top perspective view of a partial structure of a display substrate according to another embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of the display substrate shown in FIG. 3 along line BB.
  • the "same layer” of two structures means that they are formed of the same material at the same time, so they are in the same layer in the stacking relationship, but it does not mean that the distance between them and the substrate is equal, nor does it mean that they It is exactly the same as the other layer structure between the substrates.
  • two structures "located on different layers” means that the two structures are in different layers in a stacking relationship.
  • the display substrate may generally include an array substrate. Static electricity is easy to accumulate during the manufacturing process of the display substrate, and the static electricity is likely to cause damage to the display device. Generally, a part of the non-display area of the display substrate is used to achieve bonding with a structure such as a flexible circuit board. Exposed electrodes are arranged in these areas, and these exposed electrodes (also called bonding pads or bonding pads) are electrically connected to peripheral structures such as graphics processors and mobile phone motherboards through flexible circuit boards. These exposed electrodes usually contain grounded binding pads, which are usually used to connect to the casing or the earth of mobile phones, televisions, etc. Their ground potential is relatively more stable.
  • FIG. 1 is a top perspective view of a partial structure of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view of the display substrate shown in FIG. 1 along the line AA.
  • a display substrate includes a base 10 and a plurality of transistors 11 provided on the base 10.
  • the transistor 11 includes an active layer 11a.
  • the base 10 includes a display area S1 and a non-display area S2 surrounding the outer boundary of the display area S1.
  • the non-display area S2 is divided into a binding area and a non-binding area.
  • the display substrate also includes a plurality of binding pads. The orthographic projections of the pads on the substrate 10 are at least partially located in the binding area.
  • the plurality of binding pads include at least one grounded binding pad 12a.
  • the display substrate further includes an anti-static wire 13, which is the same as the active layer 11a.
  • the first end of the antistatic resistor 14 is electrically connected to the antistatic wire 13 through the first through hole H1, and the second end is electrically connected to the ground binding pad 12a through the second through hole H2,
  • the orthographic projection of the antistatic wire 13 and the antistatic resistor 14 on the substrate 10 is located in the non-display area S2 and at least surrounds the boundary of the display area S1 excluding the boundary opposite to the binding area.
  • one sub-pixel corresponds to one or more transistors 11.
  • the sub-pixels can be arranged in an array.
  • a transistor 11 is used to characterize the location of a sub-pixel.
  • the transistor 11 can be a top-gate thin film transistor 11 or a bottom-gate thin film transistor 11.
  • the above two types are both horizontal thin film transistors 11, and of course can also be vertical thin film transistors 11. This embodiment does not limit this.
  • the transistor 11 is a top-gate thin film transistor 11 as an example.
  • a transistor 11 and a data line D and a gate line G connected to the transistor are provided in the display area S1, and other circuit structures are provided in the non-display area S2, such as an antistatic wire 13, an antistatic resistor 14. Wait.
  • the non-display area S2 refers to the portion of the display substrate outside the outer boundary of the display area S1.
  • the boundary between the display area S1 and the non-display area S2 includes the boundary of a part of the sub-pixels.
  • the boundary of the sub-pixel may be the boundary of the pixel electrode in the sub-pixel, or the boundary of the outermost transistor 11 in the sub-pixel. No matter how defined, the display area S1 and the non-display area S2 of the display substrate have meanings commonly understood by those skilled in the art.
  • a part of the non-display area S2 of the display substrate is provided with a bonding pad.
  • the function of the binding pad is to combine with components such as a flexible circuit board through anisotropic conductive adhesive (ACF) to receive various electrical signals from the flexible circuit board.
  • ACF anisotropic conductive adhesive
  • the binding area is usually located in an area of the non-display area S2 on one side of the display substrate.
  • the binding area may be an area of the non-display area S2 corresponding to a circular arc on the periphery of the display substrate.
  • the plurality of binding pads include at least one grounding binding pad 12a, which is a binding pad for connecting with the ground of the whole machine such as a mobile phone casing.
  • the grounding bonding pad 12a can also be connected to the earth in the end. This depends on the connection method of the display device including the display substrate.
  • the bonding pad may also include a bonding pad for connecting with the data voltage output terminal of the driving chip (not shown), and a power supply for connecting with the power voltage terminal of the main board (not shown). Padding and so on. I won't repeat them here.
  • the antistatic resistor 14 may be simultaneously formed in the step of forming the active layer 11a of the transistor 11. In the manufacturing process of the display substrate, there is no need to increase the number of masks for this purpose.
  • the anti-static resistor 14 and the anti-static wire 13 and the grounding binding pad 12a are usually located in different layer structures, and the distances from the substrate 10 are different. Therefore, the first via H1 and the second via H2 are required to correspond to them. connected together.
  • the anti-static wire 13 is connected to the ground of the whole machine through an anti-static resistor 14.
  • the antistatic wire 13 and the antistatic resistor 14 enclose most of the outer boundary of the display area S1 as a whole.
  • the anti-static resistor 14 can cause certain consumption of static electricity and prevent electrostatic charges from entering the display area S1.
  • the static electricity can be dispersed to the ground along the anti-static wire 13 through the anti-static resistor 14. On this path, electrostatic charges will also be consumed.
  • the display substrate further includes a plurality of signal lines, and the anti-static wire 13 is provided in the same layer as at least part of the structure of at least part of the signal lines.
  • the signal lines are, for example, gate lines G, data lines D, ground lines (not shown), common electrode lines (not shown), and the like.
  • each data line D corresponds to a column of sub-pixels. Only one of the data lines D is shown in the figure.
  • the ground wire is connected to the ground potential, which is usually the potential of a case such as a mobile phone or a computer.
  • the common electrode line is used to provide a common electrode. In a liquid crystal display, the voltage difference between the potential of the common electrode and the data voltage written to the sub-pixel on the data line D determines the inversion state of the liquid crystal molecules, which in turn determines The brightness of the sub-pixel.
  • the antistatic wire 13 can be manufactured at the same time as a certain segment of the signal line.
  • the antistatic wire 13 is provided in the same layer as the gate line G and the gate 11c.
  • those skilled in the art can also arrange the anti-static wire 13 and the data line D in the same layer, and so on.
  • the transistor 11 further includes a gate insulating layer 11b covering the active layer 11a, a gate 11c disposed on the side of the gate insulating layer 11b facing away from the substrate 10, an interlayer dielectric layer 11d covering the gate 11c, and The source 11e and the drain 11f on the side of the interlayer dielectric layer 11d facing away from the substrate 10, and the source 11e and the drain 11f are respectively connected to the active layer 11a through vias penetrating the interlayer dielectric layer 11d and the gate insulating layer 11b;
  • the anti-static wire 13, at least a part of the gate line G, and the gate 11c are provided in the same layer; the first via H1 penetrates the gate insulating layer 11b, and the second via H2 penetrates the gate insulating layer 11b.
  • the gate 11c and the data line D may be made of a metal material such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), tungsten (W), etc. Or can be made of alloys including these metal materials.
  • the gate electrode 11c and the data line D may have a single-layer structure or a multi-layer structure, for example, a multi-layer structure formed of Mo, Al, Mo, a multi-layer structure formed of Ti, Cu, Ti, or a multi-layer structure formed of MoTi, Cu. Layer structure.
  • the gate insulating layer 11b and the interlayer dielectric layer 11d may be made of silicon nitride or silicon oxide, respectively.
  • the gate insulating layer 11b and the interlayer dielectric layer 11d may respectively have a single-layer structure or a multi-layer structure, for example, a multi-layer structure formed of silicon oxide and silicon nitride.
  • the display substrate includes two anti-static resistors 14 and at least two grounded binding pads 12a. Two ends of one of the anti-static resistors 14 are electrically connected to one end of the anti-static wire 13 and Two ends of one of the grounding binding pads 12a and the other antistatic resistor 14 are respectively electrically connected to the other end of the antistatic wire 13 and the other grounding binding pad 12a.
  • both ends of the antistatic wire 13 are connected to the antistatic resistor 14. Static electricity can be consumed at both ends of the anti-static wire 13.
  • only one end of the antistatic wire 13 is connected to the antistatic resistor 14.
  • the end of the anti-static wire 13 that is not connected to the anti-static resistor 14 can be connected or not connected to the grounding binding pad 12a.
  • FIG. 3 shows the anti-static wire 13 that is not connected to the anti-static resistor 14 The grounding bonding pad 12a is not connected to the end of the
  • the shape of the display area S1 is a rectangle
  • the orthographic projection of the anti-static wire 13 on the substrate 10 is opposite to three sides of the rectangle
  • the anti-static resistor 14 is opposite to the other side of the rectangle. This setting is to protect as many areas as possible on the outer boundary of the display area S1.
  • At least part of the projection of the antistatic resistor 14 on the substrate 10 may have a square waveform. This is to increase the resistance value of the anti-static resistor 14, of course, the shape of the anti-static resistor 14 is not limited to this.
  • the patterns of the antistatic resistor 14 and the active layer 11a may be formed of polysilicon, and the patterns of the antistatic resistor 14 may be doped to form an antistatic resistor, that is, the antistatic resistor 14 may be doped with polysilicon. form.
  • FIG. 3 is a top perspective view of a partial structure of a display substrate according to another embodiment of the present disclosure
  • FIG. 4 is a cross-sectional view of the display substrate shown in FIG. 3 along the line BB.
  • FIGS. 3 and 4 will not be repeated.
  • the display substrate may further include an anti-static electrode 15.
  • the anti-static electrode 15 on the base 10 and the anti-static resistor 14 on the base 10 overlap, and the anti-static electrode 15 and The anti-static resistor 14 is separated by an insulating layer, the plurality of binding pads further include a common electrode binding pad 12b, and the anti-static electrode 15 and the common electrode binding pad 12b are electrically connected through a third via H3.
  • a capacitance can be formed at the intersection of the antistatic electrode 15 and the antistatic resistor 14. Since one end of the capacitor is connected to the ground and the other end is connected to the common electrode binding pad 12b (connected to the common voltage), the potentials at both ends are relatively stable. Therefore, the capacitance effect can better absorb part of the electrostatic charge, and further reduce the damage to the display substrate. In addition, a parallel structure of resistance and capacitance is formed between the anti-static wire 13 and the binding pad, thereby enhancing the resistance to external static electricity.
  • At least part of the projection of the anti-static electrode 15 on the substrate 10 may have a square waveform.
  • the orthographic projection of the antistatic electrode 15 on the substrate 10 can also be in other shapes such as a straight line or a curve.
  • the orientation of the square waveform corresponding to the antistatic electrode 15 is different from the orientation of the square waveform corresponding to the antistatic resistor 14.
  • multiple resistors and multiple capacitors can be alternately formed.
  • the square wave shape of the antistatic electrode 15 is horizontal, and the square wave shape of the antistatic resistor 14 is vertical.
  • the transistor 11 further includes a gate insulating layer 11b covering the active layer 11a, a gate 11c disposed on the side of the gate insulating layer 11b facing away from the substrate 10, and a layer covering the gate 11c
  • the display substrate further includes a passivation layer 16 covering the source electrode 11e and the drain electrode 11f, and a pixel electrode (not shown) provided on the side of the passivation layer 16 facing away from the substrate 10 and/or A common electrode (not shown) arranged on the side of the passivation layer 16 facing away from the substrate 10; the pixel electrode and the antistatic electrode 15 are arranged on the same
  • a mask is used to process the same material layer, so that the pixel electrode and the antistatic electrode 15 are formed on the passivation layer 16 at the same time, or on the passivation layer 16
  • the common electrode and the anti-static electrode 15 are formed at the same time.
  • the three can all set relationships at the same level.
  • the third via hole H3 penetrates the passivation layer 16 and the interlayer dielectric layer 11d to connect the antistatic electrode 15 with the common electrode binding pad 12b under the interlayer dielectric layer 11d.
  • the passivation layer 16 may be formed of silicon nitride or silicon oxide, and may have a single-layer structure or a multilayer structure, for example, a multilayer structure formed of silicon oxide and silicon nitride.
  • each bonding pad is formed on the side of the gate insulating layer 11b facing away from the substrate 10, but the layer structure of the bonding pad is not limited to this.
  • the anti-static electrode 15 may be formed of indium tin oxide (ITO).
  • the present disclosure also provides a display device, which includes the display substrate as described above.
  • the display device can be a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • OLED organic light-emitting diode

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Abstract

提供一种显示基板和显示装置。该显示基板包括：基底（10）；基底（10）上的晶体管（11）、防静电导线（13）、第一防静电电阻（14）和第一接地绑定衬垫（12a），其中，第一防静电电阻（14）的第一端电连接至防静电导线（13）的第一端，第一防静电电阻（14）的第二端电连接至第一接地绑定衬垫（12a），并且第一防静电电阻（14）位于与防静电导线（13）所在层和第一接地绑定衬垫（12a）所在层不同的层，并且与晶体管（11）的有源层同层设置。基底（10）上还可包括防静电电极（15）和接收公共电压的公共电极绑定衬垫（12b），防静电电极（15）在基底（10）上的正投影与第一防静电电阻（14）在基底（10）上的正投影存在交叠。

Description

显示基板和显示装置
相关申请的交叉引用
本申请要求于2019年5月31日提交至中国知识产权局的中国专利申请No.201920813461.9的优先权，所述申请的内容通过引用其全部合并于此。
技术领域
本公开涉及显示技术领域，具体涉及一种显示基板和一种显示装置。
背景技术
显示基板(例如，OLED显示基板或液晶显示基板)通常划分为显示区和包围显示区外边界的非显示区。在显示区内设置多个亚像素，每个亚像素包含一个或多个晶体管。通常在显示基板内还会设置沿行方向延伸的多条栅线以及沿列方向延伸的多条数据线。
发明内容
本公开的一方面提供一种显示基板，所述显示基板包括：基底；所述基底上的晶体管、防静电导线、第一防静电电阻和第一接地绑定衬垫，其中，所述第一防静电电阻的第一端电连接至所述防静电导线的第一端，所述第一防静电电阻的第二端电连接至所述第一接地绑定衬垫，并且所述第一防静电电阻位于与所述防静电导线所在层和所述第一接地绑定衬垫所在层不同的层，并且与所述晶体管的有源层同层设置。
根据本公开的实施例，所述显示基板还包括：第二防静电电阻和第二接地绑定衬垫，所述第二防静电电阻的第一端电连接至所述防静电导线的第二端，所述第二防静电电阻的第二端电连接至所述第二绑定衬垫。
根据本公开的实施例，所述显示基板还包括：防静电电极和构 造为接收公共电压的公共电极绑定衬垫，所述防静电电极在所述基底上的正投影与所述第一防静电电阻在所述基底上的正投影存在交叠，所述防静电电极和所述第一防静电电阻在所述显示基板的厚度方向上彼此绝缘间隔，所述防静电电极电连接至所述公共电极绑定衬垫。
根据本公开的实施例，所述显示基板被划分为显示区和包围所述显示区的边界的非显示区，所述显示区中包括晶体管，所述非显示区包括所述防静电导线、所述第一防静电电阻、所述防静电电极和多个绑定衬垫，其中，所述多个绑定衬垫至少包括所述第一接地绑定衬垫和所述公共电极绑定衬垫。
根据本公开的实施例，所述防静电导线包围所述显示区的除与设置所述多个绑定衬垫的区域相对的边界以外的边界。
根据本公开的实施例，所述显示基板还包括信号线，所述防静电导线与信号线的至少一部分同层设置。
根据本公开的实施例，所述信号线包括栅线、数据线、地线和公共电极线中的至少一者。
根据本公开的实施例，所述晶体管包括：有源层、覆盖所述有源层的栅绝缘层、设置在所述栅绝缘层的背向所基底一侧的栅极、覆盖所述栅极的层间介质层、设置在所述层间介质层背向所述基底一侧的源极和漏极，所述源极和所述漏极各自通过贯穿所述层间绝缘层和所述栅绝缘层的过孔与所述有源层连接。
根据本公开的实施例，所述第一防静电电阻设置在所述基底和所述栅绝缘层之间，所述第一防静电电阻的第一端通过贯穿所述栅绝缘层的第一过孔电连接至所述防静电导线的第一端，所述第一防静电电阻的第二端通过贯穿所述栅绝缘层的第二过孔电连接至所述第一接地绑定衬垫。
根据本公开的实施例，所述显示区的形状为矩形，所述防静电导线沿所述矩形的三条边设置，所述第一防静电电阻沿所述矩形的剩余一条边设置。
根据本公开的实施例，所述第一防静电电阻在所述基底上的至少部分投影呈第一方波形，所述防静电电极在所述基底上的至少部分 投影呈第二方波形，所述第一方波形和所述第二方波形的朝向不同。
根据本公开的实施例，所述晶体管还包括：覆盖所述源极和所述漏极的钝化层、以及设置在所述钝化层的背向所述基底一侧的像素电极和设置在所述钝化层的背向所述基底一侧的公共电极中的至少一个。
根据本公开的实施例，所述防静电电极设置在所述钝化层上，所述防静电电极通过贯穿所述钝化层和所述层间介质层的第三过孔电连接至所述公共电极绑定衬垫。
根据本公开的实施例，所述防静电电极与所述像素电极和所述公共电极中的至少一个同层设置。
根据本公开的实施例，所述第一防静电电阻由掺杂多晶硅形成。
根据本公开的实施例，所述防静电电极由铟锡氧化物形成。
本公开的另一方面提供一种显示装置，所述显示装置包括如上所述的显示基板。
附图说明
图1为根据本公开的实施例的显示基板的部分结构的俯视透视图；
图2为图1所示显示基板沿AA线的剖面图；
图3为根据本公开的另一种实施例的显示基板的部分结构俯视透视图；
图4为图3所示显示基板沿BB线的剖面图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
在本公开中，两结构“同层”是指二者是由相同材料同时形成的，故它们在层叠关系上处于相同层中，但并不代表它们与基底间的距离相等，也不代表它们与基底间的其它层结构完全相同。相反，两结构“位于不同的层”意味着两结构在层叠关系上处于不同层中。
显示基板通常可以包括阵列基板。在显示基板的制作过程中容易有静电的积累，静电易对显示装置造成损坏。通常显示基板的非显示区的部分区域用于实现与诸如柔性电路板的结构的绑定(Bonding)。在这些区域设置裸露的电极，通过柔性电路板将这些裸露的电极(也称绑定衬垫或Bonding Pad)与诸如图形处理器、手机主板等的外围结构电连接。这些裸露的电极中通常会包含接地绑定衬垫，接地绑定衬垫通常用于连接诸如手机、电视机等的机壳或大地。它们的地电位相对更加稳定。
图1为根据本公开的实施例的显示基板的部分结构的俯视透视图，图2为图1所示显示基板沿AA线的剖面图。
参照图1和图2，根据本公开的实施例的显示基板包括基底10、设置在基底10上的多个晶体管11。晶体管11包括有源层11a。基底10包括显示区S1和包围显示区S1的外边界的非显示区S2，非显示区S2划分为绑定区和非绑定区，显示基板还包括多个绑定衬垫，每个绑定衬垫在所基底10上的正投影均至少部分位于绑定区内，多个绑定衬垫至少包括一个接地绑定衬垫12a，显示基板还包括防静电导线13、与有源层11a同层设置的至少一个防静电电阻14，防静电电阻14的第一端通过第一过孔H1电连接防静电导线13，其第二端通过第二过孔H2电连接接地绑定衬垫12a，防静电导线13与防静电电阻14在基底10上的正投影位于非显示区S2内且至少包围显示区S1的除与绑定区相对的边界以外的边界。
通常一个亚像素对应一个或多个晶体管11。亚像素可呈阵列式分布。附图中以一个晶体管11表征一个亚像素所在位置。晶体管11可以是顶栅型薄膜晶体管11，也可以是底栅型薄膜晶体管11，以上两种类型均为水平型薄膜晶体管11，当然也可以是垂直型薄膜晶体管11。本实施例对此不做限定。以下均以晶体管11为顶栅型薄膜晶体管11为例进行说明。
根据本公开的实施例，显示区S1内设置有晶体管11以及与晶体管连接的数据线D和栅线G，非显示区S2内设置有其他电路结构，例如，防静电导线13、防静电电阻14等。非显示区S2是指显示基 板的位于其显示区S1的外边界以外的部分。显示区S1与非显示区S2的分界线包括部分亚像素的边界。当然，亚像素的边界可以是亚像素中像素电极的边界，或者亚像素中最外围的晶体管11的边界等。不论如何限定，显示基板的显示区S1和非显示区S2具有本领域技术人员通常理解的含义。
显示基板的非显示区S2中的部分区域设置绑定衬垫(Bonding Pad)。绑定衬垫的作用是与诸如柔性电路板的部件通过各向异性导电胶(ACF)进行结合，从而从柔性电路板接收各类电信号。对于矩形的显示基板，绑定区通常位于非显示区S2的位于显示基板一侧的区域内。对于圆形的显示基板，绑定区可以是非显示区S2的与显示基板外围的一段圆弧对应的区域。多个绑定衬垫至少包括一个接地绑定衬垫12a，接地绑定衬垫12a是用于与诸如手机机壳的整机的地相连的绑定衬垫。当然接地绑定衬垫12a最终也可以是与大地相连。这取决于包括该显示基板的显示装置的连接方式。当然，绑定衬垫还可以包括用于与驱动芯片(未示出)的数据电压输出端相连的绑定衬垫，与用于与主板(未示出)的电源电压端相连的电源绑定衬垫等等。在此不做赘述。
防静电电阻14可以在晶体管11的有源层11a的形成步骤中同步形成。在显示基板的制造过程中，无需为此增加掩模板的数目。防静电电阻14与防静电导线13和接地绑定衬垫12a通常位于不同的层结构中，距离基底10的距离也不一样，故需要第一过孔H1和第二过孔H2将它们对应的连接在一起。
结合附图可知，防静电导线13通过防静电电阻14与整机的地相连。防静电导线13与防静电电阻14整体上包围住显示区S1的大部分外边界。当机壳上积累静电时，防静电电阻14可以对静电造成一定的消耗，阻挡静电电荷进入显示区S1。当显示基板上积累静电时，静电可以沿防静电导线13经防静电电阻14分散到地。在这条路径上，静电电荷也会有一定的消耗。
根据本公开的实施例，显示基板还包括多条信号线，防静电导线13与至少部分信号线的至少部分结构同层设置。
信号线例如是栅线G、数据线D、地线(未示出)、公共电极线(未示出)等。栅线G通常为多条，通常每条栅线G对应一行亚像素。附图中仅画出了其中一条栅线G。数据线D也可以是多条，通常每条数据线D对应一列亚像素。附图中仅示出了其中一条数据线D。当然栅线G与亚像素的对应关系、数据线D与亚像素的对应关系二者并不限于以上方式。地线连接地电位，该地电位通常为诸如手机、电脑等的机壳的电位。公共电极线用于提供公共电极，在液晶显示中，该公共电极的电位与数据线D上对亚像素写入的数据电压二者之间的电压差决定了液晶分子的翻转状态，进而决定了亚像素的亮度。
在制作该显示基板时，可以在制造其中某一段信号线的同时制造防静电导线13。在图2所示的实施方式中，防静电导线13是与栅线G以及栅极11c同层设置的。当然，本领域技术人员同样可以使防静电导线13与数据线D同层设置，等等。
参照图2，晶体管11还包括覆盖有源层11a的栅绝缘层11b、设置在栅绝缘层11b的背向基底10一侧的栅极11c、覆盖栅极11c的层间介质层11d、设置在层间介质层11d背向基底10一侧的源极11e和漏极11f，源极11e和漏极11f各自通过贯穿层间介质层11d和栅绝缘层11b的过孔连接至有源层11a；防静电导线13、栅线G的至少一部分、栅极11c三者同层设置；第一过孔H1贯穿栅绝缘层11b，第二过孔H2贯穿栅绝缘层11b。
根据本公开的实施例，栅极11c和数据线D可由诸如铜(Cu)、铝(Al)、钼(Mo)、钛(Ti)、铬(Cr)、钨(W)等的金属材料制成，或者可以由包括这些金属材料的合金制成。栅极11c和数据线D可以具有单层结构或多层结构，例如，由Mo、Al、Mo形成的多层结构、由Ti、Cu、Ti形成的多层结构或者由MoTi、Cu形成的多层结构。
根据本公开的实施例，栅绝缘层11b和层间介质层11d分别可以由氮化硅或氧化硅制成。栅绝缘层11b和层间介质层11d分别可以具有单层结构或多层结构，例如，由氧化硅、氮化硅形成的多层结构。
根据本公开的实施例，参照图1，显示基板包括两个防静电电阻 14和至少两个接地绑定衬垫12a，其中一个防静电电阻14的两端分别电连接防静电导线13的一端和其中一个接地绑定衬垫12a，另一个防静电电阻14的两端分别电连接防静电导线13的另一端和另一个接地绑定衬垫12a。
在这种实施方式中，防静电导线13的两端均连接防静电电阻14。静电在防静电导线13的两端都能得到消耗。当然，受显示基板内空间的限制，也可以如图3所示，仅在防静电导线13的一端连接防静电电阻14。当然，这种情况下，防静电导线13的未连接防静电电阻14的那一端可以连接或不连接接地绑定衬垫12a，图3中示出了防静电导线13的未连接防静电电阻14的那一端未连接接地绑定衬垫12a的情况。
根据本公开的实施例，显示区S1的形状为矩形，防静电导线13在基底10上的正投影与矩形的三条边相对，防静电电阻14与矩形的另外一条边相对。如此设置，是为了尽可能对显示区S1的外边界的尽量多的区域进行保护。
根据本公开的实施例，防静电电阻14在基底10上的至少部分投影可以呈方波形。如此是为了增大防静电电阻14的阻值，当然防静电电阻14的形状不限于此。
根据本公开的实施例，防静电电阻14和有源层11a的图形可由多晶硅形成，并通过对防静电电阻14的图形进行掺杂来形成防静电电阻，即，防静电电阻14可由掺杂多晶硅形成。
图3为根据本公开的另一种实施例的显示基板的部分结构的俯视透视图，图4为图3所示显示基板沿BB线的剖面图。在此，将不再对图3和图4中的与图1和图2相同的结构进行重复描述。
参照图3和图4，显示基板还可以包括防静电电极15，防静电电极15在基底10上的正投影与防静电电阻14在基底10上的正投影有交叠，且防静电电极15和防静电电阻14通过绝缘层分开，多个绑定衬垫还包括公共电极绑定衬垫12b，防静电电极15与公共电极绑定衬垫12b通过第三过孔H3电连接。
通过设置连接公共电极绑定衬垫12b的防静电电极15，可以在 防静电电极15和防静电电阻14的交叉位置处形成电容。由于该电容的一端连接大地，另一端连接公共电极绑定衬垫12b(连接公共电压)，这两端的电位都相对稳定。从而该电容效应可以更好地吸收一部分静电电荷，进一步减少对显示基板的伤害。并且，在防静电导线13和绑定衬垫之间形成了电阻和电容并联的结构，从而增强了对外部静电的阻挡。
根据本公开的实施例，防静电电极15在基底10上的至少部分投影可以呈方波形。当然，防静电电极15在基底10上的正投影也可以直线、曲线等其他形状。
根据本公开的实施例，防静电电极15对应的方波形的朝向与防静电电阻14对应的方波形的朝向不同。如此，可以交替地形成多段电阻和多个电容。例如，如图3所示，以当前视角，防静电电极15的方波形状是水平方向的，防静电电阻14的方波形状是竖直方向的。
根据本公开的实施例，参照图4，晶体管11还包括覆盖有源层11a的栅绝缘层11b、设置在栅绝缘层11b的背向基底10一侧的栅极11c、覆盖栅极11c的层间介质层11d、设置在层间介质层11d背向基底10一侧的源极11e和漏极11f，源极11e和漏极11f各自通过贯穿层间介质层11d和栅绝缘层11b的过孔与有源层11a连接，显示基板还包括覆盖源极11e和漏极11f的钝化层16、以及设置在钝化层16的背向基底10一侧的像素电极(未示出)和/或设置在钝化层16的背向基底10一侧的公共电极(未示出)；像素电极与防静电电极15同层设置，或者公共电极与防静电电极15同层设置，或者像素电极、公共电极和防静电电极15三者同层设置；第三过孔H3贯穿钝化层16和层间介质层11d。
在制作完晶体管11并覆盖钝化层16之后，采用一张掩模板对同一材料层进行加工，使得在钝化层16上同时形成像素电极和防静电电极15，或者使得在钝化层16上同时形成公共电极和防静电电极15。当然，在一些情况下，三者可以均为同层设置关系。第三过孔H3贯穿钝化层16和层间介质层11d以使防静电电极15与层间介质层11d下方的公共电极绑定衬垫12b相连通。
根据本公开的实施例，钝化层16可以由氮化硅或氧化硅形成，并且可以具有单层结构或多层结构，例如，由氧化硅、氮化硅形成的多层结构。
通常各绑定衬垫都是形成在栅绝缘层11b的背向基底10一侧的，但绑定衬垫的层结构并不限于此。
根据本公开的实施例，防静电电极15可有铟锡氧化物(ITO)形成。
本公开还提供一种显示装置，其包括如上所述的显示基板。
该显示装置可为液晶显示面板、有机发光二极管(OLED)显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (17)

  1. 一种显示基板，包括：
    基底；
    所述基底上的晶体管、防静电导线、第一防静电电阻和第一接地绑定衬垫，
    其中，所述第一防静电电阻的第一端电连接至所述防静电导线的第一端，所述第一防静电电阻的第二端电连接至所述第一接地绑定衬垫，并且
    所述第一防静电电阻位于与所述防静电导线所在层和所述第一接地绑定衬垫所在层不同的层，并且与所述晶体管的有源层同层设置。
  2. 根据权利要求1所述的显示基板，还包括：第二防静电电阻和第二接地绑定衬垫，所述第二防静电电阻的第一端电连接至所述防静电导线的第二端，所述第二防静电电阻的第二端电连接至所述第二绑定衬垫。
  3. 根据权利要求1或2所述的显示基板，还包括：防静电电极和构造为接收公共电压的公共电极绑定衬垫，所述防静电电极在所述基底上的正投影与所述第一防静电电阻在所述基底上的正投影存在交叠，所述防静电电极和所述第一防静电电阻在所述显示基板的厚度方向上彼此绝缘间隔，所述防静电电极电连接至所述公共电极绑定衬垫。
  4. 根据权利要求3所述的显示基板，其中，所述显示基板被划分为显示区和包围所述显示区的边界的非显示区，所述显示区中包括所述晶体管，所述非显示区包括所述防静电导线、所述第一防静电电阻、所述防静电电极和多个绑定衬垫，其中，所述多个绑定衬垫至少包括所述第一接地绑定衬垫和所述公共电极绑定衬垫。
  5. 根据权利要求4所述的显示基板，其中，所述防静电导线包围所述显示区的除与设置所述多个绑定衬垫的区域相对的边界以外的边界。
  6. 根据权利要求3所述的显示基板，其中，所述显示基板还包括信号线，所述防静电导线与信号线的至少一部分同层设置。
  7. 根据权利要求6所述的显示基板，其中，所述信号线包括栅线、数据线、地线和公共电极线中的至少一者。
  8. 根据权利要求3所述的显示基板，其中，所述晶体管包括：有源层、覆盖所述有源层的栅绝缘层、设置在所述栅绝缘层的背向所基底一侧的栅极、覆盖所述栅极的层间介质层、设置在所述层间介质层背向所述基底一侧的源极和漏极，所述源极和所述漏极各自通过贯穿所述层间绝缘层和所述栅绝缘层的过孔与所述有源层连接。
  9. 根据权利要求8所述的显示基板，其中，所述第一防静电电阻设置在所述基底和所述栅绝缘层之间，所述第一防静电电阻的第一端通过贯穿所述栅绝缘层的第一过孔电连接至所述防静电导线的第一端，所述第一防静电电阻的第二端通过贯穿所述栅绝缘层的第二过孔电连接至所述第一接地绑定衬垫。
  10. 根据权利要求4所述的显示基板，其中，所述显示区的形状为矩形，所述防静电导线沿所述矩形的三条边设置，所述第一防静电电阻沿所述矩形的剩余一条边设置。
  11. 根据权利要求3所述的显示基板，其中，所述第一防静电电阻在所述基底上的至少部分投影呈第一方波形，所述防静电电极在所述基底上的至少部分投影呈第二方波形，所述第一方波形和所述第二方波形的朝向不同。
  12. 根据权利要求8所述的显示基板，其中，所述晶体管还包括：覆盖所述源极和所述漏极的钝化层、以及设置在所述钝化层的背向所述基底一侧的像素电极和设置在所述钝化层的背向所述基底一侧的公共电极中的至少一个。
  13. 根据权利要求12所述的显示基板，其中，所述防静电电极设置在所述钝化层上，所述防静电电极通过贯穿所述钝化层和所述层间介质层的第三过孔电连接至所述公共电极绑定衬垫。
  14. 根据权利要求13所述的显示基板，其中，所述防静电电极与所述像素电极和所述公共电极中的至少一个同层设置。
  15. 根据权利要求3所述的显示基板，其中，所述第一防静电电阻由掺杂多晶硅形成。
  16. 根据权利要求3所述的显示基板，其中，所述防静电电极由铟锡氧化物形成。
  17. 一种显示装置，包括根据权利要求1-16任意一项所述的显示基板。
PCT/CN2020/091280 2019-05-31 2020-05-20 显示基板和显示装置 WO2020238722A1 (zh)

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