WO2016188056A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2016188056A1
WO2016188056A1 PCT/CN2015/094799 CN2015094799W WO2016188056A1 WO 2016188056 A1 WO2016188056 A1 WO 2016188056A1 CN 2015094799 W CN2015094799 W CN 2015094799W WO 2016188056 A1 WO2016188056 A1 WO 2016188056A1
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Prior art keywords
electrode
pixel electrode
thin film
film transistor
pixel
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PCT/CN2015/094799
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English (en)
French (fr)
Inventor
李文波
李盼
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京东方科技集团股份有限公司
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Priority to US15/127,984 priority Critical patent/US9952476B2/en
Publication of WO2016188056A1 publication Critical patent/WO2016188056A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present disclosure relates to an array substrate and a display device.
  • the liquid crystal panel in the display device includes an array substrate and a color filter substrate, and a liquid crystal between the array substrate and the color filter substrate.
  • the array substrate includes a plurality of sub-pixel units, and the liquid crystal corresponding to each of the sub-pixel units is deflected in an electric field formed by the pixel electrode and the common electrode, and each sub-pixel unit can be controlled by controlling a magnitude of a voltage of an electric field formed by the pixel electrode and the common electrode. Corresponding liquid crystal deflection angle size, thereby achieving gray scale display.
  • the display device For display devices such as mobile phones, televisions, computers, and public information display devices, in order to satisfy the user's requirement to view high-quality images on the display device from multiple angles, the display device is required to have a wide viewing angle range.
  • the voltage of the electric field for controlling the liquid crystal deflection corresponding to each sub-pixel unit is the same, and the deflection angles of the liquid crystals corresponding to each sub-pixel unit are uniform, so that the viewing angle range of the display device is narrow.
  • embodiments of the present invention provide an array substrate and a display device. Different electric fields having different voltages exist in each sub-pixel unit, so that the deflection angles of the liquid crystals corresponding to each sub-pixel unit are different, thereby realizing wide viewing angle display of the display device.
  • an embodiment of the present invention provides an array substrate including: a plurality of data lines extending in a first direction, a plurality of gate lines extending in a second direction perpendicular to the first direction, and a plurality of sub-pixel units defined by the plurality of gate lines and the plurality of data lines crossing vertically and horizontally; the sub-pixel units including first and second pixel electrodes located on opposite sides of the gate line, and located at a common electrode between the first pixel electrode and the second pixel electrode; at least one first compensation electrode is connected to one side of the common electrode, and the first compensation electrode is located at the first pixel electrode At least a portion of the projection on the plane falls within the first pixel electrode; and/or one side of the first pixel electrode is coupled to at least one second compensation electrode, and the second compensation electrode is located at the common electrode At least a portion of the projection on the plane falls within the common electrode.
  • the sub-pixel unit further includes a first thin film transistor and a second thin film transistor, and the gate line serves as a gate of the first thin film transistor and the second thin film transistor, a data line is used as a source of the first thin film transistor and the second thin film transistor, a drain of the first thin film transistor is electrically connected to the first pixel electrode, and a drain of the second thin film transistor is The second pixel electrode is electrically connected.
  • the common electrode includes a first common electrode and a second common electrode, the first common electrode is located between the first pixel electrode and the gate line, and the second common An electrode is located between the second pixel electrode and the gate line.
  • the sub-pixel unit includes a common thin film transistor shared by the first pixel electrode and the second pixel electrode, and the gate line can serve as a gate of the common thin film transistor.
  • the data line can serve as a source of the common thin film transistor, and a drain of the common thin film transistor is electrically connected to the first pixel electrode and electrically connected to the second pixel electrode.
  • the second pixel electrode covers the entire drain or a portion of the drain of the second thin film transistor.
  • the drain of the second thin film transistor includes a drain portion and a bent portion connected to the drain portion, and the projection of the drain portion on the plane where the second pixel electrode is located is at least A portion falls into the second pixel electrode, and a projection of the bent portion on a plane where the second pixel electrode is located falls outside the second pixel electrode, and a channel of the second thin film transistor is formed at the bent portion Between the source of the second thin film transistor.
  • a drain of the first thin film transistor is electrically connected to the first pixel electrode through a first via, and a drain of the second thin film transistor and the second pixel electrode pass The second via is electrically connected.
  • the first pixel electrode and the second pixel electrode are both an indium tin oxide electrode or an indium zinc oxide electrode.
  • an embodiment of the present invention further provides a display device comprising the array substrate of any of the above embodiments.
  • An embodiment of the present invention provides an array substrate and a display device including a plurality of sub-pixel units, each of the sub-pixel units including a first pixel electrode and a second pixel electrode, and a common between the first pixel electrode and the second pixel electrode An electric field exists between the first pixel electrode and the common electrode, and an electric field exists between the second pixel electrode and the common electrode; a first compensation electrode is connected to one side of the common electrode, and the first compensation electrode is located at the first pixel electrode At least a portion of the projection on the plane falls within the first pixel electrode, and a voltage generated between the first compensation electrode and the first pixel electrode can compensate for the first pixel An electric field between the pole and the common electrode, and/or at least one side of the first pixel electrode is connected to the second compensation electrode, and at least a portion of the projection of the second compensation electrode on the plane where the common electrode is located falls into the common electrode, The voltage generated between the two compensation electrodes and the common electrode can compensate for the electric field between the first pixel electrode and the common
  • the voltage of the electric field between the first pixel electrode and the common electrode is different from the voltage of the electric field between the second pixel electrode and the common electrode, and therefore, There are two electric fields with different voltages in each sub-pixel unit, so that the liquid crystals corresponding to each sub-pixel unit have different deflection angles at two different voltages, thereby realizing a wide viewing angle display of the display device.
  • FIG. 1 is a schematic structural diagram 1 of a sub-pixel unit in an array substrate according to an embodiment of the present invention
  • FIG. 2 is a second schematic structural diagram of a sub-pixel unit in an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram 3 of a sub-pixel unit in an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram 4 of a sub-pixel unit in an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram 5 of a sub-pixel unit in an array substrate according to an embodiment of the present invention.
  • Embodiments of the present invention provide an array substrate.
  • the array substrate includes a plurality of longitudinally extending data lines 10, a plurality of laterally extending gate lines 11, and a plurality of sub-pixel units defined by a plurality of gate lines 11 and a plurality of data lines 10 intersecting vertically and horizontally.
  • the sub-pixel unit includes a first pixel electrode 12 and a second pixel electrode 13 respectively located on both sides of the gate line 11, and a common electrode 14 between the first pixel electrode 12 and the second pixel electrode 13. .
  • the first compensation electrode 15a is connected to one side of the common electrode 14, and the number and shape of the first compensation electrode 15a are not limited.
  • the number of the first compensation electrodes 15a may be, for example, one or plural.
  • the shape of the first compensation electrode 15a may be, for example, a shape such as a rectangle or a fork. At least a portion of the projection of the first compensation electrode 15a on the plane in which the first pixel electrode 12 is located falls within the first pixel electrode 12. That is, the projection of the first compensation electrode 15a and the projection of the first pixel electrode 12 have overlapping portions on the plane in which the first pixel electrode 12 is located.
  • the first compensation electrode 15a is disposed on the side of the common electrode 14 such that a voltage of an electric field generated between at least a portion of the first compensation electrode 15a and the first pixel electrode 12 can be compensated for being generated between the common electrode 14 and the first pixel electrode 12.
  • a second compensation electrode 15b may be disposed on one side of the first pixel electrode 12, and the first pixel electrode 12 is connected to the second compensation electrode 15b.
  • the number and shape of the second compensation electrodes 15b are not limited.
  • the number of the second compensation electrodes 15b may be one or plural, and the shape of the second compensation electrodes 15b may be, for example, a rectangular shape or a fork shape.
  • At least a portion of the projection of the second compensation electrode 15b on the plane in which the common electrode 14 is located falls within the common electrode 14, that is, the projection of the second compensation electrode 15b and the projection of the common electrode 14. There is an overlap on the plane in which the common electrode 14 is located.
  • the second compensation electrode 15b is disposed on one side of the first pixel electrode 12 such that a voltage of an electric field generated between at least a portion of the second compensation electrode 15b and the common electrode 14 can be compensated for generation between the common electrode 14 and the first pixel electrode 12. Electric field. Further, it is also possible to provide the second compensation electrode 15b on one side of the first pixel electrode 12 and the first compensation electrode 15a on one side of the common electrode 14. Due to the above-described voltage compensation of the electric field between the first pixel electrode 12 and the common electrode 14, the voltage of the electric field between the first pixel electrode 12 and the common electrode 14 is different from that between the second pixel electrode 13 and the common electrode 14.
  • the voltage of the electric field therefore, there are two electric fields having different voltages in each sub-pixel unit, so that the liquid crystals corresponding to each sub-pixel unit have different deflection angles at two different voltages, thereby realizing wide viewing angle display of the display device. .
  • each of the sub-pixel units in the array substrate provided by the embodiment of the present invention further includes a first thin film transistor 21 and a second thin film transistor 22, and the gate line 11 can serve as The gates of the first thin film transistor 21 and the second thin film transistor 22, the data line 10 can serve as the sources of the first thin film transistor 21 and the second thin film transistor 22.
  • the drain 16 of the first thin film transistor 21 is electrically connected to the first pixel electrode 12, and the drain 17 of the second thin film transistor 22 is electrically connected to the second pixel electrode 13.
  • the drain 16 of the first thin film transistor 21 and the first pixel electrode 12 are electrically connected through the first via 19 .
  • the first via 19 may be provided in the passivation layer between the first pixel electrode 12 and the drain 16 of the first thin film transistor 21.
  • the drain 17 of the second thin film transistor 22 may be electrically connected to the second pixel electrode 13 through the second via 20.
  • the second via 20 may be disposed in the passivation layer between the second pixel electrode 13 and the drain 17 of the second thin film transistor 22.
  • the first pixel electrode 12 and the second pixel electrode 13 may be, for example, an indium tin oxide electrode or an indium zinc oxide electrode.
  • the drain 17 of the second thin film transistor 22 may pass through the second via. 20 is electrically connected to the second pixel electrode 13, and the drain 17 of the second thin film transistor 22 includes a drain portion 23 and a bent portion 24 connected to the drain portion 23, and the drain portion 23 is located at the second pixel electrode 13 At least a portion of the projection on the plane falls within the second pixel electrode 13, and the projection of the bent portion 24 on the plane in which the second pixel electrode 13 is located falls outside the second pixel electrode 13.
  • the second pixel electrode 13 Since at least a portion of the projection of the drain portion 23 of the drain 17 of the second thin film transistor 22 on the plane where the second pixel electrode 13 is located falls within the second pixel electrode 13, that is, the second pixel electrode 13 can The entire drain portion 23 is covered, and a portion of the drain portion 23 may be covered.
  • the drain portion 23 is overlapped with the second pixel electrode 13 such that the overlapping area of the drain 17 and the second pixel electrode 13 which will cause parasitic capacitance is reduced to overlap of the drain portion 23 and the second pixel electrode 13 Area, which reduces the drain
  • the overlap area between the 17 and the second pixel electrode 13 in turn reduces the parasitic capacitance.
  • the channel of the second thin film transistor 22 is formed between the bent portion 24 and the source of the second thin film transistor 22, and the bent portion 24 of the drain 17 of the second thin film transistor 22 is at the plane where the second pixel electrode 13 is located.
  • the upper projection falls outside the second pixel electrode 13, that is, the second pixel electrode 13 does not cover the bent portion 24, so that the second pixel electrode 13 does not cover the channel of the second thin film transistor 22, and also avoids the second
  • the parasitic capacitance generated between the pixel electrode 13 and the channel further reduces the interference caused by the parasitic capacitance.
  • the common electrode in the sub-pixel unit in the above array substrate provided by the embodiment of the present invention may include a first common electrode 18 and a second common electrode 25.
  • the first common electrode 18 is located between the first pixel electrode 12 and the gate line 11
  • the second common electrode 25 is located between the second pixel electrode 13 and the gate line 11. Similar to the arrangement of the compensation electrodes in FIGS.
  • one side of the first common electrode 18 is provided with a first compensation electrode 15a, the first common electrode 18 is connected to the first compensation electrode 15a, and the first compensation electrode 15a At least a portion of the projection on the plane in which the first pixel electrode 12 is located falls within the first pixel electrode 12; and/or a side of the first pixel electrode 12 is provided with a second compensation electrode (not shown), the first pixel The electrode 12 is coupled to the second compensation electrode, and at least a portion of the projection of the second compensation electrode on the plane in which the first common electrode 18 is located falls within the first common electrode 18.
  • the sub-pixel unit further includes a common thin film transistor 26 shared by the first pixel electrode 12 and the second pixel electrode 13.
  • the gate line 11 can serve as a gate of the common thin film transistor 26, and the data line 10 can be As the source of the common thin film transistor 26, the drain 27 of the common thin film transistor 26 is electrically connected to the first pixel electrode 12, and is electrically connected to the second pixel electrode 13.
  • the drain 27 of the common thin film transistor may be electrically connected to the first pixel electrode 12 and the second pixel electrode 13 through a via, and the via connected to the first pixel electrode 12 may be located at the drain 27 and the first In the passivation layer between the pixel electrodes 12, the via hole to which the drain electrode 27 and the second pixel electrode 13 are connected may be located in the passivation layer between the drain electrode 27 and the second pixel electrode 13.
  • the switching state of the electric field between the first pixel electrode 12 and the first common electrode 18 can be controlled by a common thin film transistor 26, and between the second pixel electrode 13 and the second common electrode The switching state of the electric field.
  • the embodiment of the present invention further provides a display device, which includes the array substrate in any of the above embodiments, so that the display device can also realize a wide viewing angle display of the display device, and details are not described herein again.
  • the display device may be, for example, a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like, or any product or component having a display function.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板，包括多条数据线（10），多条栅线（11），及多条栅线（11）和多条数据线（10）交叉而定义的多个子像素单元。子像素单元包括分别位于栅线（11）两侧的第一像素电极（12）和第二像素电极（13），以及位于第一像素电极（12）和第二像素电极（13）之间的公共电极（14）。公共电极（14）的至少一侧连接有至少一个第一补偿电极（15a），其在第一像素电极（11）所在的平面上的投影至少有一部分落入第一像素电极（11）内，并且/或者第一像素电极（11）的至少一侧连接有至少一个第二补偿电极（15b），其在公共电极（14）所在的平面上的投影至少有一部分落入公共电极（14）内。还提供了一种显示装置，包括阵列基板，实现宽视角显示。

Description

阵列基板及显示装置 技术领域
本公开涉及一种阵列基板及显示装置。
背景技术
随着显示技术的发展，显示装置越来越多的应用于生活、科技等各个领域。显示装置中的液晶面板包括阵列基板和彩膜基板，以及位于阵列基板和彩膜基板之间的液晶。阵列基板包括多个子像素单元，每个子像素单元所对应的液晶在像素电极和公共电极形成的电场中进行偏转，通过控制像素电极和公共电极形成的电场的电压的大小，能够控制每个子像素单元对应的液晶的偏转角度大小，从而实现灰度显示。
对于手机、电视、电脑及公共信息显示设备等显示装置，为了满足用户从多个角度均能观看到显示装置上的高质量画面的要求，需要显示装置具有宽阔的视角范围。但是，在发明人已知的显示装置中，控制每个子像素单元所对应的液晶偏转的电场的电压相同，每个子像素单元对应的液晶的偏转角度一致，使得显示装置的视角范围较窄。
发明内容
有鉴于此，本发明的实施例提供了一种阵列基板及显示装置。每个子像素单元中存在具有不同电压的不同电场，使得每个子像素单元所对应的液晶的偏转角度不同，从而实现显示装置的宽视角显示。
根据一个方面，本发明的实施例提供了一种阵列基板，其包括：在第一方向延伸的多条数据线，在垂直于第一方向的第二方向延伸的多条栅线，以及由交叉的所述多条栅线和所述多条数据线纵横交叉而定义的多个子像素单元；所述子像素单元包括位于所述栅线两侧的第一像素电极和第二像素电极，以及位于所述第一像素电极和所述第二像素电极之间的公共电极；所述公共电极的一侧连接有至少一个第一补偿电极，所述第一补偿电极在所述第一像素电极所在的平面上的投影至少有一部分落入所述第一像素电极内；和/或所述第一像素电极的一侧连接有至少一个第二补偿电极，所述第二补偿电极在所述公共电极所在的平面上的投影至少有一部分落入所述公共电极内。
在一种可能实现的方式中，所述子像素单元还包括第一薄膜晶体管和第二薄膜晶体管，所述栅线作为所述第一薄膜晶体管和所述第二薄膜晶体管的栅极，所述数据线作为所述第一薄膜晶体管和所述第二薄膜晶体管的源极，所述第一薄膜晶体管的漏极与所述第一像素电极电连接，所述第二薄膜晶体管的漏极与所述第二像素电极电连接。
在一种可能实现的方式中，所述公共电极包括第一公共电极和第二公共电极，所述第一公共电极位于所述第一像素电极与所述栅线之间，所述第二公共电极位于所述第二像素电极与所述栅线之间。
在一种可能实现的方式中，所述子像素单元包括所述第一像素电极和所述第二像素电极共用的公共薄膜晶体管，所述栅线可作为所述公共薄膜晶体管的栅极，所述数据线可作为所述公共薄膜晶体管的源极，所述公共薄膜晶体管的漏极与所述第一像素电极电连接，且与所述第二像素电极电连接。
在一种可能实现的方式中，所述第二像素电极覆盖所述第二薄膜晶体管的整个漏极或部分漏极。
在一种可能实现的方式中，所述第二薄膜晶体管的漏极包括漏极本部和与漏极本部相连的折弯部，所述漏极本部在第二像素电极所在的平面上的投影至少有一部分落入第二像素电极内，所述折弯部在第二像素电极所在的平面上的投影落在第二像素电极外，所述第二薄膜晶体管的沟道形成于所述折弯部与所述第二薄膜晶体管的源极之间。
在一种可能实现的方式中，所述第一薄膜晶体管的漏极与所述第一像素电极通过第一过孔电连接，所述第二薄膜晶体管的漏极与所述第二像素电极通过第二过孔电连接。
在一种可能实现的方式中，所述第一像素电极与所述第二像素电极均为氧化铟锡电极或氧化铟锌电极。根据另一方面，本发明的实施例还提供一种显示装置，所述显示装置包括上述任一实施例中的阵列基板。
本发明的实施例提供的阵列基板及显示装置，其包括多个子像素单元，每个子像素单元包括第一像素电极和第二像素电极，以及位于第一像素电极和第二像素电极之间的公共电极，第一像素电极和公共电极之间存在电场，第二像素电极与公共电极之间也存在电场；公共电极的一侧连接有第一补偿电极，第一补偿电极在第一像素电极所在的平面上的投影至少有一部分落入第一像素电极内，第一补偿电极与第一像素电极之间产生的电压能够补偿给第一像素电 极与公共电极之间的电场，和/或第一像素电极的至少一侧连接有第二补偿电极，第二补偿电极在公共电极所在的平面上的投影至少有一部分落入公共电极内，第二补偿电极与公共电极之间产生的电压能够补偿给第一像素电极与公共电极之间的电场。由于上述对第一像素电极与公共电极之间的电场的电压补偿，使得第一像素电极与公共电极之间的电场的电压不同于第二像素电极与公共电极之间的电场的电压，因此，每个子像素单元中都存在两个具有不同电压的电场，使得每个子像素单元对应的液晶在两个不同的电压下的偏转角度不同，进而实现了显示装置的宽视角显示。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本发明实施例提供的阵列基板中的子像素单元的结构示意图一；
图2为本发明实施例提供的阵列基板中的子像素单元的结构示意图二；
图3为本发明实施例提供的阵列基板中的子像素单元的结构示意图三；
图4为本发明实施例提供的阵列基板中的子像素单元的结构示意图四；
图5为本发明实施例提供的阵列基板中的子像素单元的结构示意图五。
附图标记：
10-数据线，                11-栅线，
12-第一像素电极，          13-第二像素电极，
14-公共电极，              15a-第一补偿电极，15b-第二补偿电极，
16-第一薄膜晶体管的漏极，  17-第二薄膜晶体管的漏极，
18-第一公共电极，          19-第一过孔，
20-第二过孔，              21-第一薄膜晶体管，
22-第二薄膜晶体管，        23-漏极本部，
24-折弯部，                25-第二公共电极，
26-公共薄膜晶体管，        27-公共薄膜晶体管的漏极。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。附图中各层膜层的厚度和形状不反映真实比例，目的只是示意说明本发明内容。
本发明的实施例提供一种阵列基板。如图1所示，该阵列基板包括纵向延伸的多条数据线10，横向延伸的多条栅线11，以及由纵横交叉的多条栅线11和多条数据线10定义的多个子像素单元，如图1所示，子像素单元包括分别位于栅线11两侧的第一像素电极12和第二像素电极13，以及位于第一像素电极12和第二像素电极13之间的公共电极14。公共电极14的一侧连接有第一补偿电极15a，对第一补偿电极15a的数量和形状并不做限定。第一补偿电极15a的数量可以例如为一个，也可以为多个。第一补偿电极15a的形状可以例如为矩形或叉形等形状。第一补偿电极15a在第一像素电极12所在的平面上的投影至少有一部分落入第一像素电极12内。也就是说，第一补偿电极15a的投影与第一像素电极12的投影在第一像素电极12所在的平面上具有重叠部分。第一补偿电极15a设置于公共电极14一侧，使得至少部分第一补偿电极15a与第一像素电极12之间产生的电场的电压能够补偿给公共电极14与第一像素电极12之间产生的电场。或者，如图2所示，也可以在第一像素电极12的一侧设置第二补偿电极15b，且第一像素电极12与第二补偿电极15b相连接。对第二补偿电极15b的数量和形状并不做限定，第二补偿电极15b的数量可以例如为一个，也可以为多个，第二补偿电极15b的形状可以例如为矩形或叉形等形状。第二补偿电极15b在公共电极14所在的平面上的投影至少有一部分落入公共电极14内，也就是说第二补偿电极15b的投影与公共电极14的投影 在公共电极14所在的平面上具有重叠部分。第二补偿电极15b设置于第一像素电极12的一侧，使得至少部分第二补偿电极15b与公共电极14之间产生的电场的电压能够补偿给公共电极14与第一像素电极12之间产生的电场。此外，也可以同时在第一像素电极12的一侧设置第二补偿电极15b并在公共电极14的一侧设置第一补偿电极15a。由于上述对第一像素电极12与公共电极14之间的电场的电压补偿，使得第一像素电极12与公共电极14之间的电场的电压不同于第二像素电极13与公共电极14之间的电场的电压，因此，每个子像素单元中都存在两个具有不同电压的电场，使得每个子像素单元对应的液晶在两个不同的电压下的偏转角度不同，进而实现了显示装置的宽视角显示。
进一步地，为了便于控制，如图1和图2所示，本发明实施例提供的上述阵列基板中的每个子像素单元还包括第一薄膜晶体管21和第二薄膜晶体管22，栅线11可作为第一薄膜晶体管21和第二薄膜晶体管22的栅极，数据线10可作为第一薄膜晶体管21和第二薄膜晶体管22的源极。第一薄膜晶体管21的漏极16与第一像素电极12电连接，第二薄膜晶体管22的漏极17与第二像素电极13电连接。具体的，第一薄膜晶体管21的漏极16与第一像素电极12通过第一过孔19电连接。第一过孔19可以设于第一像素电极12和第一薄膜晶体管21的漏极16之间的钝化层中。第二薄膜晶体管22的漏极17可以与第二像素电极13通过第二过孔20电连接。第二过孔20可以设于第二像素电极13和第二薄膜晶体管22的漏极17之间的钝化层中。第一像素电极12与第二像素电极13可以例如为氧化铟锡电极或氧化铟锌电极。
需要说明的是，如图3所示，为了尽量减少第二薄膜晶体管22的漏极17与第二像素电极13之间的寄生电容，第二薄膜晶体管22的漏极17可以通过第二过孔20与第二像素电极13电连接，而且第二薄膜晶体管22的漏极17包括漏极本部23和与漏极本部23相连的折弯部24，该漏极本部23在第二像素电极13所在的平面上的投影至少有一部分落入第二像素电极13内，该折弯部24在第二像素电极13所在的平面上的投影落在第二像素电极13外。由于第二薄膜晶体管22的漏极17的漏极本部23在第二像素电极13所在的平面上的投影至少有一部分投影落入第二像素电极13内，也就是说，第二像素电极13可以覆盖整个漏极本部23，也可以覆盖部分漏极本部23。漏极本部23与第二像素电极13交叠设置，使得将会引起寄生电容的漏极17与第二像素电极13的交叠面积减小至漏极本部23与第二像素电极13的交叠面积，从而减少了漏极 17与第二像素电极13之间的交叠面积，继而减少了寄生电容。第二薄膜晶体管22的沟道形成于折弯部24与第二薄膜晶体管22的源极之间，而第二薄膜晶体管22的漏极17的折弯部24在第二像素电极13所在的平面上的投影落在第二像素电极13外，也就是说，第二像素电极13不覆盖折弯部24，使得第二像素电极13不覆盖第二薄膜晶体管22的沟道，也避免了第二像素电极13与沟道之间产生的寄生电容，进一步降低了寄生电容引起的干扰。
如图4所示，本发明实施例提供的上述阵列基板中的子像素单元中的公共电极可以包括第一公共电极18和第二公共电极25。第一公共电极18位于第一像素电极12与栅线11之间，第二公共电极25位于第二像素电极13与栅线11之间。与图1、图2中补偿电极的设置方式相似，第一公共电极18的一侧设置有第一补偿电极15a，第一公共电极18与第一补偿电极15a相连接，且第一补偿电极15a在第一像素电极12所在的平面上的投影至少有一部分落入第一像素电极12内；和/或第一像素电极12的一侧设置有第二补偿电极(未示出)，第一像素电极12与第二补偿电极相连接，且第二补偿电极在第一公共电极18所在的平面上的投影至少有一部分落入第一公共电极18内。
为了便于控制，如图5所示，子像素单元还包括第一像素电极12与第二像素电极13共用的公共薄膜晶体管26，栅线11可作为公共薄膜晶体管26的栅极，数据线10可作为公共薄膜晶体管26的源极，公共薄膜晶体管26的漏极27与第一像素电极12电连接，且与第二像素电极13电连接。具体的，公共薄膜晶体管的漏极27可以通过过孔与第一像素电极12、第二像素电极13电连接，漏极27与第一像素电极12连接的过孔可以位于漏极27和第一像素电极12之间的钝化层中，漏极27与第二像素电极13连接的过孔可以位于漏极27和第二像素电极13之间的钝化层中。通过如图5所示的设计，能够通过一个公共薄膜晶体管26来控制第一像素电极12和第一公共电极18之间的电场的开关状态，以及第二像素电极13和第二公共电极之间的电场的开关状态。
本发明的实施例还提供了一种显示装置，该显示装置包括上述任意实施例中的阵列基板，使得该显示装置同样可以实现显示装置的宽视角显示，在此不再赘述。该显示装置可以例如为：液晶显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本公开，而并非对本公开的限制，有关技术领域 的普通技术人员，在不脱离本公开的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本公开的范畴，本公开的专利保护范围应由权利要求限定。

Claims (9)

  1. 一种阵列基板，包括在第一方向延伸的多条数据线；在垂直于第一方向的第二方向延伸的多条栅线；以及多个由交叉的所述多条栅线和所述多条数据线定义的多个子像素单元，其中所述子像素单元包括位于分别所述栅线两侧的第一像素电极和第二像素电极，以及位于所述第一像素电极和所述第二像素电极之间的公共电极，所述公共电极的一侧连接有至少一个第一补偿电极，所述第一补偿电极在所述第一像素电极所在的平面上的投影至少有一部分落入所述第一像素电极内，和/或所述第一像素电极的一侧连接有至少一个第二补偿电极，所述第二补偿电极在所述公共电极所在的平面上的投影至少有一部分落入所述公共电极内。
  2. 根据权利要求1所述的阵列基板，其中所述子像素单元还包括第一薄膜晶体管和第二薄膜晶体管，所述栅线作为所述第一薄膜晶体管和所述第二薄膜晶体管的栅极，所述数据线作为所述第一薄膜晶体管和所述第二薄膜晶体管的源极，所述第一薄膜晶体管的漏极与所述第一像素电极电连接，所述第二薄膜晶体管的漏极与所述第二像素电极电连接。
  3. 根据权利要求1所述的阵列基板，其中所述公共电极包括第一公共电极和第二公共电极，所述第一公共电极位于所述第一像素电极与所述栅线之间，所述第二公共电极位于所述第二像素电极与所述栅线之间。
  4. 根据权利要求3所述的阵列基板，其中，所述子像素单元包括所述第一像素电极和所述第二像素电极共用的公共薄膜晶体管，所述栅线作为所述公共薄膜晶体管的栅极，所述数据线作为所述公共薄膜晶体管的源极，所述公共薄膜晶体管的漏极与所述第一像素电极电连接，且与所述第二像素电极电连接。
  5. 根据权利要求2所述的阵列基板，其中所述第二像素电极覆盖所述第二薄膜晶体管的整个漏极或部分漏极。
  6. 根据权利要求2所述的阵列基板，其中所述第二薄膜晶体管的漏极包括漏极本部和与漏极本部相连的折弯部，该漏极本部在第二像素电极所在的平面上的投影至少有一部分落入第二像素电极内，该折弯部在第二像素电极所在的平面上的投影落在第二像素电极外，所述第二薄膜晶体管的沟道形成于所述折弯部与所述第二薄膜晶体管的源极之间。
  7. 根据权利要求2所述的阵列基板，其中所述第一薄膜晶体管的漏极与所述第一像素电极通过第一过孔电连接，所述第二薄膜晶体管的漏极与所述第二像素电极通过第二过孔电连接。
  8. 根据权利要求1-7中任意一项所述的阵列基板，其中所述第一像素电极与所述第二像素电极均为氧化铟锡电极或氧化铟锌电极。
  9. 一种显示装置，其特征在于，包括上述权利要求1-8中任意一项所述的阵列基板。
PCT/CN2015/094799 2015-05-26 2015-11-17 阵列基板及显示装置 WO2016188056A1 (zh)

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