WO2021088576A1 - 显示基板及其显示装置 - Google Patents

显示基板及其显示装置 Download PDF

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Publication number
WO2021088576A1
WO2021088576A1 PCT/CN2020/119145 CN2020119145W WO2021088576A1 WO 2021088576 A1 WO2021088576 A1 WO 2021088576A1 CN 2020119145 W CN2020119145 W CN 2020119145W WO 2021088576 A1 WO2021088576 A1 WO 2021088576A1
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WIPO (PCT)
Prior art keywords
electrode
base substrate
layer
display
sub
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PCT/CN2020/119145
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English (en)
French (fr)
Inventor
颜俊
董向丹
何帆
程博
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2021564585A priority Critical patent/JP2023501022A/ja
Priority to US17/286,037 priority patent/US20210399079A1/en
Priority to EP20875641.1A priority patent/EP4057367A4/en
Publication of WO2021088576A1 publication Critical patent/WO2021088576A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device thereof.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the touch technology may be FMLOC (Flexible Multi Layer On Cell) technology.
  • a display substrate including: a base substrate including a display area and a peripheral area surrounding the display area, the display area including a first boundary, a second boundary, and a third boundary; A boundary and a fourth boundary; a plurality of sub-pixels, located in the display area, at least one of the plurality of sub-pixels includes: a light-emitting element, including a first electrode located on the base substrate, located on the first electrode The light-emitting layer on the side far from the base substrate and the second electrode on the side of the light-emitting layer far from the base substrate; a plurality of first power lines are located in the display area and are connected to the plurality of sub-pixels The first electrode is electrically connected; a first power bus is located in the peripheral area on the side of the first boundary away from the display area, and the first power bus is electrically connected to the plurality of first power lines; and Two power lines are located in the peripheral area and electrically connected to the second electrode.
  • the second power line includes a first part and a second part.
  • the first part surrounds the second boundary and the second electrode of the display area.
  • the third boundary and the fourth boundary, the second part is located on the side of the first power bus far away from the display area; wherein, the first power bus and the second power line
  • the second part includes a first sub-part and a second sub-part, the first sub-part and the second sub-part are spaced apart and arranged opposite to each other; the first sub-part and the A first gap exists between the first power bus, a second gap exists between the second sub-section and the first power bus, and at least one of the first gap and the second gap is in the liner
  • the orthographic projection on the base substrate and the orthographic projection of the second electrode on the base substrate at least partially overlap.
  • the first sub-section is close to the second boundary, and the second sub-section is close to the fourth boundary.
  • the orthographic projection of the first gap and the second gap on the base substrate is located inside the orthographic projection of the second electrode on the base substrate.
  • the display substrate further includes: a plurality of touch electrode lines located in the peripheral area, and the orthographic projection of the plurality of touch electrode lines on the base substrate and the gap are in the same position.
  • the orthographic projections on the base substrate at least partially overlap.
  • the plurality of touch electrode lines includes a plurality of first touch electrode lines and a plurality of second touch electrode lines, and the first touch electrode lines surround the first touch electrode lines of the display area. A part of a border, the second border, and the third border; the second touch electrode line surrounds the other part of the first border and the fourth border of the display area.
  • the first touch electrode line is a transmitting signal line
  • the second touch electrode line is a receiving signal line
  • the display substrate further includes: a flexible circuit board electrically connected to the plurality of touch electrode lines, the first power bus line, and the second power line, and the flexible circuit board is configured To provide electrical signals to the plurality of touch electrode lines, the first power bus and the second power line.
  • the first power bus is used to receive a first voltage signal; the second power line is used to receive a second voltage signal; wherein, the first voltage signal is higher than the second voltage signal .
  • At least one of the plurality of sub-pixels further includes a thin film transistor and a connecting electrode;
  • the thin film transistor includes: an active layer located on the base substrate, and located far from the active layer.
  • the gate on one side of the base substrate, and the source and drain on the side of the gate away from the base substrate;
  • the connection electrode is located on the side of the thin film transistor away from the base substrate; wherein The source electrode or the drain electrode is electrically connected to the connecting electrode, and the connecting electrode is electrically connected to the first electrode.
  • the first power bus includes a first sub-electrode and a second sub-electrode, and the orthographic projection of the first sub-electrode and the second sub-electrode on the base substrate at least partially overlap;
  • the first sub-electrode and the source electrode or the drain are located in the same layer;
  • the second sub-electrode and the connecting electrode are located in the same layer.
  • the first portion includes a first conductive portion, a second conductive portion, and a third conductive portion; the second conductive portion is located on a side of the first conductive portion away from the base substrate, so The third conductive portion is located on a side of the second conductive portion away from the base substrate, and the first conductive portion, the second conductive portion, and the third conductive portion are electrically connected; the first conductive portion Part is located on the same layer as the source electrode or the drain electrode.
  • the second conductive portion and the connecting electrode are located on the same layer; the third conductive portion and the first electrode are located on the same layer.
  • the second portion includes a fourth conductive portion, and the fourth conductive portion is located on the same layer as the source electrode or the drain electrode, and is an integral structure formed with the first conductive portion Floor.
  • the display substrate further includes: an inorganic protective layer covering the second power line, wherein at least a part of the inorganic protective layer is between the second power line and the second electrode between.
  • the display substrate further includes: a buffer layer on the base substrate; a first insulating layer on a side of the buffer layer away from the base substrate; and a first insulating layer on the first insulating layer.
  • the plurality of first signal lines and the plurality of second signal lines on the side of the layer away from the base substrate, wherein the orthographic projection of the plurality of first signal lines on the base substrate and the plurality of The orthographic projections of the second signal lines on the base substrate are alternately arranged, and the plurality of first signal lines and the plurality of second signal lines are arranged in different layers, a part of the plurality of first signal lines
  • the orthographic projection of a part of the plurality of second signal lines on the base substrate and the orthographic projection of the gap on the base substrate at least partially overlap.
  • the display substrate further includes: a second insulating layer located between the plurality of first signal lines and the plurality of second signal lines; and covering the plurality of second signal lines An interlayer dielectric layer; wherein the second insulating layer and the interlayer dielectric layer are located between the gate and the source or the drain.
  • the display substrate further includes: a capacitor between the interlayer dielectric layer and the base substrate, and the capacitor includes a capacitor on the first insulating layer away from the base substrate.
  • a display device including: the display substrate as described above.
  • FIG. 1 is a top view showing a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is an enlarged schematic diagram showing a partial structure in the first dashed line frame 141 in FIG. 1;
  • FIG. 3 is an enlarged schematic diagram showing a partial structure in the second dashed frame 142 in FIG. 1;
  • FIG. 4 is a plan view showing the structure in FIG. 3 omitting the touch electrode line 410 and the second electrode 222;
  • FIG. 5 is a top view showing the structure in FIG. 4 after adding a second electrode 222;
  • FIG. 6 is a schematic cross-sectional view showing the structure taken along the line CC' in FIG. 3;
  • FIG. 7 is a schematic cross-sectional view showing a structure taken along line BB' in FIG. 2;
  • FIG. 8 is a schematic cross-sectional view showing the structure taken along the line AA′ in FIG. 1.
  • a specific device when it is described that a specific device is located between the first device and the second device, there may or may not be an intermediate device between the specific device and the first device or the second device.
  • the specific device When it is described that a specific device is connected to another device, the specific device may be directly connected to the other device without an intervening device, or may not be directly connected to the other device but with an intervening device.
  • FMLOC Flexible Multi Layer On Cell
  • touch electrodes are fabricated on the packaging layer.
  • the touch electrode lines can be signal shielded through a common ground line.
  • the inventor of the present disclosure found that in the related art, there is a gap between the power supply voltage line and the common ground line at the corner area of the display substrate. A part of the touch electrode line is located above the gap, and there are other signal lines below the gap (such as data lines and/or GOA circuits (Gate Driver on Array, array substrate row drive signal circuit, that is, gate drive circuit)) Wait).
  • the signals in the touch electrode line, the data line, and the GOA signal line may all be AC signals. There is a parasitic capacitance between the touch electrode line and the data line or GOA signal line. A signal change in one of these signal lines will affect the signal in the other signal line. Therefore, signal interference may occur between the touch electrode line and the data line or the GOA signal line, resulting in poor display or poor touch.
  • the embodiments of the present disclosure provide a display substrate to reduce signal interference.
  • the structure of the display substrate according to an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • FIG. 1 is a top view showing a display substrate according to an embodiment of the present disclosure.
  • FIG. 2 is an enlarged schematic diagram showing a partial structure in the first dashed line frame 141 in FIG. 1.
  • FIG. 7 is a schematic cross-sectional view showing the structure taken along the line BB′ in FIG. 2. The display substrate will be described in detail below in conjunction with FIG. 1, FIG. 2 and FIG. 7.
  • the display substrate includes a base substrate 100, a plurality of sub-pixels 200, a plurality of first power lines 311, a first power bus 310 and a second power line 320.
  • the base substrate 100 may include a display area 110 and a peripheral area 120 surrounding the display area 110.
  • the display area 110 includes a first boundary 111, a second boundary 112, a third boundary 113, and a fourth boundary 114.
  • the first boundary 111 is opposite to the third boundary 113
  • the second boundary 112 is opposite to the fourth boundary 114.
  • the plurality of sub-pixels 200 are located in the display area 110. At least one of the plurality of sub-pixels 200 includes a light-emitting element 220, as shown in FIG. 7.
  • the light-emitting element 220 may include a first electrode 221 located on the base substrate 100, a light-emitting layer 223 located on the side of the first electrode 221 away from the base substrate 100, and a light-emitting layer 223 located on the side away from the base substrate 100.
  • the second electrode 222 may receive the common ground terminal voltage signal Vss.
  • the one structure when describing a structure on another structure, the one structure may be in direct contact with the other structure, or may not be in direct contact with the other structure.
  • the first electrode 221 when describing that the first electrode 221 is located on the base substrate 100, the first electrode 221 may be above the base substrate 100 without directly contacting the base substrate.
  • a plurality of first power lines 311 are located in the display area 110.
  • the plurality of first power lines 311 are electrically connected to the first electrodes 221 of the plurality of sub-pixels.
  • the specific device may be directly electrically connected to the other device without an intervening device, or may not be directly electrically connected to the other device but with an intervening device.
  • the first power line 311 may be electrically connected to the first electrode 221 of the sub-pixel through a number of thin film transistors.
  • the first power bus 310 is located in the peripheral area 120 on the side of the first boundary 111 away from the display area 110.
  • the first power bus 310 is closer to the first boundary 111 than the boundary of other display areas.
  • the first power bus 310 is electrically connected to the plurality of first power lines 311.
  • the second power line 320 is located in the peripheral area 120 and is electrically connected to the second electrode 222.
  • the second power cord 320 may include a first part 321 and a second part 322.
  • the first part 321 surrounds the second boundary 112, the third boundary 113 and the fourth boundary 114 of the display area 110.
  • the second part 322 is located on the side of the first power bus 310 away from the display area 110.
  • the first power bus 310 is used to receive a first voltage signal
  • the second power line 320 is used to receive a second voltage signal.
  • the first voltage signal is higher than the second voltage signal.
  • the first power bus is used to receive the power voltage signal Vdd
  • the second power line is used to receive the common ground terminal voltage signal Vss.
  • the orthographic projection of the gap 331 or 332 on the base substrate 100 and the orthographic projection of the second electrode 222 on the base substrate 100 at least partially overlap.
  • the base substrate includes a display area and a peripheral area surrounding the display area.
  • a plurality of sub-pixels are located in the display area. At least one of the plurality of sub-pixels includes a light-emitting element.
  • the light-emitting element includes a first electrode located on a base substrate, a light-emitting layer located on a side of the first electrode far from the base substrate, and a second electrode located on a side of the light-emitting layer far from the base substrate.
  • a plurality of first power lines are located in the display area and are electrically connected to the first electrodes of the plurality of sub-pixels.
  • the first power bus is located in the peripheral area on the side of the first boundary away from the display area.
  • the first power bus is electrically connected to the plurality of first power lines.
  • the second power line is located in the peripheral area and is electrically connected to the second electrode.
  • the second power cord includes a first part and a second part. The first part surrounds the second boundary, the third boundary, and the fourth boundary of the display area. The second part is located on the side of the first power bus away from the display area.
  • the orthographic projection of the gap on the base substrate and the orthographic projection of the second electrode of the light-emitting element on the base substrate at least partially overlap. That is, the second electrode of the light-emitting element covers the gap. In this way, the second electrode of the light-emitting element can play a signal shielding function, thereby reducing signal interference between the signal line above the gap and the signal line below the gap, thereby improving the display effect of the display
  • the second portion 322 of the second power cord 320 may include a first sub-portion 3221 and a second sub-portion 3222.
  • the first sub-portion 3221 and the second sub-portion 3222 are spaced apart and arranged opposite to each other.
  • the first sub-portion 3221 is close to the second boundary 112
  • the second sub-portion 3222 is close to the fourth boundary 114.
  • the orthographic projection of at least one of the first gap 331 and the second gap 332 on the base substrate 100 and the orthographic projection of the second electrode 222 on the base substrate 100 at least partially overlap.
  • the orthographic projection of the first gap 331 and the second gap 332 on the base substrate 100 is located inside the orthographic projection of the second electrode 222 on the base substrate 100.
  • the second electrode can completely cover the two gaps, thereby further reducing signal interference between different signal lines, and improving the display effect of the display substrate.
  • the display substrate may further include a plurality of touch electrode lines 410 located in the peripheral area 120.
  • the orthographic projection of the plurality of touch electrode lines 410 on the base substrate 100 and the orthographic projection of the gap 331 or 332 on the base substrate 100 at least partially overlap. Therefore, when the second electrode 222 of the light-emitting element does not cover the gap 331 or 332, the touch electrode line 410 may interfere with other signal lines. It can be seen from this that the above-mentioned second electrode can play a good signal shielding effect.
  • the plurality of touch electrode lines 410 may include a plurality of first touch electrode lines 411 and a plurality of second touch electrode lines 412.
  • the first touch electrode line 411 surrounds a part of the first boundary 111, the second boundary 112 and the third boundary 113 of the display area 110.
  • the second touch electrode line 412 surrounds another part of the first boundary 111 and the fourth boundary 114 of the display area 110.
  • the first touch electrode line 411 may be a transmitting signal line
  • the second touch electrode line 412 may be a receiving signal line
  • the first touch electrode line 411 may be a receiving signal line
  • the second touch electrode line 412 may be To send the signal line.
  • the display substrate may further include a flexible circuit board 421 electrically connected to the plurality of touch electrode lines 410, the first power bus 310 and the second power line 320.
  • the flexible circuit board 421 is configured to provide electrical signals to the plurality of touch electrode lines 410, the first power bus 310, and the second power line 320.
  • the display substrate may further include a signal connection area 422 and an integrated circuit area 423.
  • the integrated circuit area 423 is electrically connected to the display area 110 through the signal connection area 422.
  • Multiple data line leads are located in the signal connection area 422.
  • the display substrate may further include a first touch electrode 341 and a second touch electrode 342 located in the display area.
  • the first touch electrode 341 is electrically connected to the first touch electrode line 411
  • the second touch electrode 342 is electrically connected to the second touch electrode line 412.
  • FIG. 2 also shows the opening 211 of the sub-pixel.
  • FIG. 3 is an enlarged schematic diagram showing a partial structure in the second dashed frame 142 in FIG. 1.
  • FIG. 4 is a top view showing the structure in FIG. 3 after the touch electrode line 410 and the second electrode 222 are omitted. The structure of FIG. 4 omits the touch electrode line 410 and the second electrode 222 to show the gap 331 more clearly (as shown by the dashed box in FIG. 4).
  • FIG. 5 is a top view showing the structure in FIG. 4 with the second electrode 222 added.
  • a gap for example, a first gap 331 between the first power bus 310 and the second portion 322 of the second power line 320.
  • the orthographic projection of the first gap 331 on the base substrate 100 and the orthographic projection of the second electrode 222 on the base substrate 100 at least partially overlap. In this way, the signal interference between the touch electrode line 410 and other signal lines (not shown in FIGS. 3 to 5) can be reduced.
  • the second electrode it is possible to ensure that the second electrode is located above the gap in consideration of the alignment accuracy of the second electrode and the shadow effect.
  • the alignment accuracy and the size range of the shadow structure may be -80 ⁇ m to -60 ⁇ m, or 60 ⁇ m to 80 ⁇ m
  • the second electrode can be made to exceed the gap by 60 ⁇ m to 80 ⁇ m after covering the gap.
  • the design size range of the second electrode here is only exemplary, and the scope of the embodiments of the present disclosure is not limited to this.
  • the above-mentioned second electrode may be a whole-layer structure. In other embodiments, the above-mentioned second electrode may be a layered structure arranged in blocks. For example, these blocks of the second electrode may be supplied with cathode signals respectively.
  • FIG. 6 is a schematic cross-sectional view showing the structure taken along the line CC′ in FIG. 3. Here, a part of the structure of the display substrate is described from the perspective of a cross-sectional view.
  • the display substrate may include a base substrate 100, a buffer layer 151 on the base substrate 100, and a first insulating layer 231 on the side of the buffer layer 151 away from the base substrate 100.
  • the material of the first insulating layer 231 may include silicon dioxide, silicon nitride, or the like.
  • the display substrate may further include a plurality of first signal lines 501 and a plurality of second signal lines 502 on the side of the first insulating layer 231 away from the base substrate 100.
  • the first signal line 501 and the second signal line 502 may be data signal lines.
  • the orthographic projections of the plurality of first signal lines 501 on the base substrate 100 and the orthographic projections of the plurality of second signal lines 502 on the base substrate 100 are alternately arranged, the plurality of first signal lines 501 and the plurality of second signal lines 502 is set in different layers. This arrangement of the signal lines 501 and 502 can save space.
  • the above-mentioned second electrode 222 can reduce the signal interference between the signal line 501 or 502 and the touch electrode line 410.
  • the display substrate may further include a second insulating layer 242 located between the plurality of first signal lines 501 and the plurality of second signal lines 502.
  • the material of the second insulating layer 242 may include silicon dioxide, silicon nitride, or the like.
  • the display substrate may further include an interlayer dielectric layer 243 covering the plurality of second signal lines 502.
  • the first power bus 310 and the second power line 320 are located on the side of the interlayer dielectric layer 243 away from the base substrate 100.
  • the first power bus 310 may include a first sub-electrode 3101 and a second sub-electrode 3102.
  • the orthographic projections of the first sub-electrode 3101 and the second sub-electrode 3102 on the base substrate 100 at least partially overlap.
  • the first sub-electrode 3101 and the source or drain of the thin film transistor of the sub-pixel (described later) are located on the same layer
  • the second sub-electrode 3102 and the connection electrode are located on the same layer.
  • “same layer” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • a patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific graphics may also be at different heights or have different thicknesses.
  • the second portion 322 of the second power cord 320 includes a fourth conductive portion.
  • the fourth conductive part is located on the same layer as the source or drain of the thin film transistor.
  • the fourth conductive portion and the first conductive portion (described later) of the first portion are integrally formed as a structural layer. That is, the second portion 322 of the second power line 320 shown in FIG. 6 may serve as the fourth conductive portion, and the fourth conductive portion is on the same layer as the source or drain of the thin film transistor.
  • the display substrate may further include an inorganic protective layer 511 covering the second power line 320. At least a part of the inorganic protective layer 511 is between the second power line 320 and the second electrode 222.
  • the material of the inorganic protective layer 511 may include an insulating material (such as silicon nitride, etc.).
  • the second power line 320 may not directly contact the second electrode 222 at the position of the peripheral area. Since the hydrophilicity of the inorganic protective layer is less than that of the second power line, it can prevent the shadow structure of the second electrode (such as the cathode) (here, the second electrode will be in the edge area blocked by the mask during evaporation). Shadow structure appears) Fragmentation causes water vapor to invade the second power cord, which can prevent water vapor from intruding into the display area through the water and oxygen channel formed on the side of the second power cord. In this way, it is possible to prevent the organic material in the display area from failing due to water vapor, thereby preventing the display failure of the display substrate.
  • the shadow structure of the second electrode such as the cathode
  • the display substrate may further include a first planarization layer 521 covering the inorganic protective layer 511; and a first planarization layer 521 covering the first power bus 310 and the first planarization layer 521 Two planarization layer 522.
  • the materials of the first planarization layer 521 and the second planarization layer 522 may include insulating materials (for example, organic insulating materials such as polyimide), respectively.
  • the display substrate may further include a pixel defining layer 523 on the side of the second planarization layer 522 away from the base substrate 100.
  • the above-mentioned second electrode 222 covers the pixel defining layer 523, the second planarization layer 522, the first planarization layer 521 and the inorganic protective layer 511.
  • the display substrate may further include an encapsulation layer 530 on the side of the second electrode 222 away from the base substrate 100.
  • the encapsulation layer 530 may include: a first inorganic encapsulation layer 531 on the side of the second electrode 222 away from the base substrate 100; an organic encapsulation layer 532 on the side of the first inorganic encapsulation layer 531 away from the base substrate 100 And the second inorganic encapsulation layer 533 on the side of the organic encapsulation layer 532 away from the base substrate 100.
  • the material of the first inorganic encapsulation layer 531 may include silicon nitride, etc.
  • the material of the organic encapsulation layer 532 may include PMMA (poly(methyl methacrylate), also known as acrylic), etc.
  • the second inorganic encapsulation layer 531 may include PMMA (poly(methyl methacrylate), also known as acrylic).
  • the material of the encapsulation layer 533 may include silicon nitride or the like.
  • the first inorganic encapsulation layer 531 may be formed on the second electrode 222 through a CVD (Chemical Vapor Deposition) process, and then an organic encapsulation layer 532 may be formed on the first inorganic encapsulation layer 531 through an inkjet printing process. Then, a second inorganic encapsulation layer 533 is formed on the organic encapsulation layer 532 through a CVD process.
  • CVD Chemical Vapor Deposition
  • the display substrate may further include a barrier layer 535 on the side of the packaging layer 530 away from the base substrate 100.
  • the material of the barrier layer 535 may include an inorganic insulating material.
  • each touch electrode line 410 may include a first wire 541 on the barrier layer 535 and a second wire 542 on a side of the first wire 541 away from the barrier layer 535.
  • the first wire 541 may include a Ti/Al/Ti (titanium/aluminum/titanium) three-layer structure
  • the second wire 542 may include a Ti/Al/Ti (titanium/aluminum/titanium) three-layer structure.
  • the display substrate may further include: a third insulating layer 536 between the first wire 541 and the second wire 542.
  • the material of the third insulating layer 536 may include silicon nitride, silicon oxide, or silicon oxynitride.
  • the first wire 541 can be electrically connected to the second wire 542 through a first conductive via (not shown in FIG. 6 but can be seen in FIG. 8), which can reduce a number of The resistance of the touch electrode line 410.
  • the display substrate may further include a covering layer 550 covering the plurality of touch electrode lines 410.
  • the material of the covering layer 550 may include an organic insulating material or an inorganic insulating material.
  • FIG. 7 is a schematic cross-sectional view showing the structure taken along the line BB′ in FIG. 2.
  • At least one of the plurality of sub-pixels 200 may include a thin film transistor 230 and a connection electrode 260 in addition to the light-emitting element 220.
  • the thin film transistor 230 may include an active layer 232 on the base substrate 100, a gate 233 on the side of the active layer 232 away from the base substrate 100, and a source 234 on the side of the gate 233 away from the base substrate 100. And drain 235.
  • the active layer 232 may be located on the buffer layer 151.
  • the first insulating layer 231 is located between the active layer 232 and the gate 233.
  • the second insulating layer 242 and the interlayer dielectric layer 243 are located between the gate and the source 234/drain 235.
  • the source electrode 234 is electrically connected to the active layer 232 through the second conductive via.
  • the second conductive via passes through the interlayer dielectric layer 243, the second insulating layer 242, and the first insulating layer 231.
  • the drain 235 is electrically connected to the active layer 232 through the third conductive via.
  • the third conductive via passes through the interlayer dielectric layer 243, the second insulating layer 242, and the first insulating layer 231.
  • the connecting electrode 260 is located on the side of the thin film transistor 230 away from the base substrate 100.
  • the source electrode 234 or the drain electrode 235 is electrically connected to the connection electrode 260.
  • the connecting electrode 260 is electrically connected to the first electrode 221.
  • the connecting electrode is electrically connected to the drain electrode 235 through the fourth conductive via.
  • the fourth conductive via passes through the first planarization layer 521 and the inorganic protection layer 511.
  • the first electrode 221 is electrically connected to the connection electrode 260 through the fifth conductive via.
  • the fifth conductive via passes through the second planarization layer 522.
  • the display substrate may further include a capacitor between the interlayer dielectric layer 243 and the base substrate 100.
  • the capacitor includes a first capacitor electrode 611 on the side of the first insulating layer 231 away from the base substrate 100 and a second capacitor electrode 612 on the side of the second insulating layer 242 away from the first capacitor electrode 611.
  • the first capacitor electrode 611 can be on the same layer as the gate 233 and separated from the gate 233.
  • the second capacitor electrode 612 can be in the same layer as the second signal line 502, and can be prepared by the same patterning process as the second signal line.
  • the second insulating layer 242 covers the first capacitor electrode 611, and the interlayer dielectric layer 243 covers the second capacitor electrode 612.
  • the same patterning process refers to using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous. These specific patterns are also May be at different heights or have different thicknesses.
  • the display substrate may further include a spacer layer 630 on the side of the pixel defining layer 523 away from the base substrate 100.
  • the second electrode 222 covers the spacer layer 630.
  • the material of the spacer layer 630 may include an inorganic insulating material or an organic insulating material.
  • the first touch electrode 341 and the second touch electrode 342 are located on the side of the third insulating layer 536 away from the base substrate 100.
  • the covering layer 550 covers the first touch electrode 341 and the second touch electrode 342.
  • FIG. 8 is a schematic cross-sectional view showing the structure taken along the line AA′ in FIG. 1.
  • the first portion 321 of the second power cord 320 includes a first conductive portion 711, a second conductive portion 712 and a third conductive portion 713.
  • the second conductive portion 712 is located on a side of the first conductive portion 711 away from the base substrate 100.
  • the third conductive portion 713 is located on the side of the second conductive portion 712 away from the base substrate 100.
  • the first conductive portion 711, the second conductive portion 712, and the third conductive portion 713 are electrically connected.
  • the first conductive portion 711 and the source electrode 234 or the drain electrode 235 are located on the same layer.
  • the second conductive portion 712 and the connection electrode 260 are located on the same layer.
  • the third conductive portion 713 and the first electrode 221 are located on the same layer.
  • the first conductive portion 711 of the first portion 321 and the fourth conductive portion of the second portion 322 of the second power line 320 are an integral structure layer.
  • the material of the first conductive portion 711 is the same as that of the source electrode 234 or the drain electrode 235, and is formed by the same patterning process as the source electrode and the drain electrode.
  • the material of the second conductive portion 712 is the same as the material of the connection electrode 260, and is formed by the same patterning process as the connection electrode.
  • the material of the third conductive portion 713 is the same as that of the first electrode 221, and is formed by the same patterning process as the first electrode 221. As shown in FIG. 8, the third conductive portion 713 may be electrically connected to the second electrode 222.
  • the display substrate may further include a first dam 810.
  • the first dam 810 may include a portion 811 in the same layer as the second planarization layer 522 and a portion 812 in the same layer as the pixel defining layer 523.
  • the display substrate may further include a second dam 820.
  • the second dam 820 may include a portion 821 in the same layer as the second planarization layer 522, a portion 822 in the same layer as the pixel defining layer 523, and a portion 823 in the same layer as the spacer layer 630.
  • the first wire 541 may be electrically connected to the second wire 542 through the first conductive via.
  • a display device may include the aforementioned display substrate (for example, the display substrate shown in FIG. 1).
  • the display device may be any product or component with a display function, such as a display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

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Abstract

本公开提供了一种显示基板及其显示装置。该显示基板包括：衬底基板，包括显示区和周边区；多个子像素，位于显示区，该子像素包括：发光元件，包括第一电极、发光层和第二电极；多条第一电源线，位于显示区；第一电源总线，位于周边区，第一电源总线与多条第一电源线电连接；以及第二电源线，位于周边区且与第二电极电连接，第二电源线包括第一部分和第二部分，第一部分围绕显示区的第二边界、第三边界和第四边界，第二部分位于第一电源总线远离显示区的一侧。第一电源总线和第二电源线的第二部分之间存在间隙。该间隙在衬底基板上的正投影与第二电极在衬底基板上的正投影至少部分重叠。本公开可以减小不同信号线之间的干扰。

Description

显示基板及其显示装置
相关申请的交叉引用
本申请是以CN申请号为201911088232.6，申请日为2019年11月8日的申请为基础，并主张其优先权，该CN申请的公开内容在此作为整体引入本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示基板及其显示装置。
背景技术
随着AMOLED(Active Matrix Organic Light Emitting Diode，有源矩阵有机发光二极管)的迅速发展，手机等智能终端的发展进入了全面屏和窄边框时代。为了给用户带来更优的使用体验，全面屏、窄边框、高分辨率、卷曲穿戴和/或折叠等特征必将成为未来AMOLED的重要发展方向。
在相关技术中，为了使得显示面板更轻更薄以适应以后的折叠及卷曲产品，触控技术被开发出来。例如，该触控技术可以为FMLOC(Flexible Multi Layer On Cell)技术。
发明内容
根据本公开实施例的一个方面，提供了一种显示基板，包括：衬底基板，包括显示区和围绕所述显示区的周边区，所述显示区包括第一边界、第二边界、第三边界和第四边界；多个子像素，位于所述显示区中，所述多个子像素中的至少一个包括：发光元件，包括位于所述衬底基板上的第一电极、位于所述第一电极远离所述衬底基板一侧的发光层和位于所述发光层远离所述衬底基板一侧的第二电极；多条第一电源线，位于所述显示区，与所述多个子像素的所述第一电极电连接；第一电源总线，位于所述第一边界远离所述显示区一侧的周边区，所述第一电源总线与所述多条第一电源线电连接；以及第二电源线，位于所述周边区且与所述第二电极电连接，所述第二电源线包括第一部分和第二部分，所述第一部分围绕所述显示区的所述第二边界、所述第三边界和所述第四边界，所述第二部分位于所述第一电源总线远离所述显示区的一侧；其中，所述第一电源总线和所述第二电源线的所述第二部分之间存在间隙，所述间隙 在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影至少部分重叠。
在一些实施例中，所述第二部分包括第一子部和第二子部，所述第一子部和所述第二子部间隔开且相对设置；所述第一子部与所述第一电源总线之间存在第一间隙，所述第二子部与所述第一电源总线之间存在第二间隙，所述第一间隙和所述第二间隙中的至少一个在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影至少部分重叠。
在一些实施例中，所述第一子部靠近所述第二边界，所述第二子部靠近所述第四边界。
在一些实施例中，所述第一间隙和所述第二间隙在所述衬底基板上的正投影位于所述第二电极在所述衬底基板上的正投影的内部。
在一些实施例中，所述显示基板还包括：位于所述周边区的多个触控电极线，所述多个触控电极线在所述衬底基板上的正投影与所述间隙在所述衬底基板上的正投影至少部分重叠。
在一些实施例中，所述多个触控电极线包括多个第一触控电极线和多个第二触控电极线，所述第一触控电极线围绕所述显示区的所述第一边界的一部分、所述第二边界和所述第三边界；所述第二触控电极线围绕所述显示区的所述第一边界的另一部分和所述第四边界。
在一些实施例中，所述第一触控电极线为发送信号线，所述第二触控电极线为接收信号线。
在一些实施例中，所述显示基板还包括：与所述多个触控电极线、所述第一电源总线和所述第二电源线电连接的柔性电路板，所述柔性电路板被配置为向所述多个触控电极线、所述第一电源总线和所述第二电源线提供电信号。
在一些实施例中，所述第一电源总线用于接收第一电压信号；所述第二电源线用于接收第二电压信号；其中，所述第一电压信号高于所述第二电压信号。
在一些实施例中，所述多个子像素中的至少一个还包括薄膜晶体管和连接电极；所述薄膜晶体管包括：位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，以及位于所述栅极远离所述衬底基板一侧的源极和漏极；所述连接电极位于所述薄膜晶体管远离所述衬底基板的一侧；其中，所述源极或所述漏极与所述连接电极电连接，所述连接电极与所述第一电极电连接。
在一些实施例中，所述第一电源总线包括第一子电极和第二子电极，所述第一子电极与所述第二子电极在所述衬底基板上的正投影至少部分重叠；所述第一子电极与所述源极或所述漏极位于同一层；所述第二子电极与所述连接电极位于同一层。
在一些实施例中，所述第一部分包括第一导电部分、第二导电部分和第三导电部分；所述第二导电部分位于所述第一导电部分远离所述衬底基板的一侧，所述第三导电部分位于所述第二导电部分远离所述衬底基板的一侧，所述第一导电部分、所述第二导电部分和所述第三导电部分电连接；所述第一导电部分与所述源极或所述漏极位于同一层。所述第二导电部分与所述连接电极位于同一层；所述第三导电部分与所述第一电极位于同一层。
在一些实施例中，所述第二部分包括第四导电部分，所述第四导电部分与所述源极或所述漏极位于同一层，且与所述第一导电部分为一体形成的结构层。
在一些实施例中，所述显示基板还包括：覆盖在所述第二电源线上的无机保护层，其中，所述无机保护层的至少一部分在所述第二电源线与所述第二电极之间。
在一些实施例中，所述显示基板还包括：在所述衬底基板上的缓冲层；在所述缓冲层远离所述衬底基板一侧的第一绝缘层；以及在所述第一绝缘层的远离所述衬底基板一侧的多个第一信号线和多个第二信号线，其中，所述多个第一信号线在所述衬底基板上的正投影与所述多个第二信号线在所述衬底基板上的正投影交替排列，且所述多个第一信号线和所述多个第二信号线设置在不同层，所述多个第一信号线的一部分和所述多个第二信号线的一部分在衬底基板上的正投影与所述间隙在所述衬底基板上的正投影至少部分重叠。
在一些实施例中，所述显示基板还包括：位于所述多个第一信号线与所述多个第二信号线之间的第二绝缘层；以及覆盖所述多个第二信号线的层间电介质层；其中，所述第二绝缘层和所述层间电介质层位于所述栅极与所述源极或所述漏极之间。
在一些实施例中，所述显示基板还包括：在所述层间电介质层与所述衬底基板之间的电容器，所述电容器包括在所述第一绝缘层的远离所述衬底基板一侧的第一电容电极和在所述第二绝缘层的远离所述第一电容电极一侧的第二电容电极，所述第一电容电极与所述栅极处于同一层且与所述栅极隔离开，所述第二电容电极与所述第二信号线处于同一层。
根据本公开实施例的另一个方面，提供了一种显示装置，包括：如前所述的显示基板。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是示出根据本公开一个实施例的显示基板的俯视图；
图2是示出在图1中的第一虚线框141内的局部结构的放大示意图；
图3是示出在图1中的第二虚线框142内的局部结构的放大示意图；
图4是示出图3中的结构省略触控电极线410和第二电极222后的俯视图；
图5是示出图4中的结构增加第二电极222后的俯视图；
图6是示出沿着图3中的线C-C'截取的结构的截面示意图；
图7是示出沿着图2中的线B-B'截取的结构的截面示意图；
图8是示出沿着图1中的线A-A'截取的结构的截面示意图。
应当明白，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定器件位于第一器件和第二器件之间时，在该特定器件与第一器件或第二器件之间可以存在居间器件，也可以不存在居间器件。当描述到特定器件连接其它器件时，该特定器件可以与所述其它器件直接连接而不具有居间器件，也可以不与所述其它器件直接连接而具有居间器件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
FMLOC(Flexible Multi Layer On Cell)技术是一种触控技术。在FMLOC技术中，触控电极被制作在封装层上。在FMLOC技术中，为了防止触控电极线与背板的其它走线发生信号串扰，触控电极线可以通过公共接地线进行信号屏蔽。但是，本公开的发明人发现，在相关技术中，在显示基板的转角区域处，电源电压线与公共接地线之间存在间隙。触控电极线的一部分位于该间隙之上，而该间隙下方还存在其他信号线(例如数据线和/或GOA电路(Gate Driver on Array，阵列基板行驱动信号电路，也即栅极驱动电路)等)。由于触控电极线、数据线和GOA信号线中的信号可以均为交流信号。触控电极线与数据线或GOA信号线之间存在寄生电容。这些信号线中的一个出现信号变动，就会影响另一个信号线中的信号。因此，触控电极线与数据线或GOA信号线可能会发生信号干扰，导致显示不良或触控(Touch)不良。
鉴于此，本公开的实施例提供了一种显示基板，以降低信号干扰。下面结合附图详细描述根据本公开一个实施例的显示基板的结构。
图1是示出根据本公开一个实施例的显示基板的俯视图。图2是示出在图1中的第一虚线框141内的局部结构的放大示意图。图7是示出沿着图2中的线B-B'截取的结构的截面示意图。下面结合图1、图2和图7详细描述该显示基板。
如图1、图2和图7所示，该显示基板包括衬底基板100、多个子像素200、多条第一电源线311、第一电源总线310和第二电源线320。
衬底基板100可以包括显示区110和围绕该显示区110的周边区120。显示区110包括第一边界111、第二边界112、第三边界113和第四边界114。这里，第一边界111与第三边界113相对，第二边界112与第四边界114相对。
所述多个子像素200位于显示区110中。所述多个子像素200中的至少一个包括发光元件220，如图7所示。该发光元件220可以包括位于衬底基板100上的第一电极221、位于第一电极221远离该衬底基板100一侧的发光层223和位于该发光层223远离该衬底基板100一侧的第二电极222。例如，该第一电极221为阳极，该第二电极222为阴极。例如，该第二电极222可以接收公共接地端电压信号Vss。
需要说明的是，在本公开的实施例中，当描述一个结构在另一个结构上时，该一个结构可以与该另一个结构直接接触，也可以与该另一个结构不直接接触。例如，在描述第一电极221位于衬底基板100上时，该第一电极221可以在衬底基板100的上方而不与该衬底基板直接接触。
如图1所示，多条第一电源线311位于显示区110。多条第一电源线311与多个子像素的第一电极221电连接。需要说明的是，当描述到特定器件电连接其它器件时，该特定器件可以与所述其它器件直接电连接而不具有居间器件，也可以不与所述其它器件直接电连接而具有居间器件。例如，第一电源线311可以通过若干薄膜晶体管来与子像素的第一电极221电连接。
如图1所示，第一电源总线310位于第一边界111远离显示区110一侧的周边区120。该第一电源总线310相比其他显示区的边界更靠近该第一边界111。第一电源总线310与所述多条第一电源线311电连接。
第二电源线320位于周边区120且与第二电极222电连接。该第二电源线320可以包括第一部分321和第二部分322。该第一部分321围绕显示区110的第二边界112、第三边界113和第四边界114。该第二部分322位于第一电源总线310远离显示区110的一侧。
在一些实施例中，第一电源总线310用于接收第一电压信号，第二电源线320用于接收第二电压信号。第一电压信号高于第二电压信号。例如，第一电源总线用于接收电源电压信号Vdd，第二电源线用于接收公共接地端电压信号Vss。
第一电源总线310和第二电源线320的第二部分322之间存在间隙331或332。该间隙331或332在衬底基板100上的正投影与第二电极222在衬底基板100上的正投影至少部分重叠。
至此，提供了根据本公开一些实施例的显示基板。在该显示基板中，衬底基板包括显示区和围绕显示区的周边区。多个子像素位于显示区中。所述多个子像素中的至少一个包括发光元件。该发光元件包括位于衬底基板上的第一电极、位于第一电极远 离衬底基板一侧的发光层和位于发光层远离衬底基板一侧的第二电极。多条第一电源线位于显示区，与所述多个子像素的第一电极电连接。第一电源总线位于第一边界远离显示区一侧的周边区。第一电源总线与所述多条第一电源线电连接。第二电源线位于周边区且与第二电极电连接。第二电源线包括第一部分和第二部分。第一部分围绕显示区的第二边界、第三边界和第四边界。第二部分位于第一电源总线远离显示区的一侧。第一电源总线和第二电源线的第二部分之间存在间隙。该间隙在衬底基板上的正投影与发光元件的第二电极在衬底基板上的正投影至少部分重叠。即，发光元件的第二电极覆盖在间隙上方。这样该发光元件的第二电极可以起到信号屏蔽作用，从而可以降低在间隙上方的信号线与在间隙下方的信号线之间的信号干扰，进而可以提高显示基板的显示效果。
在一些实施例中，如图1所示，第二电源线320的第二部分322可以包括第一子部3221和第二子部3222。该第一子部3221和该第二子部3222间隔开且相对设置。例如，该第一子部3221靠近第二边界112，该第二子部3222靠近第四边界114。该第一子部3221与第一电源总线310之间存在第一间隙331。该第二子部3222与第一电源总线310之间存在第二间隙332。该第一间隙331和该第二间隙332中的至少一个在衬底基板100上的正投影与第二电极222在衬底基板上100的正投影至少部分重叠。
在一些实施例中，第一间隙331和第二间隙332在衬底基板100上的正投影位于第二电极222在衬底基板100上的正投影的内部。这样可以使得第二电极完全覆盖这两个间隙，从而进一步减少不同信号线之间的信号干扰，提高显示基板的显示效果。
在一些实施例中，如图1所示，显示基板还可以包括位于周边区120的多个触控电极线410。该多个触控电极线410在衬底基板100上的正投影与间隙331或332在衬底基板100上的正投影至少部分重叠。因此，在发光元件的第二电极222不覆盖在间隙331或332的情况下，该触控电极线410可能会与其他信号线产生干扰。从这里可以看出，上述第二电极可以起到良好的信号屏蔽作用。
在一些实施例中，如图1所示，多个触控电极线410可以包括多个第一触控电极线411和多个第二触控电极线412。该第一触控电极线411围绕显示区110的第一边界111的一部分、第二边界112和第三边界113。该第二触控电极线412围绕显示区110的第一边界111的另一部分和第四边界114。例如，第一触控电极线411可以为发送信号线，第二触控电极线412可以为接收信号线；或者第一触控电极线411可以为接收信号线，第二触控电极线412可以为发送信号线。
在一些实施例中，如图1所示，显示基板还可以包括与多个触控电极线410、第一电源总线310和第二电源线320电连接的柔性电路板421。该柔性电路板421被配置为向多个触控电极线410、第一电源总线310和第二电源线320提供电信号。
在一些实施例中，如图1所示，显示基板还可以包括信号连接区422和集成电路区423。集成电路区423通过信号连接区422与显示区110电连接。多条数据线引线位于信号连接区422。
在一些实施例中，如图1和图2所示，显示基板还可以包括位于显示区的第一触控电极341和第二触控电极342。第一触控电极341与第一触控电极线411电连接，第二触控电极342与第二触控电极线412电连接。如图2所示，该第一触控电极341与该第二触控电极342之间的触控信号不同。另外，图2中还示出了子像素的开口211。
图3是示出在图1中的第二虚线框142内的局部结构的放大示意图。图4是示出图3中的结构省略触控电极线410和第二电极222后的俯视图。图4的结构省略了触控电极线410和第二电极222，是为了更清楚地示出间隙331(如图4中的虚线框所示)。图5是示出图4中的结构增加第二电极222后的俯视图。
如图3、图4和图5所示，第一电源总线310和第二电源线320的第二部分322之间存在间隙(例如第一间隙)331。该第一间隙331在衬底基板100上的正投影与第二电极222在衬底基板100上的正投影至少部分重叠。这样可以减少触控电极线410与其他信号线(图3至图5中未示出)之间的信号干扰。
在一些实施例中，可以在考虑第二电极的对位精度及阴影效应的情况下，保证第二电极位于间隙上方。例如，考虑到对位精度和阴影结构的尺寸范围可以为：-80μm至-60μm，或者60μm至80μm，因此，可以使得第二电极在覆盖间隙之后还要超过间隙60μm至80μm。当然，本领域技术人员应该明白，这里的第二电极的设计尺寸范围仅是示例性的，本公开实施例的范围并不仅限于此。
在一些实施例中，上述第二电极可以是整层的结构。在另一些实施例中，上述第二电极可以是分块设置的层结构。例如，可以给第二电极的这些块分别供应阴极信号。
图6是示出沿着图3中的线C-C'截取的结构的截面示意图。这里从截面图的角度描述显示基板的部分结构。
如图6所示，该显示基板可以包括衬底基板100、在衬底基板100上的缓冲层151和在该缓冲层151远离衬底基板100一侧的第一绝缘层231。例如，该第一绝缘层231的材料可以包括二氧化硅或氮化硅等。
如图6所示，该显示基板还可以包括在第一绝缘层231的远离衬底基板100一侧的多个第一信号线501和多个第二信号线502。例如，该第一信号线501和该第二信号线502可以为数据信号线。多个第一信号线501在衬底基板100上的正投影与多个第二信号线502在衬底基板100上的正投影交替排列，多个第一信号线501和多个第二信号线502设置在不同层。这样设置信号线501和502的排列，可以节省空间。
由于所述多个第一信号线501的一部分和所述多个第二信号线502的一部分在衬底基板上的正投影与间隙331或332在衬底基板上的正投影至少部分重叠，因此，上述第二电极222可以起到减小信号线501或502与触控电极线410之间的信号干扰。
如图6所示，该显示基板还可以包括位于多个第一信号线501与多个第二信号线502之间的第二绝缘层242。例如，该第二绝缘层242的材料可以包括二氧化硅或氮化硅等。
如图6所示，该显示基板还可以包括覆盖多个第二信号线502的层间电介质层243。第一电源总线310和第二电源线320位于该层间电介质层243的远离衬底基板100的一侧。
在一些实施例中，如图6所示，第一电源总线310可以包括第一子电极3101和第二子电极3102。该第一子电极3101与该第二子电极3102在衬底基板100上的正投影至少部分重叠。例如，第一子电极3101与子像素的薄膜晶体管的源极或漏极(后面将描述)位于同一层，第二子电极3102与连接电极(后面将描述)位于同一层。
需要说明的是，“同一层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在一些实施例中，如图6所示，第二电源线320的第二部分322包括第四导电部分。该第四导电部分与薄膜晶体管的源极或漏极位于同一层。该第四导电部分与第一部分的第一导电部分(后面将描述)为一体形成的结构层。即，图6所示的第二电源线320的该第二部分322可以作为第四导电部分，该第四导电部分与薄膜晶体管的源极或漏极处于同一层。如图6所示，在第二电源线320与第一电源总线310之间存在间隙331(或间隙332)。
在一些实施例中，如图6所示，显示基板还可以包括覆盖在第二电源线320上的 无机保护层511。该无机保护层511的至少一部分在第二电源线320与第二电极222之间。例如，该无机保护层511的材料可以包括绝缘材料(例如氮化硅等)。
通过在第二电源线320与第二电极222之间设置该无机保护层，可以使得在周边区的位置处第二电源线320不与第二电极222直接接触。由于无机保护层的亲水性小于第二电源线的亲水性，因此可以防止由于第二电极(例如阴极)的阴影结构(这里，第二电极在蒸镀时会在掩模遮挡的边缘区域出现阴影结构)碎裂导致水汽侵入第二电源线，进而可以防止水汽通过在第二电源线侧边形成的水氧通道侵入显示区。这样可以防止由水汽造成的显示区的有机材料失效，进而防止显示基板出现显示失效的问题。
在一些实施例中，如图6所示，显示基板还可以包括覆盖在无机保护层511上的第一平坦化层521；以及覆盖在第一电源总线310和第一平坦化层521上的第二平坦化层522。例如，第一平坦化层521和第二平坦化层522的材料可以分别包括绝缘材料(例如，诸如聚酰亚胺等的有机绝缘材料)。该显示基板还可以包括在第二平坦化层522的远离衬底基板100一侧的像素界定层523。如图6所示，上述第二电极222覆盖在像素界定层523、第二平坦化层522、第一平坦化层521和无机保护层511上。
在一些实施例中，如图6所示，显示基板还可以包括在第二电极222的远离衬底基板100一侧的封装层530。例如，该封装层530可以包括：在第二电极222的远离衬底基板100一侧的第一无机封装层531；在第一无机封装层531的远离衬底基板100一侧的有机封装层532；以及在有机封装层532的远离衬底基板100一侧的第二无机封装层533。例如，第一无机封装层531的材料可以包括氮化硅等，有机封装层532的材料可以包括PMMA(poly(methyl methacrylate)，聚甲基丙烯酸甲酯，又称为亚克力)等，第二无机封装层533的材料可以包括氮化硅等。
例如，可以通过CVD(Chemical Vapor Deposition，化学气相沉积)工艺在第二电极222上形成第一无机封装层531，然后通过喷墨打印工艺在该第一无机封装层531上形成有机封装层532，然后通过CVD工艺在该有机封装层532上形成第二无机封装层533。
在一些实施例中，如图6所示，显示基板还可以包括在封装层530的远离衬底基板100一侧的阻挡层535。例如，该阻挡层535的材料可以包括无机绝缘材料。
如图6所示，多个触控电极线410在阻挡层535的远离衬底基板100的一侧。在一些实施例中，如图6所示，每个触控电极线410可以包括在阻挡层535上的第一导线541和在第一导线541的远离阻挡层535一侧的第二导线542。例如，第一导线541 可以包括Ti/Al/Ti(钛/铝/钛)三层结构，第二导线542可以包括Ti/Al/Ti(钛/铝/钛)三层结构。
如图6所示，该显示基板还可以包括：在第一导线541和第二导线542之间的第三绝缘层536。例如，该第三绝缘层536的材料可以包括氮化硅、氧化硅或氮氧化硅等。在每个触控电极线410中，第一导线541可以通过第一导电过孔(图6中未示出，可以在图8中看出)与第二导线542电连接，可以减小多个触控电极线410的电阻。
在一些实施例中，如图6所示，显示基板还可以包括覆盖在所述多个触控电极线410上的覆盖层550。例如该覆盖层550的材料可以包括有机绝缘材料或无机绝缘材料。
图7是示出沿着图2中的线B-B'截取的结构的截面示意图。
如图7所示，所述多个子像素200中的至少一个除了包括发光元件220之外，还可以包括薄膜晶体管230和连接电极260。
薄膜晶体管230可以包括位于衬底基板100上的有源层232，位于有源层232远离衬底基板100一侧的栅极233，以及位于栅极233远离衬底基板100一侧的源极234和漏极235。例如，有源层232可以位于缓冲层151上。第一绝缘层231位于有源层232与栅极233之间。第二绝缘层242和层间电介质层243位于栅极与源极234/漏极235之间。该源极234通过第二导电过孔与有源层232电连接。该第二导电过孔穿过层间电介质层243、第二绝缘层242和第一绝缘层231。该漏极235通过第三导电过孔与有源层232电连接。该第三导电过孔穿过层间电介质层243、第二绝缘层242和第一绝缘层231。
如图7所示，连接电极260位于薄膜晶体管230远离衬底基板100的一侧。源极234或漏极235与连接电极260电连接。该连接电极260与第一电极221电连接。例如，该连接电极通过第四导电过孔与漏极235电连接。该第四导电过孔穿过第一平坦化层521和无机保护层511。第一电极221通过第五导电过孔与连接电极260电连接。该第五导电过孔穿过第二平坦化层522。
在一些实施例中，如图7所示，该显示基板还可以包括在层间电介质层243与衬底基板100之间的电容器。该电容器包括在第一绝缘层231的远离衬底基板100一侧的第一电容电极611和在第二绝缘层242的远离第一电容电极611一侧的第二电容电极612。该第一电容电极611可以与栅极233处于同一层且与该栅极233隔离开。该第二电容电极612可以与第二信号线502处于同一层，且与该第二信号线通过同一构 图工艺制备。第二绝缘层242覆盖第一电容电极611，层间电介质层243覆盖第二电容电极612。
这里，同一构图工艺是指采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成层结构。需要说明的是，根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
在一些实施例中，如图7所示，显示基板还可以包括在像素界定层523的远离衬底基板100一侧的隔垫物层630。第二电极222覆盖该隔垫物层630。例如，该隔垫物层630的材料可以包括无机绝缘材料或有机绝缘材料等。
在一些实施例中，如图7所示，第一触控电极341与第二触控电极342位于第三绝缘层536远离衬底基板100的一侧。覆盖层550覆盖该第一触控电极341与该第二触控电极342。
图8是示出沿着图1中的线A-A'截取的结构的截面示意图。
在一些实施例中，如图8所示，第二电源线320的第一部分321包括第一导电部分711、第二导电部分712和第三导电部分713。第二导电部分712位于第一导电部分711远离衬底基板100的一侧。第三导电部分713位于第二导电部分712远离衬底基板100的一侧。第一导电部分711、第二导电部分712和第三导电部分713电连接。第一导电部分711与源极234或漏极235位于同一层。第二导电部分712与连接电极260位于同一层。第三导电部分713与第一电极221位于同一层。该第一部分321的第一导电部分711与第二电源线320的第二部分322的第四导电部分为一体形成的结构层。第一导电部分711的材料与源极234或漏极235的材料相同，且与源极和漏极通过同一构图工艺形成。第二导电部分712的材料与连接电极260的材料相同，且与该连接电极通过同一构图工艺形成。第三导电部分713的材料与第一电极221的材料相同，且与该第一电极221通过同一构图工艺形成。如图8所示，该第三导电部分713可以与第二电极222电连接。
在一些实施例中，如图8所示，该显示基板还可以包括第一围堰(dam)810。该第一围堰810可以包括与第二平坦化层522处于同一层的部分811和与像素界定层523处于同一层的部分812。该显示基板还可以包括第二围堰820。该第二围堰820可以包括与第二平坦化层522处于同一层的部分821、与像素界定层523处于同一层的部 分822和与隔垫物层630处于同一层的部分823。
另外，如图8所示，第一导线541可以通过第一导电过孔与第二导线542电连接。
至此，详细描述了根据本公开一些实施例的显示基板。
在本公开的一些实施例中，还提供了一种显示装置。该显示装置可以包括如前所述的显示基板(例如图1所示的显示基板)。例如，该显示装置可以为：显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (18)

  1. 一种显示基板，包括：
    衬底基板，包括显示区和围绕所述显示区的周边区，所述显示区包括第一边界、第二边界、第三边界和第四边界；
    多个子像素，位于所述显示区中，所述多个子像素中的至少一个包括：发光元件，包括位于所述衬底基板上的第一电极、位于所述第一电极远离所述衬底基板一侧的发光层和位于所述发光层远离所述衬底基板一侧的第二电极；
    多条第一电源线，位于所述显示区，与所述多个子像素的所述第一电极电连接；
    第一电源总线，位于所述第一边界远离所述显示区一侧的周边区，所述第一电源总线与所述多条第一电源线电连接；以及
    第二电源线，位于所述周边区且与所述第二电极电连接，所述第二电源线包括第一部分和第二部分，所述第一部分围绕所述显示区的所述第二边界、所述第三边界和所述第四边界，所述第二部分位于所述第一电源总线远离所述显示区的一侧；
    其中，所述第一电源总线和所述第二电源线的所述第二部分之间存在间隙，所述间隙在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影至少部分重叠。
  2. 根据权利要求1所述的显示基板，其中，所述第二部分包括第一子部和第二子部，所述第一子部和所述第二子部间隔开且相对设置；
    所述第一子部与所述第一电源总线之间存在第一间隙，所述第二子部与所述第一电源总线之间存在第二间隙，所述第一间隙和所述第二间隙中的至少一个在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影至少部分重叠。
  3. 根据权利要求2所述的显示基板，其中，所述第一子部靠近所述第二边界，所述第二子部靠近所述第四边界。
  4. 根据权利要求2所述的显示基板，其中，所述第一间隙和所述第二间隙在所述衬底基板上的正投影位于所述第二电极在所述衬底基板上的正投影的内部。
  5. 根据权利要求1所述的显示基板，还包括：
    位于所述周边区的多个触控电极线，所述多个触控电极线在所述衬底基板上的正投影与所述间隙在所述衬底基板上的正投影至少部分重叠。
  6. 根据权利要求5所述的显示基板，其中，
    所述多个触控电极线包括多个第一触控电极线和多个第二触控电极线，所述第一触控电极线围绕所述显示区的所述第一边界的一部分、所述第二边界和所述第三边界；
    所述第二触控电极线围绕所述显示区的所述第一边界的另一部分和所述第四边界。
  7. 根据权利要求6所述的显示基板，其中，
    所述第一触控电极线为发送信号线，所述第二触控电极线为接收信号线。
  8. 根据权利要求5所述的显示基板，还包括：
    与所述多个触控电极线、所述第一电源总线和所述第二电源线电连接的柔性电路板，所述柔性电路板被配置为向所述多个触控电极线、所述第一电源总线和所述第二电源线提供电信号。
  9. 根据权利要求1至8任意一项所述的显示基板，其中，
    所述第一电源总线用于接收第一电压信号；
    所述第二电源线用于接收第二电压信号；
    其中，所述第一电压信号高于所述第二电压信号。
  10. 根据权利要求9所述的显示基板，其中，所述多个子像素中的至少一个还包括薄膜晶体管和连接电极；
    所述薄膜晶体管包括：位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，以及位于所述栅极远离所述衬底基板一侧的源极和漏极；
    所述连接电极位于所述薄膜晶体管远离所述衬底基板的一侧；
    其中，所述源极或所述漏极与所述连接电极电连接，所述连接电极与所述第一电极电连接。
  11. 根据权利要求10所述的显示基板，其中，所述第一电源总线包括第一子电极和第二子电极，所述第一子电极与所述第二子电极在所述衬底基板上的正投影至少部分重叠；
    所述第一子电极与所述源极或所述漏极位于同一层；
    所述第二子电极与所述连接电极位于同一层。
  12. 根据权利要求10所述的显示基板，其中，所述第一部分包括第一导电部分、第二导电部分和第三导电部分；
    所述第二导电部分位于所述第一导电部分远离所述衬底基板的一侧，所述第三导电部分位于所述第二导电部分远离所述衬底基板的一侧，所述第一导电部分、所述第二导电部分和所述第三导电部分电连接；
    所述第一导电部分与所述源极或所述漏极位于同一层。
    所述第二导电部分与所述连接电极位于同一层；
    所述第三导电部分与所述第一电极位于同一层。
  13. 根据权利要求12所述的显示基板，其中，所述第二部分包括第四导电部分，所述第四导电部分与所述源极或所述漏极位于同一层，且与所述第一导电部分为一体形成的结构层。
  14. 根据权利要求1所述的显示基板，还包括：
    覆盖在所述第二电源线上的无机保护层，
    其中，所述无机保护层的至少一部分在所述第二电源线与所述第二电极之间。
  15. 根据权利要求10所述的显示基板，还包括：
    在所述衬底基板上的缓冲层；
    在所述缓冲层远离所述衬底基板一侧的第一绝缘层；以及
    在所述第一绝缘层的远离所述衬底基板一侧的多个第一信号线和多个第二信号线，其中，所述多个第一信号线在所述衬底基板上的正投影与所述多个第二信号线在所述衬底基板上的正投影交替排列，且所述多个第一信号线和所述多个第二信号线设置在不同层，所述多个第一信号线的一部分和所述多个第二信号线的一部分在衬底基 板上的正投影与所述间隙在所述衬底基板上的正投影至少部分重叠。
  16. 根据权利要求15所述的显示基板，还包括：
    位于所述多个第一信号线与所述多个第二信号线之间的第二绝缘层；以及
    覆盖所述多个第二信号线的层间电介质层；
    其中，所述第二绝缘层和所述层间电介质层位于所述栅极与所述源极或所述漏极之间。
  17. 根据权利要求16所述的显示基板，还包括：
    在所述层间电介质层与所述衬底基板之间的电容器，所述电容器包括在所述第一绝缘层的远离所述衬底基板一侧的第一电容电极和在所述第二绝缘层的远离所述第一电容电极一侧的第二电容电极，所述第一电容电极与所述栅极处于同一层且与所述栅极隔离开，所述第二电容电极与所述第二信号线处于同一层。
  18. 一种显示装置，包括：如权利要求1至17任意一项所述的显示基板。
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