WO2018205620A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2018205620A1
WO2018205620A1 PCT/CN2017/116842 CN2017116842W WO2018205620A1 WO 2018205620 A1 WO2018205620 A1 WO 2018205620A1 CN 2017116842 W CN2017116842 W CN 2017116842W WO 2018205620 A1 WO2018205620 A1 WO 2018205620A1
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WIPO (PCT)
Prior art keywords
substrate
layer
insulating layer
orthographic projection
occlusion pattern
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PCT/CN2017/116842
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English (en)
French (fr)
Inventor
张洁
郭攀
李伟
樊君
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/066,162 priority Critical patent/US11574934B2/en
Publication of WO2018205620A1 publication Critical patent/WO2018205620A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • an electrical connection between two film layers for example, a connection between a source/drain metal layer and an active layer, a connection between a source/drain metal layer and a pixel electrode layer, etc.
  • a connection between a source/drain metal layer and an active layer for example, a connection between a source/drain metal layer and an active layer, a connection between a source/drain metal layer and a pixel electrode layer, etc.
  • via holes Due to the influence of via holes, the liquid crystal molecules in the via regions are irregularly arranged compared with other flat positions, which affects the uniformity of illumination of the entire display panel. In order to avoid the influence of via holes, it is necessary to perform light leakage at the via holes. Occlusion.
  • a black matrix is disposed at a position of a corresponding via hole of the opposite substrate for shielding light leakage at the via hole on the array substrate. Based on the influence of the alignment accuracy of the array substrate and the counter substrate, in order to ensure that the via holes can be completely blocked, it is often necessary to set the size of the black matrix to be slightly larger, which affects the aperture ratio of the display panel and affects the display quality.
  • the present disclosure provides an array substrate, a manufacturing method thereof, and a display device, which can increase the aperture ratio as much as possible while ensuring shielding of via holes on the array substrate.
  • an array substrate including a substrate substrate; an insulating layer; a via; and a first occlusion pattern; wherein the insulating layer is disposed on the substrate, the via Through the insulating layer; and an orthographic projection of the first occlusion pattern on the substrate substrate covers part or all of the orthographic projection of the via on the substrate.
  • the orthographic projection of the via on the substrate substrate completely overlaps the orthographic projection of the first occlusion pattern on the substrate.
  • the via and the first occlusion pattern have a regular shape, and a center of the via coincides with an orthographic projection of a center of the first occlusion pattern on the substrate.
  • the via hole and the first occlusion pattern are both circular or square.
  • the array substrate further includes a source/drain metal layer, an active layer, and a first insulating layer, wherein the first insulating layer is located between the source/drain metal layer and the active layer, and the through hole is penetrating
  • the insulating layer includes the first insulating layer.
  • the array substrate further includes a buffer layer, wherein the first occlusion pattern is on the base substrate, the buffer layer covers the first occlusion pattern, and the active layer is located on the buffer layer .
  • the array substrate further includes a source/drain metal layer, a first transparent electrode layer, and a second insulating layer, wherein the second insulating layer is located between the source/drain metal layer and the first transparent electrode layer And the insulating layer penetrating through the via includes the second insulating layer.
  • the array substrate further includes a second transparent electrode layer, wherein the second insulating layer covers the second transparent electrode layer; and the first transparent electrode layer is a pixel electrode layer and the second transparent electrode The layer is a common electrode layer, or the first transparent electrode layer is a common electrode layer and the second transparent electrode layer is a pixel electrode layer.
  • the array substrate further includes a gate metal layer, a source/drain metal layer, an active layer, and a second occlusion pattern, wherein the source/drain metal layer includes a source electrode and a drain electrode, and the gate metal layer includes a gate electrode
  • the active layer includes a channel region between the source electrode and the drain electrode and overlapping the gate electrode, and an orthographic projection of the channel region on the substrate substrate is completely located in the
  • the second occlusion pattern is in an orthographic projection area on the base substrate, and the second occlusion pattern is located on a side of the active layer adjacent to the substrate substrate.
  • an orthographic projection of the channel region on the substrate substrate and an orthographic projection of the second occlusion pattern on the substrate substrate completely overlap.
  • the first occlusion pattern and the second occlusion pattern are disposed in the same layer and the same material.
  • the insulating layer has a plurality of via holes respectively corresponding to the plurality of mutually independent first occlusion patterns, and the orthogonal projections of the plurality of via holes on the substrate substrate do not overlap each other.
  • the insulating layer has a plurality of via holes corresponding to one of the first occlusion patterns, and the plurality of via holes comprise a first via hole, wherein the plurality of via holes are apart from the first via hole
  • the orthographic projections of the outer vias on the substrate are located in the orthographic projection of the first via on the substrate, and the orthographic projection of the first via on the substrate Located entirely within the orthographic projection of the first occlusion pattern on the substrate.
  • the present disclosure also provides a display device including any of the above array substrates.
  • the display device further includes an opposite substrate, wherein the opposite substrate comprises a base substrate and a black matrix, and a region of the opposite substrate corresponding to the via is on a substrate of the opposite substrate
  • the orthographic projection on the substrate does not overlap with the orthographic projection of the black matrix on the substrate on the opposite substrate.
  • the present disclosure also provides a method for fabricating the above array substrate, comprising: providing a substrate; forming a first occlusion pattern, an insulating layer, and a via on the substrate, wherein the via The insulating layer, the orthographic projection of the first occlusion pattern on the substrate substrate covers part or all of the orthographic projection of the via on the substrate.
  • the step of forming a first occlusion pattern, an insulating layer and a via on the substrate substrate comprises:
  • first occlusion pattern Forming a first occlusion pattern, an active layer, a via, a first insulating layer, and a source/drain metal layer on the base substrate, wherein the via hole penetrates the first insulating layer, the first insulating layer
  • the orthographic projection of the via on the substrate is completely within the orthographic projection of the first occlusion pattern on the substrate.
  • the step of forming a first occlusion pattern, an insulating layer and a via on the substrate substrate comprises:
  • first occlusion pattern Forming a first occlusion pattern, a source/drain metal layer, a second insulating layer and a first transparent electrode layer on the base substrate, wherein the via hole penetrates the second insulating layer on the second insulating layer
  • the orthographic projection of the via on the substrate is completely within the orthographic projection of the first occlusion pattern on the substrate.
  • the method further includes:
  • a second occlusion pattern Forming a second occlusion pattern, an active layer, a gate metal layer, and a source/drain metal layer on the base substrate, wherein the source/drain metal layer includes a source electrode and a drain electrode, and the gate metal layer includes a gate electrode
  • the active layer includes a channel region between the source electrode and the drain electrode and overlapping the gate electrode, and an orthographic projection of the channel region on the substrate substrate is completely located in the second occlusion pattern
  • the second occlusion pattern is located on a side of the active layer adjacent to the substrate substrate in an orthographic projection area on the base substrate.
  • the first occlusion pattern and the second occlusion pattern are formed by one patterning process.
  • An occlusion pattern is arranged on the array substrate to block the via holes on the insulating layer. Since the via holes and the occlusion patterns are disposed on the array substrate, the alignment accuracy is high, so that the size of the occlusion pattern is not required to be additionally increased. It also ensures that the via holes are completely blocked, thereby increasing the aperture ratio and further improving the display quality.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a plan view showing the structure of a via region of the array substrate shown in FIG. 1.
  • An embodiment of the present disclosure provides an array substrate, including a substrate substrate and an insulating layer provided with a via hole disposed on the substrate, the array substrate further comprising: a first occlusion pattern, wherein the via hole is in the The orthographic projection on the substrate substrate is entirely within the orthographic projection of the first occlusion pattern on the substrate substrate.
  • an occlusion pattern is disposed on the array substrate to block the via holes on the insulating layer. Since the via holes and the occlusion patterns are disposed on the array substrate, the alignment accuracy is high, so that no additional interpolation is required. Increasing the size of the occlusion pattern also ensures that the via holes are completely blocked, thereby increasing the aperture ratio and further improving the display quality.
  • the deviation of the alignment accuracy between the first occlusion pattern and the via hole may reach about 1 ⁇ m, and in the related art, the method of arranging the black matrix on the opposite substrate to occlude the via hole, the deviation of the alignment precision It can only reach 2 to 3 ⁇ m.
  • the orthographic projection of the via on the substrate substrate completely overlaps with the orthographic projection of the first occlusion pattern on the substrate, thereby ensuring the first occlusion pattern
  • the aperture ratio is ensured to the utmost extent.
  • the size setting of the first occlusion pattern is slightly larger than the size of the via hole.
  • the array substrate further includes a source/drain metal layer, a first transparent electrode layer, and a second insulating layer between the source/drain metal layer and the first transparent electrode layer.
  • the insulating layer having via holes includes the second insulating layer. That is, in the embodiment of the present disclosure, a first occlusion pattern is disposed on the base substrate, and the first occlusion pattern can block the via holes on the second insulating layer.
  • the first transparent electrode layer is a pixel electrode layer, and the pixel electrode layer is connected to the source/drain metal layer through a via hole on the second insulating layer.
  • the array substrate further includes a source/drain metal layer, an active layer, and a first insulating layer between the source/drain metal layer and the active layer, the via provided
  • the insulating layer includes the first insulating layer. That is, in the embodiment of the present disclosure, a first occlusion pattern is disposed on the base substrate, and the first occlusion pattern can block the via holes on the first insulating layer.
  • the source/drain metal layer is connected to the active layer through via holes on the first insulating layer.
  • the insulating layer provided with the via hole may simultaneously include the first insulating layer and the second insulating layer, that is, the first occlusion pattern is disposed on the substrate substrate,
  • the first occlusion pattern can block via holes on the first insulating layer and the second insulating layer.
  • the array substrate further includes a gate metal layer, a source/drain metal layer, an active layer, and a second occlusion pattern, the source/drain metal layer including a source electrode and a drain electrode, the gate
  • the metal layer includes a gate electrode
  • the active layer includes a channel region between the source electrode and the drain electrode and overlapping the gate electrode, and the orthographic projection of the channel region on the substrate substrate is completely
  • the second occlusion pattern is located in an orthographic projection area on the base substrate, and the second occlusion pattern is located on a side of the active layer adjacent to the base substrate.
  • the second occlusion pattern can block the light of the backlight module from being directed to the channel region of the active layer, and the channel region of the active layer is prevented from being affected by light and affecting performance.
  • the orthographic projection of the channel region on the substrate substrate completely overlaps with the orthographic projection of the second occlusion pattern on the substrate substrate, thereby maximizing the shielding channel region while ensuring Guaranteed aperture ratio.
  • an orthographic projection of the active layer on the substrate is located in an orthographic projection of the second occlusion pattern on the substrate, so that the backlight module can be directed to the active layer. The light is completely obscured.
  • the first occlusion pattern and the second occlusion pattern are disposed in the same layer and the same material, so that the first occlusion pattern and the second occlusion pattern can be formed by one communication process, thereby saving manufacturing costs.
  • first occlusion pattern and the second occlusion pattern may be connected together to facilitate fabrication.
  • An embodiment of the present disclosure further provides a display device including the above array substrate.
  • the display device may be a display panel or a display device including a display panel and a driving circuit.
  • the display device further includes an opposite substrate, the opposite substrate includes a base substrate and a black matrix, and a region of the opposite substrate corresponding to the via is on the base substrate of the opposite substrate
  • the orthographic projection does not overlap with the orthographic projection of the black matrix on the substrate on the opposite substrate. That is, since the via holes on the insulating layer on the array substrate are blocked by the first occlusion pattern, a black matrix may not be disposed at a position corresponding to the via holes of the opposite substrate.
  • an embodiment of the present disclosure further provides a method for fabricating an array substrate, including:
  • the orthographic projection of the via on the substrate substrate completely overlaps with the orthographic projection of the first occlusion pattern on the substrate, thereby ensuring that the first occlusion pattern can completely block the via
  • the aperture ratio is guaranteed to the utmost extent.
  • the step of forming a first occlusion pattern and an insulating layer formed with a via on the substrate substrate includes:
  • first occlusion pattern Forming a first occlusion pattern, a source/drain metal layer, a second insulating layer and a first transparent electrode layer on the substrate, wherein the second insulating layer is formed with a via hole, and the second insulating layer is over
  • the orthographic projection of the aperture on the base substrate is entirely within the orthographic projection of the first occlusion pattern on the base substrate.
  • the step of forming a first occlusion pattern and an insulating layer formed with a via on the substrate substrate includes:
  • first occlusion pattern Forming a first occlusion pattern, an active layer, a first insulating layer, and a source/drain metal layer on the base substrate, wherein the first insulating layer is formed with a via hole, and the via hole on the first insulating layer is The orthographic projection on the substrate substrate is entirely within the orthographic projection of the first occlusion pattern on the substrate substrate.
  • the step of forming a first occlusion pattern and an insulating layer formed with a via on the substrate substrate includes:
  • a second occlusion pattern Forming a second occlusion pattern, an active layer, a gate metal layer, and a source/drain metal layer on the base substrate, the source/drain metal layer including a source electrode and a drain electrode, the gate metal layer including a gate electrode,
  • the active layer includes a channel region between the source electrode and the drain electrode and overlapping the gate electrode, and an orthographic projection of the channel region on the substrate substrate is completely located in the second occlusion pattern
  • the second occlusion pattern is located on a side of the active layer adjacent to the substrate substrate in an orthographic projection area on the base substrate.
  • the second occlusion pattern can block the light of the backlight module from being directed to the channel region of the active layer, and the channel region of the active layer is prevented from being affected by light and affecting performance.
  • the orthographic projection of the channel region on the substrate substrate completely overlaps with the orthographic projection of the second occlusion pattern on the substrate substrate, thereby maximizing the shielding channel region while ensuring Guaranteed aperture ratio.
  • the first occlusion pattern and the second occlusion pattern are formed by one communication process, thereby saving manufacturing costs.
  • first occlusion pattern and the second occlusion pattern may be connected together to facilitate fabrication.
  • the first occlusion pattern may be made of a metal material.
  • other opaque materials can also be used.
  • the second occlusion pattern may be made of a metal material. Of course, other opaque materials can also be used.
  • the shape of the via hole may be circular or square.
  • the shape of the first occlusion pattern is the same as the shape of the via hole.
  • the center of the via coincides with the orthographic projection of the center of the corresponding first occlusion pattern on the substrate.
  • the orthographic projection of the via on the substrate substrate completely overlaps with the orthographic projection of the first occlusion pattern on the substrate, that is, the size of the via and the corresponding first occlusion pattern
  • the shape is the same and the center is symmetrical, so that the aperture ratio can be ensured to the utmost extent.
  • the method for fabricating the array substrate specifically includes:
  • a source/drain metal layer is formed on the first insulating layer, the source/drain metal layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are connected to the active layer through the via hole.
  • the method may further include:
  • first transparent electrode layer Forming a first transparent electrode layer, the first transparent electrode layer being connected to the source/drain metal layer through a via penetrating through the second insulating layer.
  • the method may further include:
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic plan view showing a structure of a via region of the array substrate.
  • the array substrate includes: a base substrate 101, an occlusion pattern 102, a buffer layer 103, an active layer 104, a gate insulating layer 105, a gate metal layer 106, a first insulating layer 107, a source/drain metal layer 108, and a third insulating layer 109.
  • the gate metal layer 106 includes a gate electrode including a source electrode 1081 and a drain electrode 1082.
  • the array substrate may be an array substrate of an Advanced-Super Dimensional Switching (AD-SDS) technology mode.
  • AD-SDS Advanced-Super Dimensional Switching
  • the occlusion pattern 102 includes the first occlusion pattern and the second occlusion pattern in the above embodiment for the via 1 and the third insulating layer 109 penetrating the first insulating layer 107 and the gate insulating layer 105.
  • the via 2 and the via 3 on the second insulating layer 111 are shielded.
  • the via 1 is used to connect the source/drain metal layer 108 and the active layer 104.
  • the via 3 is used to connect the pixel electrode layer 112 and the source/drain metal layer 108. Since the via 2 is larger than the via 3 in the embodiment of the present disclosure, The via hole 3 is located in the via hole 2, and therefore, the occlusion pattern 102 can block the via hole 3 as long as the via hole 2 is blocked.
  • the active layer includes a channel region (such as the region 109 shown in FIG. 2) between the source electrode 1081 and the drain electrode 1082 and overlapping the gate electrode, and the occlusion pattern 102 is also used to block The channel region of the source layer 104 prevents the backlight from affecting the channel region of the active layer 104.
  • the occlusion pattern can be disposed over the substrate substrate below the active layer. Specifically, the occlusion pattern 102 is located above the base substrate 101, the buffer layer 103 covers the occlusion pattern 102, and the active layer 104 is disposed above the buffer layer 103. In some embodiments, an occlusion pattern can be placed on the side of the via or channel region adjacent to the backlight module.
  • a corresponding occlusion pattern may be disposed on the substrate substrate for one via hole of the array substrate, or a plurality of independent occlusion patterns may be respectively disposed for the plurality of via holes, and a plurality of via holes may also be used (such as the above Via 2 and via 3) set an occlusion pattern.
  • the embodiments of the present disclosure do not limit this.
  • the array substrate in the above embodiment is a top gate type array substrate.
  • the array substrate may also be a bottom gate type array substrate.
  • the positions of the common electrode layer 110 and the pixel electrode layer 112 may be interchanged.

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Abstract

提供一种阵列基板及其制作方法、显示装置。阵列基板包括衬底基板（101）；绝缘层；过孔（1，2，3）；以及第一遮挡图形；其中，绝缘层设置在衬底基板（101）上，过孔（1，2，3）贯穿绝缘层；以及第一遮挡图形在衬底基板（101）上的正投影覆盖过孔（1，2，3）在衬底基板（101）上的正投影的部分或全部。

Description

阵列基板及其制作方法、显示装置
相关申请的交叉引用
本申请要求于2017年5月11日提交中国专利局、申请号为201710331020.0的优先权，其全部内容据此通过引用并入本申请。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
目前的阵列基板中，两层膜层图形之间的电性连接，例如，源漏金属层与有源层的连接，源漏金属层与像素电极层的连接等，通常采用过孔的方式来实现。受过孔的影响，与其他平坦位置相比，过孔区域的液晶分子存在排列不规则的问题，这影响整个显示面板的发光一致性，为了避免过孔的影响，需要对过孔处的漏光进行遮挡。
在相关技术中，是在对向基板的对应过孔的位置处设置黑矩阵，用于对阵列基板上的过孔处的漏光进行遮挡。基于阵列基板和对向基板对位精度的影响，为了保证能够全部遮挡住过孔，往往需要将黑矩阵的尺寸设置的稍大，这对显示面板的开口率造成影响，从而影响显示品质。
发明内容
有鉴于此，本公开提供一种阵列基板及其制作方法、显示装置，在保证对阵列基板上的过孔进行遮挡的同时，尽可能提高开口率。
为解决上述技术问题，本公开提供一种阵列基板，包括衬底基板；绝缘层；过孔；以及第一遮挡图形；其中，所述绝缘层设置在所述衬底基板上，所述过孔贯穿所述绝缘层；以及所述第一遮挡图形在所述衬底基板上的正投影覆盖所述过孔在所述衬底基板上的正投影的部分或全部。
可选地，所述过孔在所述衬底基板上的正投影与所述第一遮挡图形在所述 衬底基板上的正投影完全重叠。
可选地，所述过孔和所述第一遮挡图形具有规则的形状，所述过孔的中心与所述第一遮挡图形的中心在所述衬底基板上的正投影重合。进一步地，所述过孔和所述第一遮挡图形均为圆形或均为方形。
可选地，所述阵列基板还包括源漏金属层、有源层和第一绝缘层，其中第一绝缘层位于所述源漏金属层和有源层之间，所述贯穿有过孔的绝缘层包括所述第一绝缘层。进一步地，所述阵列基板还包括缓冲层，其中所述第一遮挡图形位于所述衬底基板上，所述缓冲层覆盖所述第一遮挡图形，所述有源层位于所述缓冲层上。
可选地，所述阵列基板还包括源漏金属层、第一透明电极层和第二绝缘层，其中所述第二绝缘层位于所述源漏金属层和所述第一透明电极层之间，以及所述贯穿有过孔的绝缘层包括所述第二绝缘层。进一步地，所述阵列基板还包括第二透明电极层，其中所述第二绝缘层覆盖所述第二透明电极层；以及所述第一透明电极层为像素电极层以及所述第二透明电极层为公共电极层，或者所述第一透明电极层为公共电极层以及所述第二透明电极层为像素电极层。
可选地，所述阵列基板还包括栅金属层、源漏金属层、有源层和第二遮挡图形，其中所述源漏金属层包括源电极和漏电极，所述栅金属层包括栅电极，所述有源层包括位于所述源电极和所述漏电极之间且与所述栅电极重叠的沟道区域，所述沟道区域在所述衬底基板上的正投影完全位于所述第二遮挡图形在所述衬底基板上的正投影区域内，所述第二遮挡图形位于所述有源层的靠近所述衬底基板的一侧。
可选地，所述沟道区域在所述衬底基板上的正投影与所述第二遮挡图形在所述衬底基板上的正投影完全重叠。
可选地，所述第一遮挡图形和第二遮挡图形同层同材料设置。
可选地，所述绝缘层贯穿有分别对应于多个相互独立的所述第一遮挡图形的多个过孔，所述多个过孔在所述衬底基板上的正投影互不重叠。
可选地，所述绝缘层贯穿有对应一个所述第一遮挡图形的多个过孔，所述多个过孔包括第一过孔，所述多个过孔除所述第一过孔之外的过孔在所述衬底 基板上的正投影均位于所述第一过孔在所述衬底基板上的正投影内，所述第一过孔在所述衬底基板上的正投影完全位于所述第一遮挡图形在所述衬底基板上的正投影内。
本公开还提供一种显示装置，包括任一上述阵列基板。
可选地，所述显示装置还包括对向基板，其中所述对向基板包括衬底基板和黑矩阵，所述对向基板的对应所述过孔的区域在所述对向基板的衬底基板上的正投影与所述黑矩阵在所述对向基板上的衬底基板上的正投影不重叠。
本公开还提供一种用于制作上述阵列基板的制作方法，包括：提供一衬底基板；在所述衬底基板上形成第一遮挡图形、绝缘层和过孔，其中，所述过孔贯穿所述绝缘层，所述第一遮挡图形在所述衬底基板上的正投影覆盖所述过孔在所述衬底基板上的正投影的部分或全部。
可选地，所述在所述衬底基板上形成第一遮挡图形、绝缘层和过孔的步骤包括：
在所述衬底基板上形成第一遮挡图形、有源层、过孔、第一绝缘层和源漏金属层，其中所述过孔贯穿所述第一绝缘层，所述第一绝缘层上的过孔在所述衬底基板上的正投影完全位于所述第一遮挡图形在所述衬底基板上的正投影内。
可选地，所述在所述衬底基板上形成第一遮挡图形、绝缘层和过孔的步骤包括：
在所述衬底基板上形成第一遮挡图形、源漏金属层、第二绝缘层和第一透明电极层，其中所述过孔贯穿所述第二绝缘层上，所述第二绝缘层上的过孔在所述衬底基板上的正投影完全位于所述第一遮挡图形在所述衬底基板上的正投影内。
可选地，所述方法还包括：
在所述衬底基板上形成第二遮挡图形、有源层、栅金属层和源漏金属层，其中所述源漏金属层包括源电极和漏电极，所述栅金属层包括栅电极，所述有源层包括位于所述源电极和漏电极之间且与所述栅电极重叠的沟道区域，所述沟道区域在所述衬底基板上的正投影完全位于所述第二遮挡图形在所述衬底 基板上的正投影区域内，所述第二遮挡图形位于所述有源层的靠近所述衬底基板的一侧。
可选地，通过一次构图工艺形成所述第一遮挡图形和第二遮挡图形。
本公开的上述技术方案的有益效果如下：
在阵列基板上设置遮挡图形，对绝缘层上的过孔进行遮挡，由于过孔与遮挡图形均设置在阵列基板上，因而具有较高的对位精度，从而不需要额外加大遮挡图形的尺寸，也能够保证将过孔全部遮挡，从而提高了开口率，进一步提高了显示品质。
附图说明
图1为本公开实施例的阵列基板的结构示意图。
图2为图1所示的阵列基板的过孔区域的结构的俯视图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供一种阵列基板，包括衬底基板以及设置于所述衬底基板上的设有过孔的绝缘层，所述阵列基板还包括：第一遮挡图形，所述过孔在所述衬底基板上的正投影完全位于所述第一遮挡图形在所述衬底基板上的正投影内。
本公开实施例中，在阵列基板上设置遮挡图形，对绝缘层上的过孔进行遮挡，由于过孔与遮挡图形均设置在阵列基板上，因而具有较高的对位精度，从而不需要额外加大遮挡图形的尺寸，也能够保证将过孔全部遮挡，从而提高了开口率，进一步提高了显示品质。本公开实施例中，第一遮挡图形与过孔的对位精度的偏差可以达到1μm左右，而相关技术中在对向基板上设置黑矩阵对过孔进行遮挡的方案中，对位精度的偏差仅可以达到2～3μm。
本公开实施例中，优选地，所述过孔在所述衬底基板上的正投影与所述第一遮挡图形在所述衬底基板上的正投影完全重叠，从而在保证第一遮挡图形能够全部遮挡住过孔的基础上，最大程度的保证了开口率。
当然，在本公开的其他一些实施例中，也不排除将第一遮挡图形的尺寸设置比过孔的尺寸要稍微大一些。
在本公开的一些实施例中，所述阵列基板还包括源漏金属层、第一透明电极层以及位于所述源漏金属层和第一透明电极层之间的第二绝缘层，所述设有过孔的绝缘层包括所述第二绝缘层。也就是说，本公开实施例中，在衬底基板上设置第一遮挡图形，所述第一遮挡图形能够遮挡所述第二绝缘层上的过孔。
所述第一透明电极层为像素电极层，所述像素电极层通过第二绝缘层上的过孔与所述源漏金属层连接。
在本公开的一些实施例中，所述阵列基板还包括源漏金属层、有源层以及位于所述源漏金属层和有源层之间的第一绝缘层，所述设有过孔的绝缘层包括所述第一绝缘层。也就是说，本公开实施例中，在衬底基板上设置第一遮挡图形，所述第一遮挡图形能够遮挡所述第一绝缘层上的过孔。所述源漏金属层通过所述第一绝缘层上的过孔与有源层连接。
当然，在本公开的其他一些实施例中，所述设有过孔的绝缘层可以同时包括上述第一绝缘层和第二绝缘层，即，在衬底基板上设置第一遮挡图形，所述第一遮挡图形能够遮挡所述第一绝缘层和第二绝缘层上的过孔。
在本公开的一些优选实施例中，所述阵列基板还包括栅金属层、源漏金属层、有源层和第二遮挡图形，所述源漏金属层包括源电极和漏电极，所述栅金属层包括栅电极，所述有源层包括位于所述源电极和漏电极之间且与所述栅电极重叠的沟道区域，所述沟道区域在所述衬底基板上的正投影完全位于所述第二遮挡图形在所述衬底基板上的正投影区域内，所述第二遮挡图形位于所述有源层的靠近所述衬底基板的一侧。所述第二遮挡图形能够遮挡背光模组射向所述有源层的沟道区域的光线，避免有源层的沟道区域受光线的影响而影响性能。
优选地，所述沟道区域在所述衬底基板上的正投影与所述第二遮挡图形在所述衬底基板上的正投影完全重叠，从而在保证遮挡沟道区域的同时，最大程度的保证开口率。
进一步优选地，所述有源层在所述衬底基板上的正投影位于所述第二遮挡图形在所述衬底基板上的正投影内，从而可以将背光模组射向有源层的光线全部遮挡住。
在本公开的一优选实施例中，所述第一遮挡图形和第二遮挡图形同层同材料设置，从而可通过一次沟通工艺形成，节省制作成本。
此外，所述第一遮挡图形和第二遮挡图形可以连接在一起，从而方便制作。
本公开实施例还提供一种显示装置，包括上述阵列基板。
所述显示装置可以是一显示面板，也可以是包括显示面板和驱动电路的显示器件。
优选地，所述显示装置还包括对向基板，所述对向基板包括衬底基板和黑矩阵，所述对向基板的对应所述过孔的区域在所述对向基板的衬底基板上的正投影与所述黑矩阵在所述对向基板上的衬底基板上的正投影不重叠。即，由于所述阵列基板上的绝缘层上的过孔被第一遮挡图形遮挡，因此，所述对向基板的对应所述过孔的位置处可以不设置黑矩阵。基于同一发明构思，本公开实施例还提供一种阵列基板的制作方法，包括：
提供一衬底基板；
在所述衬底基板上形成第一遮挡图形和形成有过孔的绝缘层，所述过孔在所述衬底基板上的正投影完全位于所述第一遮挡图形在所述衬底基板上的正投影内。
优选地，所述过孔在所述衬底基板上的正投影与所述第一遮挡图形在所述衬底基板上的正投影完全重叠，从而在保证第一遮挡图形能够全部遮挡住过孔的基础上，最大程度的保证了开口率。
在本公开的一些实施例中，所述在所述衬底基板上形成第一遮挡图形和形成有过孔的绝缘层的步骤包括：
在所述衬底基板上形成第一遮挡图形、源漏金属层、第二绝缘层和第一透明电极层，所述第二绝缘层上形成有过孔，所述第二绝缘层上的过孔在所述衬底基板上的正投影完全位于所述第一遮挡图形在所述衬底基板上的正投影内。
在本公开的一些实施例中，所述在所述衬底基板上形成第一遮挡图形和形成有过孔的绝缘层的步骤包括：
在所述衬底基板上形成第一遮挡图形、有源层、第一绝缘层和源漏金属层，所述第一绝缘层上形成有过孔，所述第一绝缘层上的过孔在所述衬底基板上的正投影完全位于所述第一遮挡图形在所述衬底基板上的正投影内。
在本公开的一些实施例中，所述在所述衬底基板上形成第一遮挡图形和形成有过孔的绝缘层的步骤包括：
在所述衬底基板上形成第二遮挡图形、有源层、栅金属层和源漏金属层，所述源漏金属层包括源电极和漏电极，所述栅金属层包括栅电极，所述有源层包括位于所述源电极和漏电极之间且与所述栅电极重叠的沟道区域，所述沟道区域在所述衬底基板上的正投影完全位于所述第二遮挡图形在所述衬底基板上的正投影区域内，所述第二遮挡图形位于所述有源层的靠近所述衬底基板的一侧。
所述第二遮挡图形能够遮挡背光模组射向所述有源层的沟道区域的光线，避免有源层的沟道区域受光线的影响而影响性能。
优选地，所述沟道区域在所述衬底基板上的正投影与所述第二遮挡图形在所述衬底基板上的正投影完全重叠，从而在保证遮挡沟道区域的同时，最大程度的保证开口率。
优选地，所述第一遮挡图形和第二遮挡图形通过一次沟通工艺形成，从而节省制作成本。
此外，所述第一遮挡图形和第二遮挡图形可以连接在一起，从而方便制作。
上述实施例中，所述第一遮挡图形可以采用金属材料制成。当然，也可以采用其他不透光的材料制成。
所述第二遮挡图形可以采用金属材料制成。当然，也可以采用其他不透光的材料制成。
上述实施例中，所述过孔的形状可以为圆形或方形，优选的，所述第一遮挡图形的形状与所述过孔的形状相同。
优选地，所述过孔的中心与对应的第一遮挡图形的中心在衬底基板上的正投影重合。
进一步，优选地，所述过孔在衬底基板上的正投影与所述第一遮挡图形在所述衬底基板上的正投影完全重叠，即，过孔与对应的第一遮挡图形的尺寸和 形状均相同，且中心对称，从而可以最大程度的保证开口率。
在本公开的一优选实施例中，所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上形成第一遮挡图形；
形成覆盖所述第一遮挡图形的缓冲层；
在所述缓冲层上形成有源层；
形成覆盖所述有源层的栅绝缘层；
在所述栅绝缘层上形成栅金属层；
形成覆盖所述栅金属层的第一绝缘层，并形成贯通所述第一绝缘层和栅绝缘层的过孔，所述过孔在所述衬底基板上的正投影完全位于所述第一遮挡图形在所述衬底基板上的正投影内；
在所述第一绝缘层上形成源漏金属层，所述源漏金属层包括源电极和漏电极，所述源电极和漏电极通过所述过孔与所述有源层连接。
在一实施例中，所述方法还可以包括：
形成覆盖所述源漏金属层的第二绝缘层；
形成贯通所述第二绝缘层的过孔，所述贯通所述第二绝缘层的过孔在所述衬底基板上的正投影完全位于所述第一遮挡图形在所述衬底基板上的正投影内；
形成第一透明电极层，所述第一透明电极层通过贯通所述第二绝缘层的过孔与所述源漏金属层连接。
在另一实施例中，所述方法还可以包括：
形成覆盖所述源漏金属层的第三绝缘层，并贯通所述第三绝缘层的过孔，所述贯通所述第三绝缘层的过孔在所述衬底基板上的正投影完全位于所述第一遮挡图形在所述衬底基板上的正投影内；
形成第二透明电极层；
形成覆盖所述第二透明电极层的第二绝缘层，并形成贯通所述第二绝缘层的过孔，贯通所述第二绝缘层的过孔位于贯通所述第三绝缘层的过孔内；
形成第一透明电极层，所述第一透明电极层通过所述贯通所述第二绝缘层的过孔与所述源漏金属层连接。
下面结合具体实施例，对本公开实施例中的阵列基板的结构进行详细说明。
请参考图1和图2，图1为本公开实施例的阵列基板的结构示意图，图2示意性地示出了该阵列基板的过孔区域的结构的俯视图。该阵列基板包括：衬底基板101，遮挡图形102，缓冲层103，有源层104，栅绝缘层105，栅金属层106，第一绝缘层107，源漏金属层108，第三绝缘层109，公共电极层110，第二绝缘层111和像素电极层112。栅金属层106包括栅电极，所述源漏金属层108包括源电极1081和漏电极1082。可选地，该阵列基板可以为高级超维场转换(Advanced-Super Dimensional Switching，简称为“AD-SDS”)技术模式的阵列基板。
本公开实施例中，遮挡图形102包括上述实施例中的第一遮挡图形和第二遮挡图形，用于对贯通第一绝缘层107和栅绝缘层105的过孔1、第三绝缘层109上的过孔2，以及第二绝缘层111上的过孔3进行遮挡。其中，过孔1用于连接源漏金属层108和有源层104，过孔3用于连接像素电极层112和源漏金属层108，由于本公开实施例中，过孔2大于过孔3，过孔3位于过孔2中，因此，遮挡图形102只要遮挡住过孔2即可遮挡住过孔3。
本公开实施例中，有源层包括位于源电极1081和漏电极1082之间且与所述栅电极重叠的沟道区域(如图2所示的区域109)，遮挡图形102还用于遮挡有源层104的沟道区域，避免背光对有源层104的沟道区域造成影响。
在一些实施例中，遮挡图形可以设置在衬底基板的上方，有源层的下方。具体地，遮挡图形102位于衬底基板101的上方，缓冲层103覆盖该遮挡图形102，有源层104设置在缓冲层103上方。在一些实施例中，可以在过孔或沟道区域靠近背光模组的一侧设置遮挡图形。
需要说明的是，可以为阵列基板的一个过孔在衬底基板上设置相应的遮挡图形，也可以为多个过孔分别设置多个独立的遮挡图形，还可以为多个过孔(如上述过孔2和过孔3)设置一个遮挡图形。本公开实施例对此不做限制。
上述实施例中的阵列基板为顶栅型阵列基板，当然，在本公开的其他一些实施例中，阵列基板也可以为底栅型阵列基板。
上述实施例中的阵列基板中，公共电极层110和像素电极层112的位置可以互换。
除非另作定义，本公开中使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种显示装置，包括阵列基板，所述阵列基板包括衬底基板、绝缘层、过孔和第一遮挡图形；
    其中，所述绝缘层设置在所述衬底基板上，所述过孔贯穿所述绝缘层；以及所述第一遮挡图形在所述衬底基板上的正投影覆盖所述过孔在所述衬底基板上的正投影的部分或全部。
  2. 根据权利要求1所述的显示装置，其中，所述过孔在所述衬底基板上的正投影与所述第一遮挡图形在所述衬底基板上的正投影完全重叠。
  3. 根据权利要求1或2所述的显示装置，还包括对向基板，
    其中所述对向基板包括衬底基板和黑矩阵，所述对向基板的对应所述过孔的区域在所述对向基板的衬底基板上的正投影与所述黑矩阵在所述对向基板上的衬底基板上的正投影不重叠。
  4. 根据权利要求1-3任一项所述的显示装置，所述阵列基板还包括：源漏金属层、有源层和第一绝缘层，
    其中第一绝缘层位于所述源漏金属层和有源层之间，所述贯穿有过孔的绝缘层包括所述第一绝缘层。
  5. 根据权利要求1-3任一项所述的显示装置，所述阵列基板还包括：源漏金属层、第一透明电极层和第二绝缘层，
    其中所述第二绝缘层位于所述源漏金属层和所述第一透明电极层之间，以及所述贯穿有过孔的绝缘层包括所述第二绝缘层。
  6. 根据权利要求5所述的显示装置，所述阵列基板还包括：第二透明电极层，
    其中所述第二绝缘层覆盖所述第二透明电极层；以及
    所述第一透明电极层为像素电极层以及所述第二透明电极层为公共电极层，或者所述第一透明电极层为公共电极层以及所述第二透明电极层为像素电极层。
  7. 根据权利要求1-6任一项所述的显示装置，所述阵列基板还包括：栅金属层、源漏金属层、有源层和第二遮挡图形，
    其中所述源漏金属层包括源电极和漏电极，所述栅金属层包括栅电极，所 述有源层包括位于所述源电极和所述漏电极之间且与所述栅电极重叠的沟道区域，所述沟道区域在所述衬底基板上的正投影完全位于所述第二遮挡图形在所述衬底基板上的正投影区域内，所述第二遮挡图形位于所述有源层的靠近所述衬底基板的一侧。
  8. 根据权利要求7所述的阵列基板，其中，所述沟道区域在所述衬底基板上的正投影与所述第二遮挡图形在所述衬底基板上的正投影完全重叠。
  9. 一种阵列基板，包括：
    衬底基板；
    绝缘层；
    过孔；以及
    第一遮挡图形；
    其中，所述绝缘层设置在所述衬底基板上，所述过孔贯穿所述绝缘层；以及
    所述第一遮挡图形在所述衬底基板上的正投影覆盖所述过孔在所述衬底基板上的正投影的部分或全部。
  10. 根据权利要求9所述的阵列基板，其中，所述过孔在所述衬底基板上的正投影与所述第一遮挡图形在所述衬底基板上的正投影完全重叠。
  11. 根据权利要求9或10所述的阵列基板，其中，所述过孔和所述第一遮挡图形具有规则的形状，所述过孔的中心与所述第一遮挡图形的中心在所述衬底基板上的正投影重合。
  12. 根据权利要求9-11任一项所述的阵列基板，还包括：源漏金属层、有源层和第一绝缘层，其中第一绝缘层位于所述源漏金属层和有源层之间，所述贯穿有过孔的绝缘层包括所述第一绝缘层。
  13. 根据权利要求12所述的阵列基板，还包括缓冲层，其中所述第一遮挡图形位于所述衬底基板上，所述缓冲层覆盖所述第一遮挡图形，所述有源层位于所述缓冲层上。
  14. 根据权利要求9-11任一项所述的阵列基板，还包括：
    源漏金属层、第一透明电极层和第二绝缘层，
    其中所述第二绝缘层位于所述源漏金属层和所述第一透明电极层之间，以 及所述贯穿有过孔的绝缘层包括所述第二绝缘层。
  15. 根据权利要求14所述的阵列基板，还包括：
    第二透明电极层，
    其中所述第二绝缘层覆盖所述第二透明电极层；以及
    所述第一透明电极层为像素电极层以及所述第二透明电极层为公共电极层，或者所述第一透明电极层为公共电极层以及所述第二透明电极层为像素电极层。
  16. 根据权利要求9-15任一项所述的阵列基板，还包括：
    栅金属层、源漏金属层、有源层和第二遮挡图形，
    其中所述源漏金属层包括源电极和漏电极，所述栅金属层包括栅电极，所述有源层包括位于所述源电极和所述漏电极之间且与所述栅电极重叠的沟道区域，所述沟道区域在所述衬底基板上的正投影完全位于所述第二遮挡图形在所述衬底基板上的正投影区域内，所述第二遮挡图形位于所述有源层的靠近所述衬底基板的一侧。
  17. 根据权利要求16所述的阵列基板，其中，所述沟道区域在所述衬底基板上的正投影与所述第二遮挡图形在所述衬底基板上的正投影完全重叠。
  18. 根据权利要求16或17所述的阵列基板，其中，所述第一遮挡图形和所述第二遮挡图形同层同材料设置。
  19. 根据权利要求1-11任一项所述的阵列基板，其中，
    所述绝缘层贯穿有分别对应于多个相互独立的所述第一遮挡图形的多个过孔，所述多个过孔在所述衬底基板上的正投影互不重叠；或者
    所述绝缘层贯穿有对应一个所述第一遮挡图形的多个过孔，所述多个过孔包括第一过孔，所述多个过孔除所述第一过孔之外的过孔在所述衬底基板上的正投影均位于所述第一过孔在所述衬底基板上的正投影内，所述第一过孔在所述衬底基板上的正投影完全位于所述第一遮挡图形在所述衬底基板上的正投影内。
  20. 一种阵列基板的制作方法，包括：
    提供一衬底基板；
    在所述衬底基板上形成第一遮挡图形、绝缘层和过孔，其中，所述过孔贯 穿所述绝缘层，所述第一遮挡图形在所述衬底基板上的正投影覆盖所述过孔在所述衬底基板上的正投影的部分或全部。
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