WO2017004948A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

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Publication number
WO2017004948A1
WO2017004948A1 PCT/CN2015/098269 CN2015098269W WO2017004948A1 WO 2017004948 A1 WO2017004948 A1 WO 2017004948A1 CN 2015098269 W CN2015098269 W CN 2015098269W WO 2017004948 A1 WO2017004948 A1 WO 2017004948A1
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Prior art keywords
signal line
common electrode
array substrate
opening
line
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PCT/CN2015/098269
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English (en)
French (fr)
Inventor
姜文博
韩帅
王世君
吕振华
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/032,240 priority Critical patent/US20170168354A1/en
Priority to EP15851623.7A priority patent/EP3321730B1/en
Publication of WO2017004948A1 publication Critical patent/WO2017004948A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
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    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • At least one embodiment of the present invention is directed to an array substrate, a method of fabricating the same, and a display device.
  • Liquid crystal displays have been widely used due to their low power consumption, large amount of display information, easy colorization, no radiation, no pollution.
  • the liquid crystal display includes an array substrate and an opposite substrate (for example, a color filter substrate) opposed to each other, and a liquid crystal layer disposed between the array substrate and the opposite substrate, and a voltage is applied to the common electrode and the pixel electrode to control deflection of the liquid crystal molecules. And then control the light.
  • IPS Plane Switching
  • ADS Advanced-Super Dimension Switch
  • the pixel electrode and the common electrode are respectively disposed in different film layers of the array substrate, the electric field generated by the edge of the slit electrode in the same plane, and the electric field generated between the slit electrode layer and the plate electrode layer.
  • a multi-dimensional electric field is formed to cause rotation of all aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the slit electrode.
  • the pixel electrode and the common electrode are located in the same film layer of the array substrate, and brightness control is realized by controlling the liquid crystal molecules to rotate in the plane.
  • At least one embodiment of the present invention provides an array substrate, a method of fabricating the same, and a display device for reducing cross-color defects on both sides of a data line or a gate line caused by alignment and the like.
  • At least one embodiment of the present invention provides an array substrate including a first signal line extending in a first direction, and a common electrode; the first signal line being a gate line or a data line; the common electrode being located at Above the first signal line, at least one first opening is disposed in the common electrode, and the at least one first opening has an overlapping portion with an orthographic projection of the first signal line on a surface of the common electrode; And, the common electrode includes a first portion overlapping the orthographic projection portion of the first signal line and a second portion outside the orthographic projection of the first signal line, The second part is connected to the first part and arranged in the same layer.
  • At least one embodiment of the present invention also provides a display device comprising the array substrate described above.
  • At least one embodiment of the present invention also provides a method of fabricating an array substrate, comprising: forming a first signal line extending in a first direction, the first signal line being a gate line or a data line; and patterning by one time Forming a common electrode over the first signal line and at least one first opening disposed in the common electrode such that the at least one first opening and the first signal line are at the common electrode
  • the orthographic projection on the face has an overlapping portion
  • the common electrode includes a first portion overlapping the orthographic projection portion of the first signal line and a portion other than the orthographic projection of the first signal line In two parts, the second part is connected to the first part and arranged in the same layer.
  • FIG. 1 is a partial cross-sectional view of an ADS mode array substrate
  • 2a is a top plan view of a data line, a common electrode, and a pixel electrode in an array substrate;
  • Figure 2b is a schematic cross-sectional view taken along line AA' of Figure 2a;
  • 2c is a schematic diagram showing the principle of generating a cross color when the black matrix and the data line are offset;
  • 3a is a partial cross-sectional view of an ADS mode array substrate according to an embodiment of the present invention.
  • 3b is a top plan view showing a first opening of a common electrode in an ADS mode array substrate at a position corresponding to a first signal line according to an embodiment of the present invention
  • Figure 4a is a schematic cross-sectional view taken along line AA' of Figure 3b;
  • Figure 4b is a schematic cross-sectional view taken along line BB' of Figure 3b;
  • FIG. 5 is a schematic diagram of a principle for avoiding pixel cross-color on both sides of a data line according to an embodiment of the present invention
  • FIG. 6 is a schematic top plan view showing at least one edge of a first opening in a matrix substrate in a line shape according to an embodiment of the present disclosure
  • FIG. 7 is a top plan view showing a first opening and a second opening respectively disposed at positions corresponding to the first signal line and the second signal line in the array substrate according to an embodiment of the present disclosure
  • FIG. 8 is a schematic structural view of a gate line and a data line in an array substrate
  • FIG. 9 is a schematic top plan view of an array substrate including a color filter layer according to an embodiment of the present disclosure.
  • 10a is a partial cross-sectional view of an IPS mode array substrate according to an embodiment of the present invention.
  • FIG. 10b is a schematic top plan view showing a first opening of a common electrode in a position corresponding to a first signal line in an IPS mode array substrate according to an embodiment of the present disclosure
  • Figure 11 is a cross-sectional view taken along line AA' of Figure 10b;
  • FIG. 12 is a cross-sectional view of a display device according to an embodiment of the present invention.
  • FIG. 1 is a partial cross-sectional view of an ADS mode array substrate.
  • a thin film transistor 100, a first insulating layer 200, a common electrode 300, a second insulating layer 400, and a pixel electrode 500 are sequentially disposed on a base substrate.
  • the thin film transistor 100 includes a gate 110, a gate insulating layer 120 disposed on the gate 110, and a gate insulating layer 120.
  • the source layer 140 and the active layer 140 A source 131 and a drain 132 that are in contact with the active layer 140.
  • the fabrication process of the array substrate as shown in FIG. 1 may include the following steps 1 to 8.
  • Step 1 A gate electrode 110 and a plurality of gate lines (not shown in FIG. 1) are formed on the base substrate by a first patterning process (ie, a process of forming a set pattern).
  • Step 2 A gate insulating layer 120 covering the gate electrode 110 and the gate line is formed by a second patterning process.
  • Step 3 An active layer 140 is formed on the gate insulating layer 120 by a third patterning process.
  • Step 4 A source 131 and a drain 132 on the active layer 140 and in contact therewith, and a plurality of data lines 133 are formed by the fourth patterning process.
  • Step 5 Through the fifth patterning process, a first insulating layer 200 covering the source electrode 131 and the drain electrode 132, and a first insulating layer via hole located in the first insulating layer 200 are formed.
  • Step 6 A common electrode 300 and a common electrode line (not shown in FIG. 1) connected to the common electrode 300 are formed on the first insulating layer 200 by the sixth patterning process.
  • Step 7 forming a second insulating layer 400 and a second insulating layer via hole in the second insulating layer 400 through a seventh patterning process, and the second insulating layer via is in communication with the first insulating layer via.
  • Step 8 forming a pixel electrode 500 on the second insulating layer 400 by the eighth patterning process, and passing the pixel electrode 500 through the first insulating layer via and the second insulating layer via and the film formed in the above steps 5 and 7.
  • the drain 132 of the transistor 100 is connected.
  • a black matrix (BM) is disposed in the liquid crystal display, for example, the black matrix corresponds to a gate line and a data line on the array substrate.
  • the inventors of the present application noticed that the current high PPI (Pixels Per Inch) product has a narrower black matrix due to the need to increase the aperture ratio, but is currently used to pair the gate line/data line with the black matrix. The bit position of the device is limited, which can cause alignment deviation and form a cross color.
  • the common electrode 300 may be a plate electrode disposed above the data line 133.
  • the pixel electrode 500 disposed above the common electrode 300 is a slit electrode, and an electric field is formed between the pixel electrode 500 and the common electrode 300.
  • Drive liquid crystal light transmission The electric field along the AA' direction in FIG. 2a above the data line 133 is shown by the dashed line in FIG. 2b; the two sides of the data line 133 are the pixel a and the pixel b, respectively, assuming that the array substrate and the opposite substrate are assembled into a liquid crystal display.
  • the pixel a corresponds to the red filter pattern R
  • the pixel b corresponds to the green filter pattern G.
  • FIG. 2c when the black matrix in the liquid crystal display is shifted to the left (ie, the position where the a pixel is located), the side view angle can be viewed. Filter through b pixels The pattern sees the light transmitted by the a pixel and vice versa. If, due to equipment reasons, the alignment accuracy between the black matrix and the data line has reached its limit, it must be optimized in design.
  • At least one embodiment of the present invention provides an array substrate, a method of fabricating the same, and a display device.
  • the array substrate includes a first signal line extending in a first direction and a common electrode located above the first signal line; the first signal line is a gate line or a data line; and at least one first opening is disposed in the common electrode, the at least a first opening overlaps with an orthographic projection of the first signal line on a face of the common electrode; and the common electrode includes a first portion overlapping the orthographic projection portion of the first signal line and an orthographic projection of the first signal line
  • the second part of the outer part is connected to the first part and arranged in the same layer.
  • the liquid crystal between the pixels on both sides of the data line or the gate line is disturbed, so that the liquid crystal cannot be smoothly transmitted, so as to function in the array.
  • a part of the black matrix is added to the substrate to reduce the poor color of the data lines or the two sides of the gate lines caused by the alignment and other factors.
  • an array substrate provided in this embodiment includes a first signal line 71 (for example, a data line 13c) extending in a first direction (shown by an arrow in FIG. 3b), as shown in FIG. 3a.
  • a common electrode 30 located above the first signal line 71 ie, on a side of the first signal line 71 away from the base substrate 01a
  • the common electrode 30 is provided with at least one first opening 31, the at least Each of the first openings 31 has an overlapping portion with the orthographic projection of the first signal line 71 on the face of the common electrode 30, that is, each of the at least one first opening 31 is perpendicular to the first signal line 71. overlap.
  • the common electrode 30 includes a first portion 30a overlapping the orthographic projection portion of the first signal line 71 and a second portion 30b outside the orthographic projection of the first signal line 71, the second portion 30b and the first portion 30a is connected and set in the same layer. That is, the common electrode 30 corresponding to the first signal line 71 includes the first portion 30a and the second portion 30b which are integrally formed.
  • the pixel electrode 50 and the common electrode 30 are disposed separately as an example.
  • the array substrate provided in this embodiment may be an ADS mode array substrate.
  • the pixel electrode 50 may be a slit electrode located above the common electrode 30, as shown in FIGS. 3a and 3b, and the common electrode 30 is a plate-like structure.
  • the array substrate provided in this embodiment may include one The entire surface of the common electrode 30; alternatively, the array substrate may also include a plurality of plate-like common electrodes 30, each of which includes the first portion 30a and the second portion 30b described above.
  • the common electrode may be a slit electrode located above the plate-shaped pixel electrode.
  • FIG. 3a illustrates the thin film transistor 10 as a bottom gate top contact structure, that is, the thin film transistor 10 includes a gate electrode 11 and is disposed on the gate electrode 11.
  • the pixel electrode 50 is connected to the drain 13b through the first insulating layer via 21 in the first insulating layer 20 and the via 41 in the second insulating layer 40.
  • the thin film transistor 10 can also adopt a top gate structure, that is, the gate electrode 11 is disposed above the active layer 14; or, the thin film transistor 10 can also adopt a bottom contact structure, that is, the source electrode 13a and the drain electrode 13b are disposed on the active layer.
  • an insulating layer may be further disposed between the source 13a/drain 13b and the active layer 14, and the source 13a and the drain 13b are in contact with the active layer 14 through via holes in the insulating layer.
  • the first signal line 71 may also be a gate line, and the gate line is disposed in the same layer as the gate electrode 11. 3a is described by taking the first signal line 71 as the data line 13c provided in the same layer as the source 13a and the drain 13b.
  • At least one first opening 31 is disposed at a position of the common electrode 30 corresponding to the first signal line 71 such that the first signal of the common electrode 30 at the edge of each of the first openings 31 and below the first opening 31
  • the line 71 forms an electric field, which is an irregular electric field, so that the liquid crystal at the first opening 31 is disordered and does not have the ability to transmit light, that is, a so-called "dark area”.
  • FIG. 4a is a schematic cross-sectional view taken along line AA' of FIG. 3b
  • FIG. 4b is a schematic cross-sectional view taken along line BB' of FIG. 3b.
  • a transverse electric field is formed between the common electrode 30 and the first signal line 71
  • a longitudinal electric field is formed between the common electrode 30 and the first signal line 71. Therefore, the direction of the electric field at each position of the first opening 31 is different, so that the liquid crystal arrangement is disordered here, forming a dark area.
  • This is equivalent to forming a three-dimensional barrier in the box to separate adjacent two pixels located on both sides of the first signal line so that the light of each other does not interfere with each other, thereby avoiding the cross-color defect at the side viewing angle to the utmost.
  • FIG. 3b is only described by taking the shape of the first opening 31 along the surface of the common electrode 30 as a rectangle.
  • the shape of the first opening 31 along the surface on which the common electrode 30 is located is other shapes, the direction of the electric field formed between the common electrode 30 and the first signal line 71 may be in other directions.
  • the shape of the first opening may be any shape.
  • the shape of the first opening 31 along the face on which the common electrode 30 is located may include a polygon (eg, a triangle, a rectangle, etc.), a circle, or an ellipse.
  • the polygon, circle or ellipse here may be a figure that approximates a polygon, a circle, or an ellipse.
  • pixels on the first side and the second side of the first signal line 71 respectively correspond to different color filter patterns (for example, a red filter pattern).
  • R and the green green light pattern G when the black matrix BM corresponding to the first signal line 71 is shifted toward the first side of the first signal line 71 (ie, the left side of the first signal line 71 in FIG. 5), At least one first opening 31 is formed in the common electrode 30, and therefore, it is difficult to see light from the first side on the second side of the first signal line 71 (i.e., the right side of the first signal line 71 in Fig. 5).
  • the first opening 31 is formed in the common electrode 30, for example, the first opening 31 can be formed at the position by removing the common electrode material at the preset position when the common electrode 30 is fabricated, so the first opening 31 can be closed Opening.
  • the size of each of the first openings 31 in the first direction is not excessive.
  • a plurality of first openings 31 may be disposed in the common electrode 30.
  • the portion of the common electrode 30 corresponding to the first signal line 71 is divided by the plurality of openings, and the larger the number of the first openings, the smaller the size of each of the first openings in the first direction, thereby facilitating each of the first
  • the liquid crystal at the location of an opening is disordered to form a dark area.
  • the number of the first openings may correspond to the first signal line according to the material of the liquid crystal and the common electrode.
  • the portion is designed along the actual size of the first direction to avoid a large dark space formed between the first opening and the first signal line due to the large size of the first opening in the first direction. Too obvious.
  • the embodiment does not limit the number and size of the first openings, so that the common electrode forms an electric field with a different direction between each of the first openings and the first signal line below the first opening, so that the first opening It is enough to form a dark area.
  • the dimension of the first opening 31 in the first direction may be less than or equal to the dimension of the first opening 31 in a direction perpendicular to the first direction. This can avoid that the size of the first opening in the first direction is too large, causing the common electrode to form a relatively regular electric field between the first opening and the first signal line.
  • the first opening 31 may be axisymmetric with respect to the first signal line 71 as shown in FIG. 3b. This makes the light rays on both sides of the first signal line 71 more uniform.
  • the common electrode 30 may further include a third portion 30c located outside the orthographic projection of the first signal line 71, as shown in FIG. 3b, the third portion 30c is connected to the first portion 30a and disposed in the same layer, and The third portion 30c and the second portion 30b are respectively located on opposite sides of the first portion 30a. That is, the common electrode 30 corresponding to the first signal line 71 includes the first portion 30a, the second portion 30b, and the third portion 30c which are integrally formed, and the second portion 30b and the third portion 30c are respectively located at the first signal line 71 One side and second side.
  • the array substrate provided in this embodiment is different from the first embodiment in that at least one first opening 31 includes at least one edge 311 extending substantially in a first direction, and the edge 311 may be a fold line (as shown in FIG. 6) or wavy.
  • the common electrode 30 can be compared with the first signal line 71 at the edge 311 of the first opening 31 as much as possible.
  • a disordered electric field to facilitate the formation of dark areas.
  • the array substrate provided in this embodiment further includes a second signal line 72 extending in the second direction. As shown in FIG. 7, the second direction intersects the first direction, and the common electrode 30 is further disposed. At least one second opening 32, each of the at least one second opening 32 has an overlapping portion with the orthographic projection of the second signal line 72 on the face of the common electrode 30, that is, each of the at least one first opening 31 Both are vertically overlapped with the second signal line 72.
  • the first signal line 71 may be the gate line 11a
  • the second signal line 72 may be the data line 13c
  • the first signal line 71 may be the data line 13c.
  • the two signal lines 72 are gate lines 11a.
  • the array substrate provided in this embodiment differs from the array substrate provided in the first embodiment in that the array substrate further includes a color filter layer, that is, the array substrate adopts COA (Color Filter On Array) technology.
  • COA Color Filter On Array
  • the color filter layer 80 includes a plurality of columns of filter patterns (for example, a red filter pattern R, a green filter pattern G, and a blue filter pattern B), and each column of filter patterns is along the first Arranging in the direction, the color of the same column of filter patterns is the same or different, and the filter patterns corresponding to the positions of the two columns of filter patterns adjacent to each of the first signal lines 71 and located on both sides of the first signal line 71 have different colour.
  • filter patterns for example, a red filter pattern R, a green filter pattern G, and a blue filter pattern B
  • FIG. 9 only uses the first signal line 71 as the data line, and the adjacent two columns of filter patterns respectively located on the two sides of the data line 13c have different colors and are respectively located on two sides of the gate line 11a.
  • the color of the row filter pattern is the same as an example.
  • the filter pattern included in the color filter layer may also adopt other arrangements commonly used in the art, which will not be described in detail in this embodiment.
  • the array substrate provided in this embodiment is different from the array substrate provided in the first embodiment in that, as shown in FIG. 10a and FIG. 10b, the pixel electrode 50 is disposed in the same layer as the common electrode 30.
  • the common electrode 30 may include The plurality of strip-like sub-electrodes 3a
  • the pixel electrode 50 may include a plurality of strip-shaped sub-pixel electrodes 5a
  • the strip-shaped sub-common electrodes 3a and the strip-shaped sub-pixel electrodes 5a are alternately disposed. That is, the array substrate provided in this embodiment is an IPS mode array substrate.
  • the strip-shaped sub-pixel electrodes 5a included in the pixel electrode 50 extend substantially in the first direction, and are connected together by the connecting portion 5b.
  • the strip-like sub-common electrodes 3a of the common electrode 30 extend substantially in the first direction and are connected together by the connecting portion 3b.
  • the strip-shaped sub-common electrode 3a of the common electrode 30 may have a different dimension in the first direction and/or a dimension perpendicular to the first direction; to facilitate formation of at least one first opening 31 between the common electrode 30 and the first signal line 71,
  • the first opening 31 may be disposed in the sub-common electrode 3a having a larger size perpendicular to the first direction, in which case the sub-common electrode 3a is formed between the first opening 31 and the first signal line 71
  • the electric field along the AA' direction is shown in Figure 11.
  • the thin film transistor 10 is further disposed in the array substrate provided in this embodiment.
  • the array substrate provided in this embodiment.
  • the repeated description is omitted.
  • the first embodiment or the fifth embodiment may be combined with at least one of the second to fourth embodiments.
  • the embodiment provides a display device comprising the array substrate provided by any one of the above embodiments or a combination thereof.
  • the display device provided in this embodiment may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, a touch panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, a touch panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device provided in this embodiment may be a liquid crystal display device including an array substrate 01 and a counter substrate 02 opposed to each other, and a liquid crystal layer disposed therebetween. 03.
  • the display device provided in this embodiment further includes a color filter layer 80 ′, for example, the color filter layer 80 ′ includes a plurality of columns of filter patterns (eg, a red filter pattern R, a green filter pattern G, and a blue filter pattern). B), each column of the filter patterns are arranged in the first direction, and the colors of the same column of filter patterns are the same or different, and the two columns of the filter pattern adjacent to the first signal line 71 and located on both sides of the first signal line 71 are filtered. The color of the filter pattern corresponding to the position in the light pattern is different.
  • the color filter layer 80 ′ includes a plurality of columns of filter patterns (eg, a red filter pattern R, a green filter pattern G, and a blue filter pattern). B), each column of the filter patterns are arranged in the first direction, and the colors of the same column of filter patterns are the same or different, and the two columns of the filter pattern adjacent to the first signal line 71 and located on both sides of the first signal line 71 are filtered. The
  • the color filter layer may be disposed on the array substrate 01 or the opposite substrate 02. 12 is only an example in which the color filter layer 80' is disposed on the counter substrate 02.
  • the counter substrate 02 may be referred to as a color filter substrate.
  • the embodiment provides a method for fabricating an array substrate according to any one of the above embodiments or a combination thereof, the method may include: forming a first signal line extending along a first direction; and forming the first by a patterning process
  • the common electrode above the signal line and the at least one first opening of the common electrode have an overlap of the at least one first opening and the orthographic projection of the first signal line on the face of the common electrode.
  • the common electrode includes a first portion overlapping the orthographic projection portion of the first signal line and a second portion outside the orthographic projection of the first signal line, and the second portion is connected to the first portion and Layer settings.
  • the first signal line may be a gate line or a data line.
  • the manufacturing method provided in this embodiment may further include: forming a second signal line extending in the second direction before or after forming the first signal line, in the step, the second direction intersects the first direction; forming
  • the common electrode may further include forming at least one second opening disposed in the common electrode such that the at least one second opening overlaps the orthographic projection of the second signal line on the face of the common electrode.
  • the pixel electrode may be formed by a patterning process different from the patterning process of forming the common electrode, in which case the pixel electrode may be located above the common electrode or under the common electrode.
  • the array substrate can adopt an ADS mode.
  • forming the common electrode may further include forming a pixel electrode.
  • the common electrode may include a plurality of strip-shaped sub-common electrodes
  • the pixel electrode may include a plurality of strip-shaped sub-pixel electrodes
  • the strip-shaped sub-common electrodes and the strip-shaped sub-pixel electrodes are alternately disposed, that is, the array substrate adopts IPS mode.
  • the manufacturing method may include the following steps 71 to 78.
  • Step 71 The gate electrode 11 and the gate line (the gate line is not shown in FIG. 3a) are formed on the base substrate 01a by the first patterning process.
  • Step 72 Form a gate insulating layer 12 covering the gate electrode 11 and the gate line by a second patterning process.
  • Step 73 The active layer 14 is formed on the gate insulating layer 12 by the third patterning process.
  • Step 74 Forming the source 13a and the drain 13b on the active layer 14 and in contact therewith, and the data line 13c by the fourth patterning process.
  • Step 75 A first insulating layer 20 covering the source electrode 13a, the drain electrode 13b and the data line 13c, and a first insulating layer via hole 21 in the first insulating layer 20 are formed by the fifth patterning process.
  • Step 76 forming a common electrode 30 on the first insulating layer 20, at least one first opening 31 located in the common electrode 30 and vertically overlapping the data line 13c, and being connected to the common electrode 30 by the sixth patterning process Common electrode line (not shown in Figure 3a).
  • Step 77 forming a second insulating layer 40 on the common electrode 30 and a second insulating layer via 41 in the second insulating layer 40 through the seventh patterning process, the second insulating layer via 41 and the first insulating layer The vias 21 are connected.
  • Step 78 forming a pixel electrode 50 on the second insulating layer 40 by the eighth patterning process, and passing the pixel electrode 50 through the first insulating layer via 21 and the second insulating layer via 41 formed in the above steps 75 and 77. It is connected to the drain 13b of the thin film transistor 10.
  • the common electrode and the common electrode line can also be disposed in different layers.
  • the common electrode line may also be formed simultaneously with the gate line in step 71, in which case the common electrode formed in step 76 may be connected to the common electrode line through a via in the first insulating layer 20.
  • the first signal line, the second signal line, the first opening, the second opening, and the like in the array substrate may be referred to the related descriptions in Embodiments 1 through 5. No longer.

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Abstract

一种阵列基板及其制作方法和显示装置，该阵列基板包括沿第一方向延伸的第一信号线(71)、以及位于所述第一信号线(71)之上且设置有第一开口(31)的公共电极(30)；所述第一开口(31)与所述第一信号线(71)在所述公共电极(30)所在面上的正投影有重叠部分；所述公共电极(30)包括与所述第一信号线(71)的所述正投影部分重叠的第一部分(30a)、以及位于所述第一信号线(71)的所述正投影之外且与所述第一部分(30a)连接且同层设置的第二部分(30b)。该阵列基板可减轻数据线(13c)或栅线(11a)两侧串色不良。

Description

阵列基板及其制作方法和显示装置 技术领域
本发明的至少一个实施例涉及一种阵列基板及其制作方法和显示装置。
背景技术
液晶显示器由于功耗低、显示信息量大、易于彩色化、无辐射、无污染等优点而得到了广泛的应用。
液晶显示器包括相互对置的阵列基板和对置基板(例如彩膜基板)，以及设置于阵列基板和对置基板之间的液晶层，通过对公共电极和像素电极加载电压以控制液晶分子的偏转，进而控制光线。平面转换(IPS，In Plane Switching)模式和高级超维场开关(ADS，Advanced-super Dimension Switch)模式液晶显示器是两种主流的水平电场型液晶显示器。
在ADS模式液晶显示器中，像素电极和公共电极分别设置在阵列基板的不同膜层中，通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层之间产生的电场形成多维电场，使液晶盒内狭缝电极间以及狭缝电极正上方所有取向的液晶分子都能够产生旋转。
在IPS模式液晶显示器中，像素电极和公共电极位于阵列基板的同一膜层中，通过控制液晶分子在平面内转动实现亮度控制。
发明内容
本发明的至少一个实施例提供了一种阵列基板及其制作方法和显示装置，以减轻对位等因素造成的数据线或栅线两侧串色不良。
本发明的至少一个实施例提供了一种阵列基板，其包括沿第一方向延伸的第一信号线、以及公共电极；所述第一信号线为栅线或数据线；所述公共电极位于所述第一信号线之上，所述公共电极中设置有至少一个第一开口，所述至少一个第一开口与所述第一信号线在所述公共电极所在面上的正投影有重叠部分；并且，所述公共电极包括与所述第一信号线的所述正投影部分重叠的第一部分以及位于所述第一信号线的所述正投影之外的第二部分，所 述第二部分与所述第一部分连接且同层设置。
本发明的至少一个实施例还提供了一种显示装置，其包括以上所述的阵列基板。
本发明的至少一个实施例还提供了一种阵列基板的制作方法，其包括：形成沿第一方向延伸的第一信号线，所述第一信号线为栅线或数据线；以及通过一次构图工艺形成位于所述第一信号线之上的公共电极以及设置于所述公共电极中的至少一个第一开口，使所述至少一个第一开口与所述第一信号线在所述公共电极所在面上的正投影有重叠部分，并且，所述公共电极包括与所述第一信号线的所述正投影部分重叠的第一部分以及位于所述第一信号线的所述正投影之外的第二部分，所述第二部分与所述第一部分连接且同层设置。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种ADS模式阵列基板的局部剖面示意图；
图2a为一种阵列基板中的数据线、公共电极和像素电极的俯视示意图；
图2b为沿图2a中AA'方向的剖面示意图；
图2c为黑矩阵与数据线对位发生偏移时产生串色的原理示意图；
图3a为本发明实施例提供的一种ADS模式阵列基板的局部剖面示意图；
图3b为本发明实施例提供的一种ADS模式阵列基板中公共电极在对应第一信号线的位置处设置有第一开口的俯视示意图；
图4a为沿图3b中AA'方向的剖面示意图；
图4b为沿图3b中BB'方向的剖面示意图；
图5为本发明实施例避免数据线两侧的像素串色的原理示意图；
图6为本发明实施例提供的阵列基板中第一开口的至少一个边缘为折线形的俯视示意图；
图7为本发明实施例提供的阵列基板中公共电极在对应第一信号线和第二信号线的位置处分别设置有第一开口和第二开口的俯视示意图；
图8为阵列基板中栅线和数据线的结构示意图；
图9为本发明实施例提供的阵列基板包括彩色滤光层的俯视示意图；
图10a为本发明实施例提供的一种IPS模式阵列基板的局部剖面示意图；
图10b为本发明实施例提供的一种IPS模式阵列基板中公共电极在对应第一信号线的位置处设置有第一开口的俯视示意图；
图11为沿图10b中AA'方向的剖面示意图；
图12为本发明实施例提供的显示装置的剖视示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种ADS模式阵列基板的局部剖视示意图。如图1所示，在衬底基板上依次设置有薄膜晶体管100、第一绝缘层200、公共电极300、第二绝缘层400以及像素电极500。图1以该薄膜晶体管100采用底栅顶接触结构为例进行说明，即，该薄膜晶体管100包括栅极110、设置于栅极110上的栅绝缘层120、设置于栅绝缘层120上的有源层140、以及位于有源层140 上且与有源层140接触的源极131和漏极132。
例如，如图1所示的阵列基板的制作过程可以包括以下步骤1～步骤8。
步骤1：通过第一次构图工艺(即，形成设定图案的工艺)，在衬底基板上形成栅极110和多条栅线(图1中未示出)。
步骤2：通过第二次构图工艺，形成覆盖栅极110和栅线的栅绝缘层120。
步骤3：通过第三次构图工艺，在栅绝缘层120上形成有源层140。
步骤4：通过第四次构图工艺，形成位于有源层140上并且与其接触的源极131和漏极132，以及多条数据线133。
步骤5：通过第五次构图工艺，形成覆盖源极131和漏极132的第一绝缘层200，以及位于第一绝缘层200中的第一绝缘层过孔。
步骤6：通过第六次构图工艺，在第一绝缘层200上形成公共电极300以及与公共电极300连接的公共电极线(图1中未示出)。
步骤7：通过第七次构图工艺，形成第二绝缘层400以及位于第二绝缘层400中的第二绝缘层过孔，第二绝缘层过孔与第一绝缘层过孔连通。
步骤8：通过第八次构图工艺，在第二绝缘层400上形成像素电极500，使像素电极500通过上述步骤5和7中形成的第一绝缘层过孔和第二绝缘层过孔与薄膜晶体管100的漏极132连接。
液晶显示器中设置有黑矩阵(Black Matrix，BM)，例如该黑矩阵与阵列基板上的栅线和数据线对应。在研究中，本申请的发明人注意到，目前高PPI(Pixels Per Inch)产品由于增加开口率的需要，黑矩阵制作得较窄，但是目前用于将栅线/数据线与黑矩阵进行对位的设备的对位能力有限，这可造成对位偏差，形成串色。
图2a为一种阵列基板上的数据线、公共电极与像素电极的俯视示意图。如图2a所示，公共电极300可以为板状电极，设置于数据线133的上方，设置在公共电极300的上方的像素电极500为狭缝电极，像素电极500和公共电极300之间形成电场驱动液晶透光。数据线133上方的沿图2a中AA'方向的电场如图2b中的虚线所示；数据线133的两侧分别为像素a和像素b，假设将阵列基板与对置基板组装成液晶显示器之后，像素a对应红色滤光图案R，像素b对应绿色滤光图案G，如图2c所示，当液晶显示器中的黑矩阵向左(即a像素所在位置)偏移时，侧视角观看时能够透过b像素对应的滤光 图案看到a像素透过的光，反之亦然。如果由于设备原因，针对黑矩阵与数据线之间的对位精度已经达到极限，则必须在设计上进行优化。
本发明的至少一个实施例提供一种阵列基板及其制作方法和显示装置。该阵列基板包括沿第一方向延伸的第一信号线以及位于第一信号线之上的公共电极；第一信号线为栅线或数据线；公共电极中设置有至少一个第一开口，该至少一个第一开口与第一信号线在公共电极所在面上的正投影有重叠部分；并且，公共电极包括与第一信号线的正投影部分重叠的第一部分以及位于第一信号线的正投影之外的第二部分，第二部分与第一部分连接且同层设置。本发明实施例通过在数据线或栅线上方的公共电极中形成至少一个开口，将数据线或栅线两侧的像素之间的液晶打乱，使其不能顺利透光，以起到在阵列基板上增加部分黑矩阵的作用，从而减轻对位等因素造成的数据线或栅线两侧串色不良。
下面结合附图和具体实施例对本发明实施例提供的阵列基板及其制作方法和显示装置进行说明。
实施例一
如图3a和图3b所示，本实施例提供的一种阵列基板包括沿第一方向(如图3b中的箭头所示)延伸的第一信号线71(例如数据线13c，如图3a所示)、以及位于第一信号线71之上(即位于第一信号线71的远离衬底基板01a的一侧)的公共电极30，公共电极30中设置有至少一个第一开口31，该至少一个第一开口31中的每个都与第一信号线71在公共电极30所在面上的正投影有重叠部分，即该至少一个第一开口31中的每个都与第一信号线71垂直交叠。
如图3b所示，公共电极30包括与第一信号线71的正投影部分重叠的第一部分30a以及位于第一信号线71的正投影之外的第二部分30b，第二部分30b与第一部分30a连接且同层设置。即，对应该第一信号线71的公共电极30包括一体形成的第一部分30a和第二部分30b。
本实施例以像素电极50与公共电极30异层设置为例进行说明。例如，本实施例提供的阵列基板可以为ADS模式阵列基板。在这种情况下，像素电极50可以为狭缝电极位于公共电极30之上，如图3a和图3b所示，公共电极30为板状结构。在这种情况下，本实施例提供的阵列基板可以包括一个 整面的公共电极30；或者，该阵列基板也可以包括多个板状的公共电极30，每个公共电极30包括上述第一部分30a和第二部分30b。或者，例如，公共电极可以为狭缝电极位于板状的像素电极之上。
本实施例提供的阵列基板中还设置有薄膜晶体管10，图3a以该薄膜晶体管10采用底栅顶接触结构为例进行说明，即，该薄膜晶体管10包括栅极11、设置于栅极11上的栅绝缘层12、设置于栅绝缘层12上的有源层14、以及位于有源层14上且与有源层14接触的源极13a和漏极13b。像素电极50通过第一绝缘层20中的第一绝缘层过孔21和第二绝缘层40中的过孔41与漏极13b连接。当然，薄膜晶体管10也可以采用顶栅结构，即栅极11设置于有源层14的上方；或者，薄膜晶体管10也可以采用底接触结构，即源极13a和漏极13b设置于有源层14之下；此外，源极13a/漏极13b与有源层14之间还可以设置有绝缘层，并且源极13a和漏极13b通过该绝缘层中的过孔与有源层14接触。
本实施例提供的阵列基板中，第一信号线71也可以为栅线，该栅线与栅极11同层设置。图3a仅以第一信号线71为与源极13a和漏极13b同层设置的数据线13c为例进行说明。
本实施例在公共电极30对应第一信号线71的位置处设置至少一个第一开口31，使得公共电极30在每个第一开口31边缘的位置处与该第一开口31下方的第一信号线71形成电场，该电场为不规则电场，使得该第一开口31处的液晶排布混乱，不具备透光能力，也就是所谓“暗区”。
图4a为图3b中AA'方向的剖面示意图，图4b为图3b中BB'方向的剖面示意图。如图4a和4b所示，沿AA'方向，公共电极30与第一信号线71之间形成横向电场；沿BB'方向，公共电极30与第一信号线71之间形成纵向电场。因此，每个第一开口31所在位置处的电场方向各异，使得此处液晶排布混乱，形成暗区。这就相当于在盒内形成立体的屏障以隔开相邻的位于第一信号线两侧的两个像素，使彼此的光不相干扰，从而最大限度地避免侧视角时的串色不良。
需要说明的是，图3b仅以第一开口31沿公共电极30所在面上的形状为矩形为例进行说明。当第一开口31沿公共电极30所在面上的形状为其他形状时，公共电极30与第一信号线71之间形成的电场方向还可以沿其它方向。 并且，第一开口的形状可以为任意形状。例如，第一开口31的沿公共电极30所在面上的形状可以包括多边形(例如三角形、矩形等)、圆形或椭圆形。当然，此处的多边形、圆形或椭圆形可以是近似于多边形、圆形或椭圆形的图形。
如图5所示，本实施例提供的阵列基板组装成液晶显示装置之后，位于第一信号线71的第一侧和第二侧的像素分别对应不同颜色滤光图案(例如，红色滤光图案R和绿色绿光图案G)，当对应第一信号线71的黑矩阵BM向第一信号线71的第一侧(即图5中第一信号线71的左侧)偏移时，由于在公共电极30中形成有至少一个第一开口31，因此，在第一信号线71的第二侧(即图5中第一信号线71的右侧)难以看到来自第一侧的光。
由于第一开口31形成在公共电极30中，例如在制作公共电极30时通过去除预设位置处的公共电极材料即可在该位置处形成第一开口31，因此第一开口31可以为封闭式开口。
为了使每个第一开口31处形成暗区，每个第一开口31沿第一方向的尺寸不宜过大。例如，公共电极30中可以设置有多个第一开口31。这样一来，公共电极30对应第一信号线71的部分被多个开口划分，第一开口数量越多，每个第一开口沿第一方向的尺寸可以更小，从而有利于使每个第一开口所在位置处的液晶排布混乱以形成暗区。
需要说明的是，第一开口的数量(尤其是当公共电极中在对应第一信号线的位置处设置有少量或一个第一开口时)可以根据液晶的材质、公共电极与第一信号线对应的部分沿第一方向的尺寸等实际情况进行设计，以避免因第一开口沿第一方向的尺寸较大，造成公共电极在该第一开口处与第一信号线之间形成的暗区不太明显。本实施例不限定第一开口的数量和尺寸，只要使公共电极在每个第一开口处与该第一开口下方的第一信号线之间形成方向各异的电场，以使该第一开口处形成暗区即可。
例如，第一开口31沿第一方向的尺寸可以小于或等于第一开口31沿与第一方向垂直的方向的尺寸。这样可以避免第一开口的沿第一方向的尺寸过大造成公共电极在第一开口处与第一信号线之间形成较规则的电场。
例如，第一开口31可以相对于第一信号线71轴对称，如图3b所示。这样可以使第一信号线71两侧的光线更加均匀。
在本实施例中，公共电极30还可以包括位于第一信号线71的正投影之外的第三部分30c，如图3b所示，第三部分30c与第一部分30a连接且同层设置，并且第三部分30c和第二部分30b分别位于第一部分30a的相对的两侧。也就是说，对应第一信号线71的公共电极30包括一体形成的第一部分30a、第二部分30b和第三部分30c，第二部分30b和第三部分30c分别位于第一信号线71的第一侧和第二侧。
实施例二
如图6所示，本实施例提供的阵列基板与实施例一的区别在于：至少一个第一开口31包括至少一个大致沿第一方向延伸的边缘311，该边缘311可以为折线形(如图6所示)或波浪形。
本实施例通过使第一开口的大致沿第一方向延伸的边缘具有非直线型结构，可以尽量使公共电极30在该第一开口31的该边缘311处与第一信号线71之间形成比较紊乱的电场，以有利于形成暗区。
实施例三
与实施例一相比，本实施例提供的阵列基板还包括沿第二方向延伸的第二信号线72，如图7所示，第二方向与第一方向相交，公共电极30中还设置有至少一个第二开口32，该至少一个第二开口32中的每个与第二信号线72在公共电极30所在面上的正投影有重叠部分，即该至少一个第一开口31中的每个都与第二信号线72垂直交叠。
在本实施例中，例如，如图8所示，可以是第一信号线71为栅线11a，第二信号线72为数据线13c；或者可以是第一信号线71为数据线13c，第二信号线72为栅线11a。
实施例四
本实施例提供的阵列基板与实施例一提供的阵列基板的区别在于：该阵列基板还包括彩色滤光层，即，该阵列基板采用COA(Color filter On Array)技术。
例如，如图9所示，彩色滤光层80包括多列滤光图案(例如，红色滤光图案R、绿色滤光图案G、蓝色滤光图案B)，每列滤光图案沿第一方向排列，同一列滤光图案的颜色相同或不同，与每条第一信号线71相邻且位于该第一信号线71两侧的两列滤光图案中位置对应的滤光图案具有不同的颜色。
需要说明的是，图9仅以第一信号线71为数据线，并且分别位于数据线13c两侧的相邻两列滤光图案的颜色不同、且分别位于栅线11a两侧的相邻两行滤光图案的颜色相同为例进行说明。但彩色滤光层包括的滤光图案还可以采用本领域常用的其他排列方式，本实施例不做赘述。
实施例五
本实施例提供的阵列基板与实施例一提供的阵列基板的区别在于：如图10a和图10b所示，像素电极50与公共电极30同层设置，在这种情况下，公共电极30可以包括多个条状子公共电极3a，像素电极50可以包括多个条状子像素电极5a，条状子公共电极3a与条状子像素电极5a交替设置。即，本实施例提供的阵列基板为IPS模式阵列基板。
例如，在图10b中，像素电极50包括的条状子像素电极5a大致沿第一方向延伸，并且通过连接部5b连接在一起。类似地，公共电极30的条状子公共电极3a大致沿第一方向延伸，并通过连接部3b连接在一起。公共电极30的条状子公共电极3a沿第一方向的尺寸和/或沿垂直于第一方向的尺寸可以不同；为便于公共电极30与第一信号线71之间形成至少一个第一开口31，可以在沿垂直于第一方向的尺寸较大的子公共电极3a中设置第一开口31，在这种情况下，该子公共电极3a在第一开口31处与第一信号线71之间形成的沿AA'方向的电场如图11所示。
本实施例提供的阵列基板中还设置有薄膜晶体管10，其可参考实施例一中的相关描述，重复之处不再赘述。
在上述实施例一至实施例五中，实施例一或实施例五可以与实施例二至四中的至少一个进行组合。
实施例六
本实施例提供了一种显示装置，其包括上述任一项实施例或其组合提供的阵列基板。
例如，本实施例提供的显示装置可以为：液晶面板、电子纸、触控面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
例如，如图12所示，本实施例提供的显示装置可以为液晶显示装置，其包括相互对置的阵列基板01和对置基板02、以及设置于二者之间的液晶层 03。
本实施例提供的显示装置还包括彩色滤光层80'，例如该彩色滤光层80'包括多列滤光图案(例如，红色滤光图案R、绿色滤光图案G、蓝色滤光图案B)，每列滤光图案沿第一方向排列，同一列滤光图案的颜色相同或不同，滤光图案中与第一信号线71相邻且位于第一信号线71两侧的两列滤光图案中位置对应的滤光图案的颜色不同。
例如，该彩色滤光层可以设置于阵列基板01或对置基板02上。图12仅以该彩色滤光层80'设置于对置基板02上为例进行说明，在这种情况下，该对置基板02又可以称为彩膜基板。
本实施例中彩色滤光层的设置可以参考上述实施例四的相关描述，重复之处不做赘述。
实施例七
本实施例提供了一种如上述任一实施例或其组合提供的阵列基板的制作方法，该方法可以包括：形成沿第一方向延伸的第一信号线；以及通过一次构图工艺形成位于第一信号线之上的公共电极以及公共电极中的至少一个第一开口，使该至少一个第一开口与第一信号线在公共电极所在面上的正投影有重叠部分。在本实施例提供的方法中，公共电极包括与第一信号线的正投影部分重叠的第一部分以及位于第一信号线的正投影之外的第二部分，第二部分与第一部分连接且同层设置。此外，第一信号线可以为栅线或数据线。
例如，本实施例提供的制作方法还可以包括：在形成第一信号线之前或之后，形成沿第二方向延伸的第二信号线，在该步骤中，第二方向与第一方向相交；形成公共电极还可以包括形成设置于公共电极中的至少一个第二开口，使该至少一个第二开口与第二信号线在公共电极所在面上的正投影有重叠部分。
例如，在该制作方法中，可以通过与形成公共电极的构图工艺不同的构图工艺形成像素电极，在这种情况下，像素电极可以位于公共电极之上或者位于公共电极之下。例如，该阵列基板可以采用ADS模式。
或者，例如，形成公共电极还可以包括形成像素电极。在这种情况下，公共电极可以包括多个条状子公共电极，像素电极可以包括多个条状子像素电极，条状子公共电极与条状子像素电极交替设置，即，该阵列基板采用IPS 模式。
下面结合图3a所示的ADS模式阵列基板对本实施例提供的制作方法进行详细说明。例如，该制作方法可以包括以下步骤71至步骤78。
步骤71：通过第一次构图工艺，在衬底基板01a上形成栅极11以及栅线(图3a中未示出栅线)。
步骤72：通过第二次构图工艺，形成覆盖栅极11和栅线的栅绝缘层12。
步骤73：通过第三次构图工艺，在栅绝缘层12上形成有源层14。
步骤74：通过第四次构图工艺，形成位于有源层14上并且与其接触的源极13a和漏极13b，以及数据线13c。
步骤75：通过第五次构图工艺，形成覆盖源极13a、漏极13b和数据线13c的第一绝缘层20，以及位于第一绝缘层20中的第一绝缘层过孔21。
步骤76：通过第六次构图工艺，在第一绝缘层20上形成公共电极30、位于公共电极30中且与数据线13c垂直交叠的至少一个第一开口31、以及与公共电极30连接的公共电极线(图3a中未示出)。
步骤77：通过第七次构图工艺，在公共电极30上形成第二绝缘层40以及位于第二绝缘层40中的第二绝缘层过孔41，第二绝缘层过孔41与第一绝缘层过孔21连通。
步骤78：通过第八次构图工艺，在第二绝缘层40上形成像素电极50，使像素电极50通过上述步骤75和77中形成的第一绝缘层过孔21和第二绝缘层过孔41与薄膜晶体管10的漏极13b连接。
上述步骤以公共电极和公共电极线同层设置为例进行说明。当然，公共电极和公共电极线也可以异层设置。例如，公共电极线也可以在步骤71中与栅线同时形成，在这种情况下，步骤76中形成的公共电极可以通过第一绝缘层20中的过孔与公共电极线连接。
本实施例提供的阵列基板的制作方法中，阵列基板中的第一信号线、第二信号线、第一开口、第二开口等可参考实施例一至实施例五中的相关描述，重复之处不再赘述。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年7月9日递交的中国专利申请第201510400851.X 号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种阵列基板，包括：
    沿第一方向延伸的第一信号线，其中，所述第一信号线为栅线或数据线；以及
    公共电极，位于所述第一信号线之上，其中，所述公共电极中设置有至少一个第一开口，所述至少一个第一开口与所述第一信号线在所述公共电极所在面上的正投影有重叠部分；并且，所述公共电极包括与所述第一信号线的所述正投影部分重叠的第一部分以及位于所述第一信号线的所述正投影之外的第二部分，所述第二部分与所述第一部分连接且同层设置。
  2. 如权利要求1所述的阵列基板，其中，所述第一开口为封闭式开口。
  3. 如权利要求1或2所述的阵列基板，其中，所述公共电极中设置有多个所述第一开口。
  4. 如权利要求1至3任一项所述的阵列基板，其中，所述第一开口包括至少一个沿所述第一方向延伸的边缘，所述边缘为折线形或波浪形。
  5. 如权利要求1至4任一项所述的阵列基板，其中，所述第一开口沿所述第一方向的尺寸小于或等于所述第一开口沿与所述第一方向垂直的方向的尺寸。
  6. 如权利要求1至5任一项所述的阵列基板，其中，所述第一开口的沿所述公共电极所在面上的形状包括多边形、圆形或椭圆形。
  7. 如权利要求1至6任一项所述的阵列基板，其中，
    所述第一开口相对于所述第一信号线轴对称。
  8. 如权利要求1至7任一项所述的阵列基板，还包括：
    沿第二方向延伸的第二信号线，其中，所述第二方向与所述第一方向相交，所述公共电极中还设置有至少一个第二开口，所述至少一个第二开口与所述第二信号线在所述公共电极所在面上的正投影有重叠部分。
  9. 如权利要求8所述的阵列基板，其中，
    所述第一信号线为所述栅线，所述第二信号线为所述数据线；或者
    所述第一信号线为所述数据线，所述第二信号线为所述栅线。
  10. 如权利要求1至9任一项所述的阵列基板，还包括：像素电极，其 中，
    所述像素电极与所述公共电极同层设置，所述公共电极包括多个条状子公共电极，所述像素电极包括多个条状子像素电极，所述条状子公共电极与所述条状子像素电极交替设置；或者
    所述像素电极与所述公共电极异层设置，所述像素电极位于所述公共电极之上或者位于所述公共电极之下。
  11. 如权利要求1至10任一项所述的阵列基板，还包括：彩色滤光层，其中，所述彩色滤光层包括多列滤光图案，每列所述滤光图案沿所述第一方向排列，同一列所述滤光图案的颜色相同或不同，所述滤光图案中与所述第一信号线相邻且位于所述第一信号线两侧的两列滤光图案中位置对应的滤光图案具有不同的颜色。
  12. 如权利要求1-11任一项所述的阵列基板，其中，所述公共电极还包括位于所述第一信号线的所述正投影之外的第三部分，所述第三部分与所述第一部分连接且同层设置，并且所述第三部分和所述第二部分分别位于所述第一部分的相对的两侧。
  13. 一种显示装置，包括如权利要求1至10以及12中任一项所述的阵列基板。
  14. 如权利要求13所述的显示装置，还包括：彩色滤光层，其中，所述彩色滤光层包括多列滤光图案，每列所述滤光图案沿所述第一方向排列，同一列所述滤光图案的颜色相同或不同，所述滤光图案中与所述第一信号线相邻且位于所述第一信号线两侧的两列滤光图案中位置对应的滤光图案具有不同的颜色。
  15. 一种阵列基板的制作方法，包括：
    形成沿第一方向延伸的第一信号线，其中，所述第一信号线为栅线或数据线；以及
    通过一次构图工艺形成位于所述第一信号线之上的公共电极以及设置于所述公共电极中的至少一个第一开口，其中，所述至少一个第一开口与所述第一信号线在所述公共电极所在面上的正投影有重叠部分；并且，所述公共电极包括与所述第一信号线的所述正投影部分重叠的第一部分以及位于所述第一信号线的所述正投影之外的第二部分，所述第二部分与所述第一部分连 接且同层设置。
  16. 如权利要求15所述的制作方法，其中，
    形成所述公共电极还包括形成像素电极，其中，所述公共电极包括多个条状子公共电极，所述像素电极包括多个条状子像素电极，所述条状子公共电极与所述条状子像素电极交替设置；或者
    通过一次构图工艺形成像素电极，其中，所述像素电极位于所述公共电极之上或者位于所述公共电极之下。
  17. 如权利要求15或16所述的制作方法，还包括：
    在形成所述第一信号线之前或之后，形成沿第二方向延伸的第二信号线，其中，所述第二方向与所述第一方向相交；
    形成所述公共电极还包括形成设置于所述公共电极中的至少一个第二开口，其中，所述至少一个第二开口与所述第二信号线在所述公共电极所在面上的正投影有重叠部分。
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