WO2018201781A1 - 薄膜晶体管、阵列基板及显示装置 - Google Patents

薄膜晶体管、阵列基板及显示装置 Download PDF

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Publication number
WO2018201781A1
WO2018201781A1 PCT/CN2018/077333 CN2018077333W WO2018201781A1 WO 2018201781 A1 WO2018201781 A1 WO 2018201781A1 CN 2018077333 W CN2018077333 W CN 2018077333W WO 2018201781 A1 WO2018201781 A1 WO 2018201781A1
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Prior art keywords
drain
sub
connection block
thin film
film transistor
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PCT/CN2018/077333
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English (en)
French (fr)
Inventor
顾可可
杨妮
李辉
刘信
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/345,204 priority Critical patent/US10720531B2/en
Publication of WO2018201781A1 publication Critical patent/WO2018201781A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor, an array substrate, and a display device.
  • each of the sub-pixels arrayed in the array substrate of the display device generally includes at least one TFT.
  • TFTs with double U-shaped structures are widely used because of their large operating current.
  • Embodiments of the present invention provide a thin film transistor, an array substrate, and a display device. Embodiments of the present disclosure adopt the following technical solutions:
  • An embodiment of the present disclosure provides a thin film transistor including a gate, an active layer, a source, and a drain;
  • the source includes a connection portion, and first, second, and third portions that are sequentially disposed in parallel a subsection, wherein at the first end of the subsection, the connecting portion connects the first subsection, the second subsection, and the third subsection to form two adjacent recesses; a second end of the sub-portion, a distance from an end of the second sub-portion to the connecting portion is smaller than an end of the first sub-portion and an end of the third sub-portion to the connecting portion
  • the drain includes a connection block and a first drain and a second drain respectively located in the two recesses, the connection block being at least partially located at the first drain and the second drain The first drain and the second drain are connected to each other.
  • connection block is entirely located between the first drain and the second drain, and an upper edge of the connection block and an upper edge of the first drain and the second drain Flush.
  • the gate has a hollow portion, and the hollow portion corresponds to a portion of the connection block between the first drain and the second drain.
  • the dimension of the hollow portion is equal to the distance between the first drain and the second drain in the direction in a direction perpendicular to a direction from the first end to the second end.
  • a size of the hollow portion and a portion of the connection block between the first drain and the second drain are The dimensions in this direction are equal.
  • connection block is located between the first drain and the second drain, and an upper edge of the connection block is on the first drain and the second drain In the case where the edges are flush, the upper edge of the hollow portion extends beyond the upper edge of the connecting block in a direction along the first end to the second end, and the lower edge of the hollow portion exceeds the connection The lower edge of the block.
  • the hollow portion is a notch located on a side of the gate close to an upper edge of the connecting block.
  • Another aspect of the embodiments of the present disclosure further provides an array substrate, which is divided into sub-pixels arranged in an array, each sub-pixel includes a pixel electrode and the foregoing thin film transistor, and the pixel electrode is connected to a connection block of the thin film transistor.
  • Still another aspect of the embodiments of the present disclosure further provides a display device including the foregoing array substrate.
  • FIG. 1 is a schematic structural view of a thin film transistor provided in the related art
  • FIG. 2 is a schematic structural view of a sub-pixel including the thin film transistor of FIG. 1 provided in the related art
  • FIG. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another thin film transistor according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram showing a simplified structure of a thin film transistor including FIGS. 1 and 3 according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a simplified structure including the thin film transistor of FIGS. 1 and 4 according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a thin film transistor, an array substrate, and a display device.
  • the aperture ratio of the sub-pixel unit can be increased when the width to length ratio of the channel is constant.
  • Embodiments of the present disclosure provide a thin film transistor, an array substrate, and a display device.
  • the thin film transistor includes a gate, an active layer, a source, and a drain.
  • the source includes a connecting portion and a first sub-portion, a second sub-portion, and a third sub-portion that are sequentially disposed in parallel.
  • the connecting portion connects the first sub-portion, the second sub-portion, and the third sub-portion to form two adjacent recesses.
  • the distance from the end of the second sub-portion to the connecting portion is less than the distance from the end of the first sub-portion and the end of the third sub-portion to the connecting portion.
  • the drain includes a connection block and a first drain and a second drain, and the first drain and the second drain are respectively located in two recesses of the source, and the connection block is at least partially located at the first drain and the second drain A first drain and a second drain are connected.
  • FIG. 1 shows a TFT of a double U-shaped structure in an array substrate of a related display device.
  • the TFT includes a gate 10, an active layer 20, a source 31, and a drain 32.
  • the source 31 of the TFT has a parallel double U-shaped structure.
  • the drain 32 includes two sub-portions 301 respectively located in two U-shaped recesses, and the two sub-portions 301 are connected by a connection block 300.
  • the connection block 300 has a large area. Further, as shown in FIG. 2, the connection block 300 is connected to the pixel electrode 50 through a via 40 located above.
  • connection block 300 is located outside the gate 10 and is made of an opaque material. In this way, for one sub-pixel, since the area of the area corresponding to the connection block 300 is large, the relative area of the pixel electrode 50 is reduced, that is, the aperture ratio of the sub-pixel unit is small.
  • An embodiment of the present disclosure provides a thin film transistor including a gate 10, an active layer 20, a source 31, and a drain 32, as shown in FIG.
  • the thin film transistor may be of a top gate type or a bottom gate type.
  • FIG. 3 is schematically illustrated by taking a bottom gate type TFT as an example, but the present disclosure is not limited thereto. The following embodiments are all based on a bottom gate TFT as an example for further explanation.
  • the source 31 includes a connection portion 30 and a first sub-portion 311, a second sub-portion 312, and a third sub-portion 313 which are sequentially disposed.
  • the connecting portion 30 connects the first sub-portion 311, the second sub-portion 312, and the third sub-portion 313 to form two adjacent recesses.
  • the distance from the end of the second sub-portion 312 to the connecting portion 30 is smaller than the distance from the end of the first sub-portion 311 and the end of the third sub-portion 313 to the connecting portion 30.
  • the distance from the end of the second sub-portion 312 to the connecting portion 30 is smaller than the end of the first sub-portion 311 and the end of the third sub-portion 313.
  • the distance of the connecting portion 30 means that there is a certain drop between the end of the first sub-portion 311 and the end of the third sub-portion 313 and the end of the second sub-portion 312 at the second end B of the sub-portion, And the end of the second sub-portion 312 is closer to the connecting portion 30 with respect to the end of the first sub-portion 311 and the end of the third sub-portion 313, that is, the end of the first sub-portion 311 and the third sub-portion 313 The end portion protrudes from the end of the second sub-portion 312.
  • the drain 32 includes a connection block 300 and a first drain 321 and a second drain 322 respectively located in the two recesses.
  • the connection block 300 is at least partially located between the first drain 321 and the second drain 322 to connect the first The drain 321 and the second drain 322.
  • the first drain 321 and the second drain 322 of the drain 32 refer to, as shown in FIG. 3, at least the drain 32 is opposite to the sub-portion of the source 31.
  • the portion that is, the portion capable of performing effective carrier transfer with the sub-portions in the source 31 in the active state.
  • the source 31 and the drain 32 described above serve as a signal input electrode and a signal output electrode, respectively.
  • the source 31 may be a signal input electrode and the drain 32 may serve as a signal output electrode.
  • the source 31 connected to the data line is used as a signal input electrode
  • the drain 32 connected to the pixel electrode is used as a signal output electrode.
  • the drain 32 may be used as a signal input electrode
  • the source 31 may serve as a signal output electrode. This disclosure does not limit this.
  • the source 31 is used as the signal input electrode
  • the drain 32 is used as the signal output electrode as an example.
  • the dimension in the direction perpendicular to the first end A to the second end B may be The distance between the first drain 321 and the inner side of the second drain 322 is equal. Alternatively, as shown in FIG. 3, the distance between the first drain 321 and the outside of the second drain 322 is equal, as long as the distance can be ensured.
  • the size of the connection block 300 is sufficient for the subsequent connection, which is not limited in this disclosure.
  • first drain 321 and the second drain 322 refer to a portion of the drain 32 opposite to the sub-portion of the source 31 (refer to "first"), on this basis
  • first drain 321 and the second drain 322 refer to a portion of the drain 32 opposite to the sub-portion of the source 31 (refer to "first")
  • the connection block 300 is located at the first A portion of the region between the drain 321 and the second drain 322 that is opposite to each other. That is, the projection of this portion will fall into the gate 10.
  • the portion of the connection block 300 other than between the first drain 321 and the second drain 322 (refer to "third"), it is meant that the first drain 321 and the second drain 322 are opposite each other. The part outside the area.
  • the distance from the end of the second sub-portion to the connecting portion is smaller than the distance from the end of the first sub-portion and the end of the third sub-portion to the connecting portion.
  • the connection block is at least partially located between the first drain and the second drain to connect the first drain and the second drain, that is, the connection block and the gate have an overlap between the first drain and the second drain section.
  • the present disclosure can be regarded as a double U-shaped TFT in which the lengths of the first sub-section, the second sub-section, and the third sub-section are the same, and the connection block is completely outside the gate.
  • the distance between the first sub-portion and the third sub-portion is longer than that of the second sub-portion compared to the related art, and the connecting block is moved closer to the source direction than the above-mentioned lengthening or shortening.
  • the distance is such that the connection block is at least partially located between the first drain and the second drain to connect the first drain and the second drain.
  • the present disclosure can ensure not only the same channel width-to-length ratio as the TFT in the related art, but also the first sub-section and the first in the case of being applied to the display field, while ensuring that other conditions are the same.
  • the portion where the aperture ratio is reduced by the lengthening of the three sub-portions is smaller than the portion where the aperture ratio due to the movement of the connection block toward the source is increased, thereby contributing to an increase in the aperture ratio of the sub-pixel unit. That is, the present disclosure can increase the aperture ratio of the sub-pixel unit in the case where the width to length ratio of the channel is constant.
  • the upper edges of the first sub-portion 311 and the third sub-portion 313 may be flush or not flush.
  • the upper edges of the first sub-portion 311 and the third sub-portion 313 are alternatively aligned.
  • connection block 300 is entirely located between the first drain 321 and the second drain 322, and the upper edge of the connection block 300 is The upper edges of a drain 321 and the second drain 322 are flush, that is, the projections of the connection block 300 all fall into the gate 10.
  • connection block 300 and the upper edges of the first drain 321 and the second drain 322 mean that the connection block 300, the first drain 321, and the second drain 322 are away from the source.
  • connection block 300 is flush with the upper edges of the first drain 321 and the second drain 322 to avoid exceeding the connection block 300 at the upper edges of the first drain 321 and the second drain 322.
  • the first sub-portion 311 and the third sub-portion 313 in the source 31 are not effective in forming a channel in the excess portion.
  • the entire area where the excess portion is located cannot transmit light, which is disadvantageous for the increase of the aperture ratio of the entire sub-pixel.
  • connection block 300 the connection portion of the corresponding via hole in the drain 32, is square, and the side length of the square is 4H, and the connection portion (connection block 300) is The height of the lateral connection sub-portion 302 between one of the two sub-portions 301 is half the length of the square side, ie 2H.
  • connection block 300 in FIG. 3 between the first drain 321 and the second drain 322 as an example, in order to more clearly compare the aperture ratios of the TFT of FIG. 3 and the sub-pixel unit of the TFT of FIG. 5 is a schematic structural view including the TFT of FIG. 3 and the gate electrode and the connection block (black dotted portion) of FIG.
  • the first sub-portion 311 and the third sub-portion 313 in FIG. 3 are longer than the lengthened distance H in FIG. 1, and the second sub-portion 312 is compared to FIG.
  • the shortened distance in the middle is H.
  • the channel width W in FIG. 3 is reduced and the size of the increasing portion is equal, that is, the channel width W of both is the same as in FIG. 1 and FIG.
  • the TFTs in FIG. 3 have an equal channel width to length ratio (W/L) as compared with the TFTs in FIG.
  • the portion of the connection block 300 located between the portion other than the gate 10 and the data line 60 is black matrix. Occlusion cannot be used for display. When calculating the aperture ratio, this part also needs to be calculated in the opaque part.
  • the length of the first sub-portion 311 and the third sub-portion 313 and the area of the connection block 300 moving toward the source 31 are increased, which is smaller than the connection block.
  • the portion of the area 300 that is moved toward the source 31 is reduced. That is, the sum of the shadow S1 and the shadow S2 in FIG. 5 is smaller than the sum of the shadow S3 and the shadow S4 (S1+S2 ⁇ S3+S4).
  • the shadow S1 is the area of the aperture ratio reduction portion brought about by the lengthening of the first sub-portion 311 and the third sub-portion 313; the shadow S2 is a decrease in the aperture ratio of the connection block 300 in the direction of approaching the source 31.
  • the area of the portion; the shadow S3 and the shadow S4 are the areas of the opening ratio increasing portion of the connecting block 300 moving toward the source 31, wherein the shadow S3 corresponds to a portion of the connecting block 300 in FIG. 1, and the shadow S4 corresponds to the shadow.
  • S1, S2, S3, and S4 may be referred to as the respective parts, or may directly indicate the area of each part.
  • the heights of the shadow S1, the shadow S2, the shadow S3, and the shadow S4 are all the same, and are all H.
  • the lengths of the shadow S1 and the shadow S4 are close to each other (and about 1/3 to 1/2 times the length of the side of the connection block 300), wherein the length of the S4 refers to the connection between the connection block 300 and the data line 60. the distance.
  • the areas of the shadow S1 and the shadow S4 are nearly equal (S1 ⁇ S4).
  • the length of the shadow S3 is the side length of the connection block 300, and the length of the shadow S2 is smaller than the side length of the connection block 300, and the shadow S2 is smaller than the area of the shadow S3 (S2 ⁇ S3).
  • the sum of the areas of the shadow S1 and the shadow S2 is smaller than the area sum of the shadow S3 and the shadow S4, that is, S1 + S2 ⁇ S3 + S4. That is, the portion where the area of the first sub-portion 311 and the third sub-portion 313 is increased is smaller than the portion where the area of the connection block 300 is moved toward the source 31, so that the present disclosure is made.
  • the aperture ratio of the sub-pixel unit can be increased in the case where the width to length ratio of the channel is constant.
  • connection block 300 is entirely located between the first drain 321 and the second drain 322, and the upper edge of the connection block 300 is flush with the upper edges of the first drain 321 and the second drain 322.
  • FIG. 6 is a schematic diagram including the TFT of FIG. 4 and the gate of FIG. 1 and the connection block (black dotted portion).
  • connection block 300 has a portion outside the gate 10 such that a portion between the portion and the data line 60 cannot be used for display (refer to FIG. 1 or FIG. 3).
  • the connection block 300 is completely located in the area where the gate 10 is located.
  • the portion of the area which is increased by the lengthening of the first sub-portion 311 and the third sub-portion 313, that is, the shadow S1 in FIG. 6, is smaller than the connection.
  • the portion of the block 300 that is moved toward the source 31 is reduced in area, that is, the sum of the shadow S2 and the shadow S3 in FIG. 6, that is, S1 ⁇ S2 + S3, wherein the shadow S2 corresponds to the connection block 300 in FIG.
  • the shadow S3 corresponds to the area between the shadow S2 and the data line 60.
  • the heights of the shadow S1, the shadow S2, and the shadow S3 are the same, and both are 2H.
  • the lengths of the shadow S1 and the shadow S3 are close to each other (and about 1/3 to 1/2 times the length of the side of the connection block 300), that is, the areas of the shadow S1 and the shadow S3 are nearly equal (S1 ⁇ S3) ).
  • the length of the shadow S2 is the side length of the connection block 300 and has a width of 2H (i.e., half of the side length of the connection block 300).
  • the lateral connection sub-portion 302 of Figure 1 is completely located in the region of the gate 10 in Figure 4. In this case, the area of the shadow S2 corresponds to the portion where the aperture ratio is increased.
  • the portion where the area due to the lengthening of the first sub-portion 311 and the third sub-portion 313 is increased is smaller than the portion where the area of the connecting block 300 is moved toward the source 31, so that the area is reduced. It is disclosed that the aperture ratio of the sub-pixel unit can be increased in the case where the width to length ratio of the channel is constant.
  • the difference between the aperture ratio of the design in this embodiment and the aperture ratio in the related art is larger. That is, the design of the embodiment can increase the aperture ratio of the sub-pixel unit to a greater extent if the aspect ratio (W/L) of the channel is constant.
  • connection block 300 between the first drain 321 and the second drain 322 in the present disclosure overlaps with the region where the gate 10 is located (viewing from the connection block 300 toward the gate 10, the projection of both) With overlapping, not in actual sense, refer to Figure 4.
  • the first drain 321 and the second drain are located in the connection block 300.
  • the region of the gate 10 corresponding to the portion between 322 is provided with a hollow portion 70.
  • the shape and size of the hollow portion 70 are not limited, and may be square or rectangular unless the performance of the TFT is affected.
  • the area of the hollow portion 70 may be as large as the area of the portion of the connection block 300 between the first drain 321 and the second drain 322, or may be larger than the area of the portion or smaller than the area of the portion. The disclosure is not limited in this regard.
  • the size of the hollow portion 70 is equal or approximately equal to the distance of the projection of the first drain 321 and the second drain 322 on the surface in the direction; and/or, along the first end A to the second In the direction of the end B, the size of the hollow portion 70 and the projection of the portion of the connection block 300 between the first drain 321 and the second drain 322 on the surface are equal or approximately equal in size.
  • the hollow portion 70 in FIG. 8 is completely identical in shape and size to the connecting block 300, and the positions are completely overlapped.
  • connection block 300 is entirely located between the first drain 321 and the second drain 322, and the upper edge of the connection block 300 and the first drain 321 and the second In the case where the upper edge of the drain 322 is flush, on either surface of the gate 10, in the direction along the first end A to the second end B, the upper edge of the hollow portion 70 exceeds the connection block 300 at the surface On the upper edge of the upper projection, the lower edge of the hollow portion 70 extends beyond the lower edge of the projection of the connection block 300 on the surface. In this way, even if the process 32 fluctuates, the drain 32 generates a small amount of offset in the direction along the first end A to the second end B, and the overlapping area of the drain 32 and the gate 10 can remain unchanged.
  • a relatively stable parasitic capacitance C gd is provided between the drain 32 and the gate 10.
  • the hollow portion 70 is a notch located on the upper edge side of the projection of the gate 10 close to the connection block 300 on the gate electrode 10 .
  • the projections of the source 31 and the drain 32 all fall into the active layer 20.
  • the source 31, the drain 32, and the active layer 20 can be formed by a half-exposure mask (Half Tone) process by one patterning (ie, one mask) and two etchings.
  • the composition can be separately produced by two patterning processes (ie, two masks), which is not limited in the present disclosure.
  • An embodiment of the present disclosure also provides an array substrate 1000.
  • the array substrate defines a plurality of sub-pixels 500 arranged in an array by horizontally and vertically interleaved data lines and gate lines.
  • Each of the plurality of sub-pixels 500 includes a pixel electrode 50 and the aforementioned thin film transistor.
  • the pixel electrode 50 and the connection block 300 of the thin film transistor are connected by a via 40.
  • the thin film transistor in the array substrate has the same structure and advantageous effects as the thin film transistor provided in the foregoing embodiment. Since the foregoing embodiment has been described in detail for the structure and advantageous effects of the thin film transistor, it will not be described herein.
  • the array substrate may be an ADS (Advanced-Super Dimensional Switching) type, an IPS (In Plane Switch) type, or a TN (Twist Nematic, The twisted nematic type is not limited in this disclosure.
  • the embodiment of the present disclosure further provides a display device 2000, as shown in FIG. 11, including the array substrate 1000 described above.
  • the thin film transistor included in the display device has the same structure and advantageous effects as the thin film transistor provided in the foregoing embodiment. Since the foregoing embodiment has been described in detail for the structure and advantageous effects of the thin film transistor, it will not be described herein.
  • the display device may specifically include at least a liquid crystal display panel.
  • the display panel can be applied, for example, to any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.

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Abstract

一种薄膜晶体管、阵列基板及显示装置，涉及显示技术领域，在应用于显示领域的情况下，能够在沟道的宽长比一定的情况下，增加亚像素单元的开口率。该薄膜晶体管包括栅极（10）、有源层（20）、源极（31）、漏极（32）。源极包括连接部（30）以及依次平行设置的第一子部（311）、第二子部（312）、第三子部（313）。在子部的第一端，连接部连接第一子部、第二子部、第三子部以形成相邻的两个凹部。在子部的第二端，第二子部的端部到连接部的距离小于第一子部的端部和第三子部的端部到连接部的距离。漏极包括连接块（300）以及分别位于两个凹部中的第一漏极（321）和第二漏极（322），连接块至少部分位于第一漏极和第二漏极之间以连接第一漏极和第二漏极。

Description

薄膜晶体管、阵列基板及显示装置
本申请要求于2017年5月5日提交中国专利局、申请号为201710316224.7、申请名称为“一种薄膜晶体管、阵列基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种薄膜晶体管、阵列基板及显示装置。
背景技术
在显示技术领域，薄膜晶体管(Thin Film Transistor，简称TFT)作为制作显示装置的重要器件，对显示装置的显示品质起着重要作用。例如，在显示装置的阵列基板中阵列排布的每一亚像素中，一般至少包括一个TFT。双U形结构的TFT因可实现较大的工作电流而被广泛应用。
发明内容
本发明的实施例提供一种薄膜晶体管、阵列基板及显示装置。本公开的实施例采用如下技术方案：
本公开实施例一方面提供一种薄膜晶体管，包括栅极、有源层、源极、漏极；所述源极包括连接部以及依次平行设置的第一子部、第二子部、第三子部，其中，在所述子部的第一端，所述连接部连接所述第一子部、所述第二子部、所述第三子部以形成相邻的两个凹部；在所述子部的第二端，所述第二子部的端部到所述连接部的距离小于所述第一子部的端部和所述第三子部的端部到所述连接部的距离；所述漏极包括连接块以及分别位于所述两个凹部中的第一漏极和第二漏极，所述连接块至少部分位于所述第一漏极和所述第二漏极之间以连接所述第一漏极和所述第二漏极。
进一步的，所述连接块全部位于所述第一漏极和所述第二漏极之间，且所述连接块的上边缘与所述第一漏极和所述第二漏极的上边缘平齐。
进一步的，所述栅极具有镂空部，且所述镂空部与所述连接块中位于所述第一漏极和所述第二漏极之间的部分对应。
进一步的，沿与所述第一端到所述第二端的方向垂直的方向上，所述镂空部的尺寸与所述第一漏极和所述第二漏极在该方向上的距离相等。
进一步的，在沿所述第一端到所述第二端的方向上，所述镂空部的尺寸与所述连接块中位于所述第一漏极和所述第二漏极之间的部分在该方向上的尺寸相等。
进一步的，在所述连接块全部位于所述第一漏极和所述第二漏极之间，且所述连接块的上边缘与所述第一漏极和所述第二漏极的上边缘平齐的情况下，在沿所述第一端到所述第二端的方向上，所述镂空部的上边缘超出所述连接块的上边缘，所述镂空部的下边缘超出所述连接块的下边缘。
进一步的，所述镂空部为位于所述栅极靠近所述连接块的上边缘一侧的缺口。
进一步的，所述源极和所述漏极的投影均落入所述有源层。
本公开实施例另一方面还提供一种阵列基板，划分为阵列排布的亚像素，每一亚像素包括像素电极和前述的薄膜晶体管，所述像素电极与所述薄膜晶体管的连接块连接。
本公开实施例再一方面还提供一种显示装置，包括前述的阵列基板。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中提供的一种薄膜晶体管的结构示意图；
图2为相关技术中提供的包括图1中的薄膜晶体管的亚像素的结构示意图；
图3为本公开实施例提供的一种薄膜晶体管的结构示意图；
图4为本公开实施例提供的另一种薄膜晶体管的结构示意图；
图5为本公开实施例提供的一种包括图1和图3的薄膜晶体管的 简化结构示意图；
图6为本公开实施例提供的一种包括图1和图4的薄膜晶体管的简化结构示意图；
图7为本公开实施例提供的再一种薄膜晶体管的结构示意图；
图8为本公开实施例提供的又一种薄膜晶体管的结构示意图；
图9为本公开实施例提供的又一种薄膜晶体管的结构示意图；
图10为本公开实施例提供的阵列基板的结构示意图；
图11为本公开实施例提供的显示装置的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开的实施例提供一种薄膜晶体管、阵列基板及显示装置。该薄膜晶体管在应用于显示领域的情况下，能够在沟道的宽长比一定的情况下，增加亚像素单元的开口率。
本公开实施例提供一种薄膜晶体管、阵列基板及显示装置。该薄膜晶体管包括栅极、有源层、源极、漏极。源极包括连接部以及依次平行设置的第一子部、第二子部、第三子部。在子部的第一端，连接部连接第一子部、第二子部、第三子部以形成相邻的两个凹部。在子部的第二端，第二子部的端部到连接部的距离小于第一子部的端部和第三子部的端部到连接部的距离。漏极包括连接块以及第一漏极和第二漏极，且第一漏极和第二漏极分别位于源极的两个凹部中，连接块至少部分位于第一漏极和第二漏极之间以连接第一漏极和第二漏极。
图1所示为相关的显示装置的阵列基板中的一种双U形结构的TFT。该TFT包括栅极10、有源层20、源极31、漏极32。该TFT的源极31具有并列双U形的结构。漏极32包括分别位于两个U形凹部内的两个子部301，且该两个子部301通过连接块300连接。一般的，该连接块300面积较大。并且，如图2所示，该连接块300通过位于上方的过孔40与像素电极50连接。
然而，如图2所示，该连接块300位于栅极10以外的区域，并采用不透光材质制成。这样一来，对于一个亚像素而言，由于对应连接块300的区域面积较大，从而导致像素电极50的相对面积减小，即该亚像素单元的开口率较小。
本公开实施例提供一种薄膜晶体管，如图3所示，该薄膜晶体管包括栅极10、有源层20、源极31、漏极32。本公开中，该薄膜晶体管可以是顶栅型，也可以是底栅型。图3仅是以底栅型TFT为例进行示意说明的，但本公开并不限制于此。以下实施例均是以底栅型TFT为例，做进一步说明的。
源极31包括连接部30以及依次设置的第一子部311、第二子部312、第三子部313。在上述三个子部的第一端A，连接部30连接第一子部311、第二子部312、第三子部313以形成相邻的两个凹部。在子部的第二端B，第二子部312的端部到连接部30的距离小于第一子部311的端部和第三子部313的端部到连接部30的距离。
此处需要说明的是，上述在子部的第二端B，第二子部312的端部到连接部30的距离小于第一子部311的端部和第三子部313的端部到连接部30的距离是指：在子部的第二端B，第一子部311的端部和第三子部313的端部与第二子部312的端部之间具有一定的落差，且第二子部312的端部相对于第一子部311的端部和第三子部313的端部更靠近连接部30，即第一子部311的端部和第三子部313的端部比第二子部312的端部凸出。
漏极32包括连接块300以及分别位于两个凹部中的第一漏极321和第二漏极322，连接块300至少部分位于第一漏极321和第二漏极322之间以连接第一漏极321和第二漏极322。
需要说明的是，第一，上述漏极32中的第一漏极321和第二漏极322是指，如图3所示，该漏极32中至少与源极31中的子部相对的部分，即在工作状态下，能够与源极31中的子部之间进行有效载流子传输的部分。
第二，上述源极31和漏极32分别作为信号输入电极和信号输出电极。可以是源极31作为信号输入电极，漏极32作为信号输出电极。例如，在显示面板中，将与数据线连接的源极31作为信号输入电极， 与像素电极连接的漏极32作为信号输出电极。当然，也可以是漏极32作为信号输入电极，源极31作为信号输出电极。本公开对此不作限定。本实施例中，均是以源极31作为信号输入电极，漏极32作为信号输出电极作为示例进行说明。
第三，本公开中，对于连接块300位于第一漏极321和第二漏极322之间以外的部分，沿与第一端A到第二端B垂直的方向上的尺寸，可以是与第一漏极321和第二漏极322内侧之间的距离相等，也可以是如图3所示，与第一漏极321和第二漏极322外侧之间的距离相等，只要能够保证该连接块300的大小满足后续的连接即可，本公开对此不作限定。
第四，如图3所示，由于第一漏极321和第二漏极322是指漏极32中与源极31中的子部相对的部分(参考“第一”)，在此基础上，本领域的技术人员应当理解到，对于上述连接块300至少部分位于第一漏极321和第二漏极322之间的部分是指，如图3所示，该连接块300中位于第一漏极321和第二漏极322之间正对的区域中的部分。也即该部分的投影会落入栅极10中。而对于连接块300中位于第一漏极321和第二漏极322之间以外的部分(参考“第三”)是指，位于第一漏极321和第二漏极322之间正对的区域以外的部分。
综上所述，在子部的第二端，第二子部的端部到连接部的距离小于第一子部的端部和第三子部的端部到连接部的距离。且连接块至少部分位于第一漏极和第二漏极之间以连接第一漏极和第二漏极，即连接块与栅极在上述第一漏极和第二漏极之间具有重叠部分。基于此，本公开相比于相关技术中的第一子部、第二子部、第三子部长度一致、且连接块完全位于栅极以外的双U形TFT而言，示意的可以看作是，第一子部和第三子部相比于相关技术加长的距离与第二子部相比于相关技术缩短的距离相等，且连接块向靠近源极方向被移动与上述加长或者缩短相同的距离，以使得连接块至少部分位于第一漏极和第二漏极之间以连接第一漏极和第二漏极。并且，在保证其他条件相同的情况下，本公开不仅可以保证与相关技术中的TFT具有相同的沟道宽长比，并且能够在应用于显示领域的情况下，使得因第一子部和第三子部的加长所带来的开口率减小的部分，小于因连接块向靠近源极方向移动所带来的开口 率增大的部分，从而有利于增加亚像素单元的开口率。即本公开能够在沟道的宽长比一定的情况下，增加亚像素单元的开口率。
此处还需要说明的是，本公开中，第一子部311和第三子部313的上边缘，可以平齐，也可以不平齐。为了在开口率一定的情况下，尽可能的增加该TFT的沟道宽长比，可选的，第一子部311和第三子部313的上边缘平齐。
为了更进一步地增加亚像素单元的开口率，可选的，如图4所示，连接块300全部位于第一漏极321和第二漏极322之间，且连接块300的上边缘与第一漏极321和第二漏极322的上边缘平齐，也即连接块300的投影全部落入栅极10中。
需要说明的是，第一，连接块300的上边缘以及第一漏极321和第二漏极322的上边缘是指，连接块300、第一漏极321、第二漏极322背离源极31中第二子部312一侧的边缘。
第二，上述连接块300的上边缘与第一漏极321和第二漏极322的上边缘平齐是指为了避免在第一漏极321和第二漏极322的上边缘超出连接块300的上边缘时，源极31中第一子部311、第三子部313在超出部分不能有效的形成沟道。并且该超出部分所在的整个区域不能透光，不利于整个亚像素的开口率增加。
以下通过具体实施例，来进一步举例说明本公开中的TFT相对于相关技术中的TFT(如图1)，有利于增加亚像素单元的开口率。为了便于说明，如图1所示，假设相关连接块300——漏极32中对应过孔的连接部分——为正方形，且该正方形的边长为4H，该连接部分(连接块300)与两个子部301中的一个之间的横向连接子部302的高度为正方形边长的一半，即2H。
以图3中连接块300部分位于第一漏极321和第二漏极322之间为例，为了更清楚的对图3的TFT和图1的TFT的亚像素单元的开口率进行比较，图5为包括图3的TFT和图1的栅极以及连接块(加黑虚线部分)的结构示意图。
结合图1和图3，如图5所示，假设图3中第一子部311和第三子部313相比于图1中加长的距离为H，第二子部312相比于图1中缩短 的距离为H。则相比于图1中TFT，图3中沟道宽度W减小和增加部分的尺寸相等，即图1和图3相比，两者的沟道宽度W相同。那么在两者沟道长度L相等的情况下，图3中的TFT与相关图1中的TFT相比，具有相等的沟道宽长比(W/L)。
在此基础上，在应用于显示领域的情况下，如图5所示，无论对于相关技术还是本公开，连接块300位于栅极10以外的部分与数据线60之间的部分会被黑矩阵遮挡，均不能用于显示，在计算开口率时，该部分也需被计算在不透光的部分中。
对比图1和图3(参考图5)，因第一子部311和第三子部313的加长以及连接块300向靠近源极31方向移动所带来的面积增加的部分，小于因连接块300向靠近源极31方向移动所带来的面积减小的部分。即，图5中阴影S1和阴影S2之和小于阴影S3和阴影S4之和(S1+S2＜S3+S4)。具体地，阴影S1为第一子部311和第三子部313的加长所带来开口率减小部分的面积；阴影S2为连接块300向靠近源极31方向移动所带来开口率减小部分的面积；阴影S3、阴影S4为连接块300向靠近源极31方向移动所带来开口率增加部分的面积，其中，阴影S3对应图1中连接块300的一部分的区域，阴影S4对应阴影S3与数据线60之间的区域。另外，本公开中为了便于描述，S1、S2、S3、S4可以作为各部分的标号，也可以直接表示各部分的面积。
具体的，上述阴影S1、阴影S2、阴影S3、阴影S4的高度均相同，均为H。在实际的制作中，阴影S1和阴影S4的长度接近(且约为连接块300的边长的1/3～1/2倍)，其中S4的长度是指连接块300到数据线60之间的距离。则阴影S1和阴影S4的面积接近相等(S1≈S4)。另外，阴影S3的长度为连接块300的边长，而阴影S2的长度小于连接块300的边长，则阴影S2小于阴影S3的面积(S2＜S3)。因此，阴影S1与阴影S2的面积和，小于阴影S3与阴影S4的面积和，即S1+S2＜S3+S4。也即第一子部311和第三子部313的加长所带来的面积增加的部分，小于因连接块300向靠近源极31方向移动所带来的面积减小的部分，从而使得本公开能够在沟道的宽长比一定的情况下，增加亚像素单元的开口率。
在图4中，连接块300全部位于第一漏极321和第二漏极322之间，且连接块300的上边缘与第一漏极321和第二漏极322的上边缘平齐。为了更清楚的对图4的TFT和图1的TFT的亚像素单元的开口率进行比较，图6为包括图4的TFT和图1的栅极以及连接块(加黑虚线部分)的示意图。
结合图1和图4，如图6所示，在连接块300的上边缘与第一漏极321和第二漏极322的上边缘平齐的情况下，在不考虑相关技术图1中的横向连接子部302与栅极10之间的缝隙h时(参考图1)，可以近似看作：相比于图1，图4中第一子部311和第三子部313加长的长度为2H(连接块300的边长的一半)，第二子部312缩短的长度为2H。则相比于图1，图4中沟道宽度W减小和增加部分的尺寸相等，即图1和图4相比，两者的沟道宽度W相同。那么在两者沟道长度L相等的情况下，图4中的TFT与相关图1中的TFT相比，具有相等的沟道宽长比(W/L)。
在上述图3所示的实施例中，连接块300具有位于栅极10以外的部分，使得该部分与数据线60之间的部分不能用于显示(可参考图1或者图3)。而本实施例中图4所示的TFT，连接块300完全位于栅极10所在的区域。
在此情况下，对比图1和图4(参考图6)，因第一子部311和第三子部313的加长所带来的面积增加的部分，即图6中阴影S1，小于因连接块300向靠近源极31方向移动所带来的面积减小的部分，即图6中阴影S2和阴影S3之和，即S1＜S2+S3，其中，阴影S2对应图1中连接块300的一部分的区域，阴影S3对应阴影S2与数据线60之间的区域。
具体的，上述阴影S1、阴影S2、阴影S3的高度均相同，均为2H。在实际的制作中，阴影S1和阴影S3的长度接近(且约为连接块300的边长的1/3～1/2倍)，也即阴影S1和阴影S3的面积接近相等(S1≈S3)。阴影S2的长度为连接块300的边长，宽度为2H(即连接块300的边长的一半)。图1中的横向连接子部302完全位于图4中的栅极10所在的区域。这一来，阴影S2的面积则相当于开口率增加的部分。也即因第一子部311和第三子部313的加长所带来的面积增加的部 分，小于因连接块300向靠近源极31方向移动所带来的面积减小的部分，从而使得本公开能够在沟道的宽长比一定的情况下，增加亚像素单元的开口率。
综上所述，对比图3所示的实施例，本实施例中设计方案的开口率与相关技术中的开口率之间的差值更大。也即本实施例的设计方案能够更大程度的在沟道的宽长比(W/L)一定的情况下，增加亚像素单元的开口率。
由于本公开中连接块300中位于第一漏极321和第二漏极322之间的部分会与栅极10所在的区域具有交叠(从连接块300向栅极10观看，两者的投影具有交叠，并非实际意义上的交叠)，可参考图4。这样一来，会使得连接块300与栅极10之间存在较大的寄生电容C gd。因此，本公开中，为了减小连接块300与栅极10之间的寄生电容C gd，可选的，如图7所示，在连接块300中位于第一漏极321和第二漏极322之间的部分所对应的栅极10的区域设置镂空部70。
需要说明的是，本公开中对上述镂空部70的形状、大小不作限定，在不影响TFT的性能的基础上，可以是正方形，也可以是长方形。该镂空部70的面积可以与连接块300中位于第一漏极321和第二漏极322之间的部分的面积一样的大，也可以比该部分面积大，或者比该部分面积小，本公开对此均不作限定。
当然，为了最大程度的减小上述寄生电容C gd，如图8所示，可选的，在栅极10的任一表面上，沿与第一端A到第二端B的方向垂直的方向上，该镂空部70的尺寸与第一漏极321和第二漏极322在该表面上的投影在该方向上的距离相等或者近似相等；和/或，在沿第一端A到第二端B的方向上，该镂空部70的尺寸与连接块300中位于第一漏极321和第二漏极322之间的部分在该表面上的投影在该方向上的尺寸相等或者近似相等。例如，图8中镂空部70与连接块300的形状、大小完全一致，且位置完全重叠。
当漏极32因工艺波动在沿第一端A到第二端B的方向上产生偏移量时，可能会导致漏极32与栅极10的交叠面积发生变化，从而导致上述寄生电容C gd发生变化而不稳定，产生不良影响。为了避免这种情况的发生，如图9所示，在连接块300全部位于第一漏极321和第二漏极 322之间，且连接块300的上边缘与第一漏极321和第二漏极322的上边缘平齐的情况下，在栅极10的任一表面上，在沿第一端A到第二端B的方向上，镂空部70的上边缘超出连接块300在该表面上的投影的上边缘，镂空部70的下边缘超出连接块300在该表面上的投影的下边缘。这样一来，即使因工艺波动，漏极32在沿第一端A到第二端B的方向上产生少量的偏移，漏极32与栅极10的交叠面积仍然能够保持不变，从而使得漏极32与栅极10之间具有相对稳定的寄生电容C gd。
在此基础上，为了便于制作加工，可选的，如图9所示，该镂空部70为位于栅极10靠近连接块300在栅极10上的投影的上边缘一侧的缺口。
此处需要说明的是，在上述镂空部70的下边缘超出连接块300在栅极10上的投影的下边缘的情况下，如图9所示，为了避免源极31因工艺波动沿第一端A到第二端B的方向上产生偏移量，导致第二子部312的上边缘的投影伸入至该镂空部70中，在实际的制作工艺中，一般需要在栅极10对应第二子部312的上边缘的位置与该镂空部70之间预留一定的尺寸。
更进一步的，本公开中为了简化工艺，降低制作成本，可选的，如图3至图8所示，源极31和漏极32的投影均落入有源层20。这样一来，可以采用半曝光掩膜(Half Tone)工艺，通过一次构图(即一张掩膜版)、两次刻蚀形成源极31、漏极32以及有源层20。当然也可以通过两次构图工艺(即两张掩膜板)分别进行构图制作，本公开对此不作限定。
本公开实施例还提供一种阵列基板1000。如图10所示，该阵列基板由横纵交错的数据线和栅线界定出以阵列形式排布的多个亚像素500。该多个亚像素500中的每一个包括像素电极50和前述薄膜晶体管。像素电极50与薄膜晶体管的连接块300通过过孔40连接。该阵列基板中的薄膜晶体管具有与前述实施例提供的薄膜晶体管相同的结构和有益效果。由于前述实施例已经对薄膜晶体管的结构和有益效果进行了详细的描述，此处不再赘述。
需要说明的是，在本公开实施例中，上述阵列基板可以是ADS(Advanced-Super Dimensional Switching，高级超维场开关)型、IPS (In Plane Switch，横向电场效应)型或TN(Twist Nematic，扭曲向列)型，本公开对此不作限定。
本公开实施例还提供一种显示装置2000，如图11所示，包括前述的阵列基板1000。同样，该显示装置中包括的薄膜晶体管具有与前述实施例提供的薄膜晶体管相同的结构和有益效果。由于前述实施例已经对薄膜晶体管的结构和有益效果进行了详细的描述，此处不再赘述。
此处需要说明的是，在本公开实施例中，显示装置具体至少可以包括液晶显示面板。该显示面板，例如可以应用至液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件中。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种薄膜晶体管，包括栅极、有源层、源极、漏极；
    所述源极包括连接部以及依次设置的第一子部、第二子部、第三子部，其中，在所述第一子部、第二子部和第三子部的第一端，所述连接部连接所述第一子部、所述第二子部、所述第三子部以形成相邻的两个凹部；在所述子部的第二端，所述第二子部的端部到所述连接部的距离小于所述第一子部的端部和所述第三子部的端部到所述连接部的距离；
    所述漏极包括连接块以及分别位于所述两个凹部中的第一漏极和第二漏极，所述连接块至少部分位于所述第一漏极和所述第二漏极之间以连接所述第一漏极和所述第二漏极。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述连接块全部位于所述第一漏极和所述第二漏极之间，且所述连接块的上边缘与所述第一漏极和所述第二漏极的上边缘平齐。
  3. 根据权利要求1或2所述的薄膜晶体管，其中，所述栅极具有镂空部，且所述镂空部与所述连接块中位于所述第一漏极和所述第二漏极之间的部分对应。
  4. 根据权利要求3所述的薄膜晶体管，其中，在所述栅极的任一个表面上，沿与所述第一端到所述第二端的方向垂直的方向上，所述镂空部的尺寸与所述第一漏极和所述第二漏极在所述表面上的投影在该方向上的距离相等。
  5. 根据权利要求3所述的薄膜晶体管，其中，在沿所述第一端到所述第二端的方向上，所述镂空部的尺寸与所述连接块中位于所述第一漏极和所述第二漏极之间的部分在该方向上的尺寸相等。
  6. 根据权利要求3所述的薄膜晶体管，其中，在所述连接块全部位于所述第一漏极和所述第二漏极之间，且所述连接块的上边缘与所述第一漏极和所述第二漏极的上边缘平齐的情况下，在沿所述第一端到所述第二端的方向上，所述镂空部的上边缘超出所述连接块的上边缘，所述镂空部的下边缘超出所述连接块的下边缘。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述镂空部为位于所述栅极靠近所述连接块的上边缘一侧的缺口。
  8. 根据权利要求1所述的薄膜晶体管，其中，所述源极和所述漏极的投影均落入所述有源层。
  9. 一种阵列基板，划分为阵列排布的亚像素，每一亚像素包括像素电极和权利要求1-8任一项所述的薄膜晶体管，所述像素电极与所述薄膜晶体管的连接块连接。
  10. 一种显示装置，包括权利要求9所述的阵列基板。
PCT/CN2018/077333 2017-05-05 2018-02-27 薄膜晶体管、阵列基板及显示装置 WO2018201781A1 (zh)

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