WO2018196075A1 - 一种阵列基板及制备方法、显示装置 - Google Patents

一种阵列基板及制备方法、显示装置 Download PDF

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Publication number
WO2018196075A1
WO2018196075A1 PCT/CN2017/085852 CN2017085852W WO2018196075A1 WO 2018196075 A1 WO2018196075 A1 WO 2018196075A1 CN 2017085852 W CN2017085852 W CN 2017085852W WO 2018196075 A1 WO2018196075 A1 WO 2018196075A1
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Prior art keywords
layer
gate insulating
insulating layer
source
gate
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English (en)
French (fr)
Inventor
李松杉
徐源竣
刘兆松
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/541,363 priority Critical patent/US10411047B2/en
Publication of WO2018196075A1 publication Critical patent/WO2018196075A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a preparation method, and a display device.
  • IGZO indium gallium zinc oxide
  • the carrier mobility of IGZO is 20 to 30 times that of amorphous silicon, which can greatly improve the thin film transistor pair in the array substrate.
  • the charge and discharge rate of the pixel electrode increases the response speed of the pixel, achieving a faster refresh rate, and the faster response also greatly increases the line scan rate of the pixel.
  • the oxygen vacancy occurs in the conductor region, and the oxygen vacancies in the channel layer are easily directed to the channel region. Migration causes a problem of leakage of the array substrate.
  • the invention mainly provides an array substrate, a preparation method and a display device, which are intended to solve the problem of leakage of the array substrate caused by the migration of oxygen vacancies to the channel region after ion implantation of the channel layer in the array substrate. .
  • the present invention adopts a technical solution to provide an array substrate including: a channel layer; a gate insulating layer including a first portion and a second portion connected side by side, disposed in the channel layer And exposing the source and drain contact regions on the channel layer, the second portion of the gate insulating layer being located on both sides of the first portion of the gate insulating layer; the gate layer being disposed at the a first portion of the gate insulating layer; a source and a drain respectively connected to the source and drain contact regions of the channel layer, wherein the gate is not covered by the gate layer
  • the vertical projection length of the second portion of the insulating layer on the channel layer is 1-10 microns.
  • another technical solution adopted by the present invention is to provide a method for fabricating an array substrate, the method comprising: forming a channel layer; sequentially forming a gate insulating layer and a gate on the channel layer a gate layer, the gate insulating layer including a first portion and a second portion connected side by side, and exposing source and drain contact regions on the channel layer, the second portion of the gate insulating layer being located On both sides of the first portion of the gate insulating layer, the gate layer is formed on the first portion of the gate insulating layer; and a source and a drain are formed, and the source and drain of the channel layer are The pole contact areas are respectively connected.
  • a display device comprising the above array substrate or the array substrate prepared by the above method for preparing an array substrate.
  • the invention has the beneficial effects that the present invention distinguishes the second portion of the gate insulating layer disposed on the channel layer by the second portion of the gate insulating layer, and the channel layer is ion-implanted to be conductorized, and the conductorized region is different from the prior art.
  • the oxygen vacancy is difficult to pass over the channel region of the second portion of the corresponding gate insulating layer as the isolation region and then diffused to the channel region of the first portion of the corresponding gate insulating layer, thereby solving the problem of conductor formation due to ion implantation of the channel layer The problem of leakage of the array substrate.
  • FIG. 1 is a schematic cross-sectional view showing an embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic cross-sectional view showing another embodiment of the array substrate of the present invention.
  • FIG. 3 is a schematic flow chart of an embodiment of a method for preparing an array substrate provided by the present invention.
  • FIG. 4 is a schematic cross-sectional view showing formation of a channel layer in the preparation method provided in FIG. 3;
  • FIG. 5 is a schematic view showing a process of forming a gate layer and a gate insulating layer in the preparation method provided in FIG. 3;
  • FIG. 6 is a schematic cross-sectional view of the gate layer and the gate insulating layer formed in FIG. 5;
  • FIG. 7 is a schematic cross-sectional view of an array substrate prepared by the preparation method provided in FIG. 3;
  • Figure 8 is a block diagram showing an embodiment of a display device of the present invention.
  • FIG. 1 is a schematic cross-sectional view of an embodiment of an array substrate of the present invention, including:
  • the channel layer 102 may be disposed on the buffer layer 101.
  • the channel layer 102 includes a channel region 1021 and a source/drain contact region 1022.
  • the channel region 1021 is located at a position corresponding to the gate layer 104, and the source and drain contact regions 1022 are The channel region 1021 extends to both sides.
  • the gate insulating layer 103 includes a first portion 1031 and a second portion 1032 connected side by side, disposed on the channel layer 102, and exposing the source and drain contact regions 1022 on the channel layer 102, and second The portion 1031 is located on both sides of the first portion 1032.
  • the gate layer 104 is disposed on the first portion 1031.
  • the gate layer 104 is disposed on the first portion 1031 and may cover the first portion 1031.
  • the first portion 1031 may not be covered, or may be larger or smaller than the first portion 1031. Part of 1031.
  • the dielectric layer 106 is uniformly covered over the buffer layer 101, the channel layer 102, the first portion 1031, the second portion 1032, and the gate layer 104.
  • the source electrode 1051 and the drain electrode 1052 pass through the dielectric layer 106 and are respectively disposed on the source/drain contact region 1022.
  • the second portion 1032 is disposed between the first portion 1031 and the source 1051 and between the first portion 1031 and the drain 1052.
  • the second portion 1032 can be disposed between the first portion 1031 and the source 1051 or between the first portion 1031 and the drain 1052.
  • the vertical projection length of the second portion 1032 on the channel layer 102 is 1-10 microns, such as 1.2 microns, 1.4 microns, 1.6 microns, 1.8 microns, 1.9 microns, 2 microns, 2.5 microns, 3 microns, 4 microns. 5 microns, 6 microns, 7 microns, 8 microns, 9 microns or 10 microns.
  • the second portion 1032 may be an extension of the first portion 1031 in the direction of the source 1051 and/or the drain 1052, that is, the material of the second portion 1032 and the first portion 1031 are the same and the vertical from the source 1051 to the drain 1052.
  • the projections overlap.
  • the channel layer 102 may be an amorphous oxide IGZO containing indium, gallium, and zinc, and is mainly composed of In2O3, Ga2O3, and ZnO, and is an N-type semiconductor material.
  • the gate insulating layer is a silicon oxide layer, for example, the gate insulating layer is a silicon dioxide SiO2 layer.
  • the second portion 1032 may not be in contact with the first portion 1031, and the thickness of the second portion 1032 may be different than the first portion 1031.
  • the gate layer 104 is used as a mask and the second portion 1032 is used as a mask, and the source/drain contact region 1022 is ion-implanted to be conductor-conducted.
  • the channel layer 102 under the second portion 1032 is used as an isolation region, and the oxygen vacancies in the source/drain contact region 1022 are difficult to migrate into the channel region 1021, thereby solving the source-drain contact region 1022 in the array substrate for ion implantation. After the conductor is formed, the oxygen vacancies migrate to the channel region 1021, causing a problem of leakage of the array substrate.
  • FIG. 2 a cross-sectional view of another embodiment of the array substrate of the present invention, wherein the second portion 2032 of the gate insulating layer can be respectively connected to the source electrode 2051 and the drain electrode 2052.
  • the second portion 2032 can only interface with the source 2051 or the drain 2052.
  • FIG. 3 is a schematic flow chart of an embodiment of a method for fabricating an array substrate provided by the present invention
  • FIG. 4 is a schematic cross-sectional view showing a channel layer formed in the preparation method provided in FIG. 3
  • FIG. 3 is a schematic view showing a process of forming a gate layer and a gate insulating layer in the preparation method
  • FIG. 6 is a schematic cross-sectional view showing a gate layer and a gate insulating layer formed in FIG. 5
  • FIG. 7 is a manufacturing method provided in FIG. A schematic cross-sectional view of the resulting array substrate.
  • the silicon-based oxide SiOx buffer layer 401 can be formed by plasma enhanced chemical vapor deposition on the glass substrate substrate 400.
  • the buffer layer 401 can be made of silicon dioxide.
  • an IGZO layer which is prepared as a channel layer is formed on the buffer layer 401, and a physical vapor deposition method or a laser pulse deposition method may be employed, followed by exposure, development, etching, and lift-off processes, thereby obtaining a cover buffer layer 401.
  • IGZO is an amorphous oxide containing indium, gallium and zinc, mainly composed of In2O3, Ga2O3 and ZnO, and is an N-type semiconductor material.
  • S302 sequentially forming a gate insulating layer and a gate layer on the channel layer, the gate insulating layer including the first portion and the second portion connected side by side, and exposing the source and drain contact regions on the channel layer, the gate A second portion of the pole insulating layer is located on both sides of the first portion of the gate insulating layer, and a gate layer is formed on the first portion of the gate insulating layer.
  • a gate insulating layer 503 is formed on the channel layer 402, and the gate insulating layer 503 can be formed by chemical vapor deposition.
  • the gate insulating layer 503 can be a silicon oxide layer, such as silicon dioxide.
  • a gate layer 504 is formed on the gate insulating layer 503, and the metal can be deposited by physical vapor deposition to form the gate layer 504.
  • a gate insulating layer 603 including a patterned first portion 6031 and a second portion 6032 and a patterned gate layer 604 are further obtained by an exposure, development, etching, and lift-off process.
  • the photomask used in the photolithography process step may be a grayscale mask 506, which may also be called a halftone mask.
  • the grayscale mask 506 may be composed of a first gray light transmissive area 5061, a second gray light transmissive area 5062, and a third gray light transmissive area 5063.
  • the first light transmissive area 5061 has the lowest light transmittance.
  • the light transmittance of the second light transmitting region 5062 is higher than that of the first light transmitting region 5061, and the light transmittance of the third light transmitting region 5063 is higher than that of the second light transmitting region 5062.
  • a positive photoresist layer 505 is coated on the gate layer 504.
  • the positive photoresist layer 505 dissolves slowly during etching, but after the light is irradiated, the dissolution rate is affected.
  • the acceleration of the positive photoresist layer 505 becomes faster as the illumination intensity is higher, depending on the intensity and time of the illumination, that is, the illumination intensity is the same.
  • the grayscale mask 506 is disposed directly above the positive photoresist layer 505, and the positive photoresist layer 505 is vertically illuminated on the grayscale mask 506, due to the first light transmission.
  • the region 5061 has the lowest transmittance, and the first exposure region 5051 corresponding to the positive photoresist layer 505 is hardly dissolved by the light; since the second light transmission region 5062 has a certain light transmittance and corresponds to positiveness
  • the second exposure region 5052 of the photoresist layer 505 has a faster dissolution rate due to a certain illumination; since the third light transmission region 5063 has the highest transmittance, the corresponding positive photoresist layer 505 is replaced.
  • the three exposure areas 5053 receive the most illumination and the dissolution rate becomes the fastest.
  • the etching operation is performed. Since the first exposure region 5051 is difficult to dissolve, the third exposure region 5053 can protect the underlying structure from being etched and dissolved; since the second exposure region 5052 dissolves faster, a certain etching is set. In the case of the condition, the second exposed region 5052 and the corresponding gate layer 5042 below it can be etched and dissolved, and the gate insulating layer 503 is not dissolved by etching; since the third exposed region 5053 has the fastest dissolution rate, it is set When a certain etching condition is determined, the gate layer 5043 and the gate insulating layer 5033 under the third exposure region 5053 are not protected, and all of the etching can be dissolved and dissolved, and the etching solution selected here does not react with the channel layer. .
  • the light transmittance adjustment of the first light transmitting region 5061, the second light transmitting region 5062 and the third light transmitting region 5063, the control of the intensity and time of the light, the selection and ratio of the etching liquid, the etching method, and the etching are performed. Temperature and time adjustment, etc., control of factors affecting the etching speed, so that only the gate insulating layer 5033 and the gate layer 5042 and the gate layer 5043 are etched away, and the gate layer and the gate of other regions are not etched.
  • the effect of the insulating layer further results in a patterned gate insulating layer 603 and gate layer 604 as shown in FIG.
  • the source/drain contact region 6022 of the channel layer 602 is ion-implanted and self-aligned with the patterned gate layer 604 as a mask, and then annealed.
  • the ion implanted ions may be one of oxygen, argon or sulfur hexafluoride, and the second portion 6032 acts as a mask to isolate the source-drain contact region 6022 from the channel region 6021.
  • the region 6021 can be isolated as ions without being implanted.
  • the source-drain contact region 6022 after ion implantation is annealed to restore structural defects caused by ion implantation to the source-drain contact region 6022.
  • the gate insulating layer 5033, the gate layer 5042, the gate layer 5043, the second exposure region 5052, and the third exposure are not disclosed.
  • the region 5053, the second light transmitting region 5062, and the third light transmitting region 5063 are all disposed opposite to each other.
  • the isolation function of the isolation region 6021 due to the isolation function of the isolation region 6021, after the ion implantation is performed on the source/drain contact region 6022, the oxygen vacancies in the source/drain contact region 6022 are difficult to migrate to the channel through the isolation region. Area 6021.
  • S303 forming a source and a drain, and respectively connecting the source and drain contact regions of the channel layer.
  • the dielectric layer 708 is formed on the buffer layer 401 after the annealing process, and the dielectric layer 708 is uniformly covered over the buffer layer 401, the channel layer 602, the first portion 6031, the second portion 6032, and the gate layer 604.
  • a silicon oxide layer is formed by a method including, but not limited to, chemical vapor deposition.
  • the silicon oxide layer is a dielectric layer 708 capable of isolating the influence of external oxygen or water molecules on the channel layer 602.
  • the stability is protective.
  • a patterned contact hole can be formed by photoresist coating and exposure of the dielectric layer 708, and then dry etching is performed to obtain a through dielectric layer 708 and a source/drain contact region. Contact hole of 6022.
  • a metal layer may be deposited by physical vapor deposition in two contact holes, and then a metal layer is deposited on the deposited metal layer, and then exposed, developed, etched, and stripped to obtain a pattern.
  • the source electrode 7071 and the drain electrode 7072, and the obtained source electrode 7071 and the drain electrode 7072 are in contact with the source/drain contact region 6022.
  • the present invention uses the gate layer as a self-aligned mask and the second portion of the gate insulating layer as a mask in the ion implantation of the channel layer, in the source of the channel layer.
  • the oxygen vacancies in the source-drain contact region are difficult to migrate to the channel region through the isolation region, thereby solving the problem that the channel layer in the array substrate is ion-implanted and then subjected to the conductor treatment.
  • the migration of oxygen vacancies to the channel region causes a problem of leakage of the array substrate.
  • FIG. 8 is a schematic structural diagram of an embodiment of a display device according to the present invention.
  • the array substrate in the display device 80 is the array substrate prepared by the above-described array substrate of the present invention or the method for preparing the array substrate of the present invention.

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Abstract

一种阵列基板及制备方法、显示装置，阵列基板包括：沟道层（102）；栅极绝缘层（103），包括并排连接的第一部分（1031）和第二部分（1032），设置于沟道层（102）上，并且暴露出沟道层（102）上的源极和漏极接触区（1022），栅极绝缘层（103）的第二部分（1032）位于栅极绝缘层（103）的第一部分（1031）两侧；栅极层（104），设置于栅极绝缘层（103）的第一部分（1031）；源极（1051）和漏极（1052），与沟道层（102）的源极和漏极接触区（1022）分别对应连接。阵列基板解决因沟道层（102）进行离子注入使其导体化导致阵列基板漏电的问题。

Description

一种阵列基板及制备方法、显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板及制备方法、显示装置。
【背景技术】
目前，IGZO（铟镓锌氧化物）材料逐渐成为新一代阵列基板技术中的沟道层材料，IGZO的载流子迁移率是非晶硅的20~30倍，可以大大提高阵列基板中薄膜晶体管对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率。
现有技术中，在对IGZO阵列基板中的沟道层进行离子注入使其导体化处理后，会造成导体化区出现氧空位，并且导体化的沟道层中的氧空位容易向沟道区迁移，从而导致阵列基板出现漏电的问题。
【发明内容】
本发明主要提供一种阵列基板及制备方法、显示装置，旨在解决因对阵列基板中的沟道层进行离子注入使其导体化后，氧空位向沟道区迁移导致的阵列基板漏电的问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括：沟道层；栅极绝缘层，包括并排连接的第一部分和第二部分，设置于所述沟道层上，并且暴露出所述沟道层上的源极和漏极接触区，所述栅极绝缘层的第二部分位于所述栅极绝缘层的第一部分两侧；栅极层，设置于所述栅极绝缘层的第一部分；源极和漏极，与所述沟道层的所述源极和漏极接触区分别对应连接，其中，未被所述栅极层覆盖的所述栅极绝缘层的第二部分在所述沟道层上的垂直投影长度为1-10微米。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板的制备方法，所述方法包括：形成沟道层；在所述沟道层上依次形成栅极绝缘层和栅极层，所述栅极绝缘层包括并排连接的第一部分和第二部分，并且暴露出所述沟道层上的源极和漏极接触区，所述栅极绝缘层的第二部分位于所述栅极绝缘层的第一部分两侧，所述栅极层形成于所述栅极绝缘层的第一部分上；以及形成源极和漏极，与所述沟道层的所述源极和漏极接触区分别对应连接。
为解决上述技术问题，本发明采用的另一个技术方案是：一种显示装置，其包括上述阵列基板或上述一种阵列基板的制备方法制备得到的阵列基板。
本发明的有益效果是：区别于现有技术的情况，本发明通过设置在沟道层上的栅极绝缘层第二部分，使得沟道层进行离子注入使其导体化后，被导体化区域的氧空位难以越过作为隔离区的对应栅极绝缘层第二部分的沟道区进而扩散到对应栅极绝缘层第一部分的沟道区，从而解决因为沟道层进行离子注入使其导体化导致阵列基板漏电的问题。
【附图说明】
图1是本发明阵列基板一实施例的截面示意图；
图2是本发明阵列基板另一实施例的截面示意图；
图3是本发明提供的阵列基板的制备方法一实施例的流程示意图；
图4是图3提供的制备方法中的形成沟道层的截面示意图；
图5是图3提供的制备方法中的形成栅极层和栅极绝缘层的工艺示意图；
图6是图5形成的栅极层和栅极绝缘层的截面示意图；
图7是图3提供的制备方法制得的阵列基板的截面示意图；
图8是本发明显示装置一实施例的结构示意图。
【具体实施方式】
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的一种薄膜晶体管及其制备方法做进一步详细描述。
请参阅图1，本发明阵列基板一实施例的截面示意图，其中包括：
缓冲层101、沟道层102、栅极绝缘层103、栅极层104、源极1051、漏极1052、介电层106。
其中，沟道层102可以设置在缓冲层101上，沟道层102包括沟道区1021和源漏极接触区1022，沟道区1021位置与栅极层104对应，源漏极接触区1022是沟道区1021向两侧延伸。
其中，栅极绝缘层103，包括并排连接的第一部分1031和第二部分1032，设置于所述沟道层102上，并且暴露出沟道层102上的源极漏极接触区1022，第二部分1031位于第一部分1032的两侧。
其中，栅极层104设置于第一部分1031，例如：栅极层104设置于第一部分1031之上，且可以恰好覆盖第一部分1031，当然，也可以不恰好覆盖第一部分1031，也可以大于或小于第一部分1031。
进一步地，介电层106均匀覆盖在缓冲层101、沟道层102、第一部分1031、第二部分1032和栅极层104上方。
其中，源极1051和漏极1052，贯通于介电层106且分别设置于源漏极接触区1022上。
其中，第二部分1032设置于第一部分1031与源极1051之间和设置于第一部分1031与漏极1052之间。
在其他一些实施例中，第二部分1032可以设置于第一部分1031与源极1051之间或设置于第一部分1031与漏极1052之间。
进一步地，第二部分1032在沟道层102上的垂直投影长度为1-10微米，例如1.2微米、1.4微米、1.6微米、1.8微米、1.9微米、2微米、2.5微米、3微米、4微米、5微米、6微米、7微米、8微米、9微米或10微米。
进一步地，第二部分1032可以是第一部分1031向源极1051和/或漏极1052方向上的延伸，即第二部分1032和第一部分1031的材料相同及从源极1051向漏极1052的垂直投影相重叠。
其中，沟道层102可以是一种含有铟、镓和锌的非晶氧化物IGZO，主要由In2O3、Ga2O3和ZnO构成，是一种N型半导体材料。
其中，栅极绝缘层为硅氧化物层，例如：栅极绝缘层为二氧化硅SiO2层。
在其他一些实施例中，第二部分1032可以不与第一部分1031接触、第二部分1032的厚度可以与第一部分1031不同。
在本实施例中提供的阵列基板，在离子注入时，以栅极层104作为光罩、第二部分1032作为遮罩，使源漏极接触区1022被离子注入使其导体化后，由于对应第二部分1032部分下方的沟道层102作为隔离区，源漏极接触区1022中的氧空位难以迁移到沟道区1021中，从而解决阵列基板中的源漏极接触区1022进行离子注入使其导体化后，氧空位向沟道区1021迁移导致而导致阵列基板漏电的问题。
请参阅图2，本发明阵列基板另一实施例的截面示意图，其中，栅极绝缘层的第二部分2032可分别与源极2051和漏极2052相接。
在其他一些实施例中，第二部分2032可只与源极2051或漏极2052相接。
请一并参阅图3-7，图3是本发明提供的阵列基板的制备方法一实施例的流程示意图；图4是图3提供的制备方法中的形成沟道层的截面示意图；图5是图3提供的制备方法中的形成栅极层和栅极绝缘层的工艺示意图；图6是图5形成的栅极层和栅极绝缘层的截面示意图；图7是图3提供的制备方法制得的阵列基板的截面示意图。
S301：形成沟道层。
其中，准备玻璃基板400，可以通过在玻璃基板基板400用等离子体增强化学气相沉积法形成硅基氧化物SiOx缓冲层401，例如：可以用二氧化硅制成缓冲层401。
其中，在缓冲层401上形成一层预备作为沟道层的IGZO层，可采用物理气相沉积法或激光脉冲沉积法，然后进行曝光、显影、刻蚀及剥离制程，进而在得到覆盖缓冲层401的图案化的沟道层402。
其中，IGZO是一种含有铟、镓和锌的非晶氧化物，主要由In2O3、Ga2O3和ZnO构成，是一种N型半导体材料。
S302：在沟道层上依次形成栅极绝缘层和栅极层，栅极绝缘层包括并排连接的第一部分和第二部分，并且暴露出沟道层上的源极和漏极接触区，栅极绝缘层的第二部分位于栅极绝缘层的第一部分两侧，栅极层形成于栅极绝缘层的第一部分上。
其中，在沟道层402上形成一层栅极绝缘层503，可使用化学气相沉积的方法形成栅极绝缘层503，该栅极绝缘层503可以为硅氧化物层，例如：二氧化硅。
进一步地，在栅极绝缘层503上形成一层栅极层504，可使用物理气相沉积法沉积金属，形成栅极层504。
进一步地，通过曝光、显影、蚀刻及剥离制程进而在得到包括图案化的第一部分6031和第二部分6032的栅极绝缘层603以及图案化的栅极层604。
具体地，该光刻处理步骤中利用的光掩膜可以是一种灰度掩膜506，该灰度掩膜也可以叫做半色调掩膜。
进一步地，该灰度掩膜506可由第一灰度透光区5061、第二灰度透光区5062、第三灰度透光区5063构成，第一透光区5061透光率最低，第二透光区5062透光率高于第一透光区5061，第三透光区5063透光率高于第二透光区5062。
进一步地，在栅极层504上涂覆一层正性光致抗蚀剂层505，该正性光致抗蚀剂层505的在蚀刻时溶解速度缓慢，但经光照后，溶解速度会受到根据光照的强度和时间不同而不同的加快，即在受光照时间相同的情况下，光照强度越高，正性光致抗蚀剂层505溶解速度会变得更快。
进一步地，将灰度掩膜506设置在正性光致抗蚀剂层505正上方，并在灰度掩膜506上方向正性光致抗蚀剂层505垂直进行光照，由于第一透光区5061透光率最低，对应正性光致抗蚀剂层505的第一曝光区5051几乎不受到光照所以很难溶解；由于第二透光区5062有一定的透光率，且对应正性光致抗蚀剂层505的第二曝光区5052由于受到一定的光照后溶解速度变快；由于第三透光区5063透光率最高，使对应的正性光致抗蚀剂层505的第三曝光区5053受到最多的光照，溶解速度变得最快。
进一步地，进行蚀刻操作，由于第一曝光区5051很难溶解，所以第三曝光区5053能够保护下方结构不被蚀刻溶解；由于第二曝光区5052溶解速度变快，所以在设定好一定蚀刻条件的情况下，能够实现第二曝光区5052和其下方对应的栅极层5042被蚀刻溶解，而栅极绝缘层503不被蚀刻溶解；由于第三曝光区5053溶解速度最快，所以在设定好一定蚀刻条件的情况下，第三曝光区5053下方的栅极层5043和栅极绝缘层5033受不到保护，能够全部被蚀刻溶解，同时这里选用的蚀刻液不会与沟道层反应。
其中，通过对第一透光区5061、第二透光区5062和第三透光区5063的透光率调节、光照的强度和时间的控制、蚀刻液的选择和配比、蚀刻方式、蚀刻温度和时间的调节等对蚀刻速度有影响的因素的控制，从而达到只将栅极绝缘层5033和栅极层5042、栅极层5043蚀刻掉，而不蚀刻其他区域的栅极层和栅极绝缘层的效果，进而获得如图6所示的图案化的栅极绝缘层603和栅极层604。
进一步地，以图案化的栅极层604作为光罩以自对准的方式对沟道层602的源漏极接触区6022进行离子注入使其导体化，之后进行退火处理。
其中，离子注入的注入的离子可以为氧气、氩气或六氟化硫中的一种，同时第二部分6032作为遮罩，能够使源漏极接触区6022和沟道区6021之间的隔离区6021能够作为隔离不会被离子注入。
其中，对离子注入后的源漏极接触区6022进行退火处理，以恢复因离子注入对源漏极接触区6022造成的结构缺陷。
其中，从图5中能够清楚知道，虽然由于图片空间所限没能一一标注，但是上述的栅极绝缘层5033、栅极层5042、栅极层5043、第二曝光区5052、第三曝光区5053、第二透光区5062、第三透光区5063均为左右相对设置的。
综上所述，由于隔离区6021起到的隔离作用，在对源漏极接触区6022进行离子注入使其导体化后，源漏极接触区6022中的氧空位难以经过隔离区迁移到沟道区6021。
S303：形成源极和漏极，与沟道层的源极和漏极接触区分别对应连接。
其中，在退火处理后的缓冲层401上形成介电层708，介电层708均匀覆盖在缓冲层401、沟道层602、第一部分6031、第二部分6032和栅极层604上方，可采用包括但不限于化学气相沉积的方法形成氧化硅层，该氧化硅层即为介电层708，介电层708能够隔绝外界的氧气或水分子对沟道层602的影响，对沟道层602的稳定性起到保护作用。
进一步地，可通过对介电层708进行光阻涂布、曝光的方法形成图案化的接触孔，然后进行干法刻蚀，去除后即可得到贯穿介电层708且连通源漏极接触区6022的接触孔。
进一步地，可通过物理气相沉积在两个接触孔中沉积金属，形成一金属层，然后在沉积的金属层上沉积光阻层，再进行曝光、显影、刻蚀和剥离制程，以得到图案化的源极7071及漏极7072，且获得的源极7071、漏极7072与源漏极接触区6022接触。
区别于现有技术，本发明通过在对沟道层进行离子注入时，以栅极层作为自对准光罩，利用栅极绝缘层的第二部分作为遮罩，在对沟道层的源漏极接触区进行离子注入使其导体化后，源漏极接触区中的氧空位难以经过隔离区迁移到沟道区，从而解决阵列基板中的沟道层进行离子注入使其导体化处理后，氧空位向沟道区迁移导致而导致阵列基板漏电的问题。
请参阅图8，图8是本发明显示装置一实施例的结构示意图。
其中，显示装置80中的阵列基板是上述本发明的阵列基板或本发明阵列基板的制备方法制备得到的阵列基板。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (16)

  1. 一种阵列基板的制备方法，其中，所述方法包括：
    形成沟道层；
    在所述沟道层上依次形成栅极绝缘层和栅极层，所述栅极绝缘层包括并排连接的第一部分和第二部分，并且暴露出所述沟道层上的源极和漏极接触区，所述栅极绝缘层的第二部分位于所述栅极绝缘层的第一部分两侧，所述栅极层形成于所述栅极绝缘层的第一部分上；
    以所述栅极层作为光罩以自对准的方式对所述沟道层进行离子注入，使所述源极和漏极接触区的所述沟道层导体化，所述离子注入的注入的离子可以为氧气、氩气或六氟化硫中的一种；以及
    形成源极和漏极，与所述沟道层的所述源极和漏极接触区分别对应连接。
  2. 如权利要求1所述的方法，其中，所述使所述源极和漏极接触区的所述沟道层导体化之后，包括：对所述源极和漏极接触区的所述沟道层进行退火处理。
  3. 如权利要求1所述的方法，其中，
    所述形成所述栅极绝缘层及所述栅极层包括：
    在所述沟道层上依次形成第一绝缘层和金属层；
    利用光掩膜对所述栅极绝缘层和所述金属层进行光刻处理，得到所述栅极绝缘层及所述栅极层。
  4. 如权利要求3所述的方法，其中，
    在对所述栅极绝缘层和所述金属层进行光刻处理之前包括：在所述栅极层上涂覆一层正性光致抗蚀剂，形成正性光致抗蚀剂层。
  5. 如权利要求3所述的方法，其中，
    所述光掩膜由并排的第一灰度透光区、第二灰度透光区、第三灰度透光区构成，所述第一透光区透光率最低且位置与所述栅极层相对应，所述第二透光区、所述第三透光区的透光率高于所述第一透光区且位置与所述第二部分相对应。
  6. 如权利要求5所述的方法，其中，
    所述利用光掩膜对所述栅极绝缘层和所述金属层进行光刻处理包括：
    利用所述光掩膜对所述正性光致抗蚀剂层进行曝光，使得所述正性光致抗蚀剂层形成第一曝光区、第二曝光区、第二曝光区，所述第一曝光区对应所述第一灰度透光区，所述第二曝光区对应所述第一灰度透光区，所述第二曝光区对应所述第一灰度透光区；
    对所述正性光致抗蚀剂层进行蚀刻，其中所述第一曝光区蚀刻溶解速度相对最慢，所述第二曝光区、所述第三曝光区蚀刻溶解速度相对最快。
  7. 一种阵列基板，其中，包括：
    沟道层；
    栅极绝缘层，包括并排连接的第一部分和第二部分，设置于所述沟道层上，并且暴露出所述沟道层上的源极和漏极接触区，所述栅极绝缘层的第二部分位于所述栅极绝缘层的第一部分两侧；
    栅极层，设置于所述栅极绝缘层的第一部分；
    源极和漏极，与所述沟道层的所述源极和漏极接触区分别对应连接。
  8. 如权利要求7所述的阵列基板，其中，未被所述栅极层覆盖的所述栅极绝缘层的第二部分在所述沟道层上的垂直投影长度为1-10微米。
  9. 如权利要求7所述的阵列基板，其中，所述栅极绝缘层的第二部分延伸至所述源极和漏极。
  10. 如权利要求9所述的阵列基板，其中，所述栅极绝缘层的第二部分与所述源极和所述漏极互相接触。
  11. 如权利要求7所述的阵列基板，其中，所述栅极绝缘层为硅氧化物层。
  12. 一种显示装置，其中，包括阵列基板，所述种阵列基板，包括：
    沟道层；
    栅极绝缘层，包括并排连接的第一部分和第二部分，设置于所述沟道层上，并且暴露出所述沟道层上的源极和漏极接触区，所述栅极绝缘层的第二部分位于所述栅极绝缘层的第一部分两侧；
    栅极层，设置于所述栅极绝缘层的第一部分；
    源极和漏极，与所述沟道层的所述源极和漏极接触区分别对应连接。
  13. 如权利要求12所述的显示装置，其中，未被所述栅极层覆盖的所述栅极绝缘层的第二部分在所述沟道层上的垂直投影长度为1-10微米。
  14. 如权利要求12所述的显示装置，其中，所述栅极绝缘层的第二部分延伸至所述源极和漏极。
  15. 如权利要求14所述的显示装置，其中，所述栅极绝缘层的第二部分与所述源极和所述漏极互相接触。
  16. 如权利要求12所述的显示装置，其中，所述栅极绝缘层为硅氧化物层。
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