TWI566388B - 顯示面板 - Google Patents

顯示面板 Download PDF

Info

Publication number
TWI566388B
TWI566388B TW103127623A TW103127623A TWI566388B TW I566388 B TWI566388 B TW I566388B TW 103127623 A TW103127623 A TW 103127623A TW 103127623 A TW103127623 A TW 103127623A TW I566388 B TWI566388 B TW I566388B
Authority
TW
Taiwan
Prior art keywords
layer
metal oxide
display panel
thin film
film transistor
Prior art date
Application number
TW103127623A
Other languages
English (en)
Other versions
TW201607001A (zh
Inventor
沈義和
耿介 莊
Original Assignee
群創光電股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 群創光電股份有限公司 filed Critical 群創光電股份有限公司
Priority to TW103127623A priority Critical patent/TWI566388B/zh
Priority to US14/793,792 priority patent/US20160049524A1/en
Publication of TW201607001A publication Critical patent/TW201607001A/zh
Application granted granted Critical
Publication of TWI566388B publication Critical patent/TWI566388B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Description

顯示面板
本發明係關於一種顯示面板,尤指一種改善薄膜電晶體單元作動穩定性之顯示面板。
隨著顯示器技術不斷進步,使用者對於電子產品之要求越來越高,所有的裝置均朝體積小、厚度薄、重量輕等趨勢發展,故目前市面上主流之顯示器裝置已由以往之陰極射線管發展成液晶顯示裝置(LCD)或有機發光二極體裝置(OLED)。
在LCD或OLED中,由於薄膜電晶體單元(TFT)之主動層材料之能隙一般與紫外光(UV)、藍光相近,因此,TFT對於紫外光及藍光十分敏感,在紫外光或藍光照射下(例如在製程中照射紫外光或藍光、或來自外在環境的紫外光或藍光),TFT中會產生額外的電子電洞對(electron hole pair),造成TFT中的載子通道(channel)上包含額外的載子(carrier),進而造成TFT電性偏移,例如閘極電壓(Vth)負偏、漏電流上升等;更使OLED在暗態操作時會有漏光現象、或移位暫存器(Shift Register,S/R)、資料多工器(Data Mux)及其他驅動電路無法正常運作等問題。
有鑑於此,目前亟需發展一種改善上述問題之 顯示面板,提升顯示裝置的顯示品質並延長其使用壽命,期盼帶給消費者更穩定、更高品質的顯示效果。
本發明之主要目的係在提供一種顯示面板,俾能減少顯示裝置中的薄膜電晶體單元受到紫外光或藍光影響,進而有效提升顯示裝置的穩定性及顯示品質。
為達成上述目的,本發明提供一種顯示面板,包括:一基板;一薄膜電晶體單元,係設置於該基板上,且該薄膜電晶體單元包括:一閘極電極及一半導體層,其中該半導體層包含一載子通道區,且該閘極電極係對應該載子通道區設置;一第一金屬氧化層,設置於該半導體層上且覆蓋該載子通道區;以及一包含氧化矽(SiOx)或三氧化二鋁(Al2O3)的隔離層,該隔離層係設置於該半導體層與該第一金屬氧化層之間;其中,波長範圍介於210nm至350nm間的光線通過該第一金屬氧化層的穿透率為50%以下。
據此,本發明利用該第一金屬氧化層吸收短波長光線(例如在製程中照射紫外光或藍光、或來自外在環境的紫外光或藍光),有效減少短波長光線接觸到薄膜電晶體單元的半導體層,進而減少薄膜電晶體單元之電性偏移,並改善顯示裝置在暗態操作時的漏光現象、或移位暫存器、資料多工器及其他驅動電路無法正常運作等問題,因此,本發明之顯示面板可提供更穩定、更高品質的顯示效果。
1‧‧‧基板
21‧‧‧閘極電極
22‧‧‧半導體層
221‧‧‧載子通道區
222‧‧‧側壁
23‧‧‧源極電極
24‧‧‧汲極電極
33‧‧‧第二金屬氧化層
26‧‧‧絕緣層
27‧‧‧緩衝層
31‧‧‧隔離層
311‧‧‧第一接觸孔
32‧‧‧第一金屬氧化層
321‧‧‧第二接觸孔
圖1係本發明一較佳實施例之薄膜電晶體單元示意圖。
圖2係本發明另一較佳實施例之薄膜電晶體單元示意圖。
圖3係本發明再一較佳實施例之薄膜電晶體單元示意圖。
圖4A係本發明一較佳實施例之薄膜電晶體單元之分解圖。
圖4B係本發明一較佳實施例之薄膜電晶體單元之俯視圖。
以下係藉由特定的具體實施例說明本發明之實施方式,熟習此技藝之人士可由本說明書所揭示之內容輕易地了解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實施例加以施行或應用,本說明書中的各項細節亦可針對不同觀點與應用,在不悖離本創作之精神下進行各種修飾與變更。
[實施例1]
請參照圖1,本發明之顯示面板包括:一基板1;一薄膜電晶體單元,係設置於該基板1上,且該薄膜電晶體單元包括:一閘極電極21、一半導體層22及一絕緣層26,其中該半導體層22包含一載子通道區221,且該閘極電極21係對應該載子通道區221設置;一第一金屬氧化層 32,設置於該半導體層22上且覆蓋該載子通道區221;以及一包含氧化矽(SiOx)或三氧化二鋁(Al2O3)的隔離層31,該隔離層31係設置於該半導體層22與該第一金屬氧化層32之間,其中,波長範圍介於210nm至350nm間的光線通過該第一金屬氧化層32的穿透率為50%以下。
於本實施例中,該薄膜電晶體單元更可包含一源極電極23及一汲極電極24,該源極電極23與該汲極電極24係設置於該半導體層22上方,且該源極電極23與該汲極電極24與該半導體層22連接,該第一金屬氧化層32係設置於該半導體層22以及該源極電極23與該汲極電極24之間;然而,該第一金屬氧化層32亦可設置於該源極電極23與該汲極電極24上方並覆蓋該源極電極23與該汲極電極24。此外,於本實施例中,該第一金屬氧化層32設置於該半導體層22上且包覆該半導體層22的一側壁222;然而,該第一金屬氧化層32僅需至少覆蓋該載子通道區221,可視需求選擇性地包覆該半導體層22的一側壁222,若第一金屬氧化層32包覆該半導體層22的該側壁222,則更有助於減少薄膜電晶體單元之電性偏移及改善顯示裝置在暗態操作時的漏光現象。
於本實施例中,圖1所示之薄膜電晶體單元為一下閘極式(bottom gate)薄膜電晶體單元,該源極電極23與該汲極電極24係設置於該半導體層22上方,該半導體層22係設置於該閘極電極21上方,並且為蝕刻阻障層結構(etching stop layer structure,ESL)。薄膜電晶體單元可採用 習知之薄膜電晶體製程製作,故在此不再贅述。薄膜電晶體單元的結構可由本技術領域之人簡單調整,亦可為如圖2所示之一背通道蝕刻結構(back channel etching structure,BCE),或為如圖3所示之一上閘極式(top gate)薄膜電晶體單元。值得一提的是,載子通道區主要是位於半導體層中較為靠近閘極電極的位置,因此在圖1及圖2中的該載子通道區221位置不同於圖3中的該載子通道區221位置。
於本實施例中,該第一金屬氧化層32的成份不受限,可為氧化鈦(TiOx)、氧化鉬(MoOx)、氧化鋅(ZnOx)、氧化銦(InOx)、氧化鎢(WOx)、氧化鎂(MgOx)、氧化鈣(CaOx)、氧化錫(SnOx)、氧化鎵(GaOx)、氧化銦鎵鋅(IGZO)或氧化鋁(AlOx)。該第一金屬氧化層之厚度不受限,可由本技術領域之人依實際需求調整;當第一金屬氧化層之厚度為10nm至100nm時,波長範圍介於210nm至350nm間的光線通過該第一金屬氧化層的穿透率約為50%以下,當第一金屬氧化層之厚度為30nm至100nm時,波長範圍介於210nm至350nm間的光線通過該第一金屬氧化層的穿透率約為30%以下,如此已可有效地阻擋大部份的紫外線,維持薄膜電晶體單元驅動電壓的穩定度。
此外,若該隔離層31包含氧化矽(SiOx)或三氧化二鋁(Al2O3),該隔離層31之厚度、面積不受限,隔離層31之厚度較佳為5nm至20nm,隔離層31之面積較佳係大於或等於該第一金屬氧化層32之面積,如此可有效避免該半導體層22產生氧缺陷進而影響薄膜電晶體單元驅動電壓 的穩定度(當第一氧化層32氧化不完全時,與該半導體層22直接接觸之第一氧化層32會抓取半導體層22內部的氧,使半導體層22產生氧缺陷),但本發明並未受限於此。請參見圖4A、4B,其為圖1之薄膜電晶體單元之分解圖及俯視圖,為了清楚比較隔離層31和第一金屬氧化層32之面積,圖4A、4B省略繪示閘極電極21、源極電極23、汲極電極24、第二金屬氧化層33、及絕緣層26。如圖4A所示,隔離層31設有第一接觸孔311,第一金屬氧化層32設有第二接觸孔321,該第一接觸孔311及該第二接觸孔321即是設置源極電極23與汲極電極24的位置,如圖4B所示,較佳地,隔離層31之面積係大於第一金屬氧化層32之面積。
再者,第二金屬氧化層33可更設置於該源極電極23與該汲極電極24上方並覆蓋該源極電極23與該汲極電極24,更加防止薄膜電晶體單元受到紫外光或藍光影響,進而提升顯示面板之作動穩定性。第二金屬氧化層33的成份不受限,可與第一金屬氧化層32相同或相異,本技術領域中具有通常知識者可視實際需求而選用適當材料。
此外,基板1可使用本技術領域常用之基板,如玻璃基板、塑膠基板、矽基板及陶瓷基板等。再者,閘極電極21、源極電極23及汲極電極24之材料可分別使用本技術領域常用之導電材料,如金屬、合金、金屬氧化物、金屬氮氧化物、或其他本技術領域常用之電極材料;且較佳為金屬材料,但本發明不僅限於此。至於半導體層22,亦可採用本技術領域常用之半導體層材料,例如氧化銦鎵 鋅(IGZO)、氧化銦錫鋅ITZO、其他金屬氧化物半導體、非晶矽、多晶矽、結晶矽等;另外,絕緣層26之材料可為本技術領域常用之如氮化矽(SiNx)、氧化矽(SiOx)或其組合之鈍化層材料。然而,本發明並不僅限於此。
因此,來自外在環境的入射光線中(如箭頭所示),波長範圍於220nm至350nm的光線(例如在製程中照射紫外光或藍光、或來自外在環境的紫外光或藍光)會被第一金屬氧化層32和第二金屬氧化層33吸收,減少該些光線對半導體層22的影響。
圖1之圖式省略了顯示面板中的其他元件,可舉例如一液晶顯示面板(LCD)或一有機發光二極體顯示面板(OLED)。例如,作為液晶顯示面板時,除了上述之基板1、有機薄膜電晶體單元2、第一金屬氧化層32及隔離層31以外,更包含液晶單元、彩色濾光片單元、及背光模組等;或者,作為有機發光二極體顯示面板時,除了上述之基板1、有機薄膜電晶體單元2、第一金屬氧化層32及隔離層31以外,更包含有機發光二極體和封裝單元等。此外,本技術領域中具有通常知識者可輕易了解其他省略的元件,習知常用的元件皆可應用於本發明。
[實施例2]
請參照圖2,本發明另一較佳實施例之顯示面板包括:一基板1;一薄膜電晶體單元,係設置於該基板1上,且該薄膜電晶體單元包括:一閘極電極21、一半導體 層22、一源極電極23、一汲極電極24及一絕緣層26,其中該半導體層22包含一載子通道區221,該載子通道區221係介於該源極電極23與該汲極電極24之間,且該閘極電極21係對應該載子通道區221設置;一第一金屬氧化層32,設置於該半導體層22上並包覆該半導體層22的一側壁222,且覆蓋該源極電極23與該汲極電極24;以及一包含氧化矽(SiOx)或三氧化二鋁(Al2O3)的隔離層31,該隔離層31係設置於該半導體層22與該第一金屬氧化層32之間,其中,波長範圍介於210nm至350nm間的光線通過該第一金屬氧化層32的穿透率為50%以下。
此外,該第一金屬氧化層32亦可設置於該半導體層22以及該源極電極23與該汲極電極24之間,且僅需至少覆蓋該載子通道區221,可視需求選擇性地包覆該半導體層22的一側壁222。
在本實施例中,除了上述結構之外,其餘皆與實施例1相同,於實施例1中所述之各層成分、厚度、面積、特性等皆可應用於此。
因此,來自外在環境的入射光線中(如箭頭所示),波長範圍於220nm至350nm的光線(例如在製程中照射紫外光或藍光、或來自外在環境的紫外光或藍光)會被第一金屬氧化層32吸收,減少該些光線對半導體層22的影響。
[實施例3]
請參照圖3,本發明再一較佳實施例之顯示面 板包括:一基板1;一薄膜電晶體單元,係設置於該基板1上,且該薄膜電晶體單元包括:一閘極電極21、一半導體層22、一絕緣層26及一緩衝層27,其中該半導體層22包含一載子通道區221,且該閘極電極21係設置於該半導體層22上方且對應該載子通道區221設置;一第一金屬氧化層32,設置於該半導體層22上且至少覆蓋該載子通道區221;以及一包含氧化矽(SiOx)或三氧化二鋁(Al2O3)的隔離層31,該隔離層31係設置於該半導體層22與該第一金屬氧化層32之間,其中,波長範圍介於210nm至350nm間的光線通過該第一金屬氧化層32的穿透率為50%以下。
此外,該薄膜電晶體單元更包含一源極電極23及一汲極電極24,且該源極電極23及該汲極電極24設置於該半導體層22的上方,該第一金屬氧化層32位於該源極電極23及該汲極電極24之間,並且可於該第一金屬氧化層32及該源極電極23與該汲極電極24的上方設置一第二金屬氧化層33,該第二金屬氧化層33覆蓋該源極電極23與該汲極電極24,且可視需求選擇性地包覆該半導體層22的一側壁,如此可具有較佳的遮蔽紫外光效果。
在本實施例中,除了上述結構之外,其餘皆與實施例1相同,於實施例1中所述之各層成分、厚度、面積、特性等皆可應用於此。
因此,來自外在環境的入射光線中(如箭頭所示),波長範圍於220nm至350nm的光線(例如在製程中照射紫外光或藍光、或來自外在環境的紫外光或藍光)會被第 一金屬氧化層32及第二金屬氧化層33吸收,減少該些光線對半導體層22的影響。
上述實施例僅係為了方便說明而舉例而已,本發明所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。
1‧‧‧基板
21‧‧‧閘極電極
22‧‧‧半導體層
221‧‧‧載子通道區
222‧‧‧側壁
23‧‧‧源極電極
24‧‧‧汲極電極
33‧‧‧第二金屬氧化層
26‧‧‧絕緣層
31‧‧‧隔離層
32‧‧‧第一金屬氧化層

Claims (9)

  1. 一種顯示面板,包括:一基板;一薄膜電晶體單元,係設置於該基板上,且該薄膜電晶體單元包括一閘極電極及一半導體層,其中該半導體層包含一載子通道區,且該閘極電極係對應該載子通道區設置;一第一金屬氧化層,設置於該半導體層上且覆蓋該載子通道區;以及一包含氧化矽(SiOx)或三氧化二鋁(Al2O3)的隔離層,該隔離層係設置於該半導體層與該第一金屬氧化層之間;其中,波長範圍介於210nm至350nm間的光線通過該第一金屬氧化層的穿透率為50%以下;且該隔離層之面積係大於或等於該第一金屬氧化層之面積。
  2. 如申請專利範圍第1項所述之顯示面板,其中,該第一金屬氧化層的成份係為氧化鈦(TiOx)、氧化鉬(MoOx)、氧化鋅(ZnOx)、氧化銦(InOx)、氧化鎢(WOx)、氧化鎂(MgOx)、氧化鈣(CaOx)、氧化錫(SnOx)、氧化鎵(GaOx)、氧化銦鎵鋅(IGZO)或氧化鋁(AlOx)。
  3. 如申請專利範圍第1項所述之顯示面板,其中,該第一金屬氧化層之厚度為30nm至100nm。
  4. 如申請專利範圍第1項所述之顯示面板,其中,該隔離層之厚度為5nm至20nm。
  5. 如申請專利範圍第1項所述之顯示面板,其中,該薄膜電晶體單元係一上閘極式(top gate)薄膜電晶體單元或一下閘極式(bottom gate)薄膜電晶體單元。
  6. 如申請專利範圍第1項所述之顯示面板,其中,該薄膜電晶體單元更包括一源極電極與一汲極電極,該源極電極與該汲極電極係設置於該半導體層上方,該第一金屬氧化層係設置於該半導體層以及該源極電極與該汲極電極之間。
  7. 如申請專利範圍第6項所述之顯示面板,其中更包含一第二金屬氧化層,該第二金屬氧化層係設置於該源極電極與該汲極電極上方並覆蓋該源極電極與該汲極電極。
  8. 如申請專利範圍第1項所述之顯示面板,其中,該薄膜電晶體單元更包括一源極電極與一汲極電極,該第一金屬氧化層係設置於該源極電極與該汲極電極上方並覆蓋該源極電極與該汲極電極。
  9. 如申請專利範圍第1項所述之顯示面板,其中,該第一金屬氧化層包覆該半導體層的一側壁。
TW103127623A 2014-08-12 2014-08-12 顯示面板 TWI566388B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW103127623A TWI566388B (zh) 2014-08-12 2014-08-12 顯示面板
US14/793,792 US20160049524A1 (en) 2014-08-12 2015-07-08 Display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103127623A TWI566388B (zh) 2014-08-12 2014-08-12 顯示面板

Publications (2)

Publication Number Publication Date
TW201607001A TW201607001A (zh) 2016-02-16
TWI566388B true TWI566388B (zh) 2017-01-11

Family

ID=55302770

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103127623A TWI566388B (zh) 2014-08-12 2014-08-12 顯示面板

Country Status (2)

Country Link
US (1) US20160049524A1 (zh)
TW (1) TWI566388B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934330A (zh) * 2015-05-08 2015-09-23 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示面板
CN106898624B (zh) * 2017-04-28 2019-08-02 深圳市华星光电技术有限公司 一种阵列基板及制备方法、显示装置
US10411047B2 (en) 2017-04-28 2019-09-10 Shenzhen China Star Optoelectronics Technology Co., Ltd Array substrate, manufacturing method thereof and display device
US11935966B2 (en) * 2021-04-28 2024-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor device having ultraviolet attenuating capability

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201246389A (en) * 2009-12-04 2012-11-16 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
TW201246398A (en) * 2011-03-21 2012-11-16 Qualcomm Mems Technologies Inc Amorphous oxide semiconductor thin film transistor fabrication method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI241425B (en) * 2000-05-12 2005-10-11 Ind Tech Res Inst Structure of multi-domain wide-viewing angle liquid crystal display
JP2010050165A (ja) * 2008-08-19 2010-03-04 Sumitomo Chemical Co Ltd 半導体装置、半導体装置の製造方法、トランジスタ基板、発光装置、および、表示装置
KR101819197B1 (ko) * 2010-02-05 2018-02-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 및 반도체 장치의 제조 방법
KR102108572B1 (ko) * 2011-09-26 2020-05-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
US9123691B2 (en) * 2012-01-19 2015-09-01 E Ink Holdings Inc. Thin-film transistor and method for manufacturing the same
KR102054850B1 (ko) * 2013-05-30 2019-12-12 삼성디스플레이 주식회사 유기 발광 표시 장치 및 이의 제조 방법
TWI500179B (zh) * 2013-06-05 2015-09-11 Univ Nat Chiao Tung 具紫外光吸收層之薄膜電晶體

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201246389A (en) * 2009-12-04 2012-11-16 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
TW201246398A (en) * 2011-03-21 2012-11-16 Qualcomm Mems Technologies Inc Amorphous oxide semiconductor thin film transistor fabrication method

Also Published As

Publication number Publication date
TW201607001A (zh) 2016-02-16
US20160049524A1 (en) 2016-02-18

Similar Documents

Publication Publication Date Title
JP6567150B2 (ja) 半導体装置
US10403757B2 (en) Top-gate self-aligned metal oxide semiconductor TFT and method of making the same
JP6692645B2 (ja) 半導体装置
US7804088B2 (en) Semiconductor device, manufacturing method of semiconductor device, display device, and manufacturing method of display device
JP2022141642A (ja) 半導体装置
TWI584383B (zh) 半導體裝置及其製造方法
TWI471945B (zh) 包括電晶體的顯示裝置和其製造方法
JP2010171404A5 (zh)
WO2017054271A1 (zh) 低温多晶硅tft基板
KR101524726B1 (ko) Led 디스플레이 장치
JP6684769B2 (ja) アクティブマトリクス基板、液晶表示装置、有機el表示装置およびアクティブマトリクス基板の製造方法
TW201501314A (zh) 半導體裝置
KR102454087B1 (ko) 박막 트랜지스터 기판
TWI559510B (zh) 顯示裝置
JP2018170325A (ja) 表示装置
WO2016006530A1 (ja) 半導体装置およびその製造方法、ならびに液晶表示装置
TWI566388B (zh) 顯示面板
JPWO2015186602A1 (ja) 半導体装置およびその製造方法
KR20160009220A (ko) 산화물 반도체 박막 트랜지스터 및 이를 구비한 표시장치용 어레이 기판
JP6142136B2 (ja) トランジスタの製造方法、表示装置の製造方法および電子機器の製造方法
US10050092B2 (en) Array substrate, manufacturing method thereof and display device
KR101073543B1 (ko) 유기 발광 표시 장치
JP2015122417A (ja) 半導体装置およびその製造方法、並びに表示装置および電子機器
JP2014135378A (ja) 半導体装置及び表示装置
JP6727414B2 (ja) 薄膜トランジスタ基板及びその製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees