JP6727414B2 - 薄膜トランジスタ基板及びその製造方法 - Google Patents
薄膜トランジスタ基板及びその製造方法 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims description 56
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000010408 film Substances 0.000 claims description 161
- 238000010521 absorption reaction Methods 0.000 claims description 118
- 239000004065 semiconductor Substances 0.000 claims description 35
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- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 14
- 239000001257 hydrogen Substances 0.000 claims description 14
- 229910052739 hydrogen Inorganic materials 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 207
- 239000004973 liquid crystal related substance Substances 0.000 description 23
- 230000005684 electric field Effects 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
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- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
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- 244000126211 Hericium coralloides Species 0.000 description 1
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Description
本発明の実施の形態1に係る薄膜トランジスタひいては薄膜トランジスタ基板の構成について説明する。なお、以下では、バックチャネルエッチング構造と呼ばれる一般的なTFT構造に適用する場合を一例として説明する。
次に、本実施の形態1に係るアレイ基板の製造方法について説明する。図8は、本実施の形態1に係るアレイ基板の製造方法の一例を示すフローチャートである。なお、本文中で記載したレジスト塗布及びパターニングを、図8中では写真製版と記載した。また本文中で記載したレジスト除去を、図8中ではレジスト剥離及び純水洗浄と記載した。
以上のような本実施の形態1に係るアレイ基板は、基板11と、基板11上に配設されたゲート電極3と、基板11上にゲート電極3と離間して配設された、酸化物半導体を含む吸収層1と、ゲート電極3及び吸収層1上に配設されたゲート絶縁膜2とを備える。そして、当該アレイ基板は、ゲート絶縁膜2上に配設され、ゲート電極3と平面視で重ねられた、酸化物半導体を含む活性層5と、活性層5にそれぞれ接続されたソース電極4及びドレイン電極6と、活性層5、ソース電極4及びドレイン電極6上に配設された保護絶縁膜8と、ゲート絶縁膜2及び保護絶縁膜8を含む絶縁膜上で、かつ吸収層1上方に配設され、ドレイン電極6に接続された画素電極7とを備える。
図9は、本発明の実施の形態2に係るアレイ基板の構成の一例を示す断面図である。以下、本実施の形態2で説明する構成要素のうち、上述の構成要素と同じまたは類似する構成要素については同じ参照符号を付し、異なる構成要素について主に説明する。
以上のような本実施の形態1に係るアレイ基板では、画素電極7下の絶縁膜は、保護絶縁膜8を含まずにゲート絶縁膜2を含む。このような構成によれば、吸収層1と画素電極7との間の距離について平面内のばらつきを低減できる。したがって、活性層5への高い遮光効果を得ながら、平面内でばらつきの少ない良好な表示性能を得ることができる。
図10は、本発明の実施の形態3に係るアレイ基板の構成の一例を示す断面図である。以下、本実施の形態3で説明する構成要素のうち、上述の構成要素と同じまたは類似する構成要素については同じ参照符号を付し、異なる構成要素について主に説明する。
吸収層1は、絶縁膜下で、かつ吸収層1下方に配設されているため、吸収層1に電圧を印加することによって画素電極7の電荷保持性能を向上できる。すなわち、吸収層1を画素電極7の電荷保持用電極として利用できる。
Claims (12)
- 基板<11>と、
前記基板上に配設されたゲート電極<3>と、
前記基板上に前記ゲート電極と離間して配設された、酸化物半導体を含む吸収層<1>と、
前記ゲート電極及び前記吸収層上に配設されたゲート絶縁膜<2>と、
前記ゲート絶縁膜上に配設され、前記ゲート電極と平面視で重ねられた、酸化物半導体を含む活性層<5>と、
前記活性層にそれぞれ接続されたソース電極<4>及びドレイン電極<6>と、
前記活性層、前記ソース電極及び前記ドレイン電極上に配設された保護絶縁膜<8>と、
前記ゲート絶縁膜または前記ゲート絶縁膜及び前記保護絶縁膜を含む絶縁膜上で、かつ前記吸収層上方に配設され、前記ドレイン電極に接続された画素電極<7>と
を備える、薄膜トランジスタ基板。 - 請求項1に記載の薄膜トランジスタ基板であって、
前記絶縁膜は、前記保護絶縁膜<8>を含まずに前記ゲート絶縁膜<2>を含む、薄膜トランジスタ基板。 - 請求項1または請求項2に記載の薄膜トランジスタ基板であって、
前記画素電極<7>は、櫛歯状またはスリット状の形状を有する、薄膜トランジスタ基板。 - 請求項1から請求項3のうちのいずれか1項に記載の薄膜トランジスタ基板であって、
前記吸収層<1>は、前記活性層<5>と同じ金属元素を含む、薄膜トランジスタ基板。 - 請求項4に記載の薄膜トランジスタ基板であって、
前記吸収層<1>の前記金属元素の金属における組成比は、前記活性層<5>の前記金属元素の金属における組成比と同じであり、
前記吸収層における水素の含有量は、前記活性層における水素の含有量よりも多い、薄膜トランジスタ基板。 - 請求項5に記載の薄膜トランジスタ基板であって、
前記吸収層<1>における酸素の含有量は、前記活性層<5>における酸素の含有量よりも多い、薄膜トランジスタ基板。 - 請求項4から請求項6のうちのいずれか1項に記載の薄膜トランジスタ基板であって、
平面視にて前記吸収層<1>に、1以上の穴<1a>が設けられている、薄膜トランジスタ基板。 - 基板上にゲート電極を形成する工程と、
前記基板上に前記ゲート電極と離間して配設された、酸化物半導体を含む吸収層を形成する工程と、
前記ゲート電極及び前記吸収層上に配設されたゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上に配設され、前記ゲート電極と平面視で重ねられた、酸化物半導体を含む活性層を形成する工程と、
前記活性層にそれぞれ接続されたソース電極及びドレイン電極を形成する工程と、
前記活性層、前記ソース電極及び前記ドレイン電極上に配設された保護絶縁膜を形成する工程と、
前記ゲート絶縁膜または前記ゲート絶縁膜及び前記保護絶縁膜を含む絶縁膜上で、かつ前記吸収層上方に配設され、前記ドレイン電極に接続された画素電極を形成する工程と
を備える、薄膜トランジスタ基板の製造方法。 - 請求項8に記載の薄膜トランジスタ基板の製造方法であって、
前記画素電極は、櫛歯状またはスリット状の形状を有する、薄膜トランジスタ基板の製造方法。 - 請求項8または請求項9に記載の薄膜トランジスタ基板の製造方法であって、
前記吸収層は、前記活性層の形成に用いるターゲットと金属元素の組成比が同じターゲットを用いて、スパッタリング法によって形成される、薄膜トランジスタ基板の製造方法。 - 請求項10に記載の薄膜トランジスタ基板の製造方法であって、
前記吸収層は、前記活性層の形成時の水分分圧よりも高い水分分圧の状態下で形成される、薄膜トランジスタ基板の製造方法。 - 請求項11に記載の薄膜トランジスタ基板の製造方法であって、
前記吸収層は、前記活性層の形成時の酸素分圧よりも高い酸素分圧の状態下で形成される、薄膜トランジスタ基板の製造方法。
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