WO2018173263A1 - Carte de circuit imprimé - Google Patents

Carte de circuit imprimé Download PDF

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Publication number
WO2018173263A1
WO2018173263A1 PCT/JP2017/012056 JP2017012056W WO2018173263A1 WO 2018173263 A1 WO2018173263 A1 WO 2018173263A1 JP 2017012056 W JP2017012056 W JP 2017012056W WO 2018173263 A1 WO2018173263 A1 WO 2018173263A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
ground
signal
frame ground
frame
Prior art date
Application number
PCT/JP2017/012056
Other languages
English (en)
Japanese (ja)
Inventor
義章 入船
雄大 米岡
祐司 浅野
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to CN201780048945.2A priority Critical patent/CN109565927A/zh
Priority to PCT/JP2017/012056 priority patent/WO2018173263A1/fr
Priority to KR1020197003463A priority patent/KR101999509B1/ko
Priority to JP2018508254A priority patent/JP6391885B1/ja
Publication of WO2018173263A1 publication Critical patent/WO2018173263A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/71—Coupling devices for rigid printing circuits or like structures
    • H01R12/72—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures
    • H01R12/721—Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures cooperating directly with the edge of the rigid printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/066—Heatsink mounted on the surface of the PCB

Definitions

  • the present invention relates to a circuit board, and more particularly to noise countermeasures for the circuit board.
  • an auxiliary board is provided in the immediate vicinity of the connector and a capacitor is disposed on the auxiliary board in order to suppress potential fluctuations between the signal ground and the frame ground at the periphery of the connector.
  • the signal ground at a location away from the connector causes a considerable potential fluctuation with the frame ground, thereby causing malfunction of the device.
  • the location where high-frequency coupling between the frame ground and the signal ground is required may differ depending on the circuit board pattern layout, device arrangement state, wiring routing, and the like. For this reason, the frame ground is not limited to the connector position, but a countermeasure corresponding to the situation is required.
  • the present invention has been made in view of the above, and an object of the present invention is to provide a circuit board capable of ensuring a noise tolerance capable of satisfying a target noise tolerance.
  • a circuit board includes a first insulating region between a first frame ground on which an external interface connector is mounted and a first frame ground.
  • a first functional element disposed across the first insulating region between the first signal ground and the first frame ground and the first signal ground, the first functional element being connected to each other at high frequency
  • a second circuit board that includes a second functional element that is disposed across the second insulating region between the first signal ground and the second signal ground and that connects both of them at high frequency.
  • the first signal ground and the second signal ground are electrically connected.
  • the first frame ground and the second frame ground are electrically connected.
  • the circuit board according to the present invention can ensure a high noise immunity that can satisfy the target noise immunity.
  • FIG. 3 is a top view schematically showing the circuit board according to the first embodiment.
  • FIG. 2 schematically shows a circuit board according to the first embodiment, and is a cross-sectional view taken along the line II-II in FIG. The top view which abbreviate
  • FIG. 4 is a diagram schematically showing a main part of the circuit board according to the first embodiment with the substrate omitted, taken along the line IV-IV in FIG.
  • FIG. 3 is a top view schematically showing the first circuit board according to the first embodiment.
  • FIG. 5 is a diagram schematically showing a second circuit board according to the first embodiment, and is a plan view seen from the side indicated by VI in FIG. 4.
  • FIG. 5 is a diagram schematically showing a second circuit board according to the first embodiment, and is a plan view seen from the side indicated by VII in FIG. 4. Sectional drawing which shows the principal part which shows an example which concerns on the ground connection member concerning Embodiment 1
  • FIG. 10 is a diagram schematically showing a circuit board according to a second embodiment, and is a cross-sectional view taken along the line XX of FIG.
  • FIG. 11 is a diagram schematically showing a second circuit board according to the second embodiment, and is a diagram showing a surface on the XI side in FIG. 10.
  • FIG. 10 is a diagram schematically showing a circuit board according to a second embodiment, and is a cross-sectional view taken along the line XX of FIG.
  • FIG. 11 is a diagram schematically showing a second circuit board according to the second embodiment, and is a diagram showing a surface on the XI side in FIG. 10.
  • FIG. 11 is a diagram schematically illustrating a second circuit board according to the second embodiment, and is a diagram illustrating a surface on the XII side in FIG. 10.
  • Sectional drawing which shows the circuit board based on Embodiment 3 typically.
  • FIG. 14 schematically shows a second circuit board according to the third embodiment, and shows a surface on the XIV side in FIG. 13.
  • FIG. 14 schematically shows a second circuit board according to the third embodiment, and shows a surface on the XV side in FIG. 13.
  • the top view which shows typically the 1st circuit board based on Embodiment 3
  • Sectional drawing which shows the circuit board based on Embodiment 4 typically.
  • Sectional drawing which shows the circuit board based on Embodiment 5 typically.
  • Sectional drawing which shows the circuit board based on Embodiment 6 typically. Sectional drawing which shows typically the circuit board which concerns on Embodiment 7.
  • FIG. Top view of a circuit board according to the seventh embodiment Sectional drawing which shows the modification of Embodiment 7
  • FIG. 1 is a top view schematically showing a circuit board according to the first embodiment
  • FIG. 2 is a cross-sectional view taken along II-II in FIG. 1
  • FIG. 3 is an insulating substrate for explaining the circuit board according to the first embodiment
  • FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. 3, schematically showing a circuit board showing only main parts excluding the material.
  • the circuit board 100 according to the first embodiment is characterized in that the second circuit board 20 to which the frame grounds are connected is arranged opposite to the first circuit board 10 as the main board.
  • the first circuit board 10 is formed of a multilayer wiring board having a two-layer structure including a first layer base material 11a constituting a surface layer portion and a second layer base material 11b constituting a lower layer portion.
  • the first wiring of the outermost layer is disposed over two sides at the peripheral edge portion of the first circuit board 10. It has a first frame ground 12FG, a first signal ground 12SG, and a main circuit unit 12M.
  • the main circuit portion 12M is configured by an intermediate layer wiring, and neither a through hole nor a pad is shown in FIG. Are connected. The pad connected to this component may be patterned on a part of the first signal ground 12SG.
  • the frame ground is a ground that is connected to the stable ground in a direct current (DC) direction.
  • the stable ground refers to the ground of the building, the housing ground of the control panel, and the like.
  • the signal ground is isolated from the frame ground in terms of DC, and is a ground serving as a reference for the communication signal of the circuit board.
  • the second circuit board 20 is configured by forming a second wiring portion 22 on a base material 21 made of a dielectric such as glass epoxy.
  • the first signal ground is formed on the lower surface of the base 21 adjacent to the first circuit board 10, but the high frequency coupling with the components mounted on the first circuit board 10 is eased.
  • a signal ground may be formed on the upper surface of the base material 21 straddling the base material 21.
  • a signal ground may be formed in the inner layer. If the opposing layer is a signal ground, the influence of external noise on the first circuit board 10 can be reduced as compared with the case of a frame ground.
  • the first layer base material 11a and the second layer base material 11b are not shown, and only main wiring portions are shown. Further, with respect to the base material 21, in the drawings after FIG. 3, illustration is omitted except for a part, and only main wiring portions are shown.
  • the external interface connector 40 is connected to the first frame ground 12FG, which is the frame ground on the first circuit board 10, with a conductive connection portion such as a pad. Connected by pressure or solder.
  • the second circuit board 20 is disposed so as to face the first circuit board 10 and can accommodate an external interface connector 40 mounted on the first circuit board 10.
  • 24. 6 is a plan view seen from the side indicated by VI in FIG. 4
  • FIG. 7 is a plan view seen from the side indicated by VII in FIG. 4 corresponds to the IV-IV cross section of FIG.
  • a first slit 12S for DC insulation is provided between the first signal ground 12SG, which is the signal ground in the first circuit board 10, and the first frame ground 12FG.
  • the connection member 13 is disposed so as to straddle the first slit 12S in order to connect the first frame ground 12FG and the first signal ground 12SG at a high frequency.
  • a capacitive element such as a chip capacitor is generally arranged, and a capacitor having a high frequency characteristic corresponding to noise assumed by selecting the capacitance is selected.
  • the potential variation between the signal line and the signal ground due to the high frequency noise can be suppressed by selecting the capacitor having the high frequency characteristic that has a low impedance at a specific frequency corresponding to the noise. Can do.
  • a control IC (Integrated Circuit) 15 and a communication signal line 17 are arranged on the first signal ground 12 SG on the first circuit board 10.
  • the control IC 15 and the noise countermeasure component 16 are connected to the communication signal line 17 and are arranged for the purpose of suppressing the propagation of high frequency noise and reducing the influence on the IC side.
  • Specific examples include a high-frequency transformer, a common mode choke, a line-to-line capacitor, and a ground-to-ground capacitor.
  • the noise countermeasure component 16 is disposed between the external interface connector 40 and the IC 15, but the noise countermeasure component 16 may be built in the external interface connector 40 or the IC 15, and has a margin for noise resistance.
  • first frame ground 12FG Below the external interface connector 40 is a first frame ground 12FG, and the entire surface is a first signal ground 12SG via a first slit 12S.
  • the placement location, wiring type, and routing of the control IC 15 and the noise countermeasure component 16 are not limited thereto.
  • the main circuit portion 12M is formed in the wiring layer 12 on the inner layer of the first circuit board 10, but the first signal ground 12SG is notched at the portion of the wiring layer 12, and the wiring pattern of the main circuit portion is changed.
  • the first signal ground 12SG and the first frame ground 12FG may be formed in the same layer.
  • the second circuit board 20 is also provided with a second frame ground 22FG and a second signal ground 22SG corresponding to the signal ground.
  • a second slit 22S is provided between the second frame ground 22FG and the second signal ground 22SG.
  • the second frame ground 22FG is disposed on the outer periphery of the second circuit board 20, and the second signal ground 22SG is disposed in the center.
  • a second signal ground 22SG is disposed on the upper surfaces of the control IC 15 and the noise countermeasure component 16 that constitute the main circuit disposed on the opposing first circuit board 10.
  • the frame ground is formed on both sides.
  • the second frame ground 22FG is preferably arranged on one side surface on the side indicated by VI in FIG. 4, and the side surface indicated by VII is preferably a signal ground and an insulating region.
  • the frame ground may be arranged on the VII side.
  • connection member 23 that connects the second frame ground 22FG and the second signal ground 22SG at a high frequency is disposed so as to straddle the second slit 22S.
  • a capacitive element such as a chip capacitor is generally arranged, and a capacitor having a high frequency characteristic corresponding to assumed noise is selected.
  • the second frame ground 22FG has an opening 24 in which the external interface connector 40 disposed on the first circuit board 10 can be accommodated.
  • the shape of the opening is not limited to this.
  • a ground connection member 14G for contacting the side surface of the external interface connector 40 by pressure contact is disposed.
  • the connection between the ground connection member 14G and the second frame ground 22FG only needs to ensure conductivity by solder connection or by pressing with a conductive adhesive or metal structure. Since the ground connection member 14G is a member for electrically connecting to the external interface connector 40, any member that can be electrically connected may be used, such as a gasket, a pressure contact spring, and a metal support by screwing.
  • an external ground connection member 50 for connection to a stable ground is disposed on the second frame ground 22FG.
  • the external ground connection member 50 may be disposed on the first frame ground 12FG.
  • the first circuit board 10 and the second circuit board 10 are not limited to the height of the external interface connector 40 or the like when the second circuit board 20 is disposed on the first circuit board 10 so as to face each other.
  • the board-to-board distance with the circuit board 20 can be adjusted.
  • the second circuit board 20 can be disposed without extending the width direction of the circuit board 100, that is, the length in the direction perpendicular to the circuit board surface.
  • the first circuit board 10 and the second circuit board 20 face each other, and the first signal ground 12 SG and the second signal ground 22 SG are electrically connected via the conductive connection member 14. Connected to.
  • the first frame ground 12FG and the second frame ground 22FG are electrically connected via the ground connection member 14G.
  • the ground connection member 14G is arranged at multiple points, that is, at a plurality of points.
  • the connection member 13 for high-frequency connection between the first frame ground 12FG and the first signal ground 12SG includes a capacitive element such as a chip capacitor, an inductance element, or a capacitive element and an inductance element. Elements capable of high-frequency connection such as combination parts can be used. Regarding the connection member 23 for high-frequency connection between the second frame ground 22FG and the second signal ground 22SG, in addition to a capacitive element such as a capacitor, an inductance element or a combination part of a capacitive element and an inductance element, etc. An element capable of high-frequency connection can be used.
  • connection member 13 formed on the first circuit board 10 is arranged at one place, but a plurality of connection members may be arranged adjacent to each other at the same place. .
  • capacitors having different capacities adjacent to each other it becomes possible to suppress potential fluctuation in a wide band.
  • the arrangement location is not limited to the configuration shown in the first embodiment.
  • connection member 23 formed on the second circuit board 20 is similarly arranged in a single place, but a plurality of connection members may be arranged adjacent to each other in the same place. By arranging adjacent capacitors having different capacities on the second circuit board 20 side as well, it is possible to suppress potential fluctuations in a wide band. Further, the arrangement location is not limited to the configuration shown in the first embodiment.
  • ground connection member 14G is arranged at multiple points, the arrangement location and the number of the ground connection members 14G are not limited to those illustrated, and can be changed as appropriate.
  • FIG. FIG. 8 is a cross-sectional view of the main part of the ground connection member 14G and its periphery, and a first signal wiring connector 18 which is a conductive connection part on the first frame ground 12FG by the spring-shaped ground connection member 14G. It is configured to touch and press.
  • the gap between the first circuit board 10 and the second circuit board 20 can be maintained.
  • a gap between the circuit boards may be secured by an insulating spacer 19 between the first circuit board 10 and the second circuit board 20. If a holding structure using a spring-shaped conductive member is used, man-hours such as screwing can be reduced.
  • the base material is abbreviate
  • the connecting member 23 may be formed on the second signal ground 22SG and the second frame ground 22FG made of a wiring layer formed on the base material.
  • An immunity test is performed by simulating the electromagnetic interference that a device is expected to receive, exposing the device under test to the electromagnetic interference, and observing its behavior in order to evaluate the resistance of the device to electromagnetic interference. It is.
  • the main immunity tests standardized by IEC International Electrotechnical Commission) are as follows: 1) Electrostatic discharge Simulates the electrostatic discharge that occurs directly from the human body or other charged objects to the device or around the device. Basically, all points where human hands may approach when using the device are subject to evaluation, contact discharge tests are conducted for conductive parts, and non-conductive parts are taken care of. Medium discharge test applies. The influence of electrostatic discharge generated around the device is evaluated by discharge to a ground plane or a vertical coupling plate around the device.
  • Radio frequency electromagnetic field Simulate interference from a radio transmitter. The test was swept over a predetermined frequency range, typically 80 MHz to 1000 MHz, but in a range where testing up to higher frequencies is required as usage of frequencies above 1 GHz is increased. By radiating an amplitude-modulated high frequency electromagnetic field.
  • Electrical fast transient Simulates pulsed high-frequency interference on the power line or signal line due to inductive load switching or relay chattering. The power supply or other cable to the device is subject to evaluation. The jamming signal is injected using a coupling and decoupling network if applicable, or using a capacitive coupling clamp. 4) Surge Simulates high-energy interference at relatively low frequencies on power lines or long-distance signal lines due to lightning or power switching.
  • the power supply to the device and other cables are subject to evaluation. Surge is injected using a coupling and decoupling network.
  • Conductive radio frequency interference Simulate interference from radio transmitters on power supply or other cables. Although primarily intended for the assessment of interference from radio signals, the test combines an amplitude-modulated radio frequency signal that is swept in a predetermined frequency range, typically between 0.15 MHz and 80 MHz, or a decoupling network or This is done by injecting the cable using a coupling clamp or the like.
  • Power frequency magnetic field Simulate a magnetic field of 50 to 60 MHz from a large transformer or power cable around. Devices that can be determined to be less susceptible to magnetic fields may be excluded from testing.
  • the test is carried out by placing the device inside an induction coil that is energized with low frequency alternating current. 7) Voltage dip and instantaneous power failure Simulate the effects of a temporary drop in power supply voltage or a power failure.
  • the test is performed by reducing the power supplied to the device at a constant rate for a fixed time. Normally, the device continues to operate for a short time voltage dip, but for a long time voltage dip, the device is required to resume normal operation after the power supply voltage returns to the normal range.
  • the second circuit board As the second circuit board, the second signal ground and the second frame of the second circuit board according to the layout of the first circuit board constituting the main circuit. Since the layout of the ground can be freely performed, the signal ground or the frame ground can be arranged at any position including the center of the substrate. Therefore, it is possible to obtain a circuit board that can cope with any type of high-frequency noise and has a high noise tolerance that is determined to be normal in the desired item of the immunity test.
  • the potential fluctuation in the circuit board can be grasped to some extent beforehand by analysis or the like, but fine adjustment on the actual board may be necessary. However, even if a fine adjustment such as addition of a capacitor is made, if a new board is created, not only will the high frequency characteristics of the circuit board be affected, but schedule delays and man-hours will increase.
  • the second circuit board having the layout of the second signal ground and the second frame ground according to the circuit characteristics of the first circuit board 10 and the installation environment of the circuit board. By using 20, noise tolerance can be ensured with good workability.
  • the frame ground and the signal ground made of another circuit board are not provided. It is necessary to arrange a frame ground on the outer periphery of the first circuit board and form a signal ground region through the insulating region.
  • the flexibility of the layout of the main circuit is large, and the signal line Optimum wiring and other noise countermeasures can be taken, and noise resistance performance can be further improved.
  • the first signal ground 12SG of the first circuit board is formed so as to protrude larger than the second signal ground 22SG of the second circuit board.
  • the first signal ground 12SG is not limited to this shape.
  • the second signal ground 22SG can be appropriately changed over the entire position where the signal ground 12SG faces.
  • there is also a technique in which the frame ground and the signal ground are used as a single ground that is, a technique in which the frame ground is used as a signal reference ground.
  • the allowable DC voltage of the IC is limited, reliability is required. In a circuit board to be manufactured, it is desirable to separate the frame ground and the signal ground.
  • spare conductive connection portions for arranging the ground connection member 14G may be provided at a plurality of locations on the first circuit board 10 and the second circuit board 20.
  • external noise applied to the external interface connector 40 is most easily propagated to the frame ground having the same potential as the external interface connector 40.
  • the external noise propagates to the second frame ground 22FG arranged on the second circuit board 20, the second frame ground 22FG is arranged on the outer peripheral portion, so that it is far from the first signal ground 12SG.
  • the external noise is difficult to propagate on the control IC 15 and the noise countermeasure component 16. Therefore, the control IC 15 having low noise tolerance has little influence on the noise countermeasure component 16 that can be magnetically coupled to become a noise propagation path, and the tolerance can be improved.
  • the second signal ground 22SG is disposed on the control IC 15 and the noise countermeasure component 16, thereby serving as a shield.
  • the second frame ground 22FG may be disposed on the control IC 15 and the noise countermeasure component 16.
  • the potential difference between the signal ground and the communication signal line is stabilized by suppressing the occurrence of a potential difference at a high frequency between the frame ground and the signal round due to the influence of external noise application, Malfunctions due to noise can be suppressed.
  • the noise from the external interface connector since the first frame ground and the second frame ground are electrically connected by the external interface connector, the noise from the external interface connector has the same potential. Propagation efficiently from the first frame ground and the second frame ground, and propagation to the first signal ground on the first circuit board are suppressed.
  • the connection position can be freely laid out and the noise It is possible to construct a route that is effective as a countermeasure and a route that avoids restrictions on component mounting.
  • FIG. FIG. 9 is a top view schematically showing the circuit board according to the second embodiment
  • FIG. 10 is a cross-sectional view taken along the line XX of FIG. 9, schematically showing the circuit board showing only the main part except for the insulating base material. It is shown in 11 and 12 are views showing the surfaces on the XI side and the XII side in FIG. 10 of the second circuit board of the second embodiment.
  • the second frame ground 22FG on the second circuit board 20 is arranged almost on the entire surface as compared with the first embodiment, and the connection member 23 and the conductive connection member 14 are provided.
  • the second signal ground 22SG is arranged in an island shape only at the place where it is placed.
  • a quadrangular second signal ground 22SG is formed in the second frame ground 22FG via a square slit insulating region, that is, a second slit 22S which is a second insulating region.
  • a plurality of second signal grounds 22SG are arranged at equal intervals. Since others are the same as the circuit board of Embodiment 1, detailed description is abbreviate
  • the installation location of the connection member 23 and the conductive connection member 14 is not limited to the illustrated location. Further, the second signal ground and the insulating region are not limited to the shapes shown in FIG.
  • the second frame ground 22FG is the surface on the XII side of the second circuit board 20, that is, the second circuit board 20 is shown on the XII side and the XII side of the second circuit board in FIG. 1 is preferably disposed on the surface opposite to the circuit board 10, and the surface facing the first circuit board 10 is not a conductor portion but a base material 21 made of a dielectric substrate as shown in FIG. Yes. That is, there is no wiring layer on the surface of the second circuit board 20 facing the electronic parts such as the control IC 15 mounted on the wiring layer of the first circuit board 10 and the circuit portion, and it is made of a dielectric substrate. The base material 21 is exposed.
  • the first circuit board 10 Since a conductor layer such as the second frame ground 22FG is present on the surface on the XII side, that is, on the surface opposite to the first circuit board 10, the first circuit board 10 is far away from the first circuit board 10 through the base material 21, and the first Even when the distance between the circuit board 10 and the second circuit board 20 is close, the insulation distance can be secured. In addition, electrostatic discharge from the conductive portion of the second circuit board 20 to the first circuit board 10 can be suppressed.
  • an island-shaped second signal ground is selectively formed at a position where the inter-substrate connecting member is disposed, and the island-shaped second signal ground is a second insulating region. Is surrounded by a second frame ground.
  • the above configuration can stabilize the potential difference between the communication signal line and the signal ground that affects the device operation when high frequency noise is applied.
  • FIG. 13 is a cross-sectional view of the circuit board according to the third embodiment.
  • FIGS. 14 and 15 are views showing the XIV side and XV side surfaces in FIG. 13 of the second circuit board of the third embodiment, and
  • FIG. 16 is a plan view showing the first circuit board.
  • the communication signal line 26 wired inside the external interface connector 40 arranged on the second circuit board 20 is arranged adjacent to the external interface connector 40 as compared with the first embodiment.
  • the inter-board connection wiring 24G which is an inter-board connection member. Is done.
  • the connection position can be freely laid out, and the noise propagation from the frame ground and the noise propagation from the signal wiring can be separated. The degree increases.
  • a frame ground connected to the first signal line connector 18 is not arranged on the first circuit board 10.
  • the external interface connector 40 is disposed on the second circuit board 20, and the first signal line connection connector 18 is provided at a location adjacent to the external interface connector 40 on the first circuit board 10.
  • the second signal wiring connector 28 is also provided on the second circuit board 20, and the first and second signal wiring connectors 18 and 28 are connected by the inter-substrate connection wiring 24G. . Since others are the same as the circuit board of Embodiment 1, detailed description is abbreviate
  • the second circuit board 20 is provided with a second signal ground 22SG and a second frame ground 22FG made of a wiring layer formed on a base material 21 made of a dielectric substrate. Since the frame ground connected to the first signal wiring connector 18 is not disposed on the first circuit board 10, a mounting component is obtained by eliminating the need for a slit for taking an insulation distance from the signal ground. It is possible to reduce the size of the main circuit board by the concentrated arrangement.
  • the external interface connector is disposed on the second circuit board.
  • a first signal wiring connection connector is provided at a location adjacent to the external interface connector on the first circuit board, and the second circuit board is provided with a second signal wiring connection connector.
  • the first signal line connecting connector and the second signal line connecting connector are connected by an inter-board connection line. Accordingly, as described above, the size of the main circuit board can be reduced by the collective arrangement of the mounted components.
  • the first circuit configuring the main board is described.
  • a signal ground and a frame ground may be formed on the substrate 10, and only the signal ground may be formed on the second circuit substrate 20 disposed to face the substrate 10. That is, the first circuit board 10 and the second circuit board 20 are replaced in the circuit board 100 of the third embodiment shown in FIG. 13, and are arranged on the second circuit board 20 as compared with the first embodiment.
  • the communication signal line 26 wired inside the external interface connector 40 is connected to a second signal wiring connection connector 28 disposed adjacent to the external interface connector 40, and is connected to the first circuit board via the inter-board connection wiring 24G.
  • the second signal wiring connector 28 is connected to the second signal wiring connector 28 on the second circuit board 20 except that the first signal wiring connector 18 is connected to the first signal wiring connector 18. It is also possible to adopt a configuration in which the frame ground is not arranged.
  • the second circuit board 20 has a second signal ground 22SG made of a wiring layer formed on a base material 21 made of a dielectric substrate. Since the frame ground connected to the second signal wiring connector 28 is not arranged on the second circuit board 20, the main circuit board size can be reduced by the collective arrangement of the mounted components.
  • FIG. 17 is a cross-sectional view schematically showing a circuit board according to the fourth embodiment.
  • the second circuit board 20 and the third circuit board 30 are arranged so as to be sandwiched from above and below the first circuit board 10, and the respective signal grounds. And the frame ground is connected.
  • the first circuit board 10 has the first signal ground 12SG and the first frame ground 12FG, similarly to the first circuit board 10 of the first embodiment.
  • a connecting member 13 for connecting the first signal ground 12SG and the first frame ground 12FG at a high frequency is disposed.
  • the second circuit board 20 has a second signal ground 22SG and a second frame ground 22FG on a base 21 made of a dielectric substrate. .
  • a connection member 23 for connecting the second signal ground 22SG and the second frame ground 22FG at a high frequency is disposed.
  • the third circuit board 30 has a third signal ground 32SG and a third frame ground 32FG.
  • a connection member 33 for connecting the third signal ground 32SG and the third frame ground 32FG at a high frequency is disposed.
  • the first to third signal grounds 12SG, 22SG, and 32SG are connected via the conductive connection member 14.
  • the first to third frame grounds 12FG, 22FG, and 32FG are also connected through the conductive connection member 14.
  • the control IC 15 is mounted on the third circuit board 30, and the noise countermeasure component 16 is connected to the first signal ground 12 SG of the first circuit board 10. Since others are the same as the circuit board of Embodiment 3, detailed description is abbreviate
  • the high-frequency connection between the signal ground and the frame ground can be strengthened, and the shielding performance can be improved.
  • the installation location and the number of conductive connection members and connection members are not limited thereto.
  • FIG. 18 is a cross-sectional view schematically showing a circuit board according to the fifth embodiment.
  • the third circuit board 30S includes a third frame ground 32FG and a third signal ground 32SG.
  • the third circuit board 30S includes a slit (not shown) as a third insulating region between both grounds, and straddles the third insulating region.
  • a connection member (not shown) for connecting the third signal ground 32SG and the third frame ground 32FG at a high frequency is arranged.
  • the third circuit board 30S is installed perpendicularly to the first circuit board 10 and has the same board structure as that of the second circuit board 20a except that the installation direction is different. Omitted.
  • the third signal ground 32SG and the third frame ground 32FG are connected to each ground by a connecting member. Since others are the same as the circuit board of Embodiment 3, detailed description is abbreviate
  • the circuit board of the fifth embodiment when external noise is applied to the external interface connector 40, radiation noise emitted from the external interface connector 40 main body is blocked by the ground portion of the third circuit board, Noise propagation to the main circuit of the first circuit board can be reduced. Furthermore, the ground potential can be further stabilized by connecting the first and second circuit boards to the ground, and noise resistance can be improved.
  • FIG. 19 is a cross-sectional view schematically showing a circuit board according to the sixth embodiment.
  • the third circuit board 30T according to the fifth embodiment has an opening into which the external interface connector 40 can be inserted.
  • the external interface connector 40 is fitted and disposed in
  • the third circuit board 30T includes a third frame ground 32FG and a third signal ground 32SG.
  • the third circuit board 30T includes a third slit 32S as a third insulating region between the two grounds.
  • a connecting member 33 for connecting the third signal ground and the third frame ground in a high frequency manner is disposed so as to straddle.
  • the third circuit board 30T is installed perpendicularly to the first circuit board 10 and has the same board structure as that of the second circuit board 20 except that the installation direction is different. Omitted.
  • the third signal ground 32SG and the third frame ground 32FG are connected to the grounds of the first and second circuit boards 10 and 20 by connection members (not shown). Further, by electrically connecting the third frame ground 32FG and the external interface connector 40 by the connecting member 33, it is possible to further stabilize the potential. Since others are the same as the circuit board of Embodiment 3, detailed description is abbreviate
  • the noise immunity can be further improved. Furthermore, the third circuit boards 30S and 30T surround the four sides of the external interface connector 40, and the second circuit board surrounds a plane parallel to the first circuit board 10 to improve noise resistance more reliably. can do.
  • the third frame ground 32FG is connected to the external interface connector 40 via the connection member 33, and the third frame ground 32FG and the third signal ground 32SG are the first and second signals. It is only necessary to be connected to any one of the frame ground and the first and second signal grounds.
  • FIG. FIG. 20 is a cross-sectional view schematically showing a circuit board according to the seventh embodiment.
  • FIG. 21 is a top view of the circuit board according to the seventh embodiment.
  • the heat dissipating fins 33FG provided for heat dissipation are provided to face the first circuit board 10. Since the radiation fin 33FG is a metal structure and the external ground connection member 50 is connected to the stable ground, the potential of the radiation fin 33FG is a frame ground potential. Although the external ground connection member 50 is not shown on the circuit board 10, the external ground member 50 may be disposed on the circuit board 10.
  • a heat radiation sheet 15 a is sandwiched between the heat radiation fins 33 FG and the control IC 15. That is, the control IC 15 that is a heating element is thermally connected to the radiation fins 33FG via the radiation sheet 15a. The heat generated in the control IC 15 is transmitted to the heat radiating fins 33FG via the heat radiating sheet 15a, and is radiated from the heat radiating fins 33FG to the surroundings.
  • the second circuit board 20 is fitted in the recess 71 formed in the heat radiation fin 33FG.
  • a through hole 72 penetrating toward the first circuit board 10 is formed in the bottom surface of the recess 71 of the heat radiation fin 33FG.
  • the second signal ground 22SG included in the second circuit board 20 is exposed to the first circuit board 10 side through the through hole 72.
  • the second signal ground 22SG exposed to the first circuit board 10 side is electrically connected to the first signal ground 12SG through the conductive connection member 14 that passes through the through hole 72.
  • the heat radiation fin 33FG is electrically connected to the second frame ground 22FG via the connection member 23X at the bottom surface portion of the recess 71. Further, the heat radiating fins 33FG are electrically connected to the external interface connector 40. Therefore, the second frame ground 22FG included in the second circuit board 20 is electrically connected to the external interface 40 via the heat radiation fins 33FG.
  • FIG. 22 is a cross-sectional view showing a modification of the seventh embodiment.
  • FIG. 23 is a top view showing a modification of the seventh embodiment.
  • the second circuit board 20 may be placed on the heat radiation fins 33FG so as to close the through holes 72 without fitting the second circuit board 20 into the heat radiation fins 33FG. .
  • the thickness of the circuit board 100 can be reduced by fitting the second circuit board 20 into the recess 71 as shown in FIGS.
  • the shape of the radiation fin 33FG can be simplified by placing the second circuit board 20 on the radiation fin 33FG, and the radiation fin 33FG and the second frame ground 22FG can be connected to each other. Manufacturing work can be reduced because the electrical connection is facilitated.
  • the second frame ground covers all metal structures other than the printed pattern, and is not limited to the radiating fin structure exemplified in the seventh embodiment.
  • the configuration of the seventh embodiment it is possible to stabilize the potential on the substrate even when the structure having the second frame ground is not a printed circuit board. Compared to noise propagation of a thin film pattern such as a printed circuit board, the impedance of a metal structure is lower, so that the noise countermeasure effect by the connecting member 23 becomes more prominent. Further, in the case where the circuit board has a configuration in which the heat dissipating fins are essential, it is possible to take noise countermeasures with the minimum board configuration without newly arranging the second circuit board.
  • the dent 71 and the through-hole 72 provided in the radiation fin 33FG may be provided in a plurality of places.
  • FIG. FIG. 24 is a cross-sectional view schematically showing a circuit board according to the eighth embodiment.
  • the arrangement of the conductive connection member 14 will be described.
  • the position of the end of the control IC 15 on the inner peripheral side of the first circuit board 10 is X1
  • the position of the outer peripheral end of the first circuit board 10 on the side where the external interface connector 40 is provided is X2.
  • the position X where the conductive connecting member 14 is disposed is set within the following range. X1 ⁇ X ⁇ (X1 + X2) / 2 (1)
  • the noise propagating from the outer peripheral portion of the substrate is routed through the conductive connection member 14 along the way of propagation to the control IC 15 having low noise resistance.
  • the control IC 15 having low noise resistance.
  • the functional elements connected across the insulating region are not limited to this in terms of grounding location and number of arrangement.
  • the signal ground pattern and the frame ground pattern are not limited to this shape and arrangement location.
  • a capacitive element made of a chip capacitor was used as a functional element connected across the insulating region, but a stable potential between the signal ground and the frame ground can be obtained by connecting the high frequency via another high frequency element.
  • the present invention is not limited to this as long as noise resistance performance can be improved.
  • the capacitive element is not limited to a chip capacitor, and an integrated circuit patterned on the circuit may be used.
  • connection member may be selected from, for example, a capacitor, an inductor, a resistor, a noise filter, a jumper wiring, and the like.
  • the first circuit board is a three-layer circuit board including two dielectric layers.
  • a single-sided board a multilayer board is used. Any substrate may be used, and the present embodiment is not limited to three layers.
  • the second circuit board may be either a single-sided board or a multilayer board.
  • the via holes between the layers are not limited to those described in the drawings with respect to the number and location of the via holes, and can be changed as appropriate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Structure Of Printed Boards (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

Cette invention concerne une carte de circuit imprimé (100) comprenant : une première carte de circuit imprimé (10) pourvue d'un premier plan de cadre (12FG) sur lequel est monté un connecteur d'interface externe (40), un premier plan de signal (12SG), et un élément de connexion (13) assurant une connexion haute fréquence entre le premier plan de cadre (12FG) et le premier plan de signal (12SG) ; et une seconde carte de circuit imprimé (20) sur laquelle est disposé un second plan de cadre (22FG), un second plan de signal (22SG), et un élément de connexion (23) assurant une connexion haute fréquence entre le second plan de cadre (22FG) et le second plan de signal (22SG). Le premier plan de signal (12SG) et le second plan de signal (22SG) sont électriquement connectés l'un à l'autre. Le premier plan de cadre (12FG) et le second plan de cadre (22FG) sont électriquement connectés l'un à l'autre.
PCT/JP2017/012056 2017-03-24 2017-03-24 Carte de circuit imprimé WO2018173263A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201780048945.2A CN109565927A (zh) 2017-03-24 2017-03-24 电路基板
PCT/JP2017/012056 WO2018173263A1 (fr) 2017-03-24 2017-03-24 Carte de circuit imprimé
KR1020197003463A KR101999509B1 (ko) 2017-03-24 2017-03-24 회로 기판
JP2018508254A JP6391885B1 (ja) 2017-03-24 2017-03-24 回路基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/012056 WO2018173263A1 (fr) 2017-03-24 2017-03-24 Carte de circuit imprimé

Publications (1)

Publication Number Publication Date
WO2018173263A1 true WO2018173263A1 (fr) 2018-09-27

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PCT/JP2017/012056 WO2018173263A1 (fr) 2017-03-24 2017-03-24 Carte de circuit imprimé

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JP (1) JP6391885B1 (fr)
KR (1) KR101999509B1 (fr)
CN (1) CN109565927A (fr)
WO (1) WO2018173263A1 (fr)

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JP2021039973A (ja) * 2019-08-30 2021-03-11 富士通株式会社 電気チップ及び光モジュール
WO2021187241A1 (fr) * 2020-03-19 2021-09-23 株式会社ソニー・インタラクティブエンタテインメント Dispositif de communication
EP4084597A4 (fr) * 2019-12-27 2023-12-27 Hitachi Astemo, Ltd. Dispositif de commande électronique

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KR20200114709A (ko) * 2019-03-29 2020-10-07 엘지전자 주식회사 기판 구조체 및 그 제어 방법
DE112020006584B4 (de) * 2020-03-25 2024-01-04 Mitsubishi Electric Corporation Platine und elektronisches Gerät
JP7395057B2 (ja) * 2021-04-06 2023-12-08 三菱電機株式会社 プリント回路基板
CN115580983B (zh) * 2022-09-30 2023-08-29 荣耀终端有限公司 电路板组件和电子设备

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JP2003283072A (ja) * 2002-03-20 2003-10-03 Canon Inc プリント配線板ユニット
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JP2021039973A (ja) * 2019-08-30 2021-03-11 富士通株式会社 電気チップ及び光モジュール
JP7268544B2 (ja) 2019-08-30 2023-05-08 富士通株式会社 電気チップ及び光モジュール
EP4084597A4 (fr) * 2019-12-27 2023-12-27 Hitachi Astemo, Ltd. Dispositif de commande électronique
WO2021187241A1 (fr) * 2020-03-19 2021-09-23 株式会社ソニー・インタラクティブエンタテインメント Dispositif de communication

Also Published As

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JP6391885B1 (ja) 2018-09-19
KR20190018535A (ko) 2019-02-22
CN109565927A (zh) 2019-04-02
KR101999509B1 (ko) 2019-07-11
JPWO2018173263A1 (ja) 2019-03-28

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