WO2018171162A1 - 复位电路、移位寄存器电路、栅极驱动电路、显示装置以及驱动方法 - Google Patents

复位电路、移位寄存器电路、栅极驱动电路、显示装置以及驱动方法 Download PDF

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Publication number
WO2018171162A1
WO2018171162A1 PCT/CN2017/104393 CN2017104393W WO2018171162A1 WO 2018171162 A1 WO2018171162 A1 WO 2018171162A1 CN 2017104393 W CN2017104393 W CN 2017104393W WO 2018171162 A1 WO2018171162 A1 WO 2018171162A1
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WIPO (PCT)
Prior art keywords
circuit
shift register
reset
signal
adjustment
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PCT/CN2017/104393
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English (en)
French (fr)
Inventor
张杨
曹诚英
李鹏
吴鹏
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/770,904 priority Critical patent/US10290277B2/en
Priority to EP17861195.0A priority patent/EP3407342B1/en
Publication of WO2018171162A1 publication Critical patent/WO2018171162A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a reset circuit, a shift register circuit, a gate drive circuit, a display device, and a driving method.
  • the display device includes a gate drive circuit for driving the pixel circuit, such as a gate drive circuit using a Gate on Array (GOA) technology.
  • the gate driving circuit includes a cascaded shift register circuit (SR circuit, or a gate driving circuit or a GOA circuit), wherein the input clock signal is sequentially added to each of the display devices after being converted by the shift register circuit.
  • the display of the display device is controlled line by line on the gate line of the pixel row. In the gate drive circuit arrangement, it is necessary to use the output of a stage shift register circuit to reset a previous stage shift register circuit.
  • an embodiment of the present disclosure proposes a reset circuit for a shift register circuit.
  • the reset circuit includes: a first adjustment control circuit having an input end, an output end, and a control end, wherein the input end receives the ground signal via the ground input end, the control end receives the first control signal; and the second adjustment control circuit has an input end And an output end, wherein the input end receives the adjustment signal via the adjustment signal input end, the control end receives the second control signal, and the output end is connected to the output end of the first adjustment control circuit; the storage circuit is connected at the first end thereof To an output end of the first adjustment control circuit and an output end of the second adjustment control circuit, the second end is connected to a reset signal input terminal for receiving a reset signal and the shift register circuit for receiving a reset Input between the transistors.
  • the first adjustment control circuit and the second adjustment control circuit comprise thin film transistors
  • the storage circuit comprises a capacitor
  • the input terminal includes one of a source and a drain
  • the output terminal includes the other of the source and the drain
  • the control terminal includes a gate
  • the second adjustment In the control circuit, the input terminal includes one of a source and a drain, the output terminal includes the other of the source and the drain, and the control terminal includes a gate.
  • the first control signal is in phase with a gate drive input signal of the shift register circuit, and the second control signal is in phase with the reset signal.
  • the first control signal includes the gate drive input signal
  • the second control signal includes the reset signal
  • the adjustment signal includes a constant DC level adjustment signal.
  • the reset signal input is for receiving a reset signal from another shift register circuit.
  • a shift register circuit includes the reset circuit according to the above embodiments.
  • inventions of the present disclosure provide a gate drive circuit.
  • the gate driving circuit includes cascaded N shift register circuits, wherein K shift register circuits among the N shift register circuits are shift register circuits according to the present disclosure, and N and K are positive integers
  • the K shift register circuits are the N-2K+1th to NKth shift register circuits of the N shift register circuits.
  • the reset signal input terminal receives a reset signal from the Kth stage shift register circuit after the shift register circuit.
  • an embodiment of the present disclosure provides a display device.
  • the display device includes a gate drive circuit in accordance with the present disclosure.
  • embodiments of the present disclosure provide a driving method for driving a reset circuit according to the present disclosure, wherein a first end of the storage circuit and the first adjustment control circuit and a second An output of the regulation control circuit is coupled at a first node, and a second end of the storage circuit is coupled to the second node.
  • the driving method includes controlling, by the first control signal, the first adjustment control circuit to be turned on during a first period of time such that a voltage at the first node is zero; during a second period of time, The first control signal controls the first adjustment control circuit to be turned off; during the third time period, the second adjustment control power is controlled by the second control signal
  • the circuit is turned on, such that the voltage at the first node is equal to the voltage of the adjustment signal, and the reset signal is input through the reset signal input terminal, so that the voltage at the second node is equal to the reset signal The voltage is subtracted from the voltage of the adjustment signal.
  • the first time period, the second time period, and the third time period are respectively equal to 1/2 clock period.
  • Figure 1 shows a cascade diagram of a gate drive circuit.
  • Fig. 2 is a circuit diagram showing a shift register circuit.
  • FIG. 3 shows a signal timing diagram of the shift register circuit shown in FIG. 2.
  • FIG. 4 shows a circuit configuration diagram of a reset circuit according to an embodiment of the present disclosure.
  • Fig. 5 shows a more detailed circuit configuration diagram of the reset circuit shown in Fig. 4.
  • FIG. 6 shows a circuit configuration diagram of a shift register circuit according to an embodiment of the present disclosure.
  • Fig. 7 is a timing chart showing the signal of the shift register circuit shown in Fig. 6.
  • FIG. 8 illustrates a cascade diagram of gate drive circuits in accordance with an embodiment of the present disclosure.
  • FIG. 9 illustrates a cascade diagram of gate drive circuits in accordance with another embodiment of the present disclosure.
  • FIG. 10 illustrates a cascade diagram of gate drive circuits in accordance with another embodiment of the present disclosure.
  • FIG. 11 shows a flow chart of a driving method of a reset circuit according to an embodiment of the present disclosure.
  • FIG. 1 shows a cascade diagram of an exemplary gate drive circuit 100.
  • FIG. 2 shows a circuit configuration diagram of an exemplary shift register circuit 200.
  • the gate drive circuit 100 shown in FIG. 1 includes an N-stage shift register circuit. For the convenience of description, only the last four stages of shift register circuits SR(N-3) to SR(N) are shown.
  • the shift register circuit SR(N) is the last stage, which is not connected to the pixel load as an additional reset shift register circuit.
  • each stage shift register circuit is implemented as a shift register circuit 200 except for the last stage shift register circuit SR(N).
  • the shift register circuit 200 includes a first input terminal 1 for receiving the gate drive input signal INPUT, a second input terminal 2 for receiving the reset signal RESET, and an output terminal 8 for outputting the output signal OUTPUT.
  • the output signal OUTPUT output from the output terminal 8 is the gate scan signal of the shift register circuit 200.
  • the input signal INPUT received is the previous stage shift register circuit (SR( The output signal OUTPUT (G(N-2)) of N-2)), the received reset signal RESET is the output signal OUTPUT (G(N)) of the next stage (SR(N)).
  • the shift register circuit 200 may include four transistors and one capacitor, that is, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a capacitor C.
  • the gate of the first transistor M1 is connected to the source and is connected to the first input terminal 1.
  • the gate of the second transistor M2 is connected to the second input terminal 2, and the drain is connected to the low-level terminal 5 for receiving the low-level signal VSS.
  • the drain of the first transistor M1 and the source of the second transistor M2 are connected to the pull-up node PU.
  • the gate of the third transistor M3 is connected to the clock terminal 6 for receiving the clock signal CLK.
  • the gate of M3 is connected to the output 8 via a capacitor C.
  • the gate of the fourth transistor M4 is also connected to the second input terminal 2, the drain is also connected to the low level terminal 5, and the source is connected to the output terminal 8.
  • FIG. 3 shows a signal timing diagram of the shift register circuit 200.
  • One period in Fig. 3 is 1/2 clock cycle.
  • the input signal INPUT of the shift register circuit 200 of the present stage is at a high level, and the first transistor M1 turns on pre-charging the PU of the pull-up node.
  • the clock signal CLK of the shift register circuit 200 of the present stage is at a high level, and the third transistor M3 is turned on, so that the output signal OUTPUT of the output terminal 8 is at a high level.
  • the potential of the pull-up node PU is raised again.
  • the output signal outputted by the shift register circuit of the next stage is at a high level, that is, the reset signal RESET received at the second input terminal 2 is at a high level, and the second transistor M2 and the fourth transistor M4 are turned on.
  • the discharge node PU and the output terminal 8 are discharged to be reset.
  • the last stage shift register circuit SR(N) in the gate driving circuit 100 does not have a pixel load, so that the voltage of the reset signal RESET generated by the shift register circuit SR(N-1) of the upper stage is large, It adversely affects the performance of SR(N-1).
  • FIG. 4 shows a circuit configuration diagram of a reset circuit 400 according to an embodiment of the present disclosure.
  • the reset circuit 400 can be applied to various shift register circuits, for example, a shift register circuit that receives a reset signal RESET having a large voltage as described above, such as SR(N-1) in FIG. 3, thereby being controllable
  • SR(N-1) a reset signal
  • the voltage value of the reset signal actually applied to an element (for example, the second transistor M2 in FIG. 2) in the shift register circuit is lowered.
  • the reset circuit 400 provided by the embodiment of the present disclosure includes a first adjustment control circuit 410, a second adjustment control circuit 420, and a storage circuit 430.
  • the input end of the first adjustment control circuit 410 receives the ground signal GND via the ground input terminal, and the control terminal receives the first control signal.
  • the input end of the second adjustment control circuit 420 receives the adjustment signal VNN via the adjustment signal input terminal, the control terminal receives the second control signal, and the output terminal is connected to the output end of the first adjustment control circuit 410. For example, it is connected at the first node N1 shown in FIG.
  • a first end of the storage circuit 430 is coupled to the first node N1, and a second end is coupled to receive a shift register from another shift register circuit (a shift register circuit in which the reset circuit 400 is located)
  • the reset signal input terminal of the reset signal RESET of the circuit for example, in the case of turning on one line of pixels each time is the shift register circuit of the shift register circuit in which the reset circuit 400 is located, and the shift of the reset circuit 400 Between the transistors in the bit register circuit for receiving the reset input, such as at the second node N2 shown in FIG.
  • the first control signal is in phase with the gate drive input signal of the shift register circuit in which the reset circuit 400 is located, and the second control signal is in phase with the reset signal RESET.
  • the first control signal is the gate drive input signal and the second control signal is the reset signal RESET.
  • the adjustment signal VNN is a constant DC level adjustment signal.
  • the root The voltage of the regulation signal VNN is varied as needed to controllably reduce the voltage value of the reset signal actually applied to the critical components in the shift register circuit.
  • FIG. 5 shows a more detailed circuit configuration diagram of the reset circuit 400 shown in FIG.
  • the first adjustment control circuit 410 and the second adjustment control circuit 420 include thin film transistors M41 and M42, respectively.
  • the memory circuit 430 includes a capacitor C43.
  • the input of the first adjustment control circuit 410 is one of the source and the drain of M41, the output is the other of the source and the drain of M41, and the control terminal is the gate of M41.
  • the input of the second adjustment control circuit 420 is one of the source and the drain of M42, the output is the other of the source and the drain of M42, and the control terminal is the gate of M42.
  • FIG. 6 shows a circuit configuration diagram of a shift register circuit 600 in accordance with an embodiment of the present disclosure.
  • the shift register circuit 600 includes the circuit configuration of the reset circuit 400 and the shift register circuit (for example, the shift register circuit 200 shown in FIG. 2) shown in FIG. 4 (or FIG. 5).
  • the reset circuit 400 is combined with the shift register circuit 200 of FIG. 2 in FIG. 6, this is merely exemplary, and the present disclosure does not relate to the shift register circuit combined with the reset circuit 400.
  • the specific structure is limited.
  • the reset circuit 400 can also be combined with other types of shift register circuits to implement the shift register circuit of the present disclosure capable of reducing the reset signal applied to the key elements. .
  • FIG. 6 shows a more detailed exemplary circuit configuration of the reset circuit 400 in FIG.
  • the reset signal RESET received at the second input terminal 2 is lowered by the reset circuit 400 at the second node N2, thereby improving the reset signal pair M2 finally applied to the second transistor M2. Negative Effects.
  • FIG. 7 shows a signal timing diagram of the shift register circuit 600.
  • One period in Fig. 7 is 1/2 clock cycle.
  • the timing operation of the shift register circuit 600 shown in Fig. 6 will be described below with reference to Fig. 7 .
  • the input signal INPUT is at the high level.
  • the first control signal is in phase with INPUT and is therefore also high.
  • the clock signal CLK of the shift register circuit 600 is at a low level, and the reset signal RESET received by the shift register circuit 600 is also at a low level, so that the transistor M42 is turned off.
  • the clock signal CLK of the shift register circuit 600 is at a high level, and the third transistor M3 is turned on, so that the output signal OUTPUT of the output terminal 8 is at a high level, which means that it is going to be a shift register.
  • the input of the shift register circuit that circuit 600 provides the RESET signal is high.
  • the input signal INPUT of the shift register circuit 600 is no longer at a high level, the transistor M41 is turned off, and the voltage PN1 at the first node N1 is maintained at 0V.
  • the output of the shift register circuit that will supply the RESET signal to the shift register circuit 600 is at a high level, that is, the reset signal RESET received at the second input terminal 2 is at a high level. Since the second control signal is in phase with the reset signal RESET, it is also at a high level, the transistor M42 is turned on, and the voltage PN1 at the first node N1 becomes a voltage of VNN, for example, 1/4*Vgl, where Vgl is a transistor The gate of M42 is low voltage.
  • the voltage PN2 at the second node N2 is not Vreset, but Vreset-VNN, that is, Vreset-1/4*Vgl, which causes the N2 node voltage to decrease. That is, the voltage applied to the gate of the second transistor M2 is reduced by 1/4*Vgl as compared with before the setting of the reset circuit 400. Thereby, the voltage applied to the gate of the second transistor M2 can be adjusted by changing the magnitude of the voltage 1/4*Vgl of the VNN.
  • FIG. 8 shows a cascade diagram of a gate drive circuit 800 in accordance with an embodiment of the present disclosure.
  • each shift register circuit includes only a single shift register circuit, that is, only a single shift register circuit is simultaneously turned on. Pixel row.
  • the gate driving circuit 800 includes a difference from the gate driving circuit 100 of FIG. 1 in that the penultimate stage shift register circuit SR(N-1) is implemented as a shift register circuit having the reset circuit 400, for example, in FIG. Shift register circuit 700.
  • the shift register circuit SR(N-1) also receives GND and VNN to implement the function of the reset circuit 400.
  • each group includes a single shift register circuit is shown in FIG. 8, this is merely exemplary, and in other embodiments, continuous multi-level shifts may also be included in each group.
  • a register circuit that simultaneously turns on a plurality of pixel rows corresponding to the multi-stage shift register circuit in a group. At this time, it is necessary to additionally set a set of the same number of reset shift registers to reset the last set of shift registers applied to the active area, and in order to reduce the reset voltage applied to the set of shift registers, it is necessary to Each shift register circuit in the group is implemented as a shift register circuit having a reset circuit 400.
  • each of the shift register circuits includes a K-stage shift register circuit, N and K are positive integers, then the N
  • the penultimate group of K shift register circuits (i.e., N-2K+1 to NKth) in the cascade shift register circuit is implemented as a shift register circuit having the reset circuit 400.
  • each group of gate drive circuits including a two-stage shift register circuit is shown in FIG.
  • the gate driving circuit in FIG. 9 includes an N-stage shift register circuit, and only the last 6 stages thereof are shown as an example, and the last 6-stage shift register circuits are shown in broken lines to be divided into three groups, each group including Two-stage shift register circuit.
  • the first stage shift register circuit of the first stage of the set shifts the output OUTPUT of the first stage shift register circuit as the input INPUT, the first of the following groups
  • the output OUTPUT of the stage shift register circuit is used as the reset input RESET.
  • the second stage shift register in the group The output OUTPUT of the second stage shift register circuit in the above group is used as the input INPUT, and the output OUTPUT of the second stage shift register circuit in the following group is used as the reset input RESET.
  • the last set of shift register circuits SR(N-1) and SR(N) as additional reset shift registers are not connected to the pixel load, which is only used for the penultimate set of shift register circuits SR(N-2) and SR (N-3) is reset.
  • the penultimate set of shift register circuits SR(N-2) and SR(N-3) are each implemented as a shift register circuit having a reset circuit 400 (Fig. 4 or Fig. 5) to reduce the key applied thereto.
  • the reset voltage on the component eg, second transistor M2 in Figure 2.
  • each group of gate drive circuits including a three-stage shift register circuit is shown in FIG.
  • the gate driving circuit in FIG. 10 includes an N-stage shift register circuit, and only the last 6 stages thereof are shown as an example, and the last 6-stage shift register circuits are shown by a broken line box divided into 2 groups, each group including Three-stage shift register circuit.
  • the first stage shift register circuit of the first stage of the set shifts the output OUTPUT of the first stage shift register circuit as the input INPUT, the first of the following groups
  • the output OUTPUT of the stage shift register circuit is used as the reset input RESET.
  • the output of the second stage shift register circuit of the second stage of the group is the input INPUT of the second stage shift register circuit, and the output OUTPUT of the second stage shift register circuit of the following group is used as the reset input RESET.
  • the output OUTPUT of the third stage shift register circuit in the above group is used as the input INPUT, and the output OUTPUT of the third stage shift register circuit in the following group is used as the reset input RESET.
  • the last set of shift register circuits SR(N-2), SR(N-1) and SR(N) as additional reset shift registers are not connected to the pixel load, which is only used for the penultimate group of shift register circuits SR(N-5), SR(N-4), and SR(N-3) are reset.
  • the penultimate group shift register circuits SR(N-5), SR(N-4), and SR(N-3) are each implemented as a shift register circuit having a reset circuit 400 (FIG. 4 or FIG. 5). To reduce the reset voltage on the key components (eg, the second transistor M2 in FIG. 2) applied thereto.
  • FIG. 11 shows a flow diagram of a driving method 1100 of a reset circuit (eg, reset circuit 400 shown in FIGS. 4 and/or 5) in accordance with an embodiment of the present disclosure.
  • a reset circuit eg, reset circuit 400 shown in FIGS. 4 and/or 5
  • description will be made below with reference to the circuit configuration in FIG. 5.
  • the driving method 1100 includes the following steps S1110-S1130:
  • the transistor M41 is controlled to be turned on by the first control signal so that the voltage PN1 at the first node N1 is 0V.
  • the transistor M41 is controlled to be turned off by the first control signal. At this time, the voltage PN1 at the first node N1 is maintained at 0V.
  • the transistor M42 is controlled to be turned on by the second control signal such that the voltage PN1 at the first node N1 is equal to the voltage of the adjustment signal VNN (eg, 1/4*Vgl).
  • the present invention also provides a display device including the above-described gate driver.
  • the display device may be a liquid crystal display device such as a liquid crystal panel, a liquid crystal television, a mobile phone, an electronic reader, a liquid crystal display, or the like.

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  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种针对移位寄存器电路的复位电路（400）、移位寄存器电路（200）、栅极驱动电路（100）、显示装置以及驱动方法。其中，复位电路(400)包括：第一调节控制电路（410），其输入端经由接地输入端接收地线信号，控制端接收第一控制信号；第二调节控制电路（420），其输入端经由调节信号输入端接收调节信号，控制端接收第二控制信号，第二调节控制电路(420)的输出端连接到第一调节控制电路(410)的输出端；存储电路（430），其第一端连接到第二调节控制电路(420)的输出端和第一调节控制电路(410)的输出端，第二端连接在用于接收复位信号的复位信号输入端和移位寄存器电路(200)的用于接收复位输入的晶体管之间。

Description

复位电路、移位寄存器电路、栅极驱动电路、显示装置以及驱动方法
本申请要求于2017年3月24日提交的、申请号为201710181053.1的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，具体地涉及一种复位电路、移位寄存器电路、栅极驱动电路、显示装置以及驱动方法。
背景技术
显示装置包括用于驱动像素电路的栅极驱动电路，例如使用栅极驱动阵列(GOA，Gate on Array)技术的栅极驱动电路。栅极驱动电路包括级联的移位寄存器电路(SR电路，或称为栅极驱动电路或GOA电路)，其中输入的时钟信号通过移位寄存器电路的转换后会依次加在显示装置的每一像素行的栅线上，以逐行控制显示装置的显示。在栅极驱动电路布置中，需要使用之后某一级移位寄存器电路的输出来对之前某一级移位寄存器电路进行复位。比如，在将单级移位寄存器电路作为一组从而只同时开启一行像素电路的情况中，对于第n级移位寄存器电路来讲，需要使用第n+1级移位寄存器电路的输出作为其复位输入。
然而，对于最后几级移位寄存器电路，比如，以上示例情况中的最后一级，其后并不存在其他的移位寄存器电路，因此需要设置单独的复位移位寄存器电路来实现这一复位功能。这些复位移位寄存器电路并不像之前的移位寄存器电路那样连接有效区域的栅极负载，从而其产生的复位信号的电压较大，这会对最后几级移位寄存器电路的工作特性产生不利的影响。
发明内容
根据本公开的一个方面，本公开的实施例提出了一种针对移位寄存器电路的复位电路。该复位电路包括：第一调节控制电路，具有输入端、输出端和控制端，其中输入端经由接地输入端接收地线信号，控制端接收第一控制信号；第二调节控制电路，具有输入端、输出端和控制端，其中输入端经由调节信号输入端接收调节信号，控制端接收第二控制信号，输出端连接到所述第一调节控制电路的输出端；存储电路，其第一端连接 到所述第一调节控制电路的输出端和所述第二调节控制电路的输出端，第二端连接在用于接收复位信号的复位信号输入端和所述移位寄存器电路的用于接收复位输入的晶体管之间。
例如，所述第一调节控制电路和所述第二调节控制电路包括薄膜晶体管，以及所述存储电路包括电容器。
例如，在所述第一调节控制电路中，输入端包括源极和漏极中的一个，输出端包括源极和漏极中的另一个，控制端包括栅极，以及在所述第二调节控制电路中，输入端包括源极和漏极中的一个，输出端包括源极和漏极中的另一个，控制端包括栅极。
例如，所述第一控制信号与所述移位寄存器电路的栅极驱动输入信号同相，以及所述第二控制信号与所述复位信号同相。
例如，所述第一控制信号包括所述栅极驱动输入信号，以及所述第二控制信号包括所述复位信号。
例如，所述调节信号包括恒定直流电平调节信号。
例如，所述复位信号输入端用于接收来自另一移位寄存器电路的复位信号。
根据本公开的另一方面，提供了一种移位寄存器电路。该移位寄存器电路包括根据上文各实施例所述的复位电路。
根据本公开的另一方面，本公开的实施例提供了一种栅极驱动电路。该栅极驱动电路包括级联的N个移位寄存器电路，其中，所述N个移位寄存器电路中的K个移位寄存器电路是根据本公开的移位寄存器电路，N和K为正整数，所述K个移位寄存器电路是所述N个移位寄存器电路中第N-2K+1个到第N-K个移位寄存器电路。
例如，在所述K个移位寄存器电路中的每一个移位寄存器电路的复位电路中，所述复位信号输入端接收来自该移位寄存器电路之后第K级移位寄存器电路的复位信号。
根据本公开的另一方面，本公开的实施例提供了一种显示装置。该显示装置包括根据本公开的栅极驱动电路。
根据本公开的另一方面，本公开的实施例提供了一种驱动方法，用于驱动根据本公开的复位电路，其中所述存储电路的第一端与所述第一调节控制电路和第二调节控制电路的输出端在第一节点处相连，所述存储电路的第二端与第二节点相连。所述驱动方法包括：在第一时段期间，通过所述第一控制信号控制所述第一调节控制电路接通，以使得所述第一节点处的电压为零；在第二时段期间，通过所述第一控制信号控制所述第一调节控制电路关断；在第三时段期间，通过所述第二控制信号控制所述第二调节控制电 路接通，使得所述第一节点处的电压等于所述调节信号的电压，同时通过所述复位信号输入端输入所述复位信号，使得所述第二节点处的电压等于所述复位信号的电压减去所述调节信号的电压。
例如，所述第一时段、第二时段和第三时段分别等于1/2时钟周期。
附图说明
图1示出了一种栅极驱动电路的级联图。
图2示出了一种移位寄存器电路的电路结构图。
图3示出了图2所示的移位寄存器电路的信号时序图。
图4示出了根据本公开实施例的复位电路的电路结构图。
图5示出了图4所示的复位电路的更为详细的电路结构图。
图6示出了根据本公开实施例的移位寄存器电路的电路结构图。
图7示出了图6所示的移位寄存器电路的信号时序图。
图8示出了根据本公开实施例的栅极驱动电路级联图。
图9示出了根据本公开的另一实施例的栅极驱动电路级联图。
图10示出了根据本公开的另一实施例的栅极驱动电路级联图。
图11示出了根据本公开实施例的复位电路的驱动方法的流程图。
具体实施方式
下面将详细描述本公开的具体实施例，应当注意，这里描述的实施例只用于举例说明，并不用于限制本公开。在以下描述中，为了提供对本公开的透彻理解，阐述了大量特定细节。然而，对于本领域普通技术人员显而易见的是：不必采用这些特定细节来实行本公开。在其他实例中，为了避免混淆本公开，未具体描述公知的电路、材料或方法。
在整个说明书中，对“一个实施例”、“实施例”、“一个示例”或“示例”的提及意味着：结合该实施例或示例描述的特定特征、结构或特性被包含在本公开至少一个实施例中。因此，在整个说明书的各个地方出现的短语“在一个实施例中”、“在实施例中”、“一个示例”或“示例”不一定都指同一实施例或示例。此外，可以以任何适当的组合和/或子组合将特定的特征、结构或特性组合在一个或多个实施例或示例中。此外，本领域普通技术人员应当理解，在此提供的附图都是为了说明的目的，并且附图不一定是按比例绘制的。这里使用的术语“和/或”包括一个或多个相关列出的项目的任何和所 有组合。
以下参考附图对本公开进行具体描述。
首先，图1示出了一种示例性栅极驱动电路100的级联图。图2示出了一种示例性移位寄存器电路200的电路结构图。
图1中每次同时开启单个像素行，所以在对移位寄存器电路进行分组时，每个组内只包括单个移位寄存器。图1中所示的栅极驱动电路100包括N级移位寄存器电路。为了便于描述，图中只示出了最后4级的移位寄存器电路SR(N-3)～SR(N)。移位寄存器电路SR(N)为最后一级，其作为附加的复位移位寄存器电路不连接像素负载。在栅极驱动电路100中，除最后一级移位寄存器电路SR(N)之外，每一级移位寄存器电路都实现为移位寄存器电路200。
具体地，移位寄存器电路200包括用于接收栅极驱动输入信号INPUT的第一输入端1、用于接收复位信号RESET的第二输入端2和用于输出输出信号OUTPUT的输出端8。输出端8输出的输出信号OUTPUT即移位寄存器电路200的栅极扫描信号。
对于栅极驱动电路100中的任一级移位寄存器电路200，比如图1中的移位寄存器电路SR(N-1)，其接收的输入信号INPUT是上一级移位寄存器电路(SR(N-2))的输出信号OUTPUT(G(N-2))，其接收的复位信号RESET是下一级(SR(N))的输出信号OUTPUT(G(N))。
移位寄存器电路200可以包括四个晶体管和一个电容器，即第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4和电容器C。
具体地，第一晶体管M1的栅极和源极相连，并连接至第一输入端1。
第二晶体管M2的栅极连接至第二输入端2，漏极与低电平端5连接，用于接收低电平信号VSS。
第一晶体管M1的漏极与第二晶体管M2的源极连接到上拉节点PU。
第三晶体管M3的栅极与时钟端6连接，用于接收时钟信号CLK。M3的栅极经由电容器C与输出端8连接。
第四晶体管M4的栅极也连接到第二输入端2，漏极也连接到低电平端5，源极则连接到输出端8。
图3示出了移位寄存器电路200的信号时序图。图3中的一个时段为1/2个时钟周期。
首先，在时段①中，即上一级移位寄存器电路进行输出时，本级移位寄存器电路200的输入信号INPUT为高电平，第一晶体管M1开启对上拉节点PU预充电。
接下来，在时段②中，本级移位寄存器电路200的时钟信号CLK为高电平，第三晶体管M3开启，使得输出端8的输出信号OUTPUT为高电平。同时，由于自举效应，上拉节点PU的电位被再次升高。
然后，在时段③中，下一级移位寄存器电路输出的输出信号为高电平，即第二输入端2处接收的复位信号RESET为高电平，第二晶体管M2和第四晶体管M4开启，对上拉节点PU和输出端8进行放电从而复位。
栅极驱动电路100中的最后一级移位寄存器电路SR(N)不具有像素负载，从而其对上一级移位寄存器电路SR(N-1)产生的复位信号RESET的电压较大，会对SR(N-1)的性能造成不利的影响。
图4示出了根据本公开实施例的复位电路400的电路结构图。该复位电路400可以应用于各种移位寄存器电路，例如将接收到如上所述具有较大电压的复位信号RESET的移位寄存器电路，例如图3中的SR(N-1)，从而可控地降低实际施加到移位寄存器电路中元件(例如，图2中的第二晶体管M2)上的复位信号的电压值。
如图4所示，本公开实施例所提供的所述复位电路400包括第一调节控制电路410、第二调节控制电路420和存储电路430。
第一调节控制电路410的输入端经由接地输入端接收地线信号GND，控制端接收第一控制信号。
第二调节控制电路420的输入端经由调节信号输入端接收调节信号VNN，控制端接收第二控制信号，输出端与第一调节控制电路410的输出端相连。例如在图4所示的第一节点N1处相连。
存储电路430的第一端连接到所述第一节点N1，第二端连接在用于接收来自另一移位寄存器电路(复位电路400所位于的移位寄存器电路之后的某一级移位寄存器电路，比如，在每次开启一行像素的情形中是复位电路400所位于的移位寄存器电路的下一级移位寄存器电路)的复位信号RESET的复位信号输入端和复位电路400所位于的移位寄存器电路中用于接收复位输入的晶体管之间，例如图4所示的第二节点N2处。
在一个实施例中，第一控制信号与复位电路400所位于的移位寄存器电路的栅极驱动输入信号同相，并且第二控制信号与复位信号RESET同相。
在一个实施例中，第一控制信号是所述栅极驱动输入信号，并且第二控制信号是所述复位信号RESET。
在一个实施例中，调节信号VNN是恒定直流电平调节信号。在另一实施例中，可根 据需要改变调节信号VNN的电压，从而可控地降低实际施加到移位寄存器电路中关键元件上的复位信号的电压值。
图5示出了图4所示的复位电路400的更为详细的电路结构图。
从图5可见，第一调节控制电路410和第二调节控制电路420分别包括薄膜晶体管M41和M42。存储电路430包括电容器C43。
在一个实施例中，第一调节控制电路410的输入端是M41的源极和漏极中的一个，输出端是M41的源极和漏极中的另一个，控制端是M41的栅极。类似地，第二调节控制电路420的输入端是M42的源极和漏极中的一个，输出端是M42的源极和漏极中的另一个，控制端是M42的栅极。
图6示出了根据本公开实施例的移位寄存器电路600的电路结构图。所述移位寄存器电路600中包括图4(或图5)所示的复位电路400和移位寄存器电路(例如图2所示的移位寄存器电路200)的电路结构。应该理解的是，虽然在图6中将复位电路400与图2中的移位寄存器电路200进行了结合，但这只是示例性的，本公开并不对与复位电路400相结合的移位寄存器电路的具体结构进行限制，在其他实施例中，同样可以将复位电路400与其他类型的移位寄存器电路进行结合，以实现本公开所提出的能够降低施加到关键元件的复位信号的移位寄存器电路。此外，为了便于描述，图6中示出了复位电路400的更为详细的示例性电路结构。
在图6的电路结构中，通过复位电路400使得在第二输入端2处接收的复位信号RESET在第二节点N2处降低，从而改善了最终施加到第二晶体管M2上的复位信号对M2的不利影响。
图7示出了移位寄存器电路600的信号时序图。图7中的一个时段为1/2个时钟周期。以下结合图7描述图6所示的移位寄存器电路600的时序操作。
首先，在时段①中，作为一帧内移位寄存器电路600的工作时段的开始，输入信号INPUT为高电平。第一控制信号与INPUT同相，因此也为高电平。从而，晶体管M41开启，第一节点N1处的电压PN1＝0V。此时，移位寄存器电路600的时钟信号CLK为低电平，移位寄存器电路600接收的复位信号RESET也为低电平，从而晶体管M42关断。
接下来，在时段②中，移位寄存器电路600的时钟信号CLK为高电平，第三晶体管M3开启，使得输出端8的输出信号OUTPUT为高电平，这意味着，将要为移位寄存器电路600提供RESET信号的移位寄存器电路的输入为高电平。此时，移位寄存器电路600的输入信号INPUT不再为高电平，晶体管M41关断，第一节点N1处的电压PN1保持为0V。
然后，在时段③中，将要为移位寄存器电路600提供RESET信号的移位寄存器电路的输出为高电平，即第二输入端2处接收的复位信号RESET为高电平。由于第二控制信号与复位信号RESET同相，因此，其也为高电平，晶体管M42开启，第一节点N1处的电压PN1变为VNN的电压，例如1/4*Vgl，其中，Vgl是晶体管M42的栅极低电压。此时，通过电容器C43的作用，第二节点N2处的电压PN2不是Vreset，而是Vreset-VNN，即Vreset-1/4*Vgl，这使得N2节点电压降低。也就是说，施加到第二晶体管M2的栅极的电压与设置复位电路400之前相比降低了1/4*Vgl。从而，可以通过改变VNN的电压1/4*Vgl的大小来调节施加到第二晶体管M2的栅极上的电压。
图8示出了根据本公开实施例的栅极驱动电路800的级联图。为了与图1中的栅极驱动电路100的结构进行对比，与图1中类似地，每组移位寄存器电路中只包括单个移位寄存器电路，即同时只开启单个移位寄存器电路所对应的像素行。栅极驱动电路800与图1的栅极驱动电路100包括的差别在于将倒数第二级移位寄存器电路SR(N-1)实现为具有复位电路400的移位寄存器电路，例如，图7中的移位寄存器电路700。从而，移位寄存器电路SR(N-1)还接收GND和VNN，以实现复位电路400的功能。
应该理解的是，尽管图8中只是示出了每组包括单个移位寄存器电路的情形，但这只是示例性的，在其他实施例中，还可以在每组中包括连续的多级移位寄存器电路，从而可以同时开启一组中的多级移位寄存器电路所对应的多个像素行。此时，需要附加地设置一组同样数量的复位移位寄存器对作用到有效区域的最后一组移位寄存器进行复位，而为了降低施加到这一组移位寄存器上的复位电压，需要将该组中的每个移位寄存器电路都实现为具有复位电路400的移位寄存器电路。
一般地，对于包括N个级联的移位寄存器电路的栅极驱动电路来讲，如果其中每组移位寄存器电路包括K级移位寄存器电路，N和K为正整数，则所述N个级联移位寄存器电路中倒数第二组K个移位寄存器电路(即，第N-2K+1个到第N-K个)实现为具有复位电路400的移位寄存器电路。
作为示例，图9中示出了每组包括两级移位寄存器电路的栅极驱动电路的情形。图9中的栅极驱动电路包括N级移位寄存器电路，作为示例只示出了其中的最后6级，并通过虚线框示出了这最后6级移位寄存器电路分成3组，每组包括两级移位寄存器电路。
对于每一组移位寄存器电路(非最后一组)，该组中的第一级移位寄存器电路以上一组中第一级移位寄存器电路的输出OUTPUT作为输入INPUT，以下一组中第一级移位寄存器电路的输出OUTPUT作为复位输入RESET。类似地，该组中的第二级移位寄存器 电路以上一组中第二级移位寄存器电路的输出OUTPUT作为输入INPUT，以下一组中第二级移位寄存器电路的输出OUTPUT作为复位输入RESET。
最后一组移位寄存器电路SR(N-1)和SR(N)作为附加的复位移位寄存器不连接像素负载，其只用于对倒数第二组移位寄存器电路SR(N-2)和SR(N-3)进行复位。从而，倒数第二组移位寄存器电路SR(N-2)和SR(N-3)均实现为具有复位电路400(图4或图5)的移位寄存器电路，以降低施加到其中的关键元件(如，图2中的第二晶体管M2)上的复位电压。
再例如，图10中示出了每组包括三级移位寄存器电路的栅极驱动电路的情形。图10中的栅极驱动电路包括N级移位寄存器电路，作为示例只示出了其中的最后6级，并通过虚线框示出了这最后6级移位寄存器电路分成2组，每组包括三级移位寄存器电路。
对于每一组移位寄存器电路(非最后一组)，该组中的第一级移位寄存器电路以上一组中第一级移位寄存器电路的输出OUTPUT作为输入INPUT，以下一组中第一级移位寄存器电路的输出OUTPUT作为复位输入RESET。类似地，该组中的第二级移位寄存器电路以上一组中第二级移位寄存器电路的输出OUTPUT作为输入INPUT，以下一组中第二级移位寄存器电路的输出OUTPUT作为复位输入RESET，以及该组中的第三级移位寄存器电路以上一组中第三级移位寄存器电路的输出OUTPUT作为输入INPUT，以下一组中第三级移位寄存器电路的输出OUTPUT作为复位输入RESET。
最后一组移位寄存器电路SR(N-2)、SR(N-1)和SR(N)作为附加的复位移位寄存器不连接像素负载，其只用于对倒数第二组移位寄存器电路SR(N-5)、SR(N-4)和SR(N-3)进行复位。从而，倒数第二组移位寄存器电路SR(N-5)、SR(N-4)和SR(N-3)均实现为具有复位电路400(图4或图5)的移位寄存器电路，以降低施加到其中的关键元件(如，图2中的第二晶体管M2)上的复位电压。
图11示出了根据本公开实施例的复位电路(例如，图4和/或图5中所示的复位电路400)的驱动方法1100的流程图。作为示例，以下参考图5中的电路结构进行描述。
所述驱动方法1100包括以下步骤S1110-S1130：
在S1110中，在第一时段期间(例如图7中的时段①)，通过第一控制信号控制晶体管M41接通，以使得第一节点N1处的电压PN1为0V。
在S1120中，在第二时段期间(例如图7中的时段②)，通过第一控制信号控制晶体管M41关断。此时，第一节点N1处的电压PN1保持为0V。
在S1130中，在第三时段期间(例如图7中的时段③)，通过第二控制信号控制晶体管M42接通，使得第一节点N1处的电压PN1等于所述调节信号VNN的电压(例如 1/4*Vgl)。同时，在该时段中还通过复位信号输入端输入复位信号RESET，使得第二节点N2处的电压等于复位信号的电压Vreset减去调节信号的电压1/4*Vgl，即PN2＝Vreset-1/4*Vgl。
上面已经详细说明了本发明提供的复位电路、移位寄存器电路及栅极驱动电路。除此之外，本发明还提供包括上述栅极驱动器的显示装置。具体地，所述显示装置可以为液晶显示装置，例如液晶面板、液晶电视、手机、电子阅读器、液晶显示器等。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

  1. 一种针对移位寄存器电路的复位电路，包括：
    第一调节控制电路，具有输入端、输出端和控制端，其中第一调节控制电路的输入端经由接地输入端接收地线信号，控制端接收第一控制信号；
    第二调节控制电路，具有输入端、输出端和控制端，其中第二调节控制电路的输入端经由调节信号输入端接收调节信号，控制端接收第二控制信号，第二调节控制电路的输出端与所述第一调节控制电路的输出端相连；
    存储电路，具有第一端和第二端，其中存储电路的第一端连接到所述第一调节控制电路和第二调节控制电路的输出端，第二端连接在用于接收复位信号的复位信号输入端和所述移位寄存器电路的用于接收复位输入的晶体管之间。
  2. 根据权利要求1所述的复位电路，其中，所述第一调节控制电路和所述第二调节控制电路包括薄膜晶体管，以及所述存储电路包括电容器。
  3. 根据权利要求2所述的复位电路，其中，
    在所述第一调节控制电路中，输入端包括源极和漏极中的一个，输出端包括源极和漏极中的另一个，控制端包括栅极，以及
    在所述第二调节控制电路中，输入端包括源极和漏极中的一个，输出端包括源极和漏极中的另一个，控制端包括栅极。
  4. 根据权利要求1所述的复位电路，其中，所述第一控制信号与所述移位寄存器电路的栅极驱动输入信号同相，以及所述第二控制信号与所述复位信号同相。
  5. 根据权利要求4所述的复位电路，其中，所述第一控制信号包括所述栅极驱动输入信号，以及所述第二控制信号包括所述复位信号。
  6. 根据权利要求1所述的复位电路，其中，所述调节信号包括恒定直流电平调节信号。
  7. 根据权利要求1所述的复位电路，其中，所述复位信号输入端用于接收来自另一移位寄存器电路的复位信号。
  8. 一种移位寄存器电路，包括根据权利要求1-7中任一项所述的复位电路。
  9. 一种栅极驱动电路，包括级联的N个移位寄存器电路，其中，所述N个移位寄存器电路中的K个移位寄存器电路是根据权利要求8所述的移位寄存器电路，所述K个移位 寄存器电路是所述N个移位寄存器电路中第N-2K+1个到第N-K个移位寄存器电路，其中，K和N为正整数。
  10. 根据权利要求9所述的栅极驱动电路，其中，在所述K个移位寄存器电路中的每一个移位寄存器电路的复位电路中，所述复位信号输入端接收来自该移位寄存器电路之后第K级移位寄存器电路的复位信号。
  11. 一种显示装置，包括根据权利要求9或10所述的栅极驱动电路。
  12. 一种驱动方法，用于驱动根据权利要求1-7中的任一项所述的复位电路，其中所述存储电路的第一端与所述第一调节控制电路和第二调节控制电路的输出端在第一节点处相连，所述存储电路的第二端与第二节点相连，所述驱动方法包括：
    在第一时段期间，通过所述第一控制信号控制所述第一调节控制电路接通，以使得所述第一节点处的电压为零；
    在第二时段期间，通过所述第一控制信号控制所述第一调节控制电路关断；
    在第三时段期间，通过所述第二控制信号控制所述第二调节控制电路接通，使得所述第一节点处的电压等于所述调节信号的电压，同时通过所述复位信号输入端输入所述复位信号，使得所述第二节点处的电压等于所述复位信号的电压减去所述调节信号的电压。
  13. 根据权利要求12所述的驱动方法，所述第一时段、第二时段和第三时段分别等于1/2时钟周期。
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