WO2018150560A1 - 電子装置 - Google Patents

電子装置 Download PDF

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Publication number
WO2018150560A1
WO2018150560A1 PCT/JP2017/006031 JP2017006031W WO2018150560A1 WO 2018150560 A1 WO2018150560 A1 WO 2018150560A1 JP 2017006031 W JP2017006031 W JP 2017006031W WO 2018150560 A1 WO2018150560 A1 WO 2018150560A1
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WO
WIPO (PCT)
Prior art keywords
conductor layer
substrate
straight line
conductor
conductor layers
Prior art date
Application number
PCT/JP2017/006031
Other languages
English (en)
French (fr)
Inventor
宗一郎 梅田
雄司 森永
Original Assignee
新電元工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新電元工業株式会社 filed Critical 新電元工業株式会社
Priority to US15/753,527 priority Critical patent/US10615092B2/en
Priority to EP17838115.8A priority patent/EP3588547A4/en
Priority to KR1020187008211A priority patent/KR102005381B1/ko
Priority to CN201780003208.0A priority patent/CN108738366B/zh
Priority to PCT/JP2017/006031 priority patent/WO2018150560A1/ja
Priority to JP2017545985A priority patent/JP6325757B1/ja
Publication of WO2018150560A1 publication Critical patent/WO2018150560A1/ja

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Definitions

  • the present invention relates to an electronic device.
  • a semiconductor element which is an example of an electronic element
  • a conductor layer of a substrate is placed on a conductor layer of a substrate, and the surface of the semiconductor element and a terminal are connected to each other with a wire or a connector via solder, and the conductor layer, the semiconductor element
  • a semiconductor device which is an example of an electronic device that seals a wire, a connector, or the like with a sealing portion such as a sealing resin is known (see Japanese Patent Application Laid-Open No. 2014-195064). In such a semiconductor device, if the region where the conductor layer is not located on the substrate becomes long, the warpage of the substrate may increase.
  • the present invention provides an electronic device capable of preventing the substrate from warping.
  • An electronic device comprises: A substrate, A first conductor layer provided on the substrate; A second conductor layer provided on the substrate; An electronic element provided in the first conductor layer; A sealing portion that covers the substrate, the first conductor layer, the second conductor layer, and the electronic element; With In the in-plane direction of the substrate, the first conductor layer is not provided on a virtual line including the second conductor layer, The second conductor layer is enclosed in the sealing portion and covered only by the sealing portion.
  • a pair of second conductor layers are provided, A straight line connecting the pair of second conductor layers may match the virtual straight line.
  • One second conductor layer may be located at one end of the substrate, and the other second conductor layer may be located at the other end of the substrate.
  • the plurality of first conductor layers may be arranged symmetrically with respect to the virtual straight line.
  • a plurality of second conductor layers are provided; One virtual straight line and another virtual straight line are provided in parallel, The second conductor layer on the certain virtual line may be provided on one side, and the second conductor layer on the other virtual line may be provided on the other side.
  • a plurality of second conductor layers are provided;
  • the second conductor layers on a virtual straight line along the longitudinal direction of the substrate are provided in pairs,
  • the second conductor layer on the imaginary straight line along the short direction of the substrate may not form a pair.
  • a dummy second conductor layer is provided on a virtual straight line on which the first conductor layer is not provided.
  • FIG. 1 is a perspective view of a semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a perspective view showing an aspect in which the sealing portion is removed in the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is a plan view showing an aspect in which the sealing portion is removed in the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a plan view showing the positional relationship of the conductor layers in the semiconductor device according to the second embodiment of the present invention.
  • FIG. 5 is a plan view showing the positional relationship of the conductor layers in the semiconductor device according to Modification 1 of the second embodiment of the present invention.
  • FIG. 6 is a plan view showing the positional relationship of conductor layers in a semiconductor device according to Modification 2 of the second embodiment of the present invention.
  • FIG. 7 is a plan view showing the positional relationship of conductor layers in a semiconductor device according to Modification 3 of the second embodiment of the present invention.
  • the semiconductor device which is an example of the electronic device of the present embodiment includes a sealing portion 90 (see FIG. 1) made of a sealing resin and the like, and outward from the first side surface of the sealing portion 90.
  • the first main terminal 11 projecting into the sealing portion 90 and a semiconductor element 95 which is an example of an electronic element provided in the sealing portion 90 may be included.
  • a semiconductor device is used as an electronic device and a semiconductor element 95 is used as an electronic element.
  • the present invention is not limited to this, and the semiconductor device is not necessarily “semiconductor”.
  • the semiconductor device of the present embodiment has a second main terminal 12 that protrudes outward from the sealing portion 90 and through which a main current flows.
  • the semiconductor element 95 shown in FIG. 2 has a front surface electrically connected to the first main terminal 11 and a back surface electrically connected to the second main terminal 12.
  • the semiconductor device may include a substrate 5 made of, for example, an insulating material, and a conductor layer 70 provided on the substrate 5 and made of copper or the like.
  • the conductor layer 70 may include a first conductor layer 71, a second conductor layer 72, and a third conductor layer 73.
  • a semiconductor element 95 is provided in a part of the first conductor layer 71, a wire 19 is provided in another part of the first conductor layer 71, and a semiconductor element is provided in the second conductor layer 72 and the third conductor layer 73. 95 may not be provided.
  • the 3rd conductor layer 73 may correspond to the part pressed when pressing with a metal mold
  • the sealing unit 90 may cover the substrate 5, the first conductor layer 71, the second conductor layer 72, and the semiconductor element 95.
  • the substrate 5 a ceramic substrate, a resin substrate, or the like can be used.
  • a (thin) metal substrate which is a conductive material can also be used.
  • the first conductor layer 71 is not provided on the virtual line VL including the second conductor layer 72 in the in-plane direction of the substrate 5 (including the paper surface of FIG. 3). It may be completely enclosed in the sealing portion 90 and covered only by the sealing portion 90.
  • the second conductor layer 72 is a dummy conductor layer, and the semiconductor element 95 is not placed on the second conductor layer 72, and the wire 19 is not connected and is covered only by the sealing portion 90. If a straight line including the second conductor layer 72 is drawn in the in-plane direction of the substrate 5 and the first conductor layer 71 is not provided on the straight line, “the in-plane direction of the substrate 5 and the second conductor layer 72 The first conductor layer 71 is not provided on the virtual straight line VL including “.
  • a pair of second conductor layers 72 may be provided, and a straight line connecting the pair of second conductor layers 72 may match the virtual straight line VL.
  • a straight line connecting the centers of the pair of second conductor layers 72 matches the virtual straight line VL.
  • one second conductor layer 72 may be located at one end of the substrate 5, and the center of the other second conductor layer 72 may be located at the other end of the substrate 5.
  • the “end” means that the length of the substrate 5 along the virtual straight line VL is located within one tenth of the periphery.
  • the pair of first main terminals 11 may be arranged symmetrically with respect to the virtual straight line VL.
  • the pair of second main terminals 12 may be arranged symmetrically with respect to the virtual straight line VL.
  • the distance between the pair of first main terminals 11 is shorter than the distance between the pair of second main terminals 12, and one of the second conductor layers 72 is located between the first main terminals 11. Another one of the second conductor layers 72 may be located between the second main terminals 12.
  • the width of the second conductor layer 72 located between the first main terminals 11 may be longer than the width of the second conductor layer 72 located between the second main terminals 12.
  • the distance between the pair of first main terminals 11 is longer than the distance between the pair of second main terminals 12, and the width of the second conductor layer 72 located between the first main terminals 11 is:
  • the width may be shorter than the width of the second conductor layer 72 located between the second main terminals 12.
  • the “width” may be a length in a direction orthogonal to the virtual straight line VL, or may be a length in a direction along the virtual straight line VL.
  • the plurality of first conductor layers 71 may be all or partly arranged symmetrically with the virtual straight line VL.
  • Two or all (three) of the first conductor layer 71, the second conductor layer 72, and the third conductor layer 73 may be created by the same manufacturing method. Two or all (three) of the thicknesses of the first conductor layer 71, the second conductor layer 72, and the third conductor layer 73 may correspond to each other.
  • “corresponding” means that the thickness of any conductor layer is within a range of ⁇ 5% of the average thickness of the target conductor layer.
  • the thickness of the second conductor layer 72 may be made larger than the thickness of the first conductor layer 71 so that the warp of the substrate 5 can be surely prevented, and conversely, the thickness of the second conductor layer 72 that is a dummy. May be made thinner than the thickness of the first conductor layer 71.
  • the second main terminal 12 is connected to the first conductor layer 71, and the second main terminal 12 is connected to the back surface of the semiconductor element 95 via the first conductor layer 71.
  • a resist (not shown) for preventing the conductive adhesive such as solder from flowing out may be provided at the periphery of the connection portion of the second main terminal 12 with the first conductor layer 71.
  • the first main terminal 11 and the second main terminal 12 may be power terminals through which a large capacity current of about 200 A to 300 A flows.
  • the second main terminal 12 and the control terminal 15 protrude from the outside from one side surface of the sealing portion 90, and the first main terminal 11 is outside from the other side surface of the sealing portion 90. It protrudes toward.
  • the first main terminal 11, the second main terminal 12, and the control terminal 15 are bent to the front surface side, and are connected to a control board provided on the front surface side. This control board is used to control the semiconductor element 95.
  • the structure in the sealing portion 90 of the semiconductor device may be line symmetric.
  • each of the first main terminal 11, the second main terminal 12, and the conductor layer 70 (the first conductor layer 71, the second conductor layer 72, and the third conductor layer 73) is connected to the virtual straight line VL.
  • VL virtual straight line
  • the dummy second conductor layer 72 is provided on the virtual straight line VL where the first conductor layer 71 is not provided.
  • the position close to the periphery is adopted.
  • the second conductor layer 72 can be positioned, and thus the warpage of the substrate 5 can be prevented more reliably. Further, when the second conductor layer 72 is provided at the center in the in-plane direction of the substrate 5, there may be an obstacle to providing other members. It is also beneficial in that it can be prevented as much as possible.
  • the first conductor layer 71 When all or some of the plurality of first conductor layers 71 are arranged in line symmetry with the virtual straight line VL, the first conductor layer 71 is often not provided on a certain virtual straight line. For this reason, the substrate 5 may be warped. For this reason, it is beneficial to provide the second conductor layer 72 as in the present embodiment.
  • the second conductor layer 72 In particular, when all of the plurality of first conductor layers 71 are arranged in line symmetry with the virtual straight line VL, there is a very high possibility that the first conductor layer 71 is not provided on a certain virtual straight line. For this reason, possibility that the curvature of the board
  • a plurality of pairs of second conductor layers 72 are provided.
  • the aspect which is provided and / or the aspect in which the 2nd conductor layer 72 which is not paired is provided is demonstrated.
  • two virtual straight lines VL along the short direction can be drawn, and one virtual straight line VL along the longitudinal direction can be drawn.
  • a pair of second conductor layers 72 are provided on each virtual straight line VL. Further, each of the second conductor layers 72 is positioned at the end of the substrate 5. Thus, providing three or more second conductor layers 72 is advantageous in that the substrate 5 can be more reliably prevented from warping. In the embodiment shown in FIG. 4, the third conductor layer 73 is not provided.
  • the widths of the second conductor layers 72 may be different from each other. As an example, as shown in FIG. 4, the width of the second conductor layer 72 positioned on the virtual straight line VL1 in the longitudinal direction is longer than the width of the second conductor layer 72 positioned on the virtual straight line VL2 in the short-side direction. It may be.
  • the thickness of the second conductor layer 72 may be different from each other.
  • the thickness of the second conductor layer 72 positioned on the virtual straight line VL1 in the longitudinal direction may be thicker than the thickness of the second conductor layer 72 positioned on the virtual straight line VL2 in the short-side direction.
  • the second conductor layers 72 on the virtual straight line VL1 along the longitudinal direction of the substrate 5 are provided in pairs, but the second conductor layer 72 on the virtual straight line VL2 in the short direction of the substrate 5 is provided.
  • the conductor layer 72 may not form a pair. Since the warpage of the substrate 5 tends to increase in the longitudinal direction, it is beneficial to employ such an aspect in that the warpage of the substrate 5 can be prevented as much as possible while reducing the number of dummy second conductor layers 72. It is.
  • a virtual line VL and another virtual line VL are provided in parallel, the second conductor layer 72 on one virtual line VL is provided on one side, and the second conductor layer 72 on another virtual line VL is provided on the other side. May be provided.
  • the second conductor layer 72 can be positioned in both directions. This is beneficial in that it can prevent warping as much as possible.
  • the second conductor layer 72 positioned on the imaginary straight line VL2 on the left side in FIG. 6 is provided at the lower end of FIG.
  • the second conductor layer 72 positioned on the straight line VL2 is provided at the upper end of FIG.
  • the second conductor layers 72 may be alternately arranged on one side and the other side.
  • the second conductor layer 72 can be positioned in a balanced manner in both directions. This is advantageous in that the warpage of 5 can be prevented as much as possible.
  • the second conductor layer 72 positioned on the phantom straight line VL2 on the left side of FIG. 7 is provided at the lower end of FIG.
  • the second conductor layer 72 positioned on the straight line VL2 is provided at the upper end of FIG. 7, and the second conductor layer 72 positioned on the virtual straight line VL2 on the right side of FIG. Provided in the department.

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Abstract

電子装置は、基板５と、前記基板５上に設けられた複数の第一導体層７１と、前記基板５上に設けられた第二導体層７２と、前記第一導体層７１に設けられた電子素子９５と、前記基板５、前記第一導体層７１、前記第二導体層７２及び前記電子素子９５を覆う封止部９０と、を有している。前記基板５の面内方向であって、前記第二導体層７２を含む仮想直線ＶＬ上に前記第一導体層７１が設けられていない。前記第二導体層７２は、前記封止部９０内に封入されるとともに前記封止部９０のみによって覆われている。

Description

電子装置
　本発明は、電子装置に関する。
　従来から、電子素子の一例である半導体素子を基板の導体層上に載置し、当該半導体素子の表面と端子とをはんだを介してワイヤや接続子で接続し、これら導体層、半導体素子、ワイヤ、接続子等を封止樹脂等の封止部で封止する電子装置の一例である半導体装置が知られている（特開２０１４－１９５０６４号参照）。このような半導体装置において、基板上で導体層が位置していない領域が長くなると、基板の反りが大きくなってしまうことがある。
　このような点に鑑み、本発明は、基板の反りが大きくなることを防止できる電子装置を提供する。
　本発明による電子装置は、
　基板と、
　前記基板上に設けられた第一導体層と、
　前記基板上に設けられた第二導体層と、
　前記第一導体層に設けられた電子素子と、
　前記基板、前記第一導体層、前記第二導体層及び前記電子素子を覆う封止部と、
　を備え、
　前記基板の面内方向であって、前記第二導体層を含む仮想直線上に前記第一導体層が設けられておらず、
　前記第二導体層は、前記封止部内に封入されるとともに前記封止部のみによって覆われている。
　本発明による電子装置において、
　一対の第二導体層が設けられ、
　前記一対の第二導体層を結ぶ直線が前記仮想直線に合致してもよい。
　本発明による電子装置において、
　一方の第二導体層は前記基板の一方の端部に位置し、他方の第二導体層は前記基板の他方の端部に位置してもよい。
　本発明による電子装置において、
　前記複数の第一導体層は、前記仮想直線に対して線対称に配置されてもよい。
　本発明による電子装置において、
　複数の第二導体層が設けられ、
　ある仮想直線と別の仮想直線とが平行に設けられ、
　前記ある仮想直線上の第二導体層が一方側に設けられ、前記別の仮想直線上の第二導体層が他方側に設けられてもよい。
　本発明による電子装置において、
　複数の第二導体層が設けられ、
　前記基板の長手方向に沿った仮想直線上の前記第二導体層は対をなして設けられ、
　前記基板の短手方向に沿った仮想直線上の前記第二導体層は対を形成していなくてもよい。
　本発明では、第一導体層が設けられない仮想直線上にダミーの第二導体層を設ける。このような第二導体層を設けることで、基板の反りが大きくなることを防止できる。
図１は、本発明の第１の実施の形態による半導体装置の斜視図である。 図２は、本発明の第１の実施の形態による半導体装置において、封止部を除去した態様を示した斜視図である。 図３は、本発明の第１の実施の形態による半導体装置において、封止部を除去した態様を示した平面図である。 図４は、本発明の第２の実施の形態による半導体装置において、導体層の位置関係を示した平面図である。 図５は、本発明の第２の実施の形態の変形例１による半導体装置において、導体層の位置関係を示した平面図である。 図６は、本発明の第２の実施の形態の変形例２による半導体装置において、導体層の位置関係を示した平面図である。 図７は、本発明の第２の実施の形態の変形例３による半導体装置において、導体層の位置関係を示した平面図である。
第１の実施の形態
《構成》
　図２に示すように、本実施の形態の電子装置の一例である半導体装置は、封止樹脂等からなる封止部９０（図１参照）と、封止部９０の第一側面から外方に突出する第一主端子１１と、封止部９０内に設けられた電子素子の一例である半導体素子９５と、を有してもよい。
　本実施の形態では、電子装置として半導体装置を用い、電子素子として半導体素子９５を用いて説明するが、これに限られるものではなく、特に「半導体」である必要はない。
　本実施の形態の半導体装置は、封止部９０から外方に突出するとともに、主電流が流れる第二主端子１２も有している。図２に示す半導体素子９５は、第一主端子１１におもて面が電気的に接続され、第二主端子１２に裏面が電気的に接続されている。
　図２に示すように、半導体装置は、例えば絶縁性材料からなる基板５と、基板５に設けられ、銅等からなる導体層７０と、を有してもよい。導体層７０は、第一導体層７１、第二導体層７２及び第三導体層７３を有してもよい。第一導体層７１の一部には半導体素子９５が設けられ、第一導体層７１の別の一部にはワイヤ１９が設けられ、第二導体層７２及び第三導体層７３には半導体素子９５が設けられなくてもよい。第三導体層７３は、金型で押圧する際に押圧される部分に該当してもよい。このように金型で第三導体層７３が押圧される場合には、当該第三導体層７３は、封止部９０の外部に位置されてもよい（図３参照）。また、封止部９０は、基板５、第一導体層７１、第二導体層７２及び半導体素子９５を覆ってもよい。基板５としては、セラミック基板及び樹脂基板等を用いることもできる。また、導電材料ではあるが（薄い）金属基板を用いることもできる。
　基板５の面内方向（図３の紙面を含む方向）であって、第二導体層７２を含む仮想直線ＶＬ上に第一導体層７１が設けられておらず、第二導体層７２は、封止部９０内に完全に封入されるとともに封止部９０のみによって覆われてもよい。この第二導体層７２はダミーの導体層であり、第二導体層７２には半導体素子９５も載置されないし、ワイヤ１９も接続されず、封止部９０のみによって覆われることになる。第二導体層７２を含む直線を基板５の面内方向で引き、その直線上に第一導体層７１が設けられていなければ、「基板５の面内方向であって、第二導体層７２を含む仮想直線ＶＬ上に第一導体層７１が設けられて」いないことになる。
　また、一対の第二導体層７２が設けられ、一対の第二導体層７２を結ぶ直線が仮想直線ＶＬに合致するようになっていてもよい。図３に示す態様では、一対の第二導体層７２の中心を結ぶ直線が仮想直線ＶＬに合致するようになっている。３つ以上の第二導体層７２が複数設けられている場合には、２つの第二導体層７２を適宜選択することで、一対の第二導体層７２を構成するようにしてもよい（第２の実施の形態の図４及び図５参照）。
　また、一方の第二導体層７２は基板５の一方の端部に位置し、他方の第二導体層７２の中心は基板５の他方の端部に位置してもよい。ここで「端部」とは、仮想直線ＶＬに沿った基板５の長さにおいて、周縁から１０分の１以内に位置することを意味する。
　図３に示すように、一対の第一主端子１１が、仮想直線ＶＬに対して線対称に配置されてもよい。また、一対の第二主端子１２が、仮想直線ＶＬに対して線対称に配置されてもよい。そして、一対の第一主端子１１の間の距離が一対の第二主端子１２の間の距離よりも短くなっており、第一主端子１１の間に第二導体層７２の一つが位置し、第二主端子１２の間に第二導体層７２の別の一つが位置してもよい。この場合、第一主端子１１の間に位置する第二導体層７２の幅は、第二主端子１２の間に位置する第二導体層７２の幅よりも長くなってもよい。逆に、一対の第一主端子１１の間の距離が一対の第二主端子１２の間の距離よりも長くなり、第一主端子１１の間に位置する第二導体層７２の幅は、第二主端子１２の間に位置する第二導体層７２の幅よりも短くなってもよい。なお、この「幅」は、仮想直線ＶＬに直交する方向の長さであってもよいし、仮想直線ＶＬに沿った方向の長さであってもよい。
　複数の第一導体層７１は、その全部又は一部が仮想直線ＶＬと線対称に配置されてもよい。
　第一導体層７１、第二導体層７２及び第三導体層７３のうちの２つ又はその全部（３つ）は同じ製造方法で作成されてもよい。第一導体層７１の厚み、第二導体層７２の厚み及び第三導体層７３の厚みのうちの２つ又はその全部（３つ）は対応していてもよい。ここで「対応」するとは、対象となる導体層の厚みの平均値の±５％の範囲内にいずれの導体層の厚みも入っていることを意味する。また、第二導体層７２の厚みを第一導体層７１の厚みより厚くして基板５の反りを確実に防止できるようにしてもよいし、逆に、ダミーである第二導体層７２の厚みを第一導体層７１の厚みより薄くしてもよい。
　図２に示す態様では、第一導体層７１に第二主端子１２が接続され、第二主端子１２は半導体素子９５の裏面と第一導体層７１を介して接続されている。第二主端子１２の第一導体層７１との接続箇所の周縁には、はんだ等の導電性接着剤が流れ出るのを防止するためのレジスト（図示せず）が設けられてもよい。
　第一主端子１１及び第二主端子１２は、２００Ａ～３００Ａ程の大容量の電流が流れるパワー端子であってもよい。
　図１に示す態様では、封止部９０の一方側の側面から、第二主端子１２及び制御端子１５が外方から突出し、封止部９０の他方側の側面から第一主端子１１が外方に突出している。これら第一主端子１１、第二主端子１２及び制御端子１５はおもて面側に曲げられ、おもて面側に設けられた制御基板と接続されるようになっている。この制御基板は、半導体素子９５を制御するために用いられるものである。
　半導体装置の封止部９０内の構造は線対称となっていてもよい。図３に示す態様では、第一主端子１１、第二主端子１２及び導体層７０（第一導体層７１、第二導体層７２及び第三導体層７３）の各々が、仮想直線ＶＬに対して線対称となるようにして配置されている。
《作用・効果》
　次に、上述した構成からなる本実施の形態による作用・効果について説明する。なお、「作用・効果」で説明した構成も、適宜採用することができる。
　本実施の形態によれば、図３に示すように、第一導体層７１が設けられない仮想直線ＶＬ上にダミーの第二導体層７２を設ける。このような第二導体層７２を設けることで、基板５の反りが大きくなることを防止できる。
　図３に示すように、一対の第二導体層７２が設けられ、一対の第二導体層７２を結ぶ直線が仮想直線ＶＬに合致するようになっている態様を採用した場合には、仮想直線ＶＬ上に少なくとも２つの第二導体層７２を設けることができる。このため、基板５の反りをより確実に防止できる。
　一方の第二導体層７２が基板５の一方の端部に位置し、他方の第二導体層７２が基板５の他方の端部に位置する態様を採用した場合には、周縁に近い位置に第二導体層７２を位置付けることができ、このため、基板５の反りをより確実に防止できる。また、第二導体層７２を基板５の面内方向における中心部に設けた場合には他の部材を設ける障害になることがあるが、基板５の端部に設けることでこのような事態が発生することを極力防止できる点でも有益である。
　複数の第一導体層７１の全部又は一部が仮想直線ＶＬと線対称に配置されている場合には、ある仮想直線上に第一導体層７１が設けられていないことが多い。このため、基板５に反りが発生することがある。このため、本実施の形態のような第二導体層７２を設けることは有益である。特に、複数の第一導体層７１の全部が仮想直線ＶＬと線対称に配置されている場合には、ある仮想直線上に第一導体層７１が設けられていない可能性が極めて高い。このため、基板５の反りが問題となる可能性が高くなる。したがって、このような態様において、本実施の形態のような第二導体層７２を設けることは非常に有益である。
第２の実施の形態
　次に、本発明の第２の実施の形態について説明する。
　第１の実施の形態では、１つの一対の第二導体層７２が設けられている態様を用いて説明したが、第２の実施の形態では、複数の一対の第二導体層７２が設けられている態様、及び／又は、対にならない第二導体層７２が設けられている態様を用いて説明する。
　その他の構成は、第１の実施の形態と同様である。第２の実施の形態において、第１の実施の形態と同じ又は同様の部材等については同じ符号を付し、その説明を省略する。本実施の形態でも、第１の実施の形態によって実現される効果と同様の効果を得ることができる。
　図４及び図５に示す態様では、短手方向に沿った２つの仮想直線ＶＬを引くことができ、長手方向に沿った１つの仮想直線ＶＬを引くことができる。そして、仮想直線ＶＬの各々に、一対の第二導体層７２が設けられている。また、第二導体層７２の各々は、基板５の端部に位置づけられている。このように、３つ以上の第二導体層７２を設けることが、より確実に基板５が反ることを防止できる点で有益である。なお、図４に示す態様では、第三導体層７３が設けられていない。
　また、第二導体層７２の幅が互いに異なっていてもよい。一例としては、図４に示すように、長手方向の仮想直線ＶＬ１に位置づけられる第二導体層７２の幅は、短手方向の仮想直線ＶＬ２に位置づけられる第二導体層７２の幅よりも長くなっていてもよい。
　また、第二導体層７２の厚みが互いに異なっていてもよい。一例としては、長手方向の仮想直線ＶＬ１に位置づけられる第二導体層７２の厚みは、短手方向の仮想直線ＶＬ２に位置づけられる第二導体層７２の厚みよりも厚くなっていてもよい。
　図６に示すように、基板５の長手方向に沿った仮想直線ＶＬ１上の第二導体層７２は対をなして設けられているが、基板５の短手方向の仮想直線ＶＬ２上の第二導体層７２は対を形成していなくてもよい。長手方向では基板５の反りが大きくなる傾向にあるので、このような態様を採用することは、ダミーである第二導体層７２の数を減らしつつ、基板５の反りを極力防止できる点で有益である。
　ある仮想直線ＶＬと別の仮想直線ＶＬとが平行に設けられ、ある仮想直線ＶＬ上の第二導体層７２が一方側に設けられ、別の仮想直線ＶＬ上の第二導体層７２が他方側に設けられてもよい。このような態様を採用することで、スペース等の問題で異なる仮想直線ＶＬ２に第二導体層７２が設けられる場合であっても、両方向に第二導体層７２を位置付けることができ、基板５の反りを極力防止できる点で有益である。図６に示す態様では、図６の左側の短手方向の仮想直線ＶＬ２に位置づけられる第二導体層７２は図６の下側の端部に設けられ、図６の右側の短手方向の仮想直線ＶＬ２に位置づけられる第二導体層７２は図６の上側の端部に設けられている。
　また、３つ以上の仮想直線ＶＬが平行に設けられる態様では、第二導体層７２は一方側と他方側で交互に配置されるようにしてもよい。このような態様を採用することで、スペース等の問題で異なる仮想直線ＶＬ２に第二導体層７２が設けられる場合であっても、両方向に第二導体層７２をバランスよく位置付けることができ、基板５の反りを極力防止できる点で有益である。図７に示す態様では、図７の左側の短手方向の仮想直線ＶＬ２に位置づけられる第二導体層７２は図７の下側の端部に設けられ、図７の中央の短手方向の仮想直線ＶＬ２に位置づけられる第二導体層７２は図７の上側の端部に設けられ、図７の右側の短手方向の仮想直線ＶＬ２に位置づけられる第二導体層７２は図７の下側の端部に設けられている。
　最後になったが、上述した各実施の形態の記載、変形例の記載及び図面の開示は、請求の範囲に記載された発明を説明するための一例に過ぎず、上述した実施の形態の記載又は図面の開示によって請求の範囲に記載された発明が限定されることはない。また、出願当初の請求項の記載はあくまでも一例であり、明細書、図面等の記載に基づき、請求項の記載を適宜変更することもできる。
５　　　　　基板
１１　　　　第一主端子
１２　　　　第二主端子
７１　　　　第一導体層
７２　　　　第二導体層
７３　　　　第三導体層
９０　　　　封止部
９５　　　　半導体素子（電子素子）
ＶＬ　　　　仮想直線
 

Claims (6)

  1. 　基板と、
    　前記基板上に設けられた第一導体層と、
    　前記基板上に設けられた第二導体層と、
    　前記第一導体層に設けられた電子素子と、
    　前記基板、前記第一導体層、前記第二導体層及び前記電子素子を覆う封止部と、
    　を備え、
    　前記基板の面内方向であって、前記第二導体層を含む仮想直線上に前記第一導体層が設けられておらず、
    　前記第二導体層は、前記封止部内に封入されるとともに前記封止部のみによって覆われていることを特徴とする電子装置。
  2. 　一対の第二導体層が設けられ、
    　前記一対の第二導体層を結ぶ直線が前記仮想直線に合致することを特徴とする請求項１に記載の電子装置。
  3. 　一方の第二導体層は前記基板の一方の端部に位置し、他方の第二導体層は前記基板の他方の端部に位置することを特徴とする請求項２に記載の電子装置。
  4. 　前記複数の第一導体層は、前記仮想直線に対して線対称に配置されていることを特徴とする請求項１乃至３のいずれか１項に記載の電子装置。
  5. 　複数の第二導体層が設けられ、
    　ある仮想直線と別の仮想直線とが平行に設けられ、
    　前記ある仮想直線上の第二導体層が一方側に設けられ、前記別の仮想直線上の第二導体層が他方側に設けられることを特徴とする請求項１乃至４のいずれか１項に記載の電子装置。
  6. 　複数の第二導体層が設けられ、
    　前記基板の長手方向に沿った仮想直線上の前記第二導体層は対をなして設けられ、
    　前記基板の短手方向に沿った仮想直線上の前記第二導体層は対を形成していないことを特徴とする請求項１乃至５のいずれか１項に記載の電子装置。
PCT/JP2017/006031 2017-02-20 2017-02-20 電子装置 WO2018150560A1 (ja)

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KR1020187008211A KR102005381B1 (ko) 2017-02-20 2017-02-20 전자 장치
CN201780003208.0A CN108738366B (zh) 2017-02-20 2017-02-20 电子装置
PCT/JP2017/006031 WO2018150560A1 (ja) 2017-02-20 2017-02-20 電子装置
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CN108738366A (zh) 2018-11-02
JPWO2018150560A1 (ja) 2019-02-21
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US10615092B2 (en) 2020-04-07

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