CN108738366A - 电子装置 - Google Patents

电子装置 Download PDF

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Publication number
CN108738366A
CN108738366A CN201780003208.0A CN201780003208A CN108738366A CN 108738366 A CN108738366 A CN 108738366A CN 201780003208 A CN201780003208 A CN 201780003208A CN 108738366 A CN108738366 A CN 108738366A
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conductor layer
substrate
imaginary line
electronic device
conductor
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CN108738366B (zh
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梅田宗郎
梅田宗一郎
森永雄司
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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Abstract

本发明的电子装置包括：基板5；配置在基板5上的第一导体层71；配置在基板5上的第二导体层72；配置在第一导体层71上的电子元件95；以及将基板5、第一导体层71、第二导体层72、以及电子元件95覆盖的封装部90，其中，在基板5的面内方向，即包含第二导体层72的假想直线VL上未配置有第一导体层71，第二导体层72在被封入封装部90内的同时仅被封装部90所覆盖。

Description

电子装置
技术领域
本发明涉及电子装置。
背景技术
以往，将作为电子元件的半导体元件载置在基板的导体层上，并通过焊锡等将该半导体元件的表面与端子利用焊线或连接件来连接，再将这些导体层、半导体元件、焊线、连接件等通过封装树脂等封装部进行封装，这样的电子装置作为半导体装置中的一个例子已被普遍认知(参照特开2014-195064号)。在这种半导体装置中，一旦基板上未配置有导体层的区域的变长的话，就可能会导致基板的翘曲幅度变大。
鉴于上述问题，本发明的目的，是提供一种能够防止基板的翘曲幅度变大的电子装置。
发明内容
本发明所涉及的电子装置，包括：
基板；
配置在所述基板上的第一导体层；
配置在所述基板上的第二导体层；
配置在所述第一导体层上的电子元件；以及
将所述基板、所述第一导体层、所述第二导体层、以及所述电子元件覆盖的封装部，
其中，在所述基板的面内方向(In-plane direction)上的，包含所述第二导体层的假想直线上未配置有所述第一导体层，
所述第二导体层在被封入所述封装部内的同时仅被所述封装部所覆盖。
在本发明所涉及的电子装置中，可以是：
配置有一对第二导体层，
连接所述一对第二导体层的直线与所述假想直线相吻合。
在本发明所涉及的电子装置中，可以是：
一方的第二导体层位于所述基板的一方的端部，另一方的第二导体层位于所述基板的另一方的端部。
在本发明所涉及的电子装置中，可以是：
所述多个第一导体层相对于所述假想直线呈线对称配置。
在本发明所涉及的电子装置中，可以是：
配置有多个第二导体层，
某假想直线与别的假想直线平行配置，
所述某假想直线上的第二导体层配置在一侧，所述别的假想直线上的第二导体层配置在另一侧。
在本发明所涉及的电子装置中，可以是：
配置有多个第二导体层，
沿所述基板的长度方向的假想直线上的所述第二导体层成对配置，
沿所述基板的宽度方向的假想直线上的所述第二导体层未形成对。
发明效果
在本发明中，在未配置第一导体层的假想直线上配置虚设(Dummy)的第二导体层。通过配置这样的第二导体层，就能够防止基板的翘曲幅度变大。
简单附图说明
图1是本发明的第一实施方式涉及的半导体装置的斜视图。
图2是展示本发明的第一实施方式涉及的半导体装置中将封装部去除后的形态的斜视图。
图3是展示本发明的第一实施方式涉及的半导体装置中将封装部去除后的形态的平面图。
图4是展示本发明的第二实施方式涉及的半导体装置中导体层位置关系的平面图。
图5是展示本发明的第二实施方式的变形例一涉及的半导体装置中导体层位置关系的平面图。
图6是展示本发明的第二实施方式的变形例二涉及的半导体装置中导体层位置关系的平面图。
图7是展示本发明的第二实施方式的变形例三涉及的半导体装置中导体层位置关系的平面图。
具体实施方式
第一实施方式
《构成》
如图2所示，作为本实施方式的电子装置的一例的半导体装置，可以包括：由封装树脂构成的封装部90(参照图1)；从封装部90的第一侧面向外部突出的第一主端子11；以及配置在封装部90内的作为一例电子元件的半导体元件95。
在本实施方式中，虽然使用半导体装置来作为电子装置，并且使用半导体元件95来作为电子元件进行说明，但并不仅限于此，特别是，没有必要限定为“半导体”。
本实施方式的半导体装置还具有从封装部90向外部突出的同时，流通主电流的第二主端子12。图2中所示的半导体元件95的正面与第一主端子11电气连接，背面与第二主端子12电气连接。
如图2所示，半导体装置可以具有：例如由绝缘材料构成的基板5、以及配置在基板5上的，由铜等构成的导体层70。导体层70可以具有第一导体层71、第二导体层72、以及第三导体层73。可以在第一导体层71的一部分上配置有半导体元件95，在第一导体层71的另一部分上配置有金属线(Wire)19，并且在第二导体层72以及第三导体层73上不配置有半导体元件95。第三导体层73可以作为通过模具按压时被按压的那一部分。在通过模具来按压第三导体层73时，该第三导体层73也可以位于封装部90的外部(参照图3)。另外，封装部90也可以覆盖基板5、第一导体层71、第二导体层72、以及半导体元件95。可以采用陶瓷基板以及树脂基板等来作为基板5。另外，虽然是属于导电材料，但也可以使用(薄的)金属基板。
可以在基板5的面内方向(包含图3纸面的方向)上的，包含第二导体层72的假想直线VL上未配置有第一导体层71,并且第二导体层72在被完全封入封装部90内的同时仅被封装部90所覆盖。该第二导体层72为虚设的导体层，第二导体层72上即未载置有半导体元件95，又未连接有金属线19，其仅被封装部90所覆盖。在基板5的面内方向上划一条包含第二导体层72的直线，只要在该直线上未配置有第一导体层71的话，则表示“在基板5的面内方向上的，包含第二导体层72的假想直线VL上未配置有第一导体层71”。
另外，也可以配置有一对第二导体层72，连接一对第二导体层72的直线与假想直线VL相吻合。在图3所示的形态中，连接一对第二导体层72的中心的直线与假想直线VL相吻合。当配置有三个一级以上的第二导体层72时，可以通过适宜地选取其中的两个第二导体层72来构成一对第二导体层72(参照图4以及图5中的第二实施方式)。
另外，可以是一方的第二导体层72位于基板5的一方的端部，另一方的第二导体层72的中心位于基板5的另一方的端部。这里的“端部”是指沿假想直线VL的基板5的长度上位于从周缘直到长度的十分之一的位置上。
如图3所示，可以是一对第一导体层11相对于假想直线VL呈线对称配置，并且一对第二主端子12相对于假想直线VL呈线对称配置。另外，也可以是一对第一主端子11之间的距离比一对第二主端子12之间的距离更短，第二导体层72中的一个位于第一主端子11之间，第二导体层72中的另一个位于第二主端子12之间。此情况下，位于第一主端子11之间的第二导体层72的宽度可以比位于第二主端子12之间的第二导体层72的宽度更宽。相反的，也可以是一对第一主端子11之间的距离比一对第二主端子12之间的距离更长，并且位于第一主端子11之间的第二导体层72的宽度可以比位于第二主端子12之间的第二导体层72的宽度更窄。这里的“宽度”可以指与假想直线VL相垂直的方向上的长度，也可以指沿假想直线VL的方向上的长度。
多个第一导体层71可以是全部或一部分相对于假想直线VL呈线对称配置。
第一导体层71、第二导体层72、以及第三导体层73中的两个或是全部(三个)可以采用相同的制造方法来制造。第一导体层71的厚度、第二导体层72的厚度、以及第三导体层73的厚度中的两个或是全部(三个)可以是相对应的。这里的“相对应”是指任意一个导体层的厚度均在作为参照对象的导体层的厚度平均值的±5％以内。另外，也可以使第二导体层72的厚度比第一导体层71更厚从而切实地防止基板5翘曲，相反的，也可以使虚设的第二导体层72的厚度比第一导体层71的厚度更薄。
在图2所示的形态中，在第一导体层71上连接有第二主端子12，第二主端子12通过第一导体层71与半导体元件95的背面相连接。第二主端子12上的与第一导体层71相连接的部位的周缘可以配置有用于防止焊锡等导电性接合剂流出的抗蚀剂(Resist)(未图示)。
第一主端子11以及第二主端子12可以是流通200A～300A程度的大容量电流的电源端子。
在图1所示的形态中，第二主端子12以及控制端子15从封装部90的一个侧面向外部突出，第一主端子11从封装部90的另一个侧面向外部突出。这些第一主端子11、第二主端子12、以及控制端子15被朝正面一侧折弯，并且与配置在正面一侧的控制基板相连接。该控制基板用来对半导体元件95进行控制。
半导体装置的封装部90内可以呈线对称结构。在图3所示的形态中，第一主端子11、第二主端子12、以及导体层70(第一导体层71、第二导体层72、以及第三导体层73)各自相对于假想直线VL呈线对称配置。
《作用·效果》
接下来，将对由上述构成组成的本实施方式的作用以及效果进行说明。另外，也可以适宜地采用在《作用·效果》中说明的构成。
在本实施方式中，如图3所示，在未配置有第一导体层71的假想直线VL上配置虚设的第二导体层72。通过配置这样的第二导体层72，就能够防止基板5的翘曲变大。
如图3所示，在采用配置有一对第二导体层72，并且连接一对第二导体层72的直线与假想直线VL相吻合的形态的情况下，就能够在假想直线VL上至少配置两个第二导体层72。因此，就能够更加切实地防止基板5翘曲。
在采用一方的第二导体层72位于基板5的一方的端部，另一方的第二导体层72位于基板5的另一方的端部的形态的情况下，就能够使第二导体层72位于靠近周缘的位置上，这样就能够更加切实地防止基板5翘曲。另外，由于如果将第二导体层72配置在基板5的面内方向上的中央部就可能对其他构件的配置形成妨碍，因此通过将其配置在基板5的端部，从能够极力避免这种情况发生的角度来讲也是有益的。
在采用多个第一导体层71的全部或一部分相对于假想直线VL呈线对称配置的形态的情况下，在某假想直线上未配置有第一导体层71的可能性就比较大，这样，基板5就有可能发生翘曲。因此从这一点来说，如本实施方式般配置第二导体层72是有益的。尤其是，当多个第一导体层71全部相对于假想直线VL呈线对称配置时，在某假想直线上未配置有第一导体层71的可能极大，这样，基板5发生翘曲的可能性也就会变得很大。因此，如本实施方式般配置第二导体层72是非常有益的。
第二实施方式
接下来，对本发明的第二实施方式进行说明。
在第一是方式中，对配置有单个一对第二导体层72的形态进行了说明。而在第二实施方式中，将对配置有多个一对第二导体层72的形态，以及/或者配置有未成对的第二导体层72的形态进行说明。
第二实施方式中除此之外的其他构成与第一实施方式相同。在第二实施方式中，与第一实施方式相同或同样的构件等使用同一符号进行表示，并省略其说明。另外，第二实施方式也同样能够获得第一实施方式所能实现的效果。
在图4以及图5所示的形态中，能够沿宽度方向划两条假想直线VL，沿长度方向划一条假想直线VL。并且，在各条假想直线VL上均配置有一对第二导体层72。各个第二导体层72均位于基板5的端部。像这样，当配置有3个以及以上的第二导体层72时，对于能够更加切实地防止基板5翘曲来说是有益的。另外，在图4所示的形态中，未配置有第三导体层73。
第二导体层72的宽度可以互不相同。作为一例，如图4所示，位于长度方向的假想直线VL1上的第二导体层72的宽度可以比位于宽度方向的假想直线VL2上的第二导体层72的宽度更宽。
第二导体层72的厚度也可以互不相同。作为一例，位于长度方向的假想直线VL1上的第二导体层72的厚度可以比位于宽度方向的假想直线VL2上的第二导体层72的厚度更厚。
如图6所示，可以是沿基板5的长度方向的假想直线VL1上的第二导体层72成对配置，而沿基板5的宽度方向的假想直线VL2上的第二导体层72未形成对。由于基板5具有在长度方向上翘曲变大的倾向，因此通过采用这样的形态，对于能够在削减作为虚设的第二导体层72的数量的同时，极力防止基板5翘曲来说是有益的。
另外，可以是某假想直线VL与别的假想直线VL平行配置，并且某假想直线VL上的第二导体层72配置在一侧，别的假想直线VL上的第二导体层72配置在另一侧。通过采用这样的形态，即便是在因空间等问题不得不在不同的假想直线VL2上配置第二导体层72的情况下，也能够将第二导体层72配置两个方向上，从而极力防止基板5发生翘曲。在图6所示的形态中，位于图6左侧的宽度方向的假想直线VL2上的第二导体层72被配置在图6下侧的端部，而位于图6右侧的宽度方向的假想直线VL2上的第二导体层72则被配置在图6上侧的端部。
另外，在三条及以上的假想直线VL平行配置的形态中，第二导体层72可以在一侧与另一侧交互地进行配置。通过采用这样的形态，即便是在因空间等问题不得不在不同的假想直线VL2上配置第二导体层72的情况下，也能够将第二导体层72均衡地配置两个方向上，从而极力防止基板5发生翘曲。在图7所示的形态中，位于图7左侧的宽度方向的假想直线VL2上的第二导体层72被配置在图7下侧的端部，位于图7中央的宽度方向的假想直线VL2上的第二导体层72被配置在图7上侧的端部，位于图7右侧的宽度方向的假想直线VL2上的第二导体层72则被配置在图7下侧的端部。
最后，上述各实施方式、变形例中的记载以及附图中公开的图示仅为用于说明权利要求项中记载的发明的一例，因此权利要求项中记载的发明不受上述实施方式或附图中公开的内容所限定。本申请最初的权利要求项中的记载仅仅是一个示例，可以根据说明书、附图等的记载对权利要求项中的记载进行适宜的变更。
符号说明
5 基板
11 第一主端子
12 第二主端子
71 第一导体层
72 第二导体层
73 第三导体层
90 封装部
95 半导体元件(电子元件)
VL 假想直线

Claims (6)

1.一种电子装置，其特征在于，包括：
基板；
配置在所述基板上的第一导体层；
配置在所述基板上的第二导体层；
配置在所述第一导体层上的电子元件；以及
将所述基板、所述第一导体层、所述第二导体层、以及所述电子元件覆盖的封装部，
其中，在所述基板的面内方向上的，包含所述第二导体层的假想直线上未配置有所述第一导体层，
所述第二导体层在被封入所述封装部内的同时仅被所述封装部所覆盖。
2.根据权利要求1所述的电子装置，其特征在于：
其中，配置有一对第二导体层，
连接所述一对第二导体层的直线与所述假想直线相吻合。
3.根据权利要求2所述的电子装置，其特征在于：
其中，一方的第二导体层位于所述基板的一方的端部，另一方的第二导体层位于所述基板的另一方的端部。
4.根据权利要求1至3中任意一项所述的电子装置，其特征在于：
其中，所述多个第一导体层相对于所述假想直线呈线对称配置。
5.根据权利要求1至4中任意一项所述的电子装置，其特征在于：
其中，配置有多个第二导体层，
某假想直线与别的假想直线平行配置，
所述某假想直线上的第二导体层配置在一侧，所述别的假想直线上的第二导体层配置在另一侧。
6.根据权利要求1至5中任意一项所述的电子装置，其特征在于：
其中，配置有多个第二导体层，
沿所述基板的长度方向的假想直线上的所述第二导体层成对配置，
沿所述基板的宽度方向的假想直线上的所述第二导体层未形成对。
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